Multi-node serial communication method, system, device and storage medium

Abstract

The application belongs to the technical field of serial communication, and particularly relates to a multi-node serial communication method, system, device and storage medium. The multi-node serial communication method applied to a master device comprises the following steps: determining a polling period of a plurality of slave devices based on a current working mode, wherein different working modes correspond to different polling periods; polling the plurality of slave devices in turn based on the polling period; and sending an instruction frame containing a node identifier to a target slave device through a shared data channel for a target slave device currently polled, so that the target slave device replies a response frame through the shared data channel when the node identifier matches the identifier of the target slave device, and remains silent when the node identifier does not match the identifier of the target slave device. The method of the application realizes dynamic adaptation of communication frequency and business load, and guarantees high real-time performance and low power consumption demand while ensuring anti-collision reliability.

Description

Technical Field

[0001] This application belongs to the field of serial communication technology, specifically relating to a multi-node serial communication method, system, device, and storage medium. Background Technology

[0002] In multi-node serial communication systems, conventional techniques utilize CAN bus, RS485 bus, etc., to achieve one-master-multiple-slave or multiple-master-multiple-slave communication. For example... Figure 1 As shown, in multi-node serial communication based on the CAN bus, each terminal device can access the CAN bus to send data, and can also receive and parse the data it needs as required, thereby completing inter-device communication. However, implementing multi-node communication based on the bus requires the support of corresponding arbitration chips. For example, the CAN bus requires a CAN controller, and the 485 bus requires a 485 transceiver chip, which increases product cost.

[0003] To reduce hardware costs, some solutions employ a shared data channel architecture without a dedicated arbitration chip, where the master device and multiple slave devices interact via a shared transmit or receive line. However, due to the lack of a hardware-level arbitration mechanism, level conflicts are highly likely to occur when multiple slave devices simultaneously send data to the master device, leading to communication failures. To address this issue, a fixed-interval polling method is typically used to avoid conflicts, but this method cannot dynamically adjust the communication frequency according to the workload: under high load scenarios, a fixed and long polling interval results in large data response delays and poor real-time performance; under low load or standby scenarios, fixed and frequent polling causes unnecessary bus occupation and power consumption waste.

[0004] Therefore, how to ensure the anti-collision reliability of multi-node communication while taking into account the requirements of high real-time performance and low power consumption in a shared channel architecture without hardware arbitration is a technical problem that urgently needs to be solved in this field. Summary of the Invention

[0005] This application provides a multi-node serial communication method, electronic device, and storage medium, aiming to solve the problem in the prior art that it is difficult to balance anti-collision reliability, communication efficiency, and power consumption in shared channel communication without hardware arbitration. It realizes adaptive polling communication and power consumption management based on running status and identifier matching.

[0006] In a first aspect, embodiments of this application provide a multi-node serial communication method applied to a master device, wherein the master device and multiple slave devices are connected via a shared data channel without hardware arbitration, the method comprising: Based on the current working mode, the polling cycle for the multiple slave devices is determined, wherein different working modes correspond to different polling cycles; The plurality of slave devices are polled sequentially based on the polling period; For the target slave device currently being polled, an instruction frame containing a node identifier is sent to the target slave device through the shared data channel, so that the target slave device replies with a response frame through the shared data channel when the node identifier matches its own identifier, and remains silent when they do not match.

[0007] Optionally, the transmitting end of the master device is connected to the receiving end of the plurality of slave devices respectively through a first shared line, and the transmitting ends of the plurality of slave devices are connected to the receiving end of the master device through a second shared line to form the shared data channel; The step of sending a command frame containing a node identifier to the target slave device through the shared data channel, so that the target slave device replies with a response frame through the shared data channel when the node identifier matches its own identifier, and remains silent when they do not match, includes: The master device sends the instruction frame through the first shared line; Each slave device parses the node identifier in the instruction frame. If the node identifier matches its own identifier, it sends the response frame to the master device through the second shared line. If they do not match, the slave device does not send data through the second shared line to avoid level conflicts on the second shared line.

[0008] Optionally, the frame structure of the instruction frame and the response frame includes at least: The address code field is used to carry the node identifier or the self identifier, so as to realize the addressing and matching between the master device and the multiple slave devices; The instruction type code field is used to carry the instruction priority and the type of communication instruction; Data segment fields are used to carry business interaction data; The verification field is used to perform integrity checks on the entire frame of data.

[0009] Optionally, the method further includes: A timeout timer is started after the instruction frame is sent; If the response frame from the target slave device is not received within the preset timeout period, or if the received response frame fails the data verification, then a retry transmission is performed or the current target slave device is skipped, and the instruction frame is sent to the next slave device according to the polling cycle.

[0010] Optionally, the operating modes include a high-load operating mode, a normal operating mode, and a low-power standby mode. The first polling period corresponding to the high-load operating mode, the second polling period corresponding to the normal operating mode, and the third polling period corresponding to the low-power standby mode satisfy the following relationship: the first polling period is less than the second polling period, and the second polling period is less than the third polling period.

[0011] Optionally, the method further includes: If the current working mode is the low-power standby mode, then the data communication module between the master device and the multiple slave devices is controlled to enter a sleep listening state, and the status of the multiple slave devices is checked sequentially according to the third polling cycle; When an external trigger event is detected, the current working mode is switched to the normal working mode. The data communication modules of the master device and the multiple slave devices are woken up through a hardware wake-up channel independent of the shared data channel and put into normal working state. The multiple slave devices are then polled sequentially according to the second polling cycle.

[0012] Optionally, the shared data channel is implemented based on a Universal Asynchronous Receiver / Transmitter (UART) serial port.

[0013] Secondly, embodiments of this application provide a multi-node serial communication system, including a master device and multiple slave devices; The transmitting end of the master device is connected to the receiving end of each of the slave devices through a first shared line, and the transmitting ends of each of the slave devices are connected to the receiving end of the master device through a second shared line to form a shared data channel without hardware arbitration. The master device and the multiple slave devices are also provided with a hardware wake-up connection line independent of the shared data channel; The master device is configured to perform the multi-node serial communication method described in any of the preceding descriptions.

[0014] Thirdly, embodiments of this application provide an electronic device, including at least one processor and a memory communicatively connected to the at least one processor, the memory storing instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform the method described above.

[0015] Fourthly, embodiments of this application provide a computer storage medium storing instructions or programs that, when executed by at least one processor, cause the at least one processor to perform any of the methods described above.

[0016] In this application embodiment, a multi-node serial communication method is provided, which has the following beneficial effects: This application constructs a collaborative mechanism of "arbitration-free hardware topology + identifier matching anti-collision + adaptive polling". On the one hand, under a low-cost hardware architecture without a dedicated arbitration chip, the active silencing logic based on address matching of slave devices fundamentally eliminates the risk of level collision when multiple nodes transmit on the same line, ensuring the reliability of communication. On the other hand, by dynamically adjusting the polling cycle through sensing the system's working mode, the communication frequency is adapted to the service load in real time. Under high load, the polling cycle is shortened to ensure data real-time performance, and under low load, the polling cycle is extended to reduce interaction, significantly improving communication efficiency. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the existing CAN bus multi-device communication system architecture; Figure 2 This is a schematic diagram of the hardware connection structure of the multi-node serial communication system provided in the embodiments of this application; Figure 3 This is a flowchart illustrating the multi-node serial communication method provided in an embodiment of this application; Figure 4 This is a schematic diagram of the adaptive polling communication timing of the refrigerator multi-panel control system provided in the embodiments of this application; Figure 5 This is a schematic diagram of the fixed polling communication timing of a multi-panel control system for refrigerators in the prior art; Figure 6 This is a schematic diagram of the hardware structure of an electronic device provided in an embodiment of this application.

[0018] Among them, 100-master device, 200-slave device, 201-first slave device, 202-second slave device, 301-first shared line, 302-second shared line, and 400-hardware wake-up channel. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0020] According to an embodiment of this application, a multi-node serial communication system is provided. For example... Figure 2The diagram shown is a schematic of the hardware connection structure of a multi-node serial communication system provided in this application embodiment. The multi-node serial communication system includes a master device 100 and multiple slave devices 200. The transmitting end of the master device 100 is connected to the receiving end of each slave device 200 through a first shared line 301, and the transmitting ends of each slave device 200 are connected to the receiving end of the master device 100 through a second shared line 302 to form a shared data channel without hardware arbitration.

[0021] Specifically, the aforementioned physical connection structure defines an asymmetric communication topology. In the downlink direction (master to slave), the first shared line 301 presents a one-to-many broadcast physical link, with the master device 100's transmitter acting as the sole driving source, its output electrical signal being simultaneously perceived by the receivers of all slave devices 200. In the uplink direction (slave to master), the second shared line 302 presents a many-to-one convergent physical link, with the transmitters of all slave devices 200 electrically connected in parallel to the same conductor or network node. This "master-to-many, slave-to-many" topology eliminates the need for dedicated arbitration chips or transceivers required in traditional bus schemes, significantly reducing hardware costs.

[0022] In one implementation, the shared data channel is based on a Universal Asynchronous Receiver / Transmitter (UART) serial port. By leveraging the universality and low cost of the UART interface, the feasibility of this solution in various embedded systems is further enhanced.

[0023] In addition, the master device 100 and the multiple slave devices 200 are provided with a hardware wake-up connection line independent of the shared data channel, that is... Figure 2 The hardware wake-up channel 400 shown is physically isolated from the first shared line 301 and the second shared line 302, and does not constitute part of the data transmission loop. In specific implementations, it can be a dedicated GPIO signal line, an edge-triggered pulse line, or an independent control path connected via optocouplers, magnetic couplers, or other isolation devices. Decoupling the wake-up signaling from the data signaling at the physical medium is a hardware prerequisite for implementing the low-power standby mode and fast response coordination mechanism described later. If wake-up is performed using the shared data channel itself (e.g., through specific wake-up characters or baud rate detection), the data communication module must always keep some circuitry in an active listening state, preventing it from entering deep sleep. This embodiment, by setting an independent hardware wake-up channel 400, allows the data communication module to completely shut down its power or clock when there is no data interaction, with only a very low-power interrupt detection circuit monitoring the level changes on the hardware wake-up channel 400. This ensures a microsecond-level wake-up response speed while minimizing standby power consumption.

[0024] The master device 100 is configured to execute a multi-node serial communication method as described in any of the embodiments below. This means that the master device 100 integrates a corresponding processor, memory, and communication peripherals, and can perform functions such as adaptive polling, priority scheduling, and sleep / wake-up by controlling the hardware topology through software or firmware.

[0025] Based on the above hardware architecture, this application provides a multi-node serial communication method. Please refer to... Figure 3 , Figure 3 A flowchart illustrating a multi-node serial communication method is shown, which is applied to the master device 100. The following section uses... Figure 2 Taking an example, we will describe the specific implementation process of the multi-node serial communication method, which includes the following steps S301 to S303.

[0026] Step S301: Based on the current working mode, determine the polling cycle for multiple slave devices, wherein different working modes correspond to different polling cycles.

[0027] In this embodiment, the master device 100 does not use a fixed polling cycle to communicate with each slave device 200. Instead, it dynamically adjusts the polling cycle according to the current operating mode of the system. For example, when the system is in a high-load operating mode, a shorter polling cycle can be used to ensure data real-time performance; when the system is in standby or low-power operating mode, it automatically switches to a longer polling cycle to reduce invalid interactions and energy consumption. This adaptive mechanism allows communication resources to be flexibly allocated according to business needs, resolving the contradiction between real-time performance and power consumption that is difficult to balance in traditional fixed polling schemes.

[0028] Step S302: Poll multiple slave devices sequentially based on the polling cycle.

[0029] The master device 100 maintains a deterministic polling sequence list, which defines the access order of each slave device 200. At the end of each polling cycle, the master device 100 selects the next slave device 200 to communicate with as the target slave device according to this sequence list. This deterministic scheduling method avoids the uncertainty caused by random contention and provides timing guarantees for ordered communication in a non-arbitration environment.

[0030] Step S303: For the target slave device currently being polled, send an instruction frame containing the node identifier to the target slave device through the shared data channel, so that the target slave device replies with a response frame through the shared data channel when the node identifier matches its own identifier, and remains silent when they do not match.

[0031] Specifically, the master device 100 sends a command frame through the first shared line 301. Since the first shared line 301 is a one-to-many connection, all slave devices 200 can receive the command frame. Each slave device 200 parses the node identifier in the command frame. If the node identifier is consistent with its own identifier, it sends a response frame to the master device 100 through the second shared line 302. If they are inconsistent, they do not send data through the second shared line 302 to avoid level conflicts on the second shared line 302.

[0032] It should be noted that the aforementioned "remaining silent when mismatched" mechanism is the key to preventing bus conflicts in this embodiment without a hardware arbitrator. Since the transmitting ends of multiple slave devices 200 are physically connected to the second shared line 302, if two or more slave devices simultaneously drive this line to transmit data, it will inevitably lead to signal superposition, level confusion, and even device damage. Therefore, this application, through strict constraints at the protocol layer, requires that when a non-target slave device receives an instruction frame that does not match its own identifier, its transmitting end must remain in a high-impedance state or a logically silent state, which is electrically equivalent to a disconnection. Only the single target slave device that is addressed is allowed to drive the second shared line 302. This software-level anti-collision strategy essentially replaces the expensive hardware arbitration circuit with low-cost logical judgment, achieving extreme simplification of the hardware architecture while ensuring communication reliability.

[0033] In one embodiment, before sending the instruction frame containing the node identifier to the target slave device via the shared data channel, the method further includes: selecting the highest priority instruction to be sent based on the priority of each instruction to be sent corresponding to the target slave device and encapsulating it into an instruction frame according to a preset frame structure. This embodiment essentially adds an application-layer intelligent scheduling step before the master device 100 performs the physical transmission action, aiming to solve the service congestion problem of a shared channel without hardware arbitration when communication resources are scarce.

[0034] Specifically, the master device 100 maintains an independent queue of pending commands for each slave device 200. Unlike traditional First-In-First-Out (FIFO) queues, this queue supports dynamic sorting or insertion based on priority. When the polling cycle arrives and the master device 100 is ready to initiate communication with a target slave device, it does not blindly retrieve the command at the head of the queue. Instead, it first scans the priority attributes of all pending commands in the queue, identifies and extracts the command with the highest priority at the current moment, encapsulates it, and sends it. For example, within a polling window, the master device 100 has two commands in its queue for the first slave device 201: one is a periodically triggered "temperature query" command (defined as low priority), and the other is a "fault alarm" command (defined as high priority) just generated due to a sensor malfunction. If a traditional FIFO mechanism is used and the temperature query command is enqueued first, the fault alarm must wait for the former to finish sending before it can be processed, which may lead to safety hazards in emergency situations. With the priority scheduling mechanism of this embodiment, the master device 100 will directly select the "fault alarm" instruction, encapsulate it into an instruction frame, and send it through the first shared line 301, thereby ensuring that critical business data can occupy the limited communication time slots and not be blocked by regular business.

[0035] It should be understood that the priority determination criteria mentioned above are not limited to the inherent type of the instruction itself. In some optional embodiments of this application, the priority of the instruction can also be dynamically calculated. For example, the master device 100 can dynamically adjust the weight of specific instructions according to the current working mode: in a high-load working mode, the priority of data acquisition instructions may be temporarily increased to ensure system stability; while in a low-power standby mode, the priority of all service instructions except wake-up and heartbeat is downgraded. This dynamic priority mechanism, together with the adaptive polling cycle, forms a dual collaborative guarantee of "macro-time sequence + micro-content". The combination of the two enables this application to significantly improve the real-time response capability and service throughput efficiency of a multi-node serial communication system under complex working conditions without increasing hardware costs. In addition, for low-priority instructions that are not selected, they are still kept in the pending queue, waiting for the next polling window or to be covered by higher-priority instructions, thereby ensuring the eventual accessibility of non-urgent services and avoiding the loss of business logic due to long-term starvation.

[0036] In one embodiment, based on the foregoing embodiments, the communication protocol carrier supporting addressing and priority scheduling is further specified. As one implementation, the frame structure of the instruction frame and response frame includes at least: an address code field, used to carry a node identifier or its own identifier to enable addressing and matching between the master device and multiple slave devices; an instruction type code field, used to carry the instruction priority and communication instruction type; a data segment field, used to carry service interaction data; and a check field, used to perform integrity verification on the entire frame data. This frame structure design sinks the abstract addressing logic and scheduling strategy to specific bit stream definitions, enabling ordered communication in a hardware-arbitration-free environment to have a parsable data foundation.

[0037] Specifically, the address code field is the physical prerequisite for the anti-collision mechanism. When the master device 100 broadcasts a command frame through the first shared line 301, all slave devices 200 will receive the frame data. Each slave device 200 first reads the content of the address code field and compares it with its own preset unique identifier. For example, in a system containing freezer and refrigerator plates, the address code "0x01" can be defined to represent the freezer plate, and "0x02" to represent the refrigerator plate. Only when the received address code completely matches its own identifier will the slave device be activated and reply with a response frame through the second shared line 302; other mismatched slave devices will immediately enter a silent state after parsing the address code and will not drive the transmitter. This "parsing before acting" mechanism based on the address code field strictly constrains bus access permissions at the protocol level, ensuring that no level conflicts occur in a multi-to-one connected topology. It should be understood that the length and encoding method of the address code are not limited to the above example, as long as it can uniquely distinguish each node in the network, for example, MAC address fragments or custom ID sequences can also be used.

[0038] In this application, the instruction type code field serves a dual function beyond traditional classification identifiers. It not only distinguishes between emergency fault alarms, routine status queries, and low-power control instructions, but also implicitly contains the instruction's priority weight information. Before sending an instruction frame, the master device 100 selects an instruction based on the highest priority in the pending instruction queue and writes the corresponding priority mapping value into the instruction type code field. Similarly, when the slave device 200 replies with a response frame, it also reflects its current status level or task urgency in the instruction type code field. After receiving the response frame and parsing the instruction type code, the master device 100 not only completes the current business interaction but also inputs the type code as a decision factor into the adaptive polling algorithm. For example, if the master device 100 continuously receives instruction type codes representing "high load" or "abnormal" from a slave device, it can determine that the current system is in a state requiring high-frequency monitoring, and thus automatically shorten the next polling cycle for that slave device; conversely, if it only receives "idle" or "normal" feedback for a long time, it can gradually extend the polling interval to save power. It is evident that the instruction type code field constitutes an information link connecting single communication behavior with global scheduling strategy, making the adjustment of the polling cycle no longer a blind timed switch, but a precise response based on real-time business semantics.

[0039] The data segment field carries the actual service payload, such as temperature sampling values, fan speed settings, and fault codes. Its length can be fixed or dynamically variable, depending on the specific application requirements. The check field typically uses cyclic redundancy check or cumulative checksum methods to cover all or part of the address code, instruction type code, and data segment bits, used to detect bit errors during transmission. If the check fails, the master device 100 or slave device 200 can directly discard the frame and trigger a retransmission or error handling process, thus ensuring data reliability on a simple serial link without dedicated error correction hardware. It should be noted that although this embodiment lists the above four core fields, in practical applications, the frame structure can also add a synchronization header at the beginning, a stop bit at the end, or insert a reserved field between the address code and instruction type code for future functional expansion as needed. These variations are all within the scope of this invention, as long as they retain the key fields supporting identifier matching and priority awareness.

[0040] In one embodiment, to further enhance the robustness of the communication link in complex electromagnetic environments or abnormal node conditions, this application also specifies the abnormal handling mechanism of the master device 100. As one implementation, the method further includes: starting a timeout timer after sending a command frame; if no response frame is received from the target slave device within a preset timeout period, or if the received response frame fails data verification, then retrying transmission or skipping the current target slave device and continuing to send command frames to the next slave device according to the polling cycle. This mechanism constitutes a "safety valve" for the communication protocol of this application, effectively preventing the entire multi-node serial communication system from deadlocking or experiencing a sharp performance degradation due to the failure of a single slave device 200 or momentary interference.

[0041] Specifically, when the master device 100 sends a command frame to the target slave device via the first shared line 301, it simultaneously starts its internal hardware or software timeout timer. The preset timeout period of this timer should be slightly longer than the maximum theoretical time required for normal round-trip communication to accommodate signal transmission delays and the processing time of the slave device 200, while being short enough to quickly identify anomalies. When the timer overflows without detecting a valid start bit of a response frame, the master device 100 determines that "no reply has been received after timeout." This situation may be caused by various reasons, such as a power outage of the target slave device 200, an open circuit in the second shared line 302, or the target slave device 200 failing to correctly parse the address code due to an internal logic error and remaining in an incorrect silent state. For such anomalies, the master device 100 can be configured to execute a retry transmission strategy, i.e., retransmit the same command frame within a short period. The retry mechanism is mainly used to combat transient pulse interference or occasional synchronization loss in the channel, improving the communication success rate through redundant transmission. However, if a timeout still occurs after a preset maximum number of retries (e.g., 3 times), the master device 100 should decisively skip the current target slave device and directly move the communication pointer to the next slave device in the polling sequence list. This "limited retries + timely stop-loss" strategy avoids the master device 100 waiting indefinitely on a failed node, thus ensuring that the real-time communication of the remaining normal slave devices 200 is not affected.

[0042] Another abnormal situation is that the master device 100 receives a response frame within the preset timeout period, but the response frame fails the data verification. Combined with the verification field described in the previous embodiments, this usually means that although the physical connection is established, bit flipping or signal distortion occurred during transmission, causing the CRC check to fail. In this case, the master device 100 should immediately discard the erroneous frame and not load its data into the service cache to prevent error information from polluting the upper-layer control logic. Subsequently, the master device 100 can also trigger a retransmission process, requesting the target slave device 200 to re-upload the data. It is worth noting that the limit on the number of retries for verification failure can be configured independently of the timeout retries, because verification failure often indicates a more serious signal integrity problem, which may require a more conservative retry strategy or trigger a link quality alarm.

[0043] It's important to note that the above-described exception handling process is decoupled from the normal adaptive polling cycle. Specifically, the time consumed by exception handling (including timeout waiting time, retry interval, etc.) is considered an independent maintenance overhead and is not included in the defined polling cycle. For example, assuming the current operating mode is normal and the polling cycle is 100ms, if the master device 100 triggers a 50ms timeout retry process while communicating with a slave device 200, the total interaction time becomes 150ms. In this case, after handling the exception node, the master device 100 immediately initiates communication with the next node according to the original rhythm, instead of artificially inserting extra idle waiting to make up the 100ms interval, or delaying the communication time of the next node by 50ms. This decoupling design ensures that even if there are individual unstable nodes in the system, the average refresh rate of the overall polling sequence can still be maintained at the expected level, avoiding cascading delay effects. This is crucial for maintaining stable closed-loop control performance in industrial or home appliance multi-node control systems.

[0044] Furthermore, parameters such as the preset timeout time and the number of retries are not static. In some optional embodiments of this application, these parameters can also be adaptively adjusted according to the current operating mode. For example, in a high-load operating mode, to ensure the ultimate response speed, the timeout time can be set to a shorter duration and the number of retries to quickly eliminate faulty nodes; while in a low-power standby mode, considering that clock accuracy may decrease or wake-up latency may be large, the timeout threshold can be appropriately relaxed and the retry tolerance increased to reduce the energy consumption of invalid wake-up caused by misjudgments. This flexibility at the parameter level further enhances the adaptability of the present invention to different application scenarios.

[0045] In one embodiment, based on the aforementioned embodiments, the coordination mechanism between power management and response speed of the multi-node serial communication system is further specifically defined. As one implementation method, the operating modes include a high-load operating mode, a normal operating mode, and a low-power standby mode. The high-load operating mode corresponds to the first polling cycle, the normal operating mode corresponds to the second polling cycle, and the low-power standby mode corresponds to the third polling cycle. They satisfy the following relationship: the first polling cycle is shorter than the second polling cycle, and the second polling cycle is shorter than the third polling cycle. This feature establishes a multi-level gradient mapping relationship between communication frequency and system power consumption.

[0046] Specifically, the high-load operating mode typically corresponds to scenarios such as system startup initialization, fault recovery, or intensive data acquisition. In this case, the first polling cycle is set to a minimum value (e.g., 50ms) to ensure that the master device 100 can obtain the status information of the slave device 200 with the highest bandwidth, guaranteeing the real-time performance of control. The normal operating mode corresponds to the steady-state operation of the system, and the second polling cycle (e.g., 100ms) meets basic monitoring requirements while avoiding excessive bus occupancy. The low-power standby mode corresponds to idle or energy-saving scenarios, and the third polling cycle (e.g., 500ms or even longer) significantly reduces the communication frequency. This tiered cycle strategy is not a simple parameter configuration but a fine-grained allocation of communication resources based on business semantics, enabling the system to keep average power consumption at a minimum while ensuring key performance indicators. It should be understood that the above three modes are only exemplary classifications. In practical applications, more intermediate modes can be added or the specific values ​​of each cycle can be dynamically adjusted according to specific business needs. As long as the monotonic trend of shorter cycles with higher load is maintained, it falls within the protection scope of this application.

[0047] To achieve true energy savings in low-power standby mode without sacrificing rapid response to external events, this embodiment introduces a deep hardware and software collaborative wake-up mechanism. As one implementation, if the current operating mode is low-power standby mode, the data communication modules of the master device 100 and multiple slave devices 200 enter a sleep listening state, and the status of the multiple slave devices 200 is checked sequentially according to the third polling cycle. When an external trigger event is detected, the current operating mode is switched to the normal operating mode, and the data communication modules of the master device 100 and multiple slave devices 200 are woken up through a hardware wake-up channel 400 independent of the shared data channel to enter normal operating mode, and the multiple slave devices 200 are polled sequentially according to the second polling cycle.

[0048] Specifically, in low-power standby mode, the data communication modules (such as UART modules) inside the master device 100 and slave device 200 do not maintain full-speed operation while waiting for data, but instead enter an extremely low-power sleep listening state. In this state, the high-frequency clock of the data communication module is turned off or divided, retaining only the necessary wake-up logic circuit, and its static current can be reduced to the microamp level. At this time, the system only briefly wakes up the data communication module for heartbeat detection or status query according to a relatively long third polling cycle; the data communication module remains in sleep mode for the vast majority of the time, thereby cutting off the invalid static power consumption on the shared data channel. To respond to external emergencies (such as user operation, sensor alarms, etc.), this application sets up a hardware wake-up channel 400 independent of the shared data channel. Figure 2 As shown, the hardware wake-up channel 400 is physically distinct from the first shared line 301 and the second shared line 302. It can be a dedicated GPIO interrupt line, an edge-triggered signal line, or other hardwired connection. When an external trigger event occurs (e.g., the refrigerator door is opened, a user presses a button, or a temperature sensor detects an abnormal threshold), the event signal is not transmitted through the shared data channel. Instead, it is directly applied to the interrupt pins of the master device 100 and the slave device 200 via the hardware wake-up channel 400 in the form of a level transition or pulse. Because this channel is independent of the data bus, even if the data communication module is in a deep sleep state, the interrupt controller can immediately capture the signal and forcibly wake up the data communication module, instantly restoring it to normal operation. Subsequently, the master device 100 automatically switches its current operating mode from low-power standby mode to normal operating mode (or directly jumps to high-load operating mode) and adjusts the polling cycle to the corresponding second polling cycle (or the first polling cycle), initiating high-frequency data interaction.

[0049] Unlike existing technologies that rely solely on software timer polling for wake-up or keeping the data bus in a low-power listening state, this application decouples control signaling and data signaling at the physical layer. This allows the data communication module to enter a sleep listening state when there is no data transmission requirement, eliminating the need to consume any static current to maintain listening. Simultaneously, leveraging the asynchronous nature of hardware interrupts, the system can be activated by external events within microseconds, completely unaffected by the length of the third polling cycle. This hardware-software co-operation mechanism effectively breaks the zero-sum game between power consumption and response speed in traditional serial communication systems, making it particularly suitable for battery-powered IoT devices and smart home appliances with stringent energy efficiency requirements. Furthermore, the hardware wake-up channel 400 can also carry simple event encoding functions, such as indicating the trigger source type through different numbers of pulses or different level combinations, enabling the master device 100 to prioritize the most urgent tasks after wake-up, further enhancing the system's intelligence level.

[0050] To more clearly illustrate the application value of the technical solution of this application in actual industry, this embodiment provides a specific application example of applying the multi-node serial communication method described in any of the foregoing embodiments to a refrigerator multi-panel control system. It is understood that this communication method is also applicable to any other electronic device or system with master-slave communication requirements, such as air conditioners, washing machines, energy storage cabinets, and industrial control cabinets.

[0051] In this application example, the master device 100 is specifically implemented as the refrigerator's display panel, responsible for user interaction and overall system status management; multiple slave devices 200 include a first slave device 201 and a second slave device 202, corresponding to the refrigerator's freezer and refrigerator compartments respectively, responsible for temperature acquisition, fan control, and defrosting functions for their respective temperature zones. The display panel is connected to the freezer and refrigerator compartments using... Figure 2 The system shown is a hardware-free shared data channel connection with an independent hardware wake-up channel 400. Based on the adaptive polling mechanism in the aforementioned embodiments, the system exhibits differentiated communication behaviors under different operating conditions. For example... Figure 4 The diagram shown is a schematic of the adaptive polling communication timing of the refrigerator multi-panel control system provided in this application embodiment, as detailed below: In normal operating mode, the refrigerator is in normal cooling and preservation mode, with no frequent user operation and no abnormal alarms. At this time, the display board, as the master device 100, sets the polling period to the second polling period T2, for example, 100ms. The display board queries the temperature and status information of the freezer and refrigerator plates in a preset order. This period setting ensures that the real-time temperature display meets user experience requirements while avoiding excessive bus occupancy, keeping the system at a balance between performance and power consumption.

[0052] In high-load operating modes, such as when the refrigerator is first powered on and initialized, entering quick-freeze mode, or executing a defrost program, the freezer or refrigerator plates need to report temperature change curves frequently to prevent overshoot or undercooling. At this time, if the display board detects an increase in system load or receives an instruction type code indicating an urgent task, it automatically switches the polling cycle to the first polling cycle T1, for example, 50ms. This means that the number of data acquisition points per unit time doubles, and the data refresh rate is increased by 50% compared to the fixed 100ms solution. This dynamic acceleration mechanism ensures that the main control algorithm can obtain a sufficient density of feedback data during critical control windows, thereby achieving precise temperature control. In contrast, in a fixed polling solution, to meet this high-frequency requirement, the global polling interval must be permanently set to 50ms. This would result in the bus constantly running under high load during normal cooling periods lasting several hours, wasting bandwidth resources and increasing the risk of unnecessary electromagnetic interference.

[0053] In low-power standby mode, when the refrigerator remains untouched for an extended period and the temperatures in each zone are stable, the system enters an energy-saving state. The display panel sends low-power command frames to the freezer and refrigerator panels, after which the UART communication modules within all three enter a sleep listening state, extending the polling cycle to the third polling cycle T3, such as 500ms or even longer. During this period, data transmission on the shared data channel almost ceases, relying solely on extremely low-frequency heartbeat packets to maintain the link's survival. More importantly, to ensure immediate response to user door opening actions or button presses, the system utilizes a hardware wake-up channel 400 (such as the GPIO interrupt line connected to the door magnetic switch), independent of the data bus, for event monitoring. Once a door opening is detected, the hardware wake-up channel 400 immediately triggers an interrupt signal, forcibly waking up the UART module from deep sleep and restoring it to normal operating mode or high-load mode within microseconds.

[0054] Actual test data shows that, compared to a fixed polling scheme that always keeps the UART module running at full speed (such as...), Figure 5 As shown in the figure, this embodiment reduces the average power consumption of the communication module in standby mode by more than 80%. This significant energy-saving effect stems from the decoupled design of "complete data bus hibernation" and "independent hardware asynchronous wake-up", which breaks through the technical bottleneck of traditional solutions that have to sacrifice standby power consumption in order to maintain response speed.

[0055] In summary, by combining an adaptive polling strategy with a specific hardware topology, this application successfully achieved a fine-grained match between communication efficiency and energy consumption management in the aforementioned refrigerator application scenario. This technical concept of dynamically adjusting physical layer parameters based on business semantics not only solves the problems of poor real-time performance under high load and high energy consumption under low power consumption in fixed polling schemes, but also provides a general solution with both high performance and high energy efficiency for low-cost embedded multi-node communication systems.

[0056] According to an embodiment of this application, an electronic device is provided. For example... Figure 6 The diagram shown is a hardware structure schematic of an electronic device according to an embodiment of this application. The electronic device 100 includes a processor 10, a memory 20, and a communication interface 30. The processor 10, memory 20, and communication interface 30 are connected via lines. Figure 6 In the embodiment shown, the processor 10, memory 20, and communication interface 30 are connected to each other via a bus.

[0057] The memory 20 is used to store software programs, computer-executable program instructions, etc. The memory 20 may include a program storage area and a data storage area, wherein the program storage area may store the operating system and application programs required for at least one function; the data storage area may store data created based on the use of the electronic device 100, etc.

[0058] The memory 20 can be a read-only memory (ROM), or other types of static storage devices that can store static information and instructions, or random access memory (RAM), or other types of dynamic storage devices that can store information and instructions, or electrically erasable programmable read-only memory (EEPROM). The specific type is not limited here.

[0059] For example, the aforementioned memory 20 can be Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM). This memory 20 can exist independently but is connected to the processor 10. Optionally, the memory 20 can also be integrated with the processor 10, for example, integrated within one or more chips.

[0060] In some embodiments, the memory 20 may optionally include memory remotely located relative to the processor 10, and this remote memory may be connected to the electronic device 100 via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0061] The processor 10 connects various parts of the electronic device 100 using various interfaces and lines. By running or executing software programs stored in the memory 20 and calling data stored in the memory 20, it performs various functions of the electronic device 100 and processes data, such as implementing the methods described in any embodiment of this application.

[0062] The processor 10 can be a field programmable gate array (FPGA), a digital signal processor (DSP), a central processing unit (CPU), or the like.

[0063] Processor 10 can be a single-core processor or a multi-core processor. For example, processor 10 can be composed of multiple FPGAs or multiple DSPs. Furthermore, processor 10 can refer to one or more devices, circuits, and / or processing cores for processing data (e.g., computer program instructions). Processor 10 can be a standalone semiconductor chip or integrated with other circuits into a single semiconductor chip. For example, it can form a system-on-a-chip (SoC) with other circuits (such as encoding / decoding circuits, hardware acceleration circuits, or various bus and interface circuits), or it can be integrated as a built-in processor within an application-specific integrated circuit (ASIC). This ASIC with integrated processor can be packaged separately or together with other circuits.

[0064] The communication interface 30 can use a transceiver device, such as a transceiver, to enable communication between the electronic device 100 and other devices or communication networks.

[0065] This application also provides a non-volatile computer-readable storage medium storing computer-executable instructions that are executed by one or more processors, for example, to perform the steps of the multi-node serial communication method described above.

[0066] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and not to limit them; under the concept of this application, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of this application as described above, which are not provided in detail for the sake of brevity; although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A multi-node serial communication method, applied to a master device, wherein the master device and multiple slave devices are connected via a shared data channel without hardware arbitration, characterized in that, The method includes: Based on the current working mode, the polling cycle for the multiple slave devices is determined, wherein different working modes correspond to different polling cycles; The plurality of slave devices are polled sequentially based on the polling period; For the target slave device currently being polled, an instruction frame containing a node identifier is sent to the target slave device through the shared data channel, so that the target slave device replies with a response frame through the shared data channel when the node identifier matches its own identifier, and remains silent when they do not match.

2. The method according to claim 1, characterized in that, The transmitting end of the master device is connected to the receiving end of the plurality of slave devices through a first shared line, and the transmitting ends of the plurality of slave devices are connected to the receiving end of the master device through a second shared line to form the shared data channel; The step of sending a command frame containing a node identifier to the target slave device through the shared data channel, so that the target slave device replies with a response frame through the shared data channel when the node identifier matches its own identifier, and remains silent when they do not match, includes: The master device sends the instruction frame through the first shared line; Each slave device parses the node identifier in the instruction frame. If the node identifier matches its own identifier, it sends the response frame to the master device through the second shared line. If they do not match, the slave device does not send data through the second shared line to avoid level conflicts on the second shared line.

3. The method according to claim 2, characterized in that, The frame structures of the instruction frame and the response frame include at least: The address code field is used to carry the node identifier or the self identifier, so as to realize the addressing and matching between the master device and the multiple slave devices; The instruction type code field is used to carry the instruction priority and the type of communication instruction; Data segment fields are used to carry business interaction data; The verification field is used to perform integrity checks on the entire frame of data.

4. The method according to claim 1, characterized in that, The method further includes: A timeout timer is started after the instruction frame is sent; If the response frame from the target slave device is not received within the preset timeout period, or if the received response frame fails the data verification, then a retry transmission is performed or the current target slave device is skipped, and the instruction frame is sent to the next slave device according to the polling cycle.

5. The method according to any one of claims 1 to 4, characterized in that, The operating modes include a high-load operating mode, a normal operating mode, and a low-power standby mode. The first polling cycle corresponding to the high-load operating mode, the second polling cycle corresponding to the normal operating mode, and the third polling cycle corresponding to the low-power standby mode satisfy the following relationship: the first polling cycle is less than the second polling cycle, and the second polling cycle is less than the third polling cycle.

6. The method according to claim 5, characterized in that, The method further includes: If the current working mode is the low-power standby mode, then the data communication module between the master device and the multiple slave devices is controlled to enter a sleep listening state, and the status of the multiple slave devices is checked sequentially according to the third polling cycle; When an external trigger event is detected, the current working mode is switched to the normal working mode. The data communication modules of the master device and the multiple slave devices are woken up through a hardware wake-up channel independent of the shared data channel and put into normal working state. The multiple slave devices are then polled sequentially according to the second polling cycle.

7. The method according to claim 1, characterized in that, The shared data channel is implemented based on the Universal Asynchronous Receiver / Transmitter (UART) serial port.

8. A multi-node serial communication system, characterized in that, Includes a master device and multiple slave devices; The transmitting end of the master device is connected to the receiving end of each of the slave devices through a first shared line, and the transmitting ends of each of the slave devices are connected to the receiving end of the master device through a second shared line to form a shared data channel without hardware arbitration. The master device and the multiple slave devices are also provided with a hardware wake-up connection line independent of the shared data channel; The master device is configured to perform the multi-node serial communication method as described in any one of claims 1 to 7.

9. An electronic device, characterized in that, The method includes at least one processor and a memory communicatively connected to the at least one processor, the memory storing instructions executable by the at least one processor to enable the at least one processor to perform the method as described in any one of claims 1 to 7.

10. A computer storage medium, characterized in that, The computer storage medium stores instructions or programs that, when executed by at least one processor, cause the at least one processor to perform the method as described in any one of claims 1 to 7.

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