A reliable UDP communication device and method based on FPGA hardware offloading

Abstract

The application provides a reliable UDP communication device and method based on FPGA hardware offloading, relates to the technical field of network communication protocol, and solves the problem that the transmission delay, system resources, integration and other aspects of the existing reliable UDP transmission scheme cannot meet the requirements. The device comprises a FPGA soft core processor, a configuration controller, a dual-port memory and a PL area arranged in a FPGA chip; the configuration controller is connected with the configuration registers of each hardware processing module in the FPGA soft core processor and the PL, and constitutes a configuration path; one end of the dual-port memory is connected with the FPGA soft core processor, and the other end is connected with a sequence number management module and a receiving cache module in the PL, and constitutes a data path; the application separates the control and data, completely avoids the intervention of an external CPU, an operating system and a general bus, realizes single-chip FPGA reliable UDP transmission, effectively reduces resource consumption, improves transmission real-time performance, anti-interference capability and integration.

Description

Technical Field

[0001] This invention relates to the field of network communication protocol technology, and specifically to a reliable UDP communication device and method based on FPGA hardware offloading. Background Technology

[0002] User Datagram Protocol (UDP), as a connectionless transport layer protocol, has become the mainstream choice for low-latency business scenarios such as high-speed data acquisition, real-time audio and video transmission, distributed storage, and remote direct memory access due to its concise header, short transmission path, and lack of connection handshake. However, the standard UDP protocol lacks reliability mechanisms such as message acknowledgment, timeout retransmission, and out-of-order reordering. Under complex conditions such as network congestion, link jitter, or electromagnetic interference, it is prone to packet loss, duplication, or out-of-order delivery, making it difficult to meet the stringent requirements of applications with strict requirements for transmission integrity and determinism, such as industrial control, precision instrument communication, and interconnection of artificial intelligence computing power clusters.

[0003] To improve UDP transmission reliability, existing technologies primarily employ software-enhanced solutions, such as Reliable User Datagram Protocol (RUDP) and Fast User Datagram Protocol (QUIC). These solutions rely on the host CPU and operating system kernel to handle sequence number management, acknowledgment parsing, retransmission scheduling, and buffer control. Under high bandwidth and high concurrency loads, the software processing path leads to frequent context switching and memory copying, resulting in significantly increased CPU resource utilization, exacerbated processing latency jitter, and difficulty in guaranteeing system real-time performance and throughput efficiency, thus limiting their applicability in ultra-low latency scenarios.

[0004] Another technical approach attempts to implement the TCP protocol stack using FPGA hardware to enhance reliability through hardware parallelism. However, the inherent mechanisms of TCP, such as the three-way handshake, congestion control, and sliding window, are complex and consume significant FPGA logic and storage resources. This results in high connection establishment latency and a conservative protocol behavior, making it difficult to meet the demands of lightweight, fast-starting and stopping high-speed transmission. Consequently, it has significant limitations in terms of resource efficiency and response speed.

[0005] Current UDP-related designs in the FPGA field mostly focus on basic transparent transmission functions such as Media Access Control (MAC) layer forwarding and packet header parsing, without deeply embedding the core logic for reliable transmission into the hardware data path. Although some system-on-a-chip (SoC) solutions introduce external CPUs or processing system (PS) hard cores to work in conjunction with programmable logic (PL), data needs to be copied across domains multiple times, configuration interaction relies on complex bus protocols, introducing additional arbitration latency and interface overhead, resulting in low system integration, limited real-time performance, and tight hardware-software coupling, leading to insufficient deployment flexibility.

[0006] Existing technologies for enhancing UDP reliability are constrained by performance bottlenecks and uncertainties in software processing, resource and latency costs due to the complexity of the TCP protocol, or difficulties in balancing system efficiency and integration caused by hardware architecture separation. How to build a hardware-level UDP communication mechanism on a single-chip FPGA platform that requires no external CPU or operating system intervention, has controllable resource overhead, stable transmission latency, and complete reliability assurance capabilities has become a key technological challenge urgently needing breakthroughs in the field of high-speed reliable transmission. Summary of the Invention

[0007] The purpose of this invention is to solve the problems of existing reliable UDP transmission schemes, which suffer from significant transmission latency jitter, excessive system resource consumption, and insufficient overall integration due to reliance on host CPU software processing or the use of complex protocol hardware implementations in the process of improving transmission reliability. These problems make it difficult to simultaneously meet the comprehensive technical requirements of high reliability, deterministic low latency, and compact deployment in high-speed business scenarios.

[0008] This invention proposes a reliable UDP communication device and method based on FPGA hardware offloading. While retaining the core advantages of UDP—connectionless, low-latency, and lightweight—it natively implements ACK confirmation, timeout retransmission, sequence number management, on-chip buffer scheduling, and out-of-order reordering through an FPGA hardware pipelined parallel architecture. This invention replaces the traditional CPU with an FPGA soft core, implements the configuration path through an EMC controller, and implements the data path through dual-port BRAM. Control and data are separated, and the entire process is independent of external CPUs, operating systems, and general-purpose buses, achieving single-chip FPGA-integrated hardware-level reliable UDP transmission. This effectively reduces system resource overhead, improves transmission real-time performance, link anti-interference capability, and integration.

[0009] The present invention employs the following technical solutions to achieve its objective: A reliable UDP communication device based on FPGA hardware offloading includes an FPGA soft core processor, a configuration controller, a dual-port memory, and a programmable logic (PL) area, all housed within a field-programmable gate array (FPGA) chip. The configuration controller connects the FPGA soft core processor to the configuration registers of each hardware processing module in the PL area, forming a configuration path. One end of the dual-port memory is connected to the FPGA soft core processor, and the other end is connected to the serial number management module and the receive buffer module in the PL area, forming a data path. The PL area includes a message processing module, a sequence number management module, an acknowledgment and response module, a timeout retransmission module, a transmit buffer module, a receive buffer module, and a media access control (MAC) module; The message processing module is bidirectionally connected to the MAC module and is used to parse the received network messages and encapsulate the network messages to be sent. The sequence number management module connects the dual-port storage and the transmission buffer module, and is used to generate and associate message sequence identifiers; The acknowledgment and response module connects the message processing module and the timeout retransmission module, and is used to parse the acknowledgment information and generate an acknowledgment and response message; The timeout retransmission module is connected to the send buffer module and is used to monitor the message sending status and trigger retransmission operations. The sending buffer module is connected to the message processing module and is used to store messages to be sent and messages to be acknowledged. The receive buffer module connects the message processing module and the dual-port memory to store received messages and perform reassembly processing. The MAC module is used to implement Ethernet frame transmission and reception and link layer adaptation.

[0010] Specifically, the controller is configured as an external memory controller (EMC). The host-side interface of the EMC controller is connected to the bus interface of the FPGA soft-core processor, and the slave-side interface is connected to the configuration register group of each hardware processing module in the PL area. The configuration register group includes a timeout threshold register, a maximum retransmission count register, a receive window size register, an enable register, and a status flag register, which are used to store the protocol control parameters written by the FPGA soft-core processor.

[0011] Specifically, the dual-port memory is implemented using a dual-port block random access memory (BRAM). The first port of the dual-port memory is connected to the data and control signal lines of the FPGA soft-core processor, and the second port is connected to the data and address bus of the serial number management module and the receive buffer module. Both ports of the dual-port memory are used to support independent clock domain operation, providing asynchronous or synchronous access capabilities, and the access operations of the two ports are isolated from each other.

[0012] Specifically, the message processing module includes a message parsing unit and a message encapsulation unit; The message parsing unit is used to parse Address Resolution Protocol (ARP) messages, Internet Control Message Protocol (ICMP) messages, and User Datagram Protocol (UDP) messages input through the MAC module, and to extract the sequence number field and acknowledgment number field from the custom extended header located after the standard header in the UDP message; The message encapsulation unit is used to construct a message containing a standard UDP header and a custom extended header. The custom extended header includes a sequence number, acknowledgment number, packet length, and packet encoding fields. The total length of the custom extended header ranges from 8 to 16 bytes.

[0013] Specifically, the timeout retransmission module includes a hardware finite state machine and a multi-channel parallel timeout counter array; A hardware finite state machine connects the output of the acknowledgment module to the control of the transmit buffer module, and is used to track the acknowledgment status of each transmitted message; Each counter in the multi-channel parallel timeout counter array corresponds one-to-one with the unacknowledged message entry stored in the transmit buffer module. Its timing threshold is set by the timeout threshold register written by the configuration controller, and a retransmission trigger signal is generated to the transmit buffer module when the timing overflows.

[0014] Specifically, the transmit buffer module constructs a transmit retransmission buffer based on the FPGA on-chip BRAM to store the message data to be transmitted, the associated sequence number, and the buffer address index. It also performs a buffer entry release operation based on the sequence number matching signal output by the acknowledgment module or the retransmission completion signal output by the timeout retransmission module. The receive buffer module is built on the FPGA on-chip BRAM to construct an out-of-order receive buffer area, which is used to store non-contiguous message data by sequence number index. When a continuous sequence number interval is detected, the reassembled data is output to the dual-port memory. At the same time, the buffer entries that have timed out and have not been reassembled are cleaned up according to the internal timer.

[0015] Specifically, the acknowledgment module connects the parsing output of the message processing module and the input of the timeout retransmission module. It is used to match the parsed acknowledgment number with the local sending sequence number and generate an acknowledgment message containing the latest consecutive receiving sequence number maintained by the receiving buffer module. The receive buffer module is equipped with a sequence number sorting logic unit and a buffer status management unit. The sequence number sorting logic unit is used to arrange out-of-order messages according to the preset sequence number order. The buffer status management unit is used to update the receive status and trigger the data write operation to the dual-port memory after a continuous sequence interval is formed.

[0016] This invention also provides a reliable UDP communication method based on the aforementioned communication device, the method comprising the following steps: S1. The FPGA soft core processor writes protocol control parameters to the configuration registers of each hardware processing module in the PL area through the configuration controller, thereby completing the initial configuration of the communication device and isolating the configuration path and data path at the physical and logical levels. S2. The FPGA soft-core processor writes the service data to be sent into the dual-port memory. The sequence number management module reads the service data from the dual-port memory and generates a message sequence identifier. The message processing module encapsulates the message carrying the message sequence identifier and sends it to the network via the MAC module. S3. The timeout retransmission module continuously monitors the acknowledgment status of sent messages. When no acknowledgment information matching the message sequence identifier is detected within the preset timeout threshold, the retransmission operation of the corresponding message in the sending buffer module is triggered. The retransmission operation is executed independently by the hardware logic. S4. The MAC module receives messages from the network side. The message processing module parses the message and extracts the sequence number and acknowledgment number fields. The receive buffer module performs storage and reassembly processing on the message based on the sequence number and writes the reassembly result to the dual-port memory. The acknowledgment response module generates an acknowledgment response message based on the continuous receive sequence number maintained by the receive buffer module and sends it back to the network via the MAC module.

[0017] Specifically, in step S2, when the message processing module encapsulates the message, it appends a custom extension header after the standard UDP header. The custom extension header includes a sequence number field, an acknowledgment number field, a packet length field, and a packet encoding field, and the total length of the custom extension header is set to 8 to 16 bytes. In step S4, when the message processing module parses the received message, it parses the Ethernet frame header, IP header, and standard UDP header in sequence, and extracts the sequence number field and acknowledgment number field from the custom extended header.

[0018] Specifically, in step S3, the timeout retransmission module assigns an independent timeout counter to each sent and pending acknowledgment message. The timing threshold of the timeout counter is determined by the timeout threshold parameter preset in the configuration register. When the timeout overflows and no acknowledgment information matching the message sequence identifier is detected, the timeout retransmission module directly reads the original message data from the sending buffer module and triggers the retransmission operation. The retransmission process terminates when the cumulative number of retransmissions reaches the maximum number of retransmissions set in the configuration register. In step S4, the receiving buffer module stores messages with non-contiguous sequence numbers into the receiving out-of-order buffer area, dynamically sorts the messages in the buffer area according to the sequence number order, and writes the messages in the interval into the dual-port memory in order when a continuous sequence number interval is formed, and releases the buffer space occupied by the written messages in a synchronous manner. At the same time, according to the internal timing mechanism, the buffer cleanup operation is performed on the messages that have timed out and have not completed reassembly.

[0019] In summary, due to the adoption of this technical solution, the beneficial effects of this invention are as follows: This invention achieves a high degree of monolithic integration of communication functions, fully integrating the core processing unit, configuration management, data interaction and reliable transmission logic into a single chip platform, significantly improving the system's structural compactness, environmental adaptability and long-term operational stability, while effectively reducing overall power consumption and sensitivity to external electromagnetic interference.

[0020] In this invention, the configuration path and data path adopt a physically isolated dual-channel architecture to ensure that parameter configuration operations and business data flow are strictly independent at the signal and timing levels, effectively avoiding mutual interference, ensuring that the communication link continues to operate stably under high load conditions and has excellent real-time response characteristics.

[0021] In this invention, the reliable transmission mechanism is executed autonomously by dedicated hardware logic circuits. Key processes such as message acknowledgment, timeout determination, sequence management, and out-of-order reordering are all processed in parallel within the hardware pipeline, completely eliminating the need for external processing resources to participate in protocol calculations. This results in highly deterministic data transmission with minimal latency fluctuations. Furthermore, business data interacts directly between the processing unit and the hardware logic via a dedicated on-chip storage interface, completely eliminating cross-bus transmission, multiple memory copies, and interrupt scheduling. This significantly simplifies the end-to-end transmission path, substantially reduces latency, and improves data flow efficiency.

[0022] While ensuring high-reliability transmission capabilities, this invention fully inherits the lightweight kernel of UDP and significantly optimizes the utilization efficiency of internal chip logic and storage resources through streamlined and efficient hardware logic implementation, reserving ample space for system function expansion and multi-channel concurrent service processing.

[0023] In this invention, the protocol message format is minimally extended within the standard framework. The extended field structure is simple and fully compatible with the parsing logic of existing network devices. Seamless access and collaborative work can be achieved without modifying the existing network topology and infrastructure, greatly reducing deployment complexity and implementation threshold. It is suitable for a variety of critical application scenarios with stringent requirements for reliability, real-time performance and system integration, such as industrial automation, intelligent networking, high-performance computing cluster interconnection, remote memory access and high-speed real-time data acquisition. Attached Figure Description

[0024] The present invention is described in detail with reference to the following figures, which include four figures as follows: Figure 1 This is a detailed hardware architecture example diagram of the reliable UDP communication device of the present invention; Figure 2 This is a schematic diagram of the flow logic of the message parsing state machine in this invention; Figure 3 This is a schematic diagram of the reliable UDP packet format in this invention; Figure 4 This is a schematic diagram of the process logic of the hardware timeout retransmission state machine in this invention. Detailed Implementation

[0025] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0026] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0027] Example 1 A reliable UDP communication device based on FPGA hardware offloading includes an FPGA soft core processor, a configuration controller, a dual-port memory, and a programmable logic (PL) area, all located within a field-programmable gate array (FPGA) chip. The configuration controller connects the FPGA soft core processor to the configuration registers of each hardware processing module in the PL area, forming a configuration path. One end of the dual-port memory is connected to the FPGA soft core processor, and the other end is connected to the serial number management module and the receive buffer module in the PL area, forming a data path.

[0028] In this embodiment, the PL area generally includes a message processing module, a sequence number management module, an acknowledgment module, a timeout retransmission module, a transmit buffer module, a receive buffer module, and a Media Access Control (MAC) module. The functions of each module are as follows: The message processing module is bidirectionally connected to the MAC module and is used to parse the received network messages and encapsulate the network messages to be sent. The sequence number management module connects the dual-port storage and the transmission buffer module, and is used to generate and associate message sequence identifiers; The acknowledgment and response module connects the message processing module and the timeout retransmission module, and is used to parse the acknowledgment information and generate an acknowledgment and response message; The timeout retransmission module is connected to the send buffer module and is used to monitor the message sending status and trigger retransmission operations. The sending buffer module is connected to the message processing module and is used to store messages to be sent and messages to be acknowledged. The receive buffer module connects the message processing module and the dual-port memory to store received messages and perform reassembly processing. The MAC module is used to implement Ethernet frame transmission and reception and link layer adaptation.

[0029] This embodiment will now be described using... Figure 1 The specific device components are illustrated in the example to illustrate the detailed arrangement of the above overview modules and the specific details of each module.

[0030] like Figure 1As shown, the communication device is integrated into a single FPGA chip and can contain a total of 11 specific components: FPGA soft core processor, EMC controller, dual-port BRAM data interaction module, message parsing module, message encapsulation module, serial number management module, ACK detection and reply module, hardware timeout retransmission module, transmit buffer module, receive buffer module and Ethernet MAC module.

[0031] In this embodiment, one end of the EMC controller is connected to the FPGA soft-core processor, and the other end is connected to the configuration registers of each hardware module on the PL side; one end of the dual-port BRAM data interaction module is connected to the FPGA soft-core processor, and the other end is connected to the receive buffer module and the sequence number management module; the message parsing module is interconnected with the receive buffer module; the message encapsulation module is interconnected with the send buffer module; the hardware timeout retransmission module is interconnected with the ACK detection and reply module and the send buffer module respectively; and the Ethernet MAC module is connected to the message parsing module and the message encapsulation module.

[0032] The most critical feature of the device in this embodiment is that the configuration path is formed by the EMC controller, the data path is formed by the dual-port BRAM, and the hardware modules are connected in parallel in a pipeline, realizing an overall architecture with separation of control and data and complete hardware offloading.

[0033] The FPGA soft-core processor is used to run business logic. It completes hardware parameter configuration through the EMC controller and completes business data transmission and reception through dual-port BRAM. It does not participate in reliable UDP protocol processing.

[0034] The EMC controller, also known as the configuration controller mentioned in the overall device overview, serves as the configuration path. It enables the FPGA soft core to perform address-mapped reading and writing of PL terminal registers, and completes parameter configuration and status reading for parameters such as timeout threshold, maximum retransmission count, receive window, working enable, and status flags, thus completely isolating the control path from the data path.

[0035] The dual-port BRAM data interaction module, also known as the dual-port memory mentioned in the overall device overview, serves as a data path. Both ports can be accessed independently asynchronously or synchronously, enabling zero-copy, uninterrupted, and high real-time interaction of business data between the soft core and the PL.

[0036] The message parsing module and the message encapsulation module, as two message-related units, constitute the message processing module mentioned in the overall device overview. The message parsing module is used to parse the received ARP, ICMP, UDP messages, and custom extended headers, extracting the sequence number and acknowledgment number. In this embodiment, as shown... Figure 2As shown, the message parsing state transition process includes idle state, Ethernet frame header judgment state, ARP packet processing state, protocol type judgment state, ICMP packet processing state, and UDP packet processing state. The transitions between each state are based on conditions such as receiving a data packet, type=0x0806, type=0x0800 and MAC address matching, protocol number=0x1 and IP address matching, protocol number=0x11 and IP address matching, and processing completed. All of these transitions are automatically executed by the hardware logic.

[0037] The message encapsulation module is used at the sending end to perform packet encapsulation with standard UDP headers and custom extended fields, ARP message encapsulation, and ICMP message encapsulation. In this embodiment, as shown... Figure 3 As shown, the message encapsulation module constructs a message containing a standard UDP header and a custom extended header. The custom extended header includes sequence number, acknowledgment number, packet length, and packet encoding fields, with a total length ranging from 8 to 16 bytes. This message is compatible with standard UDP protocol devices, requires no modification to the existing network topology, and enables interoperability between heterogeneous devices.

[0038] The sequence number management module assigns a globally unique 32-bit sequence number to each UDP datagram to be sent, which can ensure the uniqueness of the message identifier and avoid message confusion.

[0039] The ACK detection and response module, also known as the acknowledgment and response module mentioned in the overall device overview, parses the acknowledgment information of the received message, matches the sequence number of the sending end, and generates an ACK response message carrying the latest received sequence number at the receiving end, thus completing the transmission loop.

[0040] The timeout retransmission module consists of a hardware finite state machine and a multi-channel parallel timeout counter array, independently monitoring the ACK feedback of each sent message. For messages that have not received an acknowledgment within the timeout period, automatic hardware retransmission is triggered directly, without the need for software core interrupts or operating system intervention. The hardware finite state machine connects the output of the acknowledgment module to the control of the transmit buffer module, tracking the acknowledgment status of each sent message. Each counter in the multi-channel parallel timeout counter array corresponds one-to-one with a message entry to be acknowledged stored in the transmit buffer module. Its timing threshold is set by a timeout threshold register written by the configuration controller, and a retransmission trigger signal is generated to the transmit buffer module when the timeout overflows. This allows it to adapt to scenarios with different link qualities and transmission rates.

[0041] Figure 4 The relevant logic for single-message hardware timeout retransmission state transition is shown, including idle state, waiting to send state, sent and awaiting acknowledgment state, acknowledgment successful state, timeout retransmission state, and sending failure state; the transition between each state is triggered by conditions such as sending, ACK matching, timeout overflow, and exceeding the retransmission limit, all of which are automatically executed by the hardware logic.

[0042] The transmit buffer module is built on the FPGA on-chip BRAM to construct the transmit retransmission buffer; it completes buffer writing, reading, timeout release, and ACK-triggered cleanup through hardware logic, avoiding data copy overhead.

[0043] The receive buffer module is built on the FPGA on-chip BRAM to construct a receive out-of-order reassembly buffer; it completes buffer writing and reading through hardware logic to avoid data copying overhead.

[0044] The Ethernet MAC module enables Ethernet frame transmission and reception, CRC check, link layer timing adaptation, and interfaces with the physical layer PHY chip.

[0045] This embodiment will now introduce a specific application scenario for the device, namely a 1G Ethernet Kintex-7 FPGA soft-core solution. This solution uses a Xilinx Kintex-7 FPGA chip, integrating a MicroBlaze soft-core processor, and interfacing with a 1G Ethernet PHY. The soft core and the PL (Programmable Logic Controller) use an EMC controller as the configuration interface and a dual-port BRAM as the data interface. All hardware modules are developed based on Verilog HDL and interconnected via an AXI-Stream high-speed bus and FIFO.

[0046] In terms of hardware resource configuration, the configuration path is an EMC controller with address mapping to the PL terminal configuration register, supporting 32-bit read and write; the data path is a dual-port BRAM with a depth of 16384 and a bit width of 64 bits, realizing zero-copy data interaction; a parallel timeout counter is also configured, with an independent 32-bit hardware counter for each message, timing in nanoseconds.

[0047] The message format is defined as: standard UDP header (8 bytes) + custom extended header (12 bytes): sequence number (4 bytes) + acknowledgment number (4 bytes) + packet length (2 bytes) + packet encoding (2 bytes), which is compatible with standard UDP parsing logic.

[0048] The soft core is configured via the EMC controller: a maximum of 3 retransmissions, which can be dynamically modified online. Finally, in actual 1G Ethernet transmission tests, despite multiple disconnections and reconnections of the network cable, packets were transmitted correctly, with a reliable transmission rate exceeding 80MB / s, meeting the high reliability requirements for industrial-grade transmission.

[0049] Example 2 Based on Embodiment 1, this embodiment provides a reliable UDP communication method based on FPGA hardware offloading. This method is implemented based on the communication device of Embodiment 1, meaning that the communication device of Embodiment 1 is the hardware foundation of this method. Overall, the method includes the following steps: S1. The FPGA soft core processor writes protocol control parameters to the configuration registers of each hardware processing module in the PL area through the configuration controller, thereby completing the initial configuration of the communication device and isolating the configuration path and data path at the physical and logical levels. S2. The FPGA soft-core processor writes the service data to be sent into the dual-port memory. The sequence number management module reads the service data from the dual-port memory and generates a message sequence identifier. The message processing module encapsulates the message carrying the message sequence identifier and sends it to the network via the MAC module. S3. The timeout retransmission module continuously monitors the acknowledgment status of sent messages. When no acknowledgment information matching the message sequence identifier is detected within the preset timeout threshold, the retransmission operation of the corresponding message in the sending buffer module is triggered. The retransmission operation is executed independently by the hardware logic. S4. The MAC module receives messages from the network side. The message processing module parses the message and extracts the sequence number and acknowledgment number fields. The receive buffer module performs storage and reassembly processing on the message based on the sequence number and writes the reassembly result to the dual-port memory. The acknowledgment response module generates an acknowledgment response message based on the continuous receive sequence number maintained by the receive buffer module and sends it back to the network via the MAC module.

[0050] As a preferred embodiment, in step S2, when the message processing module encapsulates the message, it appends a custom extended header after the standard UDP header. The custom extended header includes a sequence number field, an acknowledgment number field, a packet length field, and a packet encoding field, and the total length of the custom extended header is set to 8 to 16 bytes.

[0051] In step S3 of this embodiment, the timeout retransmission module allocates an independent timeout counter for each sent and pending acknowledgment message. The timing threshold of the timeout counter is determined by the timeout threshold parameter preset in the configuration register. When the timeout overflows and no acknowledgment information matching the message sequence identifier is detected, the timeout retransmission module directly reads the original message data from the sending buffer module and triggers a retransmission operation. The retransmission process terminates when the cumulative number of retransmissions reaches the maximum number of retransmissions set in the configuration register.

[0052] In step S4 of this embodiment, when the message processing module parses the received message, it sequentially parses the Ethernet frame header, IP header, and standard UDP header, and extracts the sequence number field and acknowledgment number field from the custom extended header. Simultaneously, the receive buffer module stores messages with non-contiguous sequence numbers into the out-of-order receive buffer, dynamically sorts the messages in the buffer according to the sequence number order, and when a continuous sequence number interval is formed, writes the messages in that interval into the dual-port memory in order, and simultaneously releases the buffer space occupied by the written messages. At the same time, according to the internal timing mechanism, it performs a buffer cleanup operation on messages that have timed out and have not completed reassembly.

[0053] This embodiment will now describe in detail the method steps, including configuration path initialization, reliable transmission process of the transmitting end hardware, and confirmation and reassembly process of the receiving end hardware, in conjunction with the hardware device.

[0054] First, in the configuration initialization process, the FPGA soft core processor writes parameters to the PL-side configuration register through the EMC controller, including the timeout threshold, maximum number of retransmissions, receive window size, and working enable signal, to complete the reliable UDP hardware module initialization. The configuration process is independent of the data path and does not affect the real-time performance of data transmission.

[0055] The hardware transmission process at the sending end is as follows: (1) The FPGA soft core writes the service data into the dual-port BRAM data interaction module without triggering any protocol processing; (2) The PL-side serial number management module reads data directly from the dual-port BRAM. The serial number management module assigns a globally unique serial number to the message and adds a custom extended header. (3) The message is written into the send retransmission buffer of the send buffer module, and a binding relationship of [sequence number-buffer address-timeout counter] is established; (4) The message encapsulation module adds a standard UDP header to complete reliable UDP message encapsulation; (5) The hardware timeout retransmission module starts the independent timeout counter for the corresponding message, and the Ethernet MAC module sends the message to the link; (6) The ACK detection and reply module listens to the ACK packets returned by the network side in real time, extracts the acknowledgment number and matches it with the sequence number in the sending buffer; if the match is successful, the hardware automatically releases the corresponding buffer and closes the timeout counter; (7) If the timeout counter overflows and no matching ACK is received, the hardware timeout retransmission module directly reads the original message in the buffer and triggers hardware retransmission; if no acknowledgment is received after reaching the maximum number of retransmissions, the hardware marks the transmission as failed and automatically reclaims the buffer resources.

[0056] The hardware confirmation and reassembly process at the receiving end is as follows: (1) The Ethernet MAC module receives the link frame and completes the CRC check, and the message parsing module parses the UDP header and custom extended fields to extract the message sequence number; (2) For ordered messages with consecutive sequence numbers, write them directly into the dual-port BRAM for the soft core to read; for out-of-order messages with non-consecutive sequence numbers, store them in the receive out-of-order buffer and reassemble them in ascending order of sequence number. (3) The reassembled message is written into the dual-port BRAM. The ACK detection and reply module generates an ACK reply message based on the latest continuous reception sequence number and sends it back to the sending end. (4) The receiving cache module periodically cleans up out-of-order messages that have not been reassembled after a timeout and releases the confirmed cache space in a synchronous manner to ensure efficient use of hardware storage resources.

[0057] In this embodiment, all sequence number allocation, timeout judgment, ACK matching, buffer scheduling, message retransmission, and out-of-order reassembly are completed by the FPGA hardware logic parallel pipeline. Only the soft core completes the configuration and data interaction through EMC and dual-port BRAM. There is no external CPU involved and no operating system protocol stack overhead, which is suitable for 1G / 10G / 25G high-speed Ethernet transmission scenarios.

Claims

1. A reliable UDP communication device based on FPGA hardware offloading, characterized in that: The device includes an FPGA soft core processor, a configuration controller, a dual-port memory, and a programmable logic (PL) area, all housed within the FPGA chip. The configuration controller connects the FPGA soft core processor to the configuration registers of each hardware processing module in the PL area, forming a configuration path. One end of the dual-port memory is connected to the FPGA soft core processor, and the other end is connected to the serial number management module and the receive buffer module in the PL area, forming a data path. The PL area includes a message processing module, a sequence number management module, an acknowledgment and response module, a timeout retransmission module, a transmit buffer module, a receive buffer module, and a media access control (MAC) module; The message processing module is bidirectionally connected to the MAC module and is used to parse the received network messages and encapsulate the network messages to be sent. The sequence number management module connects the dual-port storage and the transmission buffer module, and is used to generate and associate message sequence identifiers; The acknowledgment and response module connects the message processing module and the timeout retransmission module, and is used to parse the acknowledgment information and generate an acknowledgment and response message; The timeout retransmission module is connected to the send buffer module and is used to monitor the message sending status and trigger retransmission operations. The sending buffer module is connected to the message processing module and is used to store messages to be sent and messages to be acknowledged. The receive buffer module connects the message processing module and the dual-port memory to store received messages and perform reassembly processing. The MAC module is used to implement Ethernet frame transmission and reception and link layer adaptation.

2. The reliable UDP communication device according to claim 1, characterized in that: The controller is configured as an external memory controller (EMC). The host-side interface of the EMC controller is connected to the bus interface of the FPGA soft-core processor, and the slave-side interface is connected to the configuration register group of each hardware processing module in the PL area. The configuration register group includes a timeout threshold register, a maximum retransmission count register, a receive window size register, an enable register, and a status flag register, which are used to store the protocol control parameters written by the FPGA soft-core processor.

3. The reliable UDP communication device according to claim 1, characterized in that: The dual-port memory is implemented using a dual-port block random access memory (BRAM). The first port of the dual-port memory is connected to the data and control signal lines of the FPGA soft-core processor, and the second port is connected to the data and address bus of the serial number management module and the receive buffer module. Both ports of the dual-port memory are used to support independent clock domain operation, providing asynchronous or synchronous access capabilities, and the access operations of the two ports are isolated from each other.

4. The reliable UDP communication device according to claim 1, characterized in that: The message processing module includes a message parsing unit and a message encapsulation unit; The message parsing unit is used to parse Address Resolution Protocol (ARP) messages, Internet Control Message Protocol (ICMP) messages, and User Datagram Protocol (UDP) messages input through the MAC module, and to extract the sequence number field and acknowledgment number field from the custom extended header located after the standard header in the UDP message; The message encapsulation unit is used to construct a message containing a standard UDP header and a custom extended header. The custom extended header includes a sequence number, acknowledgment number, packet length, and packet encoding fields. The total length of the custom extended header ranges from 8 to 16 bytes.

5. The reliable UDP communication device according to claim 1, characterized in that: The timeout retransmission module includes a hardware finite state machine and a multi-channel parallel timeout counter array; A hardware finite state machine connects the output of the acknowledgment module to the control of the transmit buffer module, and is used to track the acknowledgment status of each transmitted message; Each counter in the multi-channel parallel timeout counter array corresponds one-to-one with the unacknowledged message entry stored in the transmit buffer module. Its timing threshold is set by the timeout threshold register written by the configuration controller, and a retransmission trigger signal is generated to the transmit buffer module when the timing overflows.

6. The reliable UDP communication device according to claim 1, characterized in that: The transmit buffer module constructs a transmit retransmission buffer area based on the FPGA on-chip BRAM. It is used to store the message data to be transmitted, the associated sequence number and the buffer address index. It performs the buffer entry release operation according to the sequence number matching signal output by the acknowledgment module or the retransmission completion signal output by the timeout retransmission module. The receive buffer module is built on the FPGA on-chip BRAM to construct an out-of-order receive buffer area, which is used to store non-contiguous message data by sequence number index. When a continuous sequence number interval is detected, the reassembled data is output to the dual-port memory. At the same time, the buffer entries that have timed out and have not been reassembled are cleaned up according to the internal timer.

7. The reliable UDP communication device according to claim 1, characterized in that: The acknowledgment module connects the parsing output of the message processing module and the input of the timeout retransmission module. It is used to match the parsed acknowledgment number with the local sending sequence number and generate an acknowledgment message containing the latest consecutive receiving sequence number maintained by the receiving buffer module. The receive buffer module is equipped with a sequence number sorting logic unit and a buffer status management unit. The sequence number sorting logic unit is used to arrange out-of-order messages according to the preset sequence number order. The buffer status management unit is used to update the receive status and trigger the data write operation to the dual-port memory after a continuous sequence interval is formed.

8. A reliable UDP communication method for the communication device according to claim 1, characterized in that, The method includes the following steps: S1. The FPGA soft core processor writes protocol control parameters to the configuration registers of each hardware processing module in the PL area through the configuration controller, thereby completing the initial configuration of the communication device and isolating the configuration path and data path at the physical and logical levels. S2. The FPGA soft-core processor writes the service data to be sent into the dual-port memory. The sequence number management module reads the service data from the dual-port memory and generates a message sequence identifier. The message processing module encapsulates the message carrying the message sequence identifier and sends it to the network via the MAC module. S3. The timeout retransmission module continuously monitors the acknowledgment status of sent messages. When no acknowledgment information matching the message sequence identifier is detected within the preset timeout threshold, the retransmission operation of the corresponding message in the sending buffer module is triggered. The retransmission operation is executed independently by the hardware logic. S4. The MAC module receives messages from the network side. The message processing module parses the message and extracts the sequence number and acknowledgment number fields. The receive buffer module performs storage and reassembly processing on the message based on the sequence number and writes the reassembly result to the dual-port memory. The acknowledgment response module generates an acknowledgment response message based on the continuous receive sequence number maintained by the receive buffer module and sends it back to the network via the MAC module.

9. The reliable UDP communication method according to claim 8, characterized in that: In step S2, when the message processing module encapsulates the message, it appends a custom extension header after the standard UDP header. The custom extension header includes a sequence number field, an acknowledgment number field, a packet length field, and a packet encoding field, and the total length of the custom extension header is set to 8 to 16 bytes. In step S4, when the message processing module parses the received message, it parses the Ethernet frame header, IP header, and standard UDP header in sequence, and extracts the sequence number field and acknowledgment number field from the custom extended header.

10. The reliable UDP communication method according to claim 8, characterized in that: In step S3, the timeout retransmission module assigns an independent timeout counter to each sent and pending acknowledgment message. The timing threshold of the timeout counter is determined by the timeout threshold parameter preset in the configuration register. When the timeout overflows and no acknowledgment information matching the message sequence identifier is detected, the timeout retransmission module directly reads the original message data from the sending buffer module and triggers the retransmission operation. The retransmission process terminates when the cumulative number of retransmissions reaches the maximum number of retransmissions set in the configuration register. In step S4, the receiving buffer module stores messages with non-contiguous sequence numbers into the receiving out-of-order buffer area, dynamically sorts the messages in the buffer area according to the sequence number order, and writes the messages in the interval into the dual-port memory in order when a continuous sequence number interval is formed, and releases the buffer space occupied by the written messages in a synchronous manner. At the same time, according to the internal timing mechanism, the buffer cleanup operation is performed on the messages that have timed out and have not completed reassembly.

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