Terminal verification method, system, medium and program product

Abstract

This invention provides a terminal verification method, system, medium, and program product. In this system, a host computer is connected to an edge calculator, a baseband acceleration unit, and a radio frequency (RF) front-end unit. The edge calculator is connected to both the host computer and the baseband acceleration unit, and is used to perform application layer data processing, high-level protocol stack processing, physical layer data processing, AI data processing, and data interaction. The baseband acceleration unit is connected to both the host computer and the edge calculator, and also to the RF front-end unit or an RF chip adapter board, and is used to perform physical layer data processing, data interaction, and system control and management. The RF front-end unit is used for symbol-level data processing, digital front-end processing, digital front-end driving, and data interaction. Thus, through reasonable data transmission and partitioning between the components, the verification requirements for AI computing power, the U6G new frequency band, large bandwidth, multiple channels, and high data throughput of 6G terminals can be met.

Description

Technical Field

[0001] This invention relates to the field of wireless technology, and in particular to a terminal verification method, system, medium, and program product. Background Technology

[0002] 6th generation mobile communication system (6 th The development of 6G (6G) wireless communication system is accelerating. Base station prototypes and UE prototypes are important 6G technology verification platforms and important test networks for building end-to-end 6G new technology verification.

[0003] Currently, the block diagram of an integrated service terminal system based on software-defined radio is as follows: Figure 1 As shown, using a traditional hardware architecture, it achieves certain functions of radio frequency signal transmission and reception and data processing. However, it has drawbacks such as limited data processing interface rate, limited radio frequency signal transmission and reception frequency band, and unsuitability for 6G new technology verification due to the degree of hardware decoupling. Furthermore, it lacks artificial intelligence (AI) computing capabilities and cannot meet the multi-dimensional and multi-element new technology verification requirements of 6G terminals. Summary of the Invention

[0004] The purpose of this invention is to provide a terminal verification method, system, medium, and program product to solve the problem that existing terminal verification systems cannot meet the verification requirements of 6G terminals.

[0005] To achieve the above objectives, in a first aspect, embodiments of the present invention provide a terminal verification system, including: a host computer, an edge calculator, a baseband acceleration unit, a radio frequency front-end unit, a radio frequency board, a power supply system, and a clock system; The host computer is connected to the edge calculator, the baseband acceleration unit, and the radio frequency front-end unit respectively; the host computer is used to monitor and manage the hardware and software status of the edge calculator, the baseband acceleration unit, and the radio frequency front-end unit. The edge calculator is connected to the host computer and the baseband acceleration unit respectively; the edge calculator is used to perform application layer data processing, high-level protocol stack processing, physical layer data processing, AI data processing, and data interaction; The baseband acceleration unit is connected to the host computer and the edge calculator, and is also connected to the RF front-end unit or the RF chip adapter board; the baseband acceleration unit is used to perform physical layer data processing, data interaction and system control management; the RF chip adapter board is used to connect the RF chip to be verified; The radio frequency front-end unit is connected to the host computer and the radio frequency board respectively, and is also connected to the baseband acceleration unit or the baseband chip adapter board; the radio frequency front-end unit is used for symbol-level data processing, digital front-end processing, digital front-end driving and data interaction; the baseband chip adapter board is used to connect to the baseband chip to be verified; The radio frequency board is used to perform radio frequency signal transmission and reception; The power system is used to power the edge calculator, the baseband acceleration unit, the radio frequency front-end unit, and the radio frequency board; The clock system is used to provide clock signals for the baseband acceleration unit, the radio frequency front-end unit, and the radio frequency board.

[0006] In some embodiments, the edge calculator is further configured to load a first software data package to be verified, the first software data package including one or more of the following: software data packages for application layer data processing, software data packages for higher layer protocol stack processing, software data packages for physical layer data processing, and software data packages for AI data processing.

[0007] In some embodiments, the baseband acceleration unit is further configured to load a software data package to be verified for physical layer bit-level data processing.

[0008] In some embodiments, the radio frequency front-end unit is further configured to load a second software data package to be verified, the second software data package including one or more of a software data package for symbol-level data processing, a software data package for digital front-end processing, and a software data package for digital front-end driving.

[0009] In some embodiments, the baseband acceleration unit is a SoC chip with a logic resource capacity greater than a first preset capacity. The programmable logic unit of the SoC chip performs physical layer bit-level data processing and high-speed data interaction; the operating system of the SoC chip performs system control management and some physical layer data processing.

[0010] In some embodiments, the baseband acceleration unit includes a first network port and two high-speed data interfaces, wherein the first network port is connected to the host computer, one high-speed data interface is connected to the radio frequency front-end unit for performing uplink and downlink service data transmission, and the other high-speed data interface is connected to the radio frequency chip to be verified.

[0011] In some embodiments, the radio frequency front-end unit includes a programmable gate array (FPGA) with a capacity greater than a second preset capacity and a radio frequency system-on-a-chip (RFSOC) chip. The FPGA is used to perform interface data interaction and transmit first control commands for the non-real-time requirements of the radio frequency board. The RFSOC chip is used to perform data interaction, symbol-level data processing, digital front-end processing, digital front-end driving, analog-to-digital converter (ADC) / digital-to-analog converter (DAC), and transmit second control commands for the real-time requirements of the radio frequency board.

[0012] In some embodiments, the radio frequency front-end unit further includes two sets of high-speed data interfaces, one set of which is connected to the baseband acceleration unit for performing physical layer bit-level data interaction; the other set of which is connected to the baseband chip to be verified.

[0013] Secondly, embodiments of the present invention also provide a terminal verification method, applied to the terminal verification system described in the first aspect above, the method comprising: When the host computer determines that the target object to be verified is the first object, it transmits the first object to the corresponding first unit; the first unit loads the first object; after determining that the first object has been loaded, the host computer executes communication with the base station through a third control instruction to perform relevant verification; wherein, the first object includes a first software data packet, a software data packet for physical layer bit-level data processing and / or a second software data packet; the first software data includes one or more of the following: a software data packet for application layer data processing, a software data packet for higher-layer protocol stack processing, a software data packet for physical layer data processing, and a software data packet for AI data processing; the second software data packet includes one or more of the following: a software data packet for symbol-level data processing, a software data packet for digital front-end processing, and a software data packet for digital front-end driving; the first unit includes an edge calculator, a baseband acceleration unit and / or a radio frequency front-end unit; When the host computer determines that the target object to be verified is a baseband chip, it controls the radio frequency front-end unit to connect with the baseband chip adapter board, and performs communication with the base station through the fourth control signaling to perform performance-related verification of the baseband chip. When the host computer determines that the target object to be verified is an RF chip, it controls the baseband acceleration unit to connect with the RF chip adapter board and performs communication with the base station through the fifth control signaling to perform performance-related verification of the RF chip.

[0014] Thirdly, embodiments of the present invention also provide a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps in the terminal verification method described in the first aspect above.

[0015] Fourthly, embodiments of the present invention also provide a computer program product, including computer instructions, which, when executed by a processor, implement the steps in the terminal verification method described in the first aspect above.

[0016] The above-described technical solution of the present invention has at least the following beneficial effects: The terminal verification system of this invention includes a host computer, an edge calculator, a baseband acceleration unit, a radio frequency (RF) front-end unit, an RF board, a power supply system, and a clock system. The host computer is connected to the edge calculator, the baseband acceleration unit, and the RF front-end unit. The host computer monitors and manages the hardware and software status of the edge calculator, the baseband acceleration unit, and the RF front-end unit. The edge calculator is connected to both the host computer and the baseband acceleration unit. The edge calculator performs application layer data processing, high-level protocol stack processing, physical layer data processing, AI data processing, and data interaction. The baseband acceleration unit is connected to both the host computer and the edge calculator, and is also connected to the RF front-end unit or an RF chip. The system comprises several components: an adapter board for connecting the baseband acceleration unit (for physical layer data processing, data interaction, and system control and management), an RF chip adapter board for connecting the RF chip to be verified, an RF front-end unit for connecting to the host computer and the RF board, and also for connecting to the baseband acceleration unit or the baseband chip adapter board; a power supply system for powering the edge calculator, baseband acceleration unit, RF front-end unit, and RF board; and a clock system for providing clock signals to the baseband acceleration unit, RF front-end unit, and RF board. Through reasonable data transmission and partitioning among these components, the system enables air interface transmission between the terminal verification system and the base station. This provides the industry with a testing environment and business data channel based on the terminal verification system, facilitating the verification of new 6G services and scenarios, and meeting the verification requirements for AI computing power, U6G new frequency bands, high bandwidth, multiple channels, and high data throughput for 6G terminals. Attached Figure Description

[0017] Figure 1 This represents a block diagram of an existing integrated service terminal system based on software radio. Figure 2 This diagram illustrates the structural block diagram of the terminal verification system provided in an embodiment of the present invention. Figure 3 This is a flowchart illustrating the terminal verification method provided in an embodiment of this application; Figure 4 This diagram illustrates the structure of the software verification system implemented using the terminal verification system provided in this embodiment of the invention. Figure 5This is a schematic diagram of the software verification process provided by the present invention; Figure 6 This diagram illustrates the structure of a baseband chip verification system implemented using the terminal verification system provided in this embodiment of the invention. Figure 7 This diagram illustrates the structure of the radio frequency chip verification system implemented using the terminal verification system provided in this embodiment of the invention. Figure 8 This is a schematic diagram illustrating the process of baseband chip verification and radio frequency chip verification provided by the present invention. Detailed Implementation

[0018] To make the technical problems, technical solutions and advantages of the present invention clearer, a detailed description will be given below in conjunction with the accompanying drawings and specific embodiments.

[0019] This invention addresses the problem that terminal verification systems cannot meet the verification requirements of 6G terminals, and provides a terminal verification method, system, medium, and program product to adapt to the characteristic requirements of 6G communication technology research, including new features of AI computing power, U6G new frequency band, large bandwidth (400MHz / 800MHz), multi-channel (8T8R), and high data throughput. The method and apparatus are based on the same concept in the same application. Since the principles of the method and apparatus in solving the problem are similar, their implementations can be referred to interchangeably, and repeated details will not be elaborated further.

[0020] like Figure 2 The diagram shown is a structural block diagram of a terminal verification system provided in an embodiment of the present invention. The terminal verification system may include: a host computer 201, an edge calculator 202, a baseband acceleration unit 203, a radio frequency front-end unit 204, a radio frequency board 205, a power supply system 206, and a clock system 207.

[0021] The host computer 201 is connected to the edge calculator 202, the baseband acceleration unit 203 and the radio frequency front-end unit 204 respectively; the host computer 201 is used to monitor and manage the hardware and software status of the edge calculator 202, the baseband acceleration unit 203 and the radio frequency front-end unit 204.

[0022] Specifically, the host computer 201 is connected to the edge calculator 202, the baseband acceleration unit 203 and the radio frequency front-end unit 204 via the network port. It interacts with the status monitoring modules of the above units (or components) to realize the main functions such as operation status monitoring and display, mode switching, control command data and software firmware version upgrade.

[0023] The edge calculator 202 is connected to the host computer 201 and the baseband acceleration unit 203 respectively; the edge calculator 202 is used to perform application layer data processing, high-level protocol stack processing, physical layer data processing, AI data processing and data interaction.

[0024] It should be noted that the Edge Calculator 202 has AI computing power and can also be called an AI computing unit.

[0025] Optionally, the Edge Calculator 202 employs an x86 or ARM architecture processor and integrates AI computing power to achieve status monitoring, application layer data processing, high-level protocol stack processing, physical layer data processing, AI data processing, and data interaction functions. These functions support the air interface communication capabilities of the terminal verification system (or platform).

[0026] Optionally, the edge calculator 202 includes a second network port and a high-speed data interface. Optionally, the high-speed data interface is a PCIe Gen4×16 data interface. The second network port communicates in real-time with the host computer 201 to monitor the status and manage the edge calculator 202; the high-speed data interface connects to the data interface of the baseband acceleration unit 203 (optionally, this data interface is a CPM5 interface) for physical layer data interaction.

[0027] The baseband acceleration unit 203 is connected to the host computer 201 and the edge calculator 202, and is also connected to the radio frequency front-end unit 204 or the radio frequency chip adapter board 208. The baseband acceleration unit 203 is used to perform physical layer data processing, data interaction and system control management. The radio frequency chip adapter board 208 is used to connect to the radio frequency chip 209 to be verified.

[0028] In an optional embodiment, the baseband acceleration unit 203 is a system-on-chip (SoC) chip with a logic resource capacity greater than a first preset capacity. The programmable logic unit (PL) of the SoC chip performs physical layer bit-level data processing and high-speed data interaction; the operating system (PS) of the SoC chip performs system control management and some physical layer data processing.

[0029] Here, the SoC chip with a logic resource capacity greater than the first preset capacity can meet the data processing requirements of high bandwidth (400MHz / 800MHz), multiple channels (8T8R), and high data throughput. The PL section of the SoC chip performs physical layer bit-level data processing and data interaction (including high-speed data interaction), and, in conjunction with the CPM5 hard core module (i.e., the data interface of the baseband acceleration unit 203), realizes PCIe GEN4×16 data processing. It should be noted that both the PL and PS sections of the SoC chip provide flexible and configurable API interfaces, facilitating the access and verification of more physical layer software modules.

[0030] The radio frequency front-end unit 204 is connected to the host computer 201 and the radio frequency board 205 respectively, and is also connected to the baseband acceleration unit 203 or the baseband chip adapter board 210; the radio frequency front-end unit 204 is used for symbol-level data processing, digital front-end processing, digital front-end driving and data interaction; the baseband chip adapter board 210 is used to connect to the baseband chip 211 to be verified.

[0031] In an optional embodiment, the radio frequency front-end unit 204 includes a field programmable gate array (FPGA) with a capacity greater than a second preset capacity and a radio frequency system on chip (RFSOC) chip. The FPGA is used to perform interface data interaction and transmit first control commands for the non-real-time requirements of the radio frequency board 205. The RFSOC chip is used to perform data interaction, symbol-level data processing, digital front-end processing, digital front-end driving, analog-to-digital converter (ADC) / digital-to-analog converter (DAC), and transmit second control commands for the real-time requirements of the radio frequency board 205.

[0032] It should be noted that the digital front-end (DFE) processing functions mainly include various filtering functions (implemented through filters), digital pre-distortion (DPD), crest factor reduction (CFR), and other functions to improve signal transmission performance.

[0033] Specifically, the PL section of the RFSOC chip transmits control signals to the RF board 205 that require real-time processing. The PS section of the RFSOC chip implements the operation and status management module of the digital front-end (DFE) driver. The DFE driver configures the DFE module parameters of the PL section according to the real-time status of the signal. The status management module realizes bidirectional data interaction with the host computer 201 through the network port, thereby realizing the function of status monitoring and control.

[0034] Both the PL and PS sections of the FPGA and RFSOC chips provide flexible and configurable API interfaces, facilitating the access and verification of more physical layer software modules, DFE modules, and other software.

[0035] Here, since the RFSOC chip can implement ADC / DAC functions, optionally, the RFSOC chip also includes 8 ADC channels, 8 DAC channels, and 2 ADC feedback channels. The sampling rate of the 8 ADC channels is 2.4576 GSPS, the sampling rate of the 8 DAC channels is 9.8304 GSPS, and the sampling rate of the 2 ADC feedback channels is 4.9152 GSPS. By selecting appropriate digitally controlled oscillator (NCO) frequency and Nyquist domain, distortion-free and complete acquisition of transmitted and received signals is ensured, improving the overall performance of the terminal verification system.

[0036] To meet the new characteristics of the U6G frequency band and to take into account the need for miniaturization, the RF section of the RFSOC chip uses direct RF sampling of the U6G frequency band signal to improve the stability and consistency of the link.

[0037] The RF board 205 is used to perform RF signal transmission and reception. It should be noted that the RF board 205 mainly implements the functions of amplification, filtering, and analog signal conversion for the 8T8R RF signal transmission and reception link. Specifically, the signal transmission process involves receiving the RF signal transmitted by the DAC channel of the RF front-end unit 204, filtering, amplifying, and switching it via electronic switches, and then connecting it to an external antenna to achieve signal forwarding. It also provides two feedback coupling paths to facilitate signal power detection by the RF front-end unit, enabling DPD functionality. The signal reception process involves receiving the air interface signal from the external antenna, passing it through analog devices such as electronic switches, a low-noise amplifier (LNA), and filters, and then transmitting the signal to the RF front-end unit 204 for subsequent analog-to-digital converter (ADC) processing.

[0038] The power system 206 is used to supply power to the edge calculator 202, the baseband acceleration unit 203, the radio frequency front-end unit 204 and the radio frequency board 205.

[0039] It should be noted that the power supply system 206 provides a reliable and stable power signal for the terminal verification system. It mainly includes a DC-AC to AC-DC conversion module and a DC-DC to DC-DC conversion module. The AC-DC conversion module converts 220V to 48V to power the RF board 205 and the RF front-end unit 204. At the same time, to improve the electromagnetic interference (EMI) characteristics of the terminal, the AC-DC conversion module is connected in series with an EMI filter. The DC-DC conversion module converts 48V to 12V to power the baseband acceleration unit 203 and the edge calculator 202.

[0040] The clock system 207 is used to provide clock signals for the baseband acceleration unit 203, the radio frequency front-end unit 204 and the radio frequency board 205.

[0041] It should be noted that the clock system 207 provides a reliable and stable clock signal for the terminal verification system. The external access can be the pulse per second (PPS) signal output by the Global Navigation Satellite System (GNSS) receiver module or the internal oven-controlled crystal oscillator (OCXO) signal. It provides a 100M reference clock to the internal RF front-end unit 204, a 100M reference clock to the RF board 205, and a 10M reference clock to the baseband acceleration unit 203.

[0042] The terminal verification system of this invention includes a host computer, an edge calculator, a baseband acceleration unit, a radio frequency (RF) front-end unit, an RF board, a power supply system, and a clock system. The host computer is connected to the edge calculator, the baseband acceleration unit, and the RF front-end unit. The host computer monitors and manages the hardware and software status of the edge calculator, the baseband acceleration unit, and the RF front-end unit. The edge calculator is connected to both the host computer and the baseband acceleration unit. The edge calculator performs application layer data processing, high-level protocol stack processing, physical layer data processing, AI data processing, and data interaction. The baseband acceleration unit is connected to both the host computer and the edge calculator, and is also connected to the RF front-end unit or an RF chip. The system comprises several components: an adapter board for connecting the baseband acceleration unit (for physical layer data processing, data interaction, and system control and management), an RF chip adapter board for connecting the RF chip to be verified, an RF front-end unit for connecting to the host computer and the RF board, and also for connecting to the baseband acceleration unit or the baseband chip adapter board; a power supply system for powering the edge calculator, baseband acceleration unit, RF front-end unit, and RF board; and a clock system for providing clock signals to the baseband acceleration unit, RF front-end unit, and RF board. Through reasonable data transmission and partitioning among these components, the system enables air interface transmission between the terminal verification system and the base station. This provides the industry with a testing environment and business data channel based on the terminal verification system, facilitating the verification of new 6G services and scenarios, and meeting the verification requirements for AI computing power, U6G new frequency bands, high bandwidth, multiple channels, and high data throughput for 6G terminals.

[0043] In some embodiments, the edge calculator 202 is further configured to load a first software data package to be verified, the first software data package including one or more of the following: software data package for application layer data processing, software data package for higher layer protocol stack processing, software data package for physical layer data processing, and software data package for AI data processing.

[0044] Specifically, the edge calculator 202 may include a status monitoring module, an application layer data processing module, a high-level protocol stack processing module, a physical layer data processing module, an AI data processing module, and a data interaction module. Each module defines an accessible Application Programming Interface (API) to support the verification of software data packets for application layer data processing, high-level protocol stack processing, physical layer data processing, and AI data processing, thereby further enhancing the engineering verification capabilities of 6G new features.

[0045] In some embodiments, the baseband acceleration unit 203 is further configured to load a software data package to be verified for physical layer bit-level data processing.

[0046] It should be noted that the baseband acceleration unit 203 defines an accessible API interface, through which the software data packets to be verified for physical layer bit-level data processing are accessed, thereby realizing link communication and software function verification.

[0047] Optionally, the baseband acceleration unit 203 includes a first network port and two high-speed data interfaces. The first network port is connected to the host computer 201, one high-speed data interface is connected to the radio frequency front-end unit 204 for performing uplink and downlink service data transmission, and the other high-speed data interface is connected to the radio frequency chip 209 to be verified.

[0048] Optionally, the two high-speed data interfaces are two QSFPDD 200Gbps data interfaces. One QSFPDD 200Gbps data interface is directly connected to the RF front-end unit 204 for uplink and downlink service data transmission; the other QSFPDD 200Gbps data interface is a reserved interface for connecting to the RF chip 209 to be verified.

[0049] It should be noted that the baseband acceleration unit 203 reserves two high-speed data interfaces of QSFPDD 200Gbps, one of which supports connection to the high-speed interface of the adapter board 208 of the RF chip to be verified 209, forming a complete transmission link to meet the verification requirements of the RF chip.

[0050] In some embodiments, the radio frequency front-end unit 204 is further configured to load a second software data package to be verified, the second software data package including one or more of a software data package for symbol-level data processing, a software data package for digital front-end processing, and a software data package for digital front-end driving.

[0051] Optionally, the RFSOC chip of the RF front-end unit 204 defines an accessible API interface, through which one or more of the software data packets to be verified, such as those for symbol-level data processing, digital front-end processing, and digital front-end driving, can be accessed to achieve link communication and software function verification.

[0052] In some embodiments, the radio frequency front-end unit 204 further includes two sets of high-speed data interfaces, one set of which is connected to the baseband acceleration unit 203 for performing physical layer bit-level data interaction; the other set of which is connected to the baseband chip 211 to be verified.

[0053] Optionally, the FPGA of the RF front-end unit 204 includes two sets of high-speed data interfaces. These two sets of high-speed data interfaces are two sets of 2×100Gbps QSFP28 fiber optic data interfaces. One set of 2×100Gbps QSFP28 fiber optic data interfaces is directly connected to the baseband acceleration unit 203 for physical layer bit-level data interaction. The other set of 2×100Gbps QSFP28 fiber optic data interfaces is a reserved interface for connecting to the high-speed data interface of the adapter board 210 of the baseband chip 211 to be verified, thus realizing the baseband chip verification function. Internally, the FPGA includes two 100Gbps high-speed data interaction interfaces to realize bidirectional transmission and reception of service data with the RFSOC chip.

[0054] like Figure 3 The diagram shown is a flowchart illustrating the terminal verification method provided in this embodiment. This method is applied to the methods described above. Figure 2 The terminal verification system shown. The method may include: Step 301: When the host computer determines that the target object to be verified is the first object, it transmits the first object to the corresponding first unit; the first unit loads the first object; after determining that the first object has been loaded, the host computer executes communication with the base station through a third control instruction to perform relevant verification; wherein, the first object includes a first software data packet, a software data packet for physical layer bit-level data processing, and / or a second software data packet; the first software data includes one or more of the following: a software data packet for application layer data processing, a software data packet for higher-layer protocol stack processing, a software data packet for physical layer data processing, and a software data packet for AI data processing; the second software data packet includes one or more of the following: a software data packet for symbol-level data processing, a software data packet for digital front-end processing, and a software data packet for digital front-end driving; the first unit includes an edge calculator, a baseband acceleration unit, and / or a radio frequency front-end unit; Step 302: When the host computer determines that the target object to be verified is a baseband chip, it controls the radio frequency front-end unit to connect with the baseband chip adapter board, and performs communication with the base station through the fourth control signaling to perform performance-related verification of the baseband chip. Step 303: When the host computer determines that the target object to be verified is an RF chip, it controls the baseband acceleration unit to connect with the RF chip adapter board and performs communication with the base station through the fifth control signaling to perform performance-related verification of the RF chip.

[0055] The terminal verification method of the present invention can support the verification of one or more of the following: software data packets for application layer data processing, software data packets for high-level protocol stack processing, software data packets for physical layer data processing, software data packets for AI data processing, software data packets for physical layer bit-level data processing, software data packets for symbol-level data processing, software data packets for digital front-end processing, and software data packets for digital front-end driving. It also supports the verification of terminal baseband chips and / or radio frequency chips, thus meeting the multi-dimensional and multi-element new technology verification requirements of 6G terminals.

[0056] This invention, while implementing the basic functions of the terminal, also provides verification requirements for one or more of the following: software data packets for high-level protocol stack processing, software data packets for physical layer data processing, software data packets for AI data processing, software data packets for physical layer bit-level data processing, software data packets for symbol-level data processing, software data packets for digital front-end processing, and software data packets for digital front-end driving. A block diagram is shown below. Figure 4 As shown.

[0057] In one example, based on software verification requirements, the design scheme of this invention is as follows: The edge calculator 202 adopts a general-purpose x86 or ARM architecture processor. The processor's software function modules adopt a modular design, and the data exchange module uses a flexibly accessible API interface, facilitating the access of the software modules to be verified (application data processing module, high-level protocol stack processing module, physical layer data processing module, AI data processing module, etc.). Here, the software module is also known as the software data packet. The baseband acceleration unit 203 adopts a flexible programmable adaptive SOC chip, providing a flexibly accessible API interface, allowing the software modules to be verified (application data processing module, high-level protocol stack processing module, physical layer data processing module, AI data processing module, etc.) to access the data exchange module. The physical layer bit-level data processing module (e.g., DFE) is placed in the programmable logic (PL) section and ultimately combined with other software modules in the baseband acceleration unit 203 into a single bit file package to enable the access of the software module to be verified. The radio frequency front-end unit 204 employs a flexible programmable FPGA and RFSOC chip. The physical layer symbol-level processing module and DFE algorithm module to be verified are placed in the PL section and combined with other software modules in the RF front-end unit 204 into a single bit file package. The PS section of the RFSOC chip runs the corresponding DFE driver to be verified, enabling the access of the software module to be verified. Based on this design and combined with the collaborative work of other hardware and software modules in the terminal verification system, the simultaneous verification of one or more software modules can be achieved.

[0058] like Figure 5 As shown below, the implementation process of step 301 will be explained in detail.

[0059] Step 3011: The host computer determines the type of the software data packet to be verified, and transmits it to the corresponding component through the network port according to the different types. Step 3012: The edge calculator loads the received first software data packets to be verified: software data packets for application layer data processing, software data packets for higher layer protocol stack processing, software data packets for physical layer data processing, and software data packets for AI data processing. Step 3013: The baseband acceleration unit loads the received software data packet for physical layer bit-level data processing to be verified. Step 3014: The RF front-end unit loads the received second software data package to be verified: software data package for symbol-level data processing, software data package for digital front-end processing, and software data package for digital front-end driving; It should be noted that the edge calculator / baseband acceleration unit / RF front-end unit will load the received software data packets to be verified into the corresponding main processing chip. If there are other software modules to be verified, the corresponding components will also load them into the corresponding software modules (i.e., software data packets).

[0060] Step 3015: Determine whether the software data package has been fully loaded; If yes, proceed to step 3016; otherwise, continue with step 3015.

[0061] Step 3016: Access the terminal verification system via the API interface; That is, after the software data package is loaded, the software data package to be verified is connected to the terminal verification system through the API interface.

[0062] Step 3017: The terminal verification system communicates with the base station based on the new software and hardware modules to perform relevant verifications; Step 3018: Determine whether the verification is complete; If yes, proceed to step 3019; otherwise, continue with step 3018.

[0063] Step 3019: The terminal verification system automatically restores its basic functions.

[0064] In other words, after verification is completed, the terminal verification system automatically reloads the free software modules and restores their basic functions.

[0065] This invention, while implementing the basic functions of the terminal, also provides chip verification for the terminal baseband chip or RF chip. In one example, based on the terminal baseband chip verification requirements, the design scheme of this invention is as follows: the RF front-end unit 204 reserves two sets of 2×100Gbps QSFP28 baseband data interaction interfaces, one of which is directly connected to the baseband acceleration unit 203 for baseband data interaction, and the other is used to connect to the baseband chip adapter board 210. The baseband data interaction interface is switched through the mode switching command of the host computer 201, such as... Figure 6 As shown. The baseband acceleration unit 203 reserves two QSFPDD 200Gbps interfaces for external baseband data interaction. One interface is directly connected to the RF front-end unit 204 for baseband data interaction, and the other is used to connect to the RF chip adapter board 208. The baseband data interaction interface is switched via mode switching commands from the host computer 201, such as... Figure 7 As shown in the diagram. Based on the above design and in conjunction with the collaborative work of other hardware and software modules of the terminal verification system, the verification of baseband chips and / or radio frequency chips can be achieved simultaneously.

[0066] like Figure 8 As shown below, the implementation process of steps 302 and 303 will be explained in detail.

[0067] S1. The host computer determines whether the current mode is baseband chip verification mode or radio frequency chip verification mode; If it is a baseband chip verification mode, then proceed to step S2; if it is an RF chip verification mode, then proceed to step S6.

[0068] S2. The terminal verification system retains software modules such as the RF front-end unit and RF board, while the RF front-end unit is switched to a 200Gbps interactive interface with the baseband chip adapter board.

[0069] S3. The terminal communicates with the base station to perform baseband chip performance verification. S4. Determine whether the verification is complete; If yes, proceed to step S5; otherwise, continue with step S4.

[0070] S5. The terminal verification system switches to normal working mode. Here, the normal working mode means that the terminal verification system implements the basic functions of the terminal and / or the software verification function.

[0071] S6 The terminal verification system retains software modules such as the edge calculator and baseband acceleration unit, while the baseband acceleration unit is switched to a 200Gbps interactive interface with the radio frequency chip adapter board.

[0072] S7. The terminal communicates with the base station to perform performance verification related to the radio frequency chip. S8. Determine whether the verification is complete; If yes, proceed to step S5; otherwise, continue to step S8.

[0073] This invention also provides a computer-readable storage medium storing a computer program. When executed by a processor, this program implements the various processes described in the terminal verification method embodiments above, achieving the same technical effects. To avoid repetition, it will not be described again here. The computer-readable storage medium may be a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, etc.

[0074] This invention also provides a computer program product, including computer instructions, which, when executed by a processor, implement the above-described functionality. Figure 3 The steps in the terminal verification method shown.

[0075] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-readable storage media (including, but not limited to, disk storage and optical storage) containing computer-usable program code.

[0076] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 A device for one or more processes and / or the functions specified in one or more boxes.

[0077] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce a paper article including an instruction means, the instruction means being implemented in a process Figure 1 One or more processes and / or boxes Figure 1The function specified in one or more boxes.

[0078] These computer program instructions can also be loaded onto a computer or other programmable data processing equipment, causing the computer or other programmable equipment to perform a series of operational steps to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0079] The above description represents the preferred embodiments of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A terminal verification system, characterized in that, include: Host computer, edge calculator, baseband acceleration unit, RF front-end unit, RF board, power supply system and clock system; The host computer is connected to the edge calculator, the baseband acceleration unit, and the radio frequency front-end unit respectively; the host computer is used to monitor and manage the hardware and software status of the edge calculator, the baseband acceleration unit, and the radio frequency front-end unit. The edge calculator is connected to the host computer and the baseband acceleration unit respectively; the edge calculator is used to perform application layer data processing, high-level protocol stack processing, physical layer data processing, AI data processing, and data interaction; The baseband acceleration unit is connected to the host computer and the edge calculator, and is also connected to the RF front-end unit or the RF chip adapter board; the baseband acceleration unit is used to perform physical layer data processing, data interaction and system control management; the RF chip adapter board is used to connect the RF chip to be verified; The radio frequency front-end unit is connected to the host computer and the radio frequency board respectively, and is also connected to the baseband acceleration unit or the baseband chip adapter board; the radio frequency front-end unit is used for symbol-level data processing, digital front-end processing, digital front-end driving and data interaction; the baseband chip adapter board is used to connect to the baseband chip to be verified; The radio frequency board is used to perform radio frequency signal transmission and reception; The power system is used to power the edge calculator, the baseband acceleration unit, the radio frequency front-end unit, and the radio frequency board; The clock system is used to provide clock signals for the baseband acceleration unit, the radio frequency front-end unit, and the radio frequency board.

2. The terminal verification system according to claim 1, characterized in that, The edge calculator is also used to load a first software data package to be verified, the first software data package including one or more of the following: software data package for application layer data processing, software data package for higher layer protocol stack processing, software data package for physical layer data processing, and software data package for AI data processing.

3. The terminal verification system according to claim 1, characterized in that, The baseband acceleration unit is also used to load software data packets for physical layer bit-level data processing to be verified.

4. The terminal verification system according to claim 1, characterized in that, The radio frequency front-end unit is also used to load a second software data package to be verified, the second software data package including one or more of the following: a software data package for symbol-level data processing, a software data package for digital front-end processing, and a software data package for digital front-end driving.

5. The terminal verification system according to claim 1, characterized in that, The baseband acceleration unit is a SoC chip with a logic resource capacity greater than a first preset capacity. The programmable logic unit of the SoC chip performs physical layer bit-level data processing and high-speed data interaction; the operating system of the SoC chip performs system control management and some physical layer data processing.

6. The terminal verification system according to claim 1, characterized in that, The baseband acceleration unit includes a first network port and two high-speed data interfaces. The first network port is connected to the host computer, one high-speed data interface is connected to the radio frequency front-end unit for performing uplink and downlink service data transmission, and the other high-speed data interface is connected to the radio frequency chip to be verified.

7. The terminal verification system according to claim 1, characterized in that, The radio frequency front-end unit includes a programmable gate array (FPGA) with a capacity greater than a second preset capacity and a radio frequency system-on-a-chip (RFSOC) chip. The FPGA is used to perform interface data interaction and transmit first control commands for the non-real-time requirements of the radio frequency board. The RFSOC chip is used to perform data interaction, symbol-level data processing, digital front-end processing, digital front-end driving, analog-to-digital converter (ADC) / digital-to-analog converter (DAC), and transmit second control commands for the real-time requirements of the radio frequency board.

8. The terminal verification system according to claim 1, characterized in that, The radio frequency front-end unit also includes two sets of high-speed data interfaces. One set of high-speed data interfaces is connected to the baseband acceleration unit and is used to perform physical layer bit-level data interaction. The other set of high-speed data interfaces is connected to the baseband chip to be verified.

9. A terminal verification method, characterized in that, Applied to the terminal verification system as described in any one of claims 1 to 8, the method comprises: When the host computer determines that the target object to be verified is the first object, it transmits the first object to the corresponding first unit; the first unit loads the first object; after determining that the first object has been loaded, the host computer executes communication with the base station through a third control instruction to perform relevant verification; wherein, the first object includes a first software data packet, a software data packet for physical layer bit-level data processing and / or a second software data packet; the first software data includes one or more of the following: a software data packet for application layer data processing, a software data packet for higher-layer protocol stack processing, a software data packet for physical layer data processing, and a software data packet for AI data processing; the second software data packet includes one or more of the following: a software data packet for symbol-level data processing, a software data packet for digital front-end processing, and a software data packet for digital front-end driving; the first unit includes an edge calculator, a baseband acceleration unit and / or a radio frequency front-end unit; When the host computer determines that the target object to be verified is a baseband chip, it controls the radio frequency front-end unit to connect with the baseband chip adapter board, and performs communication with the base station through the fourth control signaling to perform performance-related verification of the baseband chip. When the host computer determines that the target object to be verified is an RF chip, it controls the baseband acceleration unit to connect with the RF chip adapter board and performs communication with the base station through the fifth control signaling to perform performance-related verification of the RF chip.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the program is executed by the processor, it implements the steps in the terminal verification method as described in claim 9.

11. A computer program product, characterized in that, It includes computer instructions that, when executed by a processor, implement the steps in the terminal verification method as described in claim 9.

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