A process for precise bonding of multilayer stacked positioning integrated circuit boards

Abstract

This invention discloses a precise bonding fabrication process for a multilayer stacked integrated circuit board, comprising substrate pretreatment, three-level positioning and alignment, progressive gradient pressure bonding, layer stress release, and repeated stacking steps. This process achieves layer-by-layer alignment sequentially through mechanical coarse positioning, optical fine positioning, and electrical nano-calibration. Bonding is performed using a zoned, graded, and staged pressure application method. Each layer undergoes gradient annealing after bonding, and quality inspection and cumulative error compensation are performed during the stacking process. This invention improves the alignment accuracy and bonding quality of multilayer stacking, effectively suppresses stress accumulation and error amplification effects, and results in high reliability of the multilayer integrated circuit board stack structure.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit packaging technology, and more specifically to a process for precise bonding of multilayer stacked integrated circuit boards. Background Technology

[0002] With the continuous development of integrated circuit technology, chip integration density is constantly increasing. The wiring density within a single chip plane is gradually approaching the physical limit, making three-dimensional stacking integration an important technical approach to improve system integration and performance. Multilayer integrated circuit board stacking can expand the integration space in the vertical direction, significantly shorten the interconnect length, reduce signal transmission delay, improve system operating speed, and at the same time reduce the overall package size, achieving higher functional density.

[0003] Existing multilayer stacking bonding processes still have many shortcomings in practical applications. Traditional single-layer positioning methods cannot simultaneously meet the requirements of alignment speed and accuracy. Mechanical positioning accuracy is limited, and purely optical positioning is susceptible to environmental interference and cannot verify the actual electrical connection status. The one-time pressure application method during bonding can easily lead to problems such as residual bubbles at the interface and uneven pressure distribution, affecting bonding quality. During multilayer stacking, internal stress accumulates continuously with the number of layers, which can easily cause substrate warping and deformation, and even lead to interface cracking and structural failure. In addition, the cumulative effect of errors during the stacking process means that the more layers there are, the greater the alignment deviation, which severely limits the further increase in the number of stacked layers. At the same time, there is a lack of effective process quality monitoring methods, making it difficult to detect defects in the early stages, resulting in a low overall yield. Summary of the Invention

[0004] The purpose of this invention is to provide a precise bonding process for multilayer stacked integrated circuit boards to solve the technical problems of substrate warping and large alignment deviations caused by existing multilayer stacking.

[0005] To achieve the above objectives, the present invention provides the following technical solution:

[0006] A process for precisely bonding and fabricating a multilayer stacked integrated circuit board includes the following steps:

[0007] The substrate pretreatment step involves preparing a positioning mark array and bonding interface on the surface of each integrated circuit board layer;

[0008] The three-stage positioning and alignment process sequentially achieves the alignment of adjacent integrated circuit boards through mechanical coarse positioning, optical fine positioning, and electrical nano-calibration.

[0009] The progressive gradient pressure bonding process employs a zoned, graded, and phased pressure application method for pre-bonding and formal bonding.

[0010] The layered stress relief process involves gradient annealing after each layer is bonded.

[0011] Repeat the stacking steps until all layers are stacked.

[0012] As a preferred embodiment of the present invention, the substrate pretreatment step specifically includes:

[0013] Cross-shaped optical positioning marks are prepared in the four corner areas of the integrated circuit board. The line width of the marks ranges from 5 micrometers to 20 micrometers, and the size of the marks ranges from 50 micrometers to 200 micrometers.

[0014] A grating-type nanocalibration mark is fabricated in the central region of an integrated circuit board, with a grating period ranging from 200 nanometers to 800 nanometers;

[0015] A dielectric layer and a metal bonding pad are prepared at the bonding interface, with the thickness of the dielectric layer ranging from 100 nm to 500 nm and the thickness of the metal bonding pad ranging from 50 nm to 300 nm.

[0016] The bonding interface is activated by plasma, with a power range of 100 watts to 500 watts and a processing time range of 10 seconds to 60 seconds.

[0017] As a preferred embodiment of the present invention, the mechanical coarse positioning in the three-level positioning and alignment step specifically includes:

[0018] Precision mechanical positioning pins are used in conjunction with positioning holes. The diameter of the positioning pins ranges from 1 mm to 5 mm, and the gap between the positioning holes and the positioning pins ranges from 1 micrometer to 5 micrometers.

[0019] By identifying the reference marks on the corners of the integrated circuit board using a vision system, preliminary alignment in the X and Y axes can be achieved with an alignment accuracy range of 5 micrometers to 20 micrometers.

[0020] Perform θ angle rotation correction, with a rotation adjustment range of ±0.5 degrees and an adjustment accuracy range of 0.01 degrees to 0.1 degrees.

[0021] As a preferred embodiment of the present invention, the optical precision positioning in the three-level positioning and alignment step specifically includes:

[0022] A high-resolution microscopic vision system was used to identify cross-shaped optical positioning marks, with a magnification range of 100x to 1000x.

[0023] The deviation between the upper and lower layer marks is calculated. The deviation compensation range in the X and Y axis directions is ±50 micrometers, and the compensation accuracy range is 50 nanometers to 200 nanometers.

[0024] A subpixel image matching algorithm is used to calculate the deviation, and the image matching accuracy ranges from 0.01 pixels to 0.1 pixels.

[0025] As a preferred embodiment of the present invention, the electrical nanocalibration in the three-level positioning and alignment step specifically includes:

[0026] Alignment verification was performed by testing the contact resistance of the upper and lower metal bonding pads, with a contact resistance threshold range of 1 milliohm to 10 milliohms.

[0027] When the contact resistance exceeds the threshold, nanometer-level position fine-tuning is performed, with a fine-tuning step size ranging from 10 nanometers to 50 nanometers.

[0028] The overall alignment deviation is calculated by analyzing the resistance distribution in the four corner regions, and global position optimization is performed.

[0029] As a preferred embodiment of the present invention, the progressive gradient pressure bonding step specifically includes:

[0030] During the pre-bonding stage, the first pressure is applied in the range of 0.1 MPa to 0.5 MPa, and the holding time is in the range of 10 seconds to 60 seconds;

[0031] During the zoned pressurization phase, the pressure is gradually increased from the central area to the peripheral area, with the pressure range in the central area being 0.5 MPa to 2 MPa and the pressure range in the peripheral area being 1 MPa to 3 MPa.

[0032] During the formal bonding stage, a uniform pressure ranging from 2 MPa to 10 MPa is applied, while a heating process is carried out at a temperature ranging from 150 degrees Celsius to 400 degrees Celsius.

[0033] As a further preferred embodiment of the present invention, real-time closed-loop control is adopted in the formal bonding stage:

[0034] Pressure sensors are used to monitor the pressure distribution in each area in real time, and the pressure uniformity is controlled at over 95%.

[0035] The temperature distribution is monitored in real time by an infrared temperature measurement system, and the temperature uniformity is controlled within ±5 degrees Celsius.

[0036] By observing the bonding interface in real time through an in-situ optical monitoring system, interface bubbles can be detected and eliminated in a timely manner.

[0037] As a preferred embodiment of the present invention, the layered stress relief step specifically includes:

[0038] After bonding is completed, the temperature is reduced at a first cooling rate ranging from 5 degrees Celsius to 20 degrees Celsius per minute to an intermediate temperature range of 100 degrees Celsius to 200 degrees Celsius.

[0039] Stress relaxation treatment is performed by holding the material at an intermediate temperature for 30 to 120 minutes.

[0040] Then, cool down to room temperature at a second cooling rate ranging from 1 degree Celsius to 5 degrees Celsius per minute;

[0041] After each layer is stacked, warpage is tested, and the warpage is controlled within the range of 1 micrometer to 5 micrometers per centimeter.

[0042] As a preferred embodiment of the present invention, a real-time quality detection step during the stacking process is also included:

[0043] After each layer is bonded, an acoustic scanning microscope is used to inspect the interface defects, which are larger than 1 micrometer.

[0044] X-ray tomography was performed to verify the alignment accuracy between layers.

[0045] Perform electrical performance tests, including continuity resistance, insulation resistance, and signal integrity tests.

[0046] In a preferred embodiment of the present invention, during the repeated stacking step, a surface flattening process is performed after each layer is stacked:

[0047] The surface is smoothed by chemical mechanical polishing, and the surface roughness after polishing ranges from 0.1 nanometers to 1 nanometer.

[0048] Prepare the bonding interface and positioning marks for the next layer, ensuring that the coordinate system of the positioning marks in each layer is consistent;

[0049] Cumulative error compensation adjusts the positioning parameters of subsequent layers based on the actual alignment deviations of the previous layers.

[0050] As a preferred embodiment of the present invention, the number of stacked layers of the integrated circuit board ranges from 2 to 32, the thickness of a single integrated circuit board ranges from 50 micrometers to 300 micrometers, and the overall stacked thickness ranges from 100 micrometers to 5000 micrometers.

[0051] As a preferred embodiment of the present invention, the plasma activation treatment uses a mixture of argon and nitrogen gas, with the volume ratio of argon ranging from 70% to 90%, the volume ratio of nitrogen ranging from 10% to 30%, and the vacuum degree of the treatment chamber ranging from 0.1 Pa to 10 Pa.

[0052] Compared with the prior art, the present invention has the following beneficial effects:

[0053] This process, through systematic process design and the synergistic application of multiple technologies, comprehensively improves the fabrication quality and reliability of multilayer integrated circuit board stacking. The three-stage progressive alignment mechanism effectively solves the problem of balancing accuracy and efficiency in traditional positioning methods, significantly improving interlayer alignment accuracy and ensuring the accuracy and reliability of interconnects in multilayer structures.

[0054] The progressive gradient pressure bonding method effectively improves the interfacial bonding quality, reduces the generation of interfacial bubbles and defects, and increases the bonding strength and uniformity. The bonding interface is more stable and reliable and can withstand various stresses during subsequent processes and use.

[0055] The layered stress release mechanism fundamentally solves the problem of stress accumulation in the multilayer stacking process, effectively controls substrate warping deformation, avoids problems such as interface cracking and structural failure caused by internal stress, and significantly improves the mechanical stability and long-term reliability of multilayer stacked structures.

[0056] The quality inspection and error compensation mechanism after each layer stacking realizes closed-loop control of the process, which can promptly detect and resolve problems in each layer, prevent defects from being passed down, and effectively suppress the error accumulation effect during the stacking process. This ensures that good alignment accuracy and bonding quality can be maintained even when the number of stacked layers increases, and significantly increases the maximum number of stacked layers that can be achieved.

[0057] The overall process route is rationally designed, with smooth transitions between each step, precise parameter control, and good process stability and repeatability, effectively improving product yield and reducing production costs. The fabricated multilayer stacked structure exhibits high alignment accuracy, good bonding quality, low internal stress, and high reliability, meeting the application requirements of three-dimensional integration of high-performance integrated circuits. Attached Figure Description

[0058] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only examples of embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0059] Figure 1 This is a flowchart of an embodiment of the present invention. Detailed Implementation

[0060] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the embodiments of the present invention will be further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are only for explaining the present invention and are not intended to limit the present invention.

[0061] See Figure 1 As shown in the figure, an embodiment of the present invention provides a process for precise bonding of a multilayer stacked positioning integrated circuit board, comprising the following steps:

[0062] The S1 substrate pretreatment step involves preparing a positioning mark array and bonding interface on the surface of each integrated circuit board layer;

[0063] The S2 three-level positioning and alignment process sequentially achieves the alignment of adjacent integrated circuit boards through mechanical coarse positioning, optical fine positioning, and electrical nano-calibration.

[0064] The S3 progressive gradient pressure bonding process uses a zoned, graded, and phased pressure application method for pre-bonding and formal bonding.

[0065] S4 layered stress relief step, after each layer is bonded, gradient annealing is performed;

[0066] S5 repeats the stacking steps, repeating the above steps until all layers are stacked.

[0067] The above solution, through a step-by-step process design, breaks down the bonding process into multiple independent and controllable stages. Each stage addresses specific technical challenges at different stages, achieving refined control over the entire stacking process. Substrate pretreatment lays the foundation for subsequent positioning and bonding; three-level positioning and alignment progressively improves alignment accuracy; incremental pressurization ensures interface bonding quality; layered stress release prevents internal stress accumulation during stacking; and repeated stacking ensures the consistency and stability of the multilayer structure. The overall process route is rationally designed, with smooth transitions between steps, effectively improving the overall yield and reliability of the multilayer stacked structure.

[0068] The substrate pretreatment steps specifically include:

[0069] Cross-shaped optical positioning marks are prepared in the four corner areas of the integrated circuit board. The line width of the marks ranges from 5 micrometers to 20 micrometers, and the size of the marks ranges from 50 micrometers to 200 micrometers.

[0070] A grating-type nanocalibration mark is fabricated in the central region of an integrated circuit board, with a grating period ranging from 200 nanometers to 800 nanometers;

[0071] A dielectric layer and a metal bonding pad are prepared at the bonding interface, with the thickness of the dielectric layer ranging from 100 nm to 500 nm and the thickness of the metal bonding pad ranging from 50 nm to 300 nm.

[0072] The bonding interface is activated by plasma, with a power range of 100 watts to 500 watts and a processing time range of 10 seconds to 60 seconds.

[0073] The above scheme prepares different types of positioning marks in different regions, balancing the dual needs of coarse positioning and fine calibration. Optical marks in the corner areas facilitate rapid identification and initial positioning by the vision system, while grating marks in the central area enable higher-precision nanoscale alignment verification. The fabrication of the dielectric layer and metal bonding pads provides a good interfacial foundation for subsequent bonding, ensuring electrical connectivity and mechanical bonding between layers. Plasma activation treatment effectively cleans the bonding interface, increases surface energy, enhances interfacial adhesion, reduces interfacial defects, and improves bonding quality and long-term reliability.

[0074] The mechanical coarse positioning in the three-level positioning alignment process specifically includes:

[0075] Precision mechanical positioning pins are used in conjunction with positioning holes. The diameter of the positioning pins ranges from 1 mm to 5 mm, and the gap between the positioning holes and the positioning pins ranges from 1 micrometer to 5 micrometers.

[0076] The vision system identifies the reference marks on the corners of the integrated circuit board to achieve preliminary alignment in the X and Y axes, with an alignment accuracy range of 5 micrometers to 20 micrometers.

[0077] Perform θ angle rotation correction, with a rotation adjustment range of ±0.5 degrees and an adjustment accuracy range of 0.01 degrees to 0.1 degrees.

[0078] Mechanical coarse positioning, as the first stage of the three-stage alignment, can quickly determine the approximate position of the substrate, narrowing the adjustment range for subsequent precise positioning. The cooperation between the mechanical positioning pins and positioning holes provides a stable physical reference, ensuring the consistency of the initial position. The vision system's recognition of corner marks enables rapid positional adjustments in two directions within the plane, while angle rotation correction solves the deflection problem during substrate placement. By combining mechanical and vision methods, positioning efficiency is significantly improved and the overall process time is shortened while maintaining a certain level of alignment accuracy.

[0079] The optical precision positioning in the three-level positioning and alignment process specifically includes:

[0080] A high-resolution microscopic vision system was used to identify cross-shaped optical positioning marks, with a magnification range of 100x to 1000x.

[0081] The deviation between the upper and lower layer marks is calculated. The deviation compensation range in the X and Y axis directions is ±50 micrometers, and the compensation accuracy range is 50 nanometers to 200 nanometers.

[0082] A subpixel image matching algorithm is used to calculate the deviation, and the image matching accuracy ranges from 0.01 pixels to 0.1 pixels.

[0083] Optical fine positioning further improves alignment accuracy based on mechanical coarse positioning. A high-magnification microscope system can clearly observe minute positioning marks and accurately capture their positional information. Through precise calculation and compensation of the deviation between upper and lower layer marks, residual positional errors from the mechanical positioning stage can be effectively eliminated. The sub-pixel image matching algorithm overcomes the physical limitations of hardware pixels, further improving the accuracy of deviation calculation. This enables optical positioning to achieve sub-micron level alignment, laying a solid foundation for subsequent nanometer-level calibration and significantly improving overall alignment accuracy.

[0084] The electrical nanocalibration in the three-level positioning and alignment process specifically includes:

[0085] Alignment verification was performed by testing the contact resistance of the upper and lower metal bonding pads, with a contact resistance threshold range of 1 milliohm to 10 milliohms.

[0086] When the contact resistance exceeds the threshold, nanometer-level position fine-tuning is performed, with a fine-tuning step size ranging from 10 nanometers to 50 nanometers.

[0087] The overall alignment deviation is calculated by analyzing the resistance distribution in the four corner regions, and global position optimization is performed.

[0088] Electrical nanocalibration, as the final step in the three-stage alignment process, elevates alignment accuracy to the nanometer level. Contact resistance testing directly reflects the actual alignment status of the upper and lower bonding pads; the resistance value is directly related to the degree of alignment, enabling quantitative evaluation of the alignment effect. When alignment deviations are large, nanometer-level fine-tuning gradually optimizes the alignment, with minute adjustment steps ensuring calibration accuracy and stability. Multi-point resistance distribution measurement comprehensively reflects the alignment of the entire substrate, achieving global position optimization and ensuring alignment consistency across the entire bonding interface.

[0089] The progressive gradient pressure bonding process specifically includes:

[0090] During the pre-bonding stage, the first pressure is applied in the range of 0.1 MPa to 0.5 MPa, and the holding time is in the range of 10 seconds to 60 seconds;

[0091] During the zoned pressurization phase, the pressure is gradually increased from the central area to the peripheral area, with the pressure range in the central area being 0.5 MPa to 2 MPa and the pressure range in the peripheral area being 1 MPa to 3 MPa.

[0092] During the formal bonding stage, a uniform pressure ranging from 2 MPa to 10 MPa is applied, while a heating process is carried out at a temperature ranging from 150 degrees Celsius to 400 degrees Celsius.

[0093] The progressive gradient pressurization design avoids the impact and damage to the substrate caused by a single high pressure. The low pressure in the pre-bonding stage allows for initial interface contact, expelling most of the air between the interfaces. The phased pressurization, progressing gradually from the center to the edge, facilitates the smooth expulsion of gas between the interfaces, reduces bubble formation, and makes the interface bonding more uniform. The combination of uniform pressurization and heating treatment in the formal bonding stage promotes the mutual diffusion and bonding between atoms at the bonding interface, forming a stable and reliable bonding interface. The phased pressurization strategy balances bonding quality and substrate protection, effectively improving the bonding strength and uniformity of the bonding interface.

[0094] Real-time closed-loop control is used during the formal bonding stage:

[0095] Pressure sensors monitor the pressure distribution in each area in real time, and the pressure uniformity is controlled at over 95%.

[0096] The infrared temperature measurement system monitors the temperature distribution in real time, and the temperature uniformity is controlled within ±5 degrees Celsius.

[0097] The in-situ optical monitoring system observes the bonding interface in real time, promptly detecting and eliminating interface bubbles.

[0098] A real-time closed-loop control system enables dynamic monitoring and adjustment of the bonding process. Pressure monitoring ensures uniform stress across the entire substrate surface, preventing uneven bonding quality caused by excessive or insufficient local pressure. Temperature monitoring ensures a consistent temperature field at the bonding interface, providing a stable thermal environment for the bonding reaction and reducing thermal stress. In-situ optical monitoring allows for direct observation of interface changes during bonding, enabling timely detection of defects such as bubbles and appropriate corrective measures. Real-time monitoring and feedback adjustment of multiple parameters ensure the stability and repeatability of the bonding process, improving the consistency of bonding quality.

[0099] The specific steps for layered stress relief include:

[0100] After bonding is completed, the temperature is reduced at a first cooling rate ranging from 5 degrees Celsius to 20 degrees Celsius per minute to an intermediate temperature range of 100 degrees Celsius to 200 degrees Celsius.

[0101] Stress relaxation treatment is performed by holding the material at an intermediate temperature for 30 to 120 minutes.

[0102] Then, cool down to room temperature at a second cooling rate ranging from 1 degree Celsius to 5 degrees Celsius per minute;

[0103] After each layer is stacked, warpage is tested, and the warpage is controlled within the range of 1 micrometer to 5 micrometers per centimeter.

[0104] Layered stress relief treatment effectively solves the internal stress problem caused by temperature changes and differences in the thermal expansion coefficients of materials during bonding. Gradual cooling avoids stress concentration caused by rapid cooling, and the intermediate temperature holding stage provides time for stress relaxation, allowing internal stress to be fully released. Slow final cooling further reduces the generation of new stress during the cooling process. Warpage detection after each layer is completed allows for timely assessment of the stress relief effect, ensuring the flatness of each substrate layer and providing a good foundation for the stacking of the next layer. Layered treatment avoids stress accumulation during multi-layer stacking, effectively preventing substrate deformation and cracking.

[0105] Specifically, this also includes real-time quality inspection steps during the stacking process:

[0106] After each layer is bonded, an acoustic scanning microscope is used to inspect the interface defects, which are larger than 1 micrometer.

[0107] X-ray tomography was performed to verify the alignment accuracy between layers.

[0108] Perform electrical performance tests, including continuity resistance, insulation resistance, and signal integrity tests.

[0109] Quality inspection after each layer is stacked enables quality control throughout the process. Acoustic scanning effectively detects internal defects such as voids and cracks at the bonding interface, ensuring the quality of the interface bonding. X-ray tomography allows for direct observation of the alignment between layers, verifying the actual effect of positioning and alignment. Electrical performance testing directly verifies the functional characteristics of the stacked structure, ensuring the reliability of electrical connections and insulation performance. Layer-by-layer inspection can promptly identify problems in each layer, preventing defects from accumulating in subsequent layers, reducing material waste and rework costs, and providing data support for optimizing process parameters, thus ensuring the overall quality of the final product.

[0110] During the repeated stacking process, a surface smoothing process is performed after each layer is stacked.

[0111] The surface is smoothed by chemical mechanical polishing, and the surface roughness after polishing ranges from 0.1 nanometers to 1 nanometer.

[0112] Prepare the bonding interface and positioning marks for the next layer, ensuring that the coordinate system of the positioning marks in each layer is consistent;

[0113] Cumulative error compensation adjusts the positioning parameters of subsequent layers based on the actual alignment deviations of the previous layers.

[0114] The surface planarization process after each layer stacking provides an ideal reference surface for the bonding of the next layer. Chemical mechanical polishing achieves extremely low surface roughness, ensuring tight interfacial contact. A unified coordinate system ensures the consistency of positioning marks across layers, avoiding alignment errors caused by coordinate system mismatches between layers. A cumulative error compensation mechanism proactively adjusts the positioning parameters of subsequent layers by analyzing the alignment data of the previous layers, effectively offsetting the gradual accumulation of errors during stacking and improving the overall alignment accuracy of multilayer stacking. These measures ensure the continuity and consistency of the multilayer stacking process, maintaining good alignment and bonding quality even as the number of stacked layers increases.

[0115] Specifically, the number of stacked layers of the integrated circuit board ranges from 2 to 32, the thickness of a single integrated circuit board ranges from 50 micrometers to 300 micrometers, and the overall stack thickness ranges from 100 micrometers to 5000 micrometers.

[0116] The wide range of applicable layer counts and thicknesses allows the process to meet the needs of various applications, from simple two-layer stacks to complex multi-layer stacks. The appropriate selection of single-layer substrate thickness balances the mechanical strength of the substrate with the overall thickness after stacking; excessively thin substrates are prone to deformation, while excessively thick substrates increase the overall volume. The overall stack thickness range is designed to balance package volume limitations with structural stability. The flexible parameter range makes the process highly adaptable, allowing adjustments to be made according to specific product requirements, and suitable for the fabrication of different types and specifications of integrated circuit board stacks.

[0117] Specifically, the plasma activation treatment uses a mixture of argon and nitrogen, with the volume ratio of argon ranging from 70% to 90% and the volume ratio of nitrogen ranging from 10% to 30%, and the vacuum degree of the treatment chamber ranging from 0.1 Pa to 10 Pa.

[0118] Argon and nitrogen mixed-gas plasma treatment achieves better interface activation. Argon primarily functions to physically bombard and clean the interface, while nitrogen forms nitrogen-containing active groups at the interface, enhancing its bonding ability. The optimal ratio of these two gases balances cleaning effectiveness and surface activation performance, avoiding the limitations of single-gas treatment. An appropriate vacuum range ensures stable plasma generation and uniform distribution, allowing for thorough and uniform treatment of the entire substrate surface. Optimized gas composition and process conditions significantly improve interface activation quality, providing a favorable interface state for subsequent bonding.

[0119] In summary, the working principle of the precise bonding fabrication process for a multilayer stacked positioning integrated circuit board in this embodiment is as follows:

[0120] This process employs a step-by-step technical approach, achieving precise bonding of multilayer integrated circuit boards through the synergistic action of multiple stages. The entire process is based on the organic integration of four major technical principles: a three-level alignment mechanism, gradient pressure bonding, layer stress control, and process quality feedback.

[0121] The three-stage alignment mechanism follows a progressive principle from coarse to fine. First, it achieves rapid initial positioning through a combination of mechanical and visual methods to reduce the range of positional deviation. Then, a high-resolution optical system is used for sub-micron level precision adjustments to further eliminate positional errors. Finally, direct measurement of electrical parameters achieves nanometer-level final calibration, ensuring truly precise alignment between the upper and lower substrates. Each of the three stages has its own focus and complements the others, balancing positioning efficiency and accuracy requirements.

[0122] The gradient pressure bonding principle is based on the evolution of interfacial bonding. By gradually increasing the pressure and controlling the zones, it guides the orderly discharge of interfacial gases and avoids bubble trapping. The pre-bonding stage achieves initial interfacial contact, the zoned pressure stage promotes the gradual expansion of interfacial bonding, and the formal bonding stage, under the combined action of temperature and pressure, achieves diffusion and bonding between interfacial atoms, forming a stable and reliable bonding interface.

[0123] The layered stress control principle addresses the thermal mismatch problem during bonding by providing stress release channels within the material through gradient cooling and intermediate heat preservation, thus preventing stress concentration. Each layer undergoes independent stress release treatment after stacking to prevent stress accumulation in the multilayer structure and ensure good flatness of each substrate layer.

[0124] The process quality feedback principle evaluates the process effect in a timely manner through multi-dimensional inspection after each layer is stacked, discovers potential defects, and adjusts subsequent process parameters based on actual inspection results. This achieves proactive error compensation and continuous process optimization, ensuring the stability and consistency of the overall quality of multi-layer stacking.

[0125] How to use:

[0126] This process is carried out sequentially according to a standardized procedure. First, the substrate is pretreated by preparing different types of positioning marks and bonding interfaces on the surface of each substrate layer, and then surface activation treatment is performed to prepare for subsequent processes.

[0127] The process then proceeds to a three-stage positioning and alignment process. First, mechanical coarse positioning is performed, where the positioning mechanism works in conjunction with a vision system to complete the initial position adjustment and angle correction of the substrate. Next, optical fine positioning is performed, where a high-magnification microscope system is used to accurately identify and match the positioning marks, and to calculate and compensate for positional deviations. Finally, electrical nanocalibration is performed, where the alignment status is verified by measuring the electrical parameters of the bonding interface, and nanoscale fine-tuning and optimization are carried out until the ideal alignment effect is achieved.

[0128] After alignment, progressive gradient pressure bonding is performed, applying pressure step by step in the order of pre-bonding, zoned pressure application, and formal bonding, while coordinating with appropriate temperature treatment. At the same time, a real-time monitoring system is used to ensure the uniformity of pressure and temperature and to observe the bonding interface status.

[0129] Immediately after each bonding layer is completed, a delamination stress release process is performed, cooling is carried out gradually according to a set cooling curve, and heat preservation treatment is performed in the intermediate temperature range to fully release internal stress. After cooling, the substrate warpage is checked to confirm that the flatness meets the requirements.

[0130] Subsequently, quality inspection of this layer was conducted. Multiple inspection methods were used to check interface defects, alignment accuracy, and electrical properties. After confirming there were no quality issues, surface smoothing was performed to prepare the bonding interface for the next layer. Error analysis was performed based on the inspection data of the completed layer, and the positioning parameters for the next layer were adjusted.

[0131] Repeat all the above steps to complete the stacking of each layer in sequence until the designed number of stacking layers is reached, and finally complete the fabrication of the entire multi-layer stacked structure.

[0132] In addition, this application also provides the following two implementation examples.

[0133] Implementation Example 1:

[0134] This embodiment provides a precise bonding fabrication process for a four-layer stacked integrated circuit board, the specific steps of which are as follows:

[0135] Step 1: Substrate Pretreatment

[0136] Four integrated circuit boards, each 100 micrometers thick, were selected as the stacking substrate. Cross-shaped optical positioning marks were fabricated at the four corners of each integrated circuit board, with a linewidth of 10 micrometers and a mark size of 100 micrometers. A grating-type nanocalibration mark with a grating period of 400 nanometers was fabricated in the central region of the integrated circuit board. A 200-nanometer-thick silicon dioxide dielectric layer and a 150-nanometer-thick copper bonding pad were fabricated at the bonding interface. Plasma activation was performed using a mixture of argon and nitrogen gases, with an argon ratio of 80% and a nitrogen ratio of 20%, at a processing power of 300 watts, a processing time of 30 seconds, and a chamber vacuum of 1 Pa.

[0137] Step 2: Stack the first and second layers

[0138] First, mechanical coarse positioning is performed: a precision positioning pin with a diameter of 2 mm is used to fit into the positioning hole, with a positioning gap of 2 micrometers. The X and Y axes are initially aligned by identifying the corner reference marks through a vision system, with an alignment accuracy of 10 micrometers. Then, θ angle rotation correction is performed, with an adjustment accuracy of 0.05 degrees.

[0139] Then, optical precision positioning is performed: a high-resolution microscopic vision system with a magnification of 500x is used to identify the cross-shaped positioning mark, and a sub-pixel image matching algorithm is used to calculate the deviation with a matching accuracy of 0.05 pixels. X and Y axis deviation compensation is performed with a compensation accuracy of 100 nanometers.

[0140] Next, electrical nanocalibration is performed: the contact resistance of the upper and lower metal bonding pads is tested, with a threshold of 5 milliohms. When the resistance exceeds the threshold, the position is fine-tuned in 20-nanometer steps until the resistance meets the standard. The global deviation is calculated by the resistance distribution at the four corners, and the overall position is optimized.

[0141] Step 3: Gradient pressure bonding

[0142] Pre-bonding stage: Apply 0.3 MPa pressure and hold for 30 seconds to allow the interface to make initial contact.

[0143] Partition pressurization phase: Pressurization is gradually increased from the center to the edge, with the pressure in the central area being 1 MPa and the pressure in the edge area being 2 MPa, to achieve gradual contact at the interface.

[0144] Formal bonding stage: Apply a uniform pressure of 5 MPa while simultaneously heating to 250 degrees Celsius. The pressure uniformity is monitored by a pressure sensor to reach 98%, the temperature uniformity is monitored by an infrared temperature measurement system to be ±3 degrees Celsius, and an in-situ optical system is used to monitor and eliminate interface bubbles.

[0145] Step 4: Layered Stress Relief

[0146] After bonding, the temperature was lowered to 150 degrees Celsius at a rate of 10 degrees Celsius per minute, held at that temperature for 60 minutes for stress relaxation, and then lowered to room temperature at a rate of 3 degrees Celsius per minute. The warpage was measured at 2 micrometers per centimeter, which meets the requirements.

[0147] Step 5: Quality Inspection

[0148] Acoustic scanning microscopy revealed no interface defects larger than 1 micrometer; X-ray tomography showed an interlayer alignment accuracy of 150 nanometers; electrical performance tests showed that conduction resistance, insulation resistance, and signal integrity all met the standards.

[0149] Step Six: Surface Smoothing and Stacking of the Next Layer

[0150] Surface smoothing was performed using chemical mechanical polishing, resulting in a surface roughness of 0.5 nm. The bonding interface and positioning markers for the third layer were then prepared. Cumulative error compensation was performed based on the alignment deviations of the first two layers. Steps two through five were repeated to complete the stacking of the third and fourth layers.

[0151] The final product is a four-layer stacked integrated circuit board with a total thickness of 420 micrometers, an overall alignment accuracy better than 200 nanometers, an interface bonding strength greater than 20 MPa, and stable performance after 1000 temperature cycle tests.

[0152] Implementation Example 2:

[0153] The difference between this embodiment and Embodiment 1 is that the number of stacked layers is 8, the thickness of a single layer is 75 micrometers, the bonding temperature is 300 degrees Celsius, and the bonding pressure is 7 MPa. The final result is an 8-layer stacked integrated circuit board with a total thickness of 650 micrometers and an overall alignment accuracy better than 250 nanometers, meeting the requirements for high-density integration.

[0154] The above description illustrates the basic principles of the present invention. The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. The above embodiments and descriptions in the specification are only for illustrating the principles of the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and scope of the present invention without departing from the scope of the present invention should be included within the protection scope of the present invention.

Claims

1. A process for precisely bonding and fabricating a multilayer stacked positioning integrated circuit board, characterized in that... Includes the following steps: The substrate pretreatment step involves preparing a positioning mark array and bonding interface on the surface of each integrated circuit board layer; The three-stage positioning and alignment process sequentially achieves the alignment of adjacent integrated circuit boards through mechanical coarse positioning, optical fine positioning, and electrical nano-calibration. The progressive gradient pressure bonding process employs a zoned, graded, and phased pressure application method for pre-bonding and formal bonding. The layered stress relief process involves gradient annealing after each layer is bonded. Repeat the stacking steps until all layers are stacked.

2. The process for precise bonding of a multilayer stacked positioning integrated circuit board according to claim 1, characterized in that, The substrate pretreatment step specifically includes: Cross-shaped optical positioning marks are prepared in the four corner areas of the integrated circuit board. The line width of the marks ranges from 5 micrometers to 20 micrometers, and the size of the marks ranges from 50 micrometers to 200 micrometers. A grating-type nanocalibration mark is fabricated in the central region of an integrated circuit board, with a grating period ranging from 200 nanometers to 800 nanometers; A dielectric layer and a metal bonding pad are prepared at the bonding interface, with the thickness of the dielectric layer ranging from 100 nm to 500 nm and the thickness of the metal bonding pad ranging from 50 nm to 300 nm. The bonding interface is activated by plasma, with a power range of 100 watts to 500 watts and a processing time range of 10 seconds to 60 seconds.

3. The process for precise bonding of a multilayer stacked positioning integrated circuit board according to claim 1, characterized in that, The mechanical coarse positioning in the three-level positioning and alignment process specifically includes: Precision mechanical positioning pins are used in conjunction with positioning holes. The diameter of the positioning pins ranges from 1 mm to 5 mm, and the gap between the positioning holes and the positioning pins ranges from 1 micrometer to 5 micrometers. By identifying the reference marks on the corners of the integrated circuit board using a vision system, preliminary alignment in the X and Y axes can be achieved with an alignment accuracy range of 5 micrometers to 20 micrometers. Perform θ angle rotation correction, with a rotation adjustment range of ±0.5 degrees and an adjustment accuracy range of 0.01 degrees to 0.1 degrees.

4. The process for precise bonding of a multilayer stacked positioning integrated circuit board according to claim 1, characterized in that, The optical precision positioning in the three-level positioning and alignment process specifically includes: A high-resolution microscopic vision system was used to identify cross-shaped optical positioning marks, with a magnification range of 100x to 1000x. The deviation between the upper and lower layer marks is calculated. The deviation compensation range in the X and Y axis directions is ±50 micrometers, and the compensation accuracy range is 50 nanometers to 200 nanometers. A subpixel image matching algorithm is used to calculate the deviation, and the image matching accuracy ranges from 0.01 pixels to 0.1 pixels.

5. The process for precise bonding of a multilayer stacked positioning integrated circuit board according to claim 1, characterized in that, The electrical nanocalibration in the three-level positioning and alignment steps specifically includes: Alignment verification was performed by testing the contact resistance of the upper and lower metal bonding pads, with a contact resistance threshold range of 1 milliohm to 10 milliohms. When the contact resistance exceeds the threshold, nanometer-level position fine-tuning is performed, with a fine-tuning step size ranging from 10 nanometers to 50 nanometers. The overall alignment deviation is calculated by analyzing the resistance distribution in the four corner regions, and global position optimization is performed.

6. The process for precise bonding of a multilayer stacked positioning integrated circuit board according to claim 1, characterized in that, The progressive gradient pressure bonding step specifically includes: During the pre-bonding stage, the first pressure is applied in the range of 0.1 MPa to 0.5 MPa, and the holding time is in the range of 10 seconds to 60 seconds; During the zoned pressurization phase, the pressure is gradually increased from the central area to the peripheral area, with the pressure range in the central area being 0.5 MPa to 2 MPa and the pressure range in the peripheral area being 1 MPa to 3 MPa. During the formal bonding stage, a uniform pressure ranging from 2 MPa to 10 MPa is applied, while a heating process is carried out at a temperature ranging from 150 degrees Celsius to 400 degrees Celsius.

7. The process for precise bonding of a multilayer stacked positioning integrated circuit board according to claim 6, characterized in that, The formal bonding stage employs real-time closed-loop control: Pressure sensors are used to monitor the pressure distribution in each area in real time, and the pressure uniformity is controlled at over 95%. The temperature distribution is monitored in real time by an infrared temperature measurement system, and the temperature uniformity is controlled within ±5 degrees Celsius. By observing the bonding interface in real time through an in-situ optical monitoring system, interface bubbles can be detected and eliminated in a timely manner.

8. The process for precise bonding of multilayer stacked positioning integrated circuit boards according to claim 1, characterized in that, The layered stress relief steps specifically include: After bonding is completed, the temperature is reduced at a first cooling rate ranging from 5 degrees Celsius to 20 degrees Celsius per minute to an intermediate temperature range of 100 degrees Celsius to 200 degrees Celsius. Stress relaxation treatment is performed by holding the material at an intermediate temperature for 30 to 120 minutes. Then, cool down to room temperature at a second cooling rate ranging from 1 degree Celsius to 5 degrees Celsius per minute; After each layer is stacked, warpage is tested, and the warpage is controlled within the range of 1 micrometer to 5 micrometers per centimeter.

9. The process for precise bonding of a multilayer stacked positioning integrated circuit board according to claim 1, characterized in that, It also includes real-time quality inspection steps during the stacking process: After each layer is bonded, an acoustic scanning microscope is used to inspect the interface defects, which are larger than 1 micrometer. X-ray tomography was performed to verify the alignment accuracy between layers. Perform electrical performance tests, including continuity resistance, insulation resistance, and signal integrity tests.

10. The process for precise bonding of a multilayer stacked positioning integrated circuit board according to claim 1, characterized in that, In the repeated stacking step, a surface smoothing process is performed after each layer is stacked: The surface is smoothed by chemical mechanical polishing, and the surface roughness after polishing ranges from 0.1 nanometers to 1 nanometer. Prepare the bonding interface and positioning marks for the next layer, ensuring that the coordinate system of the positioning marks in each layer is consistent; Cumulative error compensation adjusts the positioning parameters of subsequent layers based on the actual alignment deviations of the previous layers.

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