High-speed high-frequency PCB line manufacturing process and burr control method

Abstract

This invention discloses a high-speed, high-frequency PCB circuit manufacturing process and a burr control method, belonging to the technical field of high-speed, high-frequency PCB circuit manufacturing. The burr control method includes copper surface polishing of incoming materials during the high-speed, high-frequency PCB circuit manufacturing process, double exposure after film lamination, and a supplementary etching stage after vacuum etching lines following development. In the burr control process, this invention optimizes the copper surface polishing of incoming PCB materials, the improved circuit exposure design, and the etching production method after circuit exposure. This achieves precise and stable control of circuit burrs ≤5µm, with a post-etching circuit tolerance of approximately ±5% and an etching factor >5, thus meeting the production requirements for high-speed, high-frequency PCB circuits suitable for 5G communication, AI servers, and other applications.

Description

Technical Field

[0001] This invention relates to the field of high-speed, high-frequency PCB board circuit manufacturing technology, specifically to a method for controlling burrs on high-speed, high-frequency PCB board circuits and a PCB board circuit manufacturing process. Background Technology

[0002] The copper traces in high-speed, high-frequency PCBs are not simply conductive traces, but rather high-speed, high-frequency signal transmission channels, impedance-controlled carriers, electromagnetic isolation structures, and the backbone of system interconnection. They directly determine signal integrity, impedance matching, attenuation loss, EMC (electromagnetic compatibility), and overall high-speed performance. However, the complexity, variability, and uncontrollability of the burrs on these traces have always been a challenge in PCB manufacturing processes, mainly due to the following factors:

[0003] First, the variation in the depth and size of the copper teeth on the PCB board leads to complex and varied burrs on the circuit.

[0004] Secondly, after the dry film pattern is developed, the circuit is affected by the impact and penetration of the chemicals, and the uniformity and consistency issues also contribute to the complexity, variability and uncontrollability of the burrs on the circuit.

[0005] Third, the fluctuation of etching solution concentration in the vacuum etching line and the pool effect generated during the etching of circuit boards make it difficult to control the burrs on the etched circuits.

[0006] The combination of these factors ultimately makes it extremely difficult to control burrs during the manufacturing process of high-speed, high-frequency PCB circuits, and seriously affects the consistency of signal layers and transmission rates on high-speed, high-frequency PCBs.

[0007] Therefore, this patent application is filed. Summary of the Invention

[0008] The purpose of this invention is to provide a method for controlling burrs on high-speed, high-frequency PCB circuits, and also to provide a manufacturing process for high-speed, high-frequency PCB circuits. In the burr control process, the copper surface polishing of the incoming PCB material, the improved design of circuit exposure, and the etching production method after circuit exposure are optimized, thereby achieving precise and stable control of circuit burrs, thus meeting the production requirements of high-speed, high-frequency PCB circuits suitable for 5G communication, AI servers, etc.

[0009] The purpose of this invention is to provide a method for controlling burrs on high-speed, high-frequency PCB circuits, including polishing the copper surface of the incoming material during the fabrication of the high-speed, high-frequency PCB circuit, performing two exposures after film lamination, and adding a re-etching process after vacuum etching lines following development.

[0010] As a preferred technical solution, the incoming material is selected as reverse copper foil, and the copper surface polishing is performed by polishing the rough surface of the reverse copper foil with a non-woven fabric brush.

[0011] As a preferred technical solution, the non-woven fabric brush is provided in two sets, and a 1500-mesh non-woven fabric brush is used.

[0012] The varying depth of the copper teeth on the substrate affects the burrs on the etched circuits; the greater the depth of the copper teeth, the larger the burrs formed after etching. Traditional electrolytic copper foil typically combines a rough surface with a resin substrate, which can easily leave copper roots at the bottom of the etched circuit edges, resulting in uneven edges (i.e., larger burrs).

[0013] In this invention, the incoming material is selected as RTF2 or higher reverse copper foil. The rough surface of the copper foil is then polished again using a non-woven brush. The reverse copper foil combines the smooth surface of the copper foil with the resin substrate, placing the rough surface on the smooth surface of the circuit board. After etching, the circuit edges are more vertical, with no residual copper and neat (small burrs). The final copper foil tooth depth is reduced to 2μm, and the surface roughness of the circuit is more uniform.

[0014] As a preferred technical solution, the polishing process consists of sequentially feeding plates with an automatic plate feeder, acid washing, water washing, plate polishing, water washing, and drying. The plate polishing uses a 1500-mesh non-woven fabric brush.

[0015] As a preferred technical solution, when exposing the film twice, a dry film with a thickness of 30μm is used. The width of the circuit design data in the first exposure is 3μm larger than the width of the circuit design data in the second exposure. The exposure parameter energy is 5.5 divisions in the first exposure and 6 divisions in the second exposure.

[0016] As a preferred technical solution, the first and second exposures are performed using the same exposure machine and an automatic expansion / contraction mode.

[0017] Higher exposure energy strengthens the bond between the dry film and the copper surface when exposing circuit patterns. However, excessive exposure energy can lead to poor exposure and short circuits. The traditional production method in the PCB industry is to expose circuit patterns using a dry film with a thickness of approximately 30μm or 40μm, using an exposure film, and exposing in one step with an LED exposure machine. The resulting circuit pattern tolerance is approximately ±10%.

[0018] In this invention, the exposure circuit pattern is improved by using a 30μm thick dry film and exposing it twice. At the same time, the first exposure pattern data and the second exposure pattern data are specially designed. As a result, the adhesion of the dry film in the exposed area after two exposures is stronger, and the developing and etching solutions are difficult to penetrate. The tolerance of the dry film pattern circuit reaches within ±5%.

[0019] As a preferred technical solution, the vacuum etching line processing is divided into three stages, with etching solution added in each stage and micro-etching solution added in the re-etching stage.

[0020] As a preferred technical solution, the etching process consists of a pre-etching stage, a main etching stage, and a fine etching stage, and the etching solution is a copper chloride-hydrochloric acid system;

[0021] And / or, the micro-etching solution is a sodium persulfate-sulfuric acid system, and the process of the repair etching section is to perform a secondary rinsing process on the etched line burrs using the micro-etching solution to reduce the line burrs.

[0022] The process of etching copper layers to form circuit patterns is affected by the thickness of the copper layer. The thicker the copper layer, the worse the chemical exchange capacity between the lines and the more obvious the pooling effect, which leads to burrs after the circuit is etched.

[0023] During the etching stage, the process of etching the copper layer to form the circuit pattern is affected by the thickness of the copper layer. The thicker the copper, the worse the exchange capacity of the etching solution at the bottom between the lines, and the more obvious the pooling effect, resulting in burrs after etching. The traditional circuit production solution in the PCB industry uses a vacuum etching line, which is divided into three sections. The etching solution is filled in all three sections. The tolerance of the etched circuit is about ±20%, and the etching factor is about 3. The etched circuit has a large slope and burrs.

[0024] To address the issue of large burrs and bevels in the circuit during etching, this invention employs a vacuum etching line (divided into three sections) with an additional etching section. A micro-etching solution is added to this section to further treat the burrs. After etching, the burrs are precisely and stably controlled to ≤5µm, and the etched circuit is virtually burr-free. The post-etching circuit tolerance is approximately ±5%, and the etching factor is >5.

[0025] This invention achieves precise and stable control of burrs on the circuit board through multiple improvements, including PCB board material selection, copper surface processing, circuit exposure pattern design, and optimization of circuit exposure etching production methods. The etched circuits are almost free of sloping burrs, and the tolerance of the etched circuits is about ±5%, which meets the requirements for the production of high-speed and high-frequency PCB circuits suitable for 5G communication, AI servers, and other applications.

[0026] The second objective of this invention is to provide a high-speed, high-frequency PCB board circuit manufacturing process, including copper surface polishing of incoming materials, medium roughening pretreatment, film application, double exposure, development, vacuum etching lines, re-etching sections, and film removal.

[0027] As a preferred technical solution, the pretreatment process for roughening consists of sequentially performing plate placement, pickling, water washing, plate polishing, water washing, and drying.

[0028] The advantages and beneficial effects of this invention compared to the prior art are:

[0029] 1. In this invention, the incoming material is selected as reverse copper foil, and the rough surface of the copper foil is polished again by using a non-woven brush. The final copper foil tooth depth is reduced to 2μm, and the surface roughness of the circuit is more uniform.

[0030] 2. In this invention, the exposure circuit pattern is improved by using a dry film with a thickness of 30μm and exposing it twice. At the same time, the first exposure pattern data and the second exposure pattern data are specially designed. As a result, the adhesion of the dry film in the exposure area after two exposures is stronger, and the developing and etching solutions are difficult to penetrate. The tolerance of the dry film pattern circuit reaches within ±5%.

[0031] 3. In this invention, a vacuum etching line (divided into three sections) is supplemented with an additional etching section. A micro-etching solution is added to this section to perform a secondary treatment on the burrs of the circuit. After etching, the burrs on the circuit are precisely and stably controlled to ≤5µm, and the etched circuit is almost free of beveled burrs. The tolerance of the etched circuit is approximately ±5%, and the etching factor is >5.

[0032] With the above improvements, this invention finally achieves precise and stable control of burrs on the circuit lines, meeting the requirements for the production of high-speed, high-frequency PCB lines suitable for 5G communication, AI servers, and other applications. Attached Figure Description

[0033] To more clearly illustrate the technical solutions of the exemplary embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly described below. It should be understood that the following drawings only show some embodiments of the present invention and should not be considered as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort. In the drawings:

[0034] Figure 1 The images shown are physical images and SEM images of the board material obtained after copper surface polishing of the inverted copper foil in Example 1. 1(a) and 1(c) are physical images and SEM images of a cross section obtained using ordinary HTE copper foil, respectively. 1(b) and 1(d) are physical images and SEM images of a cross section obtained using inverted copper foil, respectively.

[0035] Figure 2 These are the graphic images from the first and second exposures during the exposure process.

[0036] Figure 3 For the etching section, vacuum etching line and the repair etching section (i.e. Figure 3 The flowchart of the compensation section in the process. Detailed Implementation

[0037] To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the embodiments and accompanying drawings. The illustrative embodiments and descriptions of the present invention are only used to explain the present invention and are not intended to limit the present invention.

[0038] Throughout this specification, references to "an embodiment," "an example," or "an example" mean that a particular feature, structure, or characteristic described in connection with that embodiment or example is included in at least one embodiment of the invention. Therefore, the phrases "an embodiment," "an example," "an example," or "an example" appearing in various places throughout the specification do not necessarily refer to the same embodiment or example. Furthermore, specific features, structures, or characteristics can be combined in one or more embodiments or examples in any suitable combination and / or sub-combination. Moreover, those skilled in the art will understand that the illustrations provided herein are for illustrative purposes and are not necessarily drawn to scale. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0039] In the description of this invention, the terms "front", "rear", "left", "right", "up", "down", "vertical", "horizontal", "high", "low", "inner", and "outer" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting the scope of protection of this invention.

[0040] The "range" disclosed in this application is defined by a lower limit and an upper limit. A given range is defined by selecting a lower limit and an upper limit, which define the boundaries of a particular range. Ranges defined in this way can include or exclude endpoints and can be arbitrarily combined; that is, any lower limit can be combined with any upper limit to form a range. For example, if ranges of 60–120 and 80–110 are listed for a specific parameter, it is understood that ranges of 60–110 and 80–120 are also expected. Furthermore, if minimum range values ​​of 1 and 2 are listed, and if maximum range values ​​of 3, 4, and 5 are listed, then the following ranges are all expected: 1–3, 1–4, 1–5, 2–3, 2–4, and 2–5. In this application, unless otherwise stated, the numerical range "a–b" represents a shortened representation of any combination of real numbers between a and b, where a and b are real numbers. For example, the numerical range "0~5" indicates that all real numbers between "0~5" have been listed in this article; "0~5" is simply a shortened representation of these numerical combinations. Furthermore, when a parameter is stated as an integer ≥2, it is equivalent to disclosing that the parameter is, for example, an integer such as 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, etc.

[0041] Unless otherwise specified, all steps in this application may be performed sequentially or randomly, preferably sequentially. For example, the method includes steps (a) and (b), indicating that the method may include steps (a) and (b) performed sequentially, or it may include steps (b) and (a) performed sequentially. For example, the mention that the method may also include step (c) indicates that step (c) may be added to the method in any order. For example, the method may include steps (a), (b), and (c), or it may include steps (a), (c), and (b), or it may include steps (c), (a), and (b), etc.

[0042] Unless otherwise specified, the terms "comprising" and "including" as used in this application can be open-ended or closed-ended. For example, "comprising" and "including" can mean that other components not listed may also be included, or that only the listed components may be included.

[0043] Example 1:

[0044] A high-speed, high-frequency PCB manufacturing process includes copper surface polishing of incoming materials, pre-roughening treatment, film lamination, double exposure, development, vacuum etching lines, re-etching sections, and film removal. After film removal, quality linewidth and impedance measurements are performed. The process achieves precise control of burrs on the PCB circuitry through copper surface polishing of incoming materials, double exposure after film lamination, vacuum etching lines after development, and the addition of a re-etching section.

[0045] The specific preparation process is as follows:

[0046] 1. Polish the copper surface of the incoming material.

[0047] Material selection: Select RTF2 or higher grade (such as RTF3, RTF4 or even higher grade) reverse copper foil.

[0048] Grinding: Grind the reversed copper foil using two sets of 1500-grit non-woven brushes to further polish the rough surface of the copper foil. The specific polishing process is as follows:

[0049] The process is as follows: automatic plate feeding machine, pickling, water washing, plate polishing (two sets of 1500-mesh non-woven fabric brushes, two on the top and two on the bottom), water washing, and drying.

[0050] Through material selection and grinding / polishing processes, the following results are obtained: Figure 1 The figures shown in (b) and 1(d) are compared with those obtained by using ordinary HTE copper foil sheets after the same treatment. It is found that when using ordinary copper foil sheets, the bottom of the copper foil has large undulations and copper roots, and the edges are uneven. However, the copper foil obtained by the processing method of this embodiment (material selection, grinding, polishing) has an almost smooth bottom and neat edges.

[0051] 2. Pretreatment for coarsening

[0052] The specific process is as follows: automatic plate feeding machine, pickling, water washing, plate polishing (two sets of 1500-mesh non-woven fabric brushes, two on the top and two on the bottom), water washing, and drying.

[0053] 3. Applying a screen protector

[0054] The specific process is as follows: the automatic board feeding machine places the boards, the dust removal machine cleans the board surface, the film is applied, and the automatic board collecting machine collects the boards.

[0055] 4. Double exposure

[0056] The circuit pattern was exposed using a dry film with a thickness of approximately 30µm. Two exposures were performed using an LDI exposure machine, with the line width in the first exposure (circuit design data 1) being 3µm larger than the line width in the second exposure (circuit design data 2). The energy parameters for the first exposure were 5.5 divisions, and for the second exposure, 6 divisions. Figure 2 The image shows the first and second exposure graphic data. It can be seen that the line width of the first exposure graphic data is greater than the line width of the second exposure graphic data.

[0057] The first exposure process is performed in sequence: automatic plate feeding machine places plate, dust removal machine cleans plate surface, exposes front side, automatic flipping machine flips plate, dust removal machine cleans plate surface, exposes back side, and automatic plate collecting machine collects plate.

[0058] Note: The first exposure process uses exposure data 1, with an exposure parameter of energy of 5.5 divisions.

[0059] The second exposure process is performed in sequence: automatic plate feeding machine places plate, dust removal machine cleans plate surface, exposes the front side, automatic flipping machine flips plate, dust removal machine cleans plate surface, exposes the back side, and automatic plate collecting machine collects plate.

[0060] The same exposure machine was used for both the first and second exposures, and an automatic expansion / contraction mode was employed.

[0061] Note: The first exposure process uses exposure data 2, with an exposure parameter of energy of 6 bars.

[0062] Using the above two-exposure process in this embodiment, the dry film adhesion in the second-exposure area is stronger, and the developing and etching solutions are difficult to penetrate. After the second exposure in this embodiment, the dry film is soaked in alkaline solution, and the dry film peeling time is longer, and the tolerance of the dry film pattern line is within ±5%.

[0063] 5. Development

[0064] The specific process is as follows: the automatic plate feeder places the plates, the developing machine develops them, the washing machine washes them, and the plates are then ejected.

[0065] 6. Vacuum etching lines

[0066] The process is divided into three sections: pre-etching, main etching, and fine etching. Each section uses an independent chemical tank and pump, with controllable pressure and temperature. All sections employ an etching equipment structure combining spraying and circulating tanks, and the specific etching equipment utilizes existing vacuum etching line processes. The etching solutions used in the pre-etching, main etching, and fine etching sections are all based on a copper chloride-hydrochloric acid system.

[0067] 7. Repair section

[0068] The micro-etching solution uses a sodium persulfate-sulfuric acid system, with a sodium persulfate concentration of 60–80 g / L and a sulfuric acid concentration of 10–20 mL / L. The re-etching section also uses an independent chemical tank and pump, with controllable pressure and temperature. The etching equipment structure combines spraying and circulation tanks, and the specific etching equipment follows the existing vacuum etching line process equipment.

[0069] The specific etching process for the re-etching section is as follows: The etched circuit burrs are then rinsed a second time using a micro-etching solution to reduce their size. Specifically: board exiting the fine etching section, board entering the re-etching section, micro-etching the circuit burrs in the re-etching section, board exiting the re-etching section, and water rinsing. Re-etching section parameters: Pressure 2.8 kg / cm². 2 Temperature: 50℃.

[0070] Figure 3The diagram shows a process flow chart for the etching section (vacuum etching line + re-etching section).

[0071] Through the etching steps (6) and (7), the burrs on the circuit are precisely and stably controlled to ≤5µm, and the etched circuit is almost free of bevel burrs. The tolerance of the etched circuit is approximately ±5%, and the etching factor is >5.

[0072] 8. Remove the film.

[0073] The specific process is as follows: board loading, expansion, film removal 1, film removal 2, water washing, and drying.

[0075] In summary, this invention mainly addresses the problem of unstable burr control in PCB circuit production. It finds a suitable technical method for controlling burrs in high-speed, high-frequency PCB circuit production processes. Through material selection, circuit pattern design, and process design production control technology, it ultimately achieves precise and stable control of circuit burrs ≤5um.

[0076] The above specific embodiments further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above are merely specific embodiments of the present invention and are not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for controlling burrs on high-speed, high-frequency PCB circuit boards, characterized in that, This includes polishing the copper surface of incoming materials during the production of high-speed, high-frequency PCB circuit boards, performing two exposures after film lamination, and adding a re-etching process after vacuum etching lines following development.

2. The method for controlling burrs on high-speed, high-frequency PCB circuit boards according to claim 1, characterized in that, The incoming material is selected as reverse copper foil, and the copper surface polishing is performed by polishing the rough surface of the reverse copper foil with a non-woven brush.

3. The method for controlling burrs on high-speed, high-frequency PCB circuit boards according to claim 1, characterized in that, The non-woven fabric brush is provided in two sets, using 1500-mesh non-woven fabric brushes.

4. The method for controlling burrs on high-speed, high-frequency PCB circuits according to claim 1, characterized in that, The polishing process consists of sequentially feeding plates with an automatic plate feeder, acid washing, water washing, plate polishing, water washing, and drying. The plate polishing uses a 1500-mesh non-woven fabric brush.

5. The method for controlling burrs on high-speed, high-frequency PCB circuit boards according to claim 1, characterized in that, When exposing the film twice, a dry film with a thickness of 30μm was used. The width of the circuit design data in the first exposure was 3μm larger than the width of the circuit design data in the second exposure. The exposure parameter energy was 5.5 divisions in the first exposure and 6 divisions in the second exposure.

6. The method for controlling burrs on high-speed, high-frequency PCB circuit boards according to claim 1, characterized in that, The first and second exposures were performed using the same exposure machine with automatic expansion and contraction mode.

7. The method for controlling burrs on high-speed, high-frequency PCB circuit boards according to claim 1, characterized in that, The vacuum etching line processing is divided into three stages, with etching solution added in each stage and micro-etching solution added in the re-etching stage.

8. A method for controlling burrs on high-speed, high-frequency PCB circuit boards according to claim 7, characterized in that, The etching process consists of a pre-etching stage, a main etching stage, and a fine etching stage, and the etching solution is a copper chloride-hydrochloric acid system. And / or, the micro-etching solution is a sodium persulfate-sulfuric acid system, and the process of the repair etching section is to perform a secondary rinsing process on the etched line burrs using the micro-etching solution to reduce the line burrs.

9. A high-speed, high-frequency PCB board circuit manufacturing process, characterized in that, This includes copper surface polishing of incoming materials, medium roughening pretreatment, film application, double exposure, development, vacuum etching lines, re-etching sections, and film removal.

10. The high-speed, high-frequency PCB board circuit manufacturing process according to claim 9, characterized in that, The roughening pretreatment process consists of sequentially placing the plate, acid washing, water washing, grinding and polishing, water washing, and drying.

Images