Semiconductor structure and method of manufacturing the same, storage system

Abstract

The disclosure provides a semiconductor structure and a preparation method thereof and a storage system, and relates to the technical field of semiconductor chips. The semiconductor structure comprises a plurality of gate isolation structures and a first gate stack structure, a first dielectric stack structure and a second gate stack structure arranged in sequence along a first direction. The plurality of gate isolation structures comprises a first gate isolation structure and a second gate isolation structure arranged adjacent to and spaced apart from each other along the first direction. The first gate isolation structure penetrates the first gate stack structure along a second direction, and the second gate isolation structure penetrates the second gate stack structure along the second direction. The size of the first dielectric stack structure in a third direction is greater than the size of the first gate isolation structure in the third direction and greater than the size of the second gate isolation structure in the third direction. Isolating the first gate stack structure and the second gate stack structure by the first dielectric stack structure is conducive to reducing the proportion of conductive materials, thereby improving the coupling problem between the conductive materials.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor chip technology, and in particular to a semiconductor structure, its fabrication method, and a storage system. Background Technology

[0002] As the feature size of memory cells approaches the lower limit of the process, planar processes and manufacturing technologies become challenging and costly, causing the storage density of 2D or planar NAND flash memory to approach its upper limit.

[0003] To overcome the limitations of 2D or planar NAND flash memory, the industry has developed memory with a three-dimensional structure (3D NAND), which increases storage density by arranging storage cells three-dimensionally on a substrate. Summary of the Invention

[0004] Embodiments of this disclosure provide a semiconductor structure, a method for fabricating the same, and a memory system.

[0005] The embodiments of this disclosure adopt the following technical solutions:

[0006] On one hand, some embodiments of this disclosure provide a semiconductor structure, including: a plurality of gate isolation structures and a first gate stack structure, a first dielectric stack structure, and a second gate stack structure arranged sequentially along a first direction. The first gate stack structure includes a plurality of first gate layers and a plurality of first dielectric layers alternately stacked along a second direction. The second gate stack structure includes a plurality of second gate layers and a plurality of second dielectric layers alternately stacked along the second direction. The first dielectric stack structure includes a plurality of third dielectric layers and a plurality of fourth dielectric layers alternately stacked along the second direction. The plurality of gate isolation structures include a first gate isolation structure and a second gate isolation structure arranged adjacent to and spaced apart along the first direction. The first gate isolation structure penetrates the first gate stack structure along the second direction, and the second gate isolation structure penetrates the second gate stack structure along the second direction. The dimension of the first dielectric stack structure in a third direction is greater than the dimension of the first gate isolation structure in the third direction, and the dimension of the first dielectric stack structure in the third direction is greater than the dimension of the second gate isolation structure in the third direction. The first direction intersects the second direction, and the third direction intersects the plane containing the first direction and the second direction.

[0007] In some embodiments, the third dielectric layer is adjacent to the first gate layer along the first direction, and the third dielectric layer is adjacent to the second gate layer along the first direction, the third dielectric layer has an end in the third direction, and at least a portion of the width of the third dielectric layer in the first direction is smaller than the width of the end in the first direction.

[0008] In some embodiments, the third dielectric layer has two sidewalls disposed opposite to each other along the first direction, and the edges of the sidewalls include arcuate edges.

[0009] In some embodiments, the third dielectric layer is adjacent to the first gate layer along the first direction, and the third dielectric layer is adjacent to the second gate layer along the first direction, wherein the dimension of the third dielectric layer in the first direction is greater than 3 μm.

[0010] In some embodiments, the gate isolation structure includes a first sub-isolation structure, a second sub-isolation structure, and an isolation layer. The length of the second sub-isolation structure along its extension direction is greater than the length of the first sub-isolation structure along its extension direction. The first sub-isolation structure and the second sub-isolation structure are spaced apart. The isolation layer is disposed around the first sub-isolation structure and around the second sub-isolation structure. The isolation layer is also located between the first sub-isolation structure and the second sub-isolation structure. On a plane parallel to the first direction and the third direction, the first sub-isolation structure, the second sub-isolation structure, and the isolation layer form a closed pattern.

[0011] In some embodiments, the first sub-isolation structure extends along the third direction.

[0012] In some embodiments, the plurality of gate isolation structures further includes a third gate isolation structure, which is located on the side of the first gate isolation structure opposite to the second gate isolation structure, and the third gate isolation structure and the first gate isolation structure share a portion of the structure.

[0013] In some embodiments, the semiconductor structure further includes a second dielectric stack structure, the second dielectric stack structure including a plurality of fifth dielectric layers and a plurality of sixth dielectric layers alternately stacked along the second direction, the first gate stack structure being disposed around the second dielectric stack structure, and the first gate isolation structure being disposed around the second dielectric stack structure.

[0014] In some embodiments, the semiconductor structure further includes: a plurality of channel structures, at least one of the channel structures penetrating the first gate stack structure along the second direction, at least one of the channel structures penetrating the second gate stack structure along the second direction, and at least one of the channel structures penetrating the first dielectric stack structure along the second direction.

[0015] In some embodiments, the semiconductor structure further includes: a plurality of support pillars arranged in multiple rows and columns, wherein the support pillars penetrate the first dielectric stack structure along the second direction.

[0016] In some embodiments, the first dielectric layer, the second dielectric layer, and the fourth dielectric layer are made of the same material.

[0017] On the other hand, some embodiments of this disclosure also provide a method for fabricating a semiconductor structure, including: forming a first gate stack structure, a first dielectric stack structure, and a second gate stack structure arranged sequentially along a first direction, wherein the first gate stack structure includes a plurality of first gate layers and a plurality of first dielectric layers alternately stacked along a second direction, the second gate stack structure includes a plurality of second gate layers and a plurality of second dielectric layers alternately stacked along the second direction, and the first dielectric stack structure includes a plurality of third dielectric layers and a plurality of fourth dielectric layers alternately stacked along the second direction; forming a plurality of gate isolation structures, wherein the plurality of gate isolation structures include a first gate isolation structure and a second gate isolation structure arranged adjacent to and spaced apart along the first direction, the first gate isolation structure penetrates the first gate stack structure along the second direction, the second gate isolation structure penetrates the second gate stack structure along the second direction, the dimension of the first dielectric stack structure in a third direction is greater than the dimension of the first gate isolation structure in the third direction, and the dimension of the first dielectric stack structure in the third direction is greater than the dimension of the second gate isolation structure in the third direction; wherein the first direction intersects the second direction, and the third direction intersects the plane containing the first direction and the second direction.

[0018] In some embodiments, forming a first gate stack structure, a first dielectric stack structure, and a second gate stack structure arranged sequentially along a first direction includes: forming a dielectric stack structure, the dielectric stack structure including a plurality of dielectric layers and a plurality of sacrificial layers alternately stacked along a second direction; forming a plurality of gate slots, the plurality of gate slots being spaced apart along the first direction and penetrating the dielectric stack structure along the second direction; removing a portion of the sacrificial layer through the gate slots to form a filling space; and filling the filling space with conductive material to form the first gate layer and the second gate layer.

[0019] In some embodiments, forming a plurality of gate spacers includes: forming a plurality of vias spaced apart and penetrating the dielectric stack structure along the second direction; connecting some of the vias to form a first spacer and a second spacer, the first spacer and the second spacer being spaced apart along the third direction, and a portion of the vias being located between the first spacer and the second spacer; filling the first spacer and the second spacer with a sacrificial material; connecting the vias located between the first spacer and the second spacer to form a third spacer, the first spacer, the second spacer and the third spacer forming a closed pattern, the first spacer, the second spacer and the third spacer together constituting the gate spacer.

[0020] In some embodiments, forming a plurality of gate isolation structures includes: sequentially forming a first isolation layer and a first sub-isolation structure in the third partition, wherein the first isolation layer is disposed around the first sub-isolation structure; removing the sacrificial material; sequentially forming a second isolation layer and a second sub-isolation structure in the first partition and the second partition, wherein the second isolation layer is disposed around the second sub-isolation structure, wherein the first isolation layer, the second isolation layer, the first sub-isolation structure and the second sub-isolation structure together constitute the gate isolation structure.

[0021] In another aspect, a storage system is provided, comprising the semiconductor structure and controller as described above. The controller is coupled to the semiconductor structure to control the semiconductor structure to store data. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0023] Figure 1 A cross-sectional view of a three-dimensional memory provided for some embodiments of this disclosure;

[0024] Figure 2 A top view of a semiconductor structure provided for some embodiments of this disclosure. Figure 1 ;

[0025] Figure 3 A cross-sectional view of a semiconductor structure provided for some embodiments of this disclosure;

[0026] Figure 4A top view of a semiconductor structure provided for some embodiments of this disclosure. Figure 2 ;

[0027] Figure 5 for Figure 4 AA section diagram;

[0028] Figure 6 A top view of a semiconductor structure provided for some embodiments of this disclosure. Figure 3 ;

[0029] Figure 7 A method flow for fabricating a semiconductor structure provided in some embodiments of this disclosure Figure 1 ;

[0030] Figure 8 This is a schematic diagram of the structure after forming a dielectric stack structure according to some embodiments of this disclosure;

[0031] Figure 9 A method flow for fabricating a semiconductor structure provided in some embodiments of this disclosure Figure 2 ;

[0032] Figure 10 This is a schematic diagram of the structure after forming a through hole, provided in some embodiments of this disclosure;

[0033] Figure 11 This is a schematic diagram of the structure after the formation of the channel structure provided in some embodiments of this disclosure;

[0034] Figure 12 This is a schematic diagram of the structure after the formation of the first and second partitions provided in some embodiments of this disclosure;

[0035] Figure 13 This is a schematic diagram of the structure after filling with a second sacrificial material, provided in some embodiments of this disclosure;

[0036] Figure 14 This is a schematic diagram of the structure after forming the first sub-isolation structure according to some embodiments of this disclosure;

[0037] Figure 15 This is a schematic diagram of the structure after removing the second sacrificial material, provided for some embodiments of this disclosure;

[0038] Figure 16 This is a schematic diagram of the structure after the formation of the first filling space, provided by some embodiments of this disclosure;

[0039] Figure 17 This is a schematic diagram of the structure after the formation of the third sacrificial material, provided for some embodiments of this disclosure;

[0040] Figure 18This is a schematic diagram of the structure after the formation of the second filling space, provided for some embodiments of this disclosure;

[0041] Figure 19 This is a schematic diagram of the structure after the filling space is formed, provided for some embodiments of this disclosure;

[0042] Figure 20 This is a schematic diagram of the structure after the gate layer is formed, provided in some embodiments of this disclosure;

[0043] Figure 21 Framework of storage systems provided for some embodiments of this disclosure Figure 1 ;

[0044] Figure 22 Framework of storage systems provided for some embodiments of this disclosure Figure 2 .

[0045] Figure Descriptions: 200, Semiconductor structure; X, First direction; Y, Second direction; Z, Third direction; 210, First gate stack structure; 211, First gate layer; 212, First dielectric layer; 220, First dielectric stack structure; 221, Third dielectric layer; 2211, End; 2212, Sidewall; 22121, Arc edge; 222, Fourth dielectric layer; 230, Second gate stack structure; 231, Second gate layer; 232, Second dielectric layer; 240, Gate isolation structure; 2401, First gate isolation structure; 2402, Second gate isolation structure; 2403, Third gate isolation structure; 241, First sub-isolation structure; 2 42. Second sub-isolation structure; 243. Isolation layer; 2431. First isolation layer; 2432. Second isolation layer; 250. Channel structure; 260. Second dielectric stack structure; 261. Fifth dielectric layer; 262. Sixth dielectric layer; 270. Support pillar; 300. Dielectric stack structure; 310. Dielectric layer; 320. Sacrificial layer; 330. Gate trench; 331. First trench; 332. Second trench; 333. Third trench; 340. Fill space; 341. First fill space; 342. Second fill space; 350. Through-hole; 361. First sacrificial material; 362. Second sacrificial material; 363. Third sacrificial material. Detailed Implementation

[0046] In the description of this disclosure, it should be understood that the terms "upper", "lower", "front", "rear", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure.

[0047] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary," or "some examples" are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0048] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0049] In describing some embodiments, the term "connection" and its derivative expressions may be used. For example, the term "connection" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0050] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0051] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0052] The use of “applies to” or “configured to” in this article implies an open and inclusive language that does not preclude applicability to or configuration to devices that perform additional tasks or steps.

[0053] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0054] In this disclosure, the meanings of “on,” “above,” and “above” should be interpreted in the broadest possible sense, such that “on” means not only “directly on” something, but also includes “on” something with intermediate features or layers in between, and “above” or “above” means not only “above” or “above” something, but also “above” or “above” something without intermediate features or layers in between (i.e., directly on something).

[0055] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched regions shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0056] As used herein, the term "substrate" refers to a material on which subsequent material layers can be added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic, or sapphire wafer.

[0057] The term "three-dimensional memory" refers to a semiconductor structure formed by strings of memory cell transistors (referred to herein as "memory cell strings," such as NAND memory cell strings) arranged in an array on the main surface of a substrate or source layer and extending in a direction perpendicular to the substrate or source layer. As used herein, the term "vertical / perpendicularly" means nominally perpendicular to the main surface of the substrate or source layer (i.e., the lateral surface).

[0058] Figure 1 This is a cross-sectional view of a three-dimensional memory according to some embodiments. It should be noted that... Figure 1 In this context, the three-dimensional memory 10 is located in the XYZ three-dimensional coordinate system and extends in the XZ plane. The first direction X and the third direction Z are, for example, two orthogonal directions in the plane where the semiconductor structure 200 is located (e.g., the plane where the source layer SL is located): the first direction X is, for example, the extension direction of the bit line, and the third direction Z is, for example, the extension direction of the word line. The second direction Y is perpendicular to the plane where the semiconductor structure 200 is located, that is, perpendicular to the XZ plane.

[0059] As used in embodiments of this disclosure, whether a component (e.g., a layer, structure, or device) is "on," "above," or "below" another component (e.g., a layer, structure, or device) of a semiconductor structure (e.g., a three-dimensional memory) is determined relative to the substrate or source layer of the semiconductor structure in the third direction Z, when the substrate or source layer SL is located in the lowest plane of the semiconductor structure in the third direction Z. The same concepts are applied throughout the embodiments of this disclosure to describe spatial relationships.

[0060] In order to show the structure of the device more clearly, in Figure 1 The image shows a view of the core region CA and a view of the connecting region SS. The view of the core region CA is based on the left coordinate system, while the view of the connecting region SS is based on the right coordinate system. That is, the view of the core region CA shows the cross-sectional structure along the Z direction, while the view of the connecting region SS shows the cross-sectional structure along the X direction.

[0061] See Figure 1 Some embodiments of this disclosure provide a three-dimensional memory 10. The three-dimensional memory 10 may include a semiconductor structure 200. The semiconductor structure 200 may include a source layer SL and an array interconnect layer 290. The three-dimensional memory 10 may also include peripheral devices 100 coupled to the semiconductor structure 200. The peripheral devices 100 may be disposed on the side of the array interconnect layer 290 away from the source layer SL.

[0062] The source layer SL may include a semiconductor material, such as single-crystal silicon, single-crystal germanium, group III-V compound semiconductor materials, group II-VI compound semiconductor materials, and other suitable semiconductor materials. The source layer SL may be partially or completely doped. For example, the source layer SL may include doped regions doped with p-type dopant. The source layer SL may also include undoped regions.

[0063] Semiconductor structure 200 may include arrayed strings of memory cell transistors (referred to herein as “memory cell string 400”, such as NAND memory cell strings). Source layer SL may be coupled to the source ends of multiple memory cell strings 400.

[0064] See also Figure 1 In some embodiments, the array interconnect layer 290 may be coupled to the memory cell string 400. The array interconnect layer 290 may include the drain (i.e., bit line) of the memory cell string 400, which may be coupled to the semiconductor channel of at least one transistor in the memory cell string 400.

[0065] The array interconnect layer 290 may include one or more first interlayer insulating layers 292, and may also include a plurality of contacts insulated from each other by these first interlayer insulating layers 292. The contacts may include, for example, bit line contacts BL-CNT coupled to bit lines; drain select gate contacts coupled to drain select gates; and gate line contacts 293 coupled to gate layer 203. The array interconnect layer 290 may also include one or more first interconnect conductor layers 291. The first interconnect conductor layer 291 may include a plurality of interconnect lines, such as bit lines, and word line interconnect lines coupled to word lines. The materials of the first interconnect conductor layers 291 and the contacts may include conductive materials, such as tungsten, cobalt, copper, aluminum, and one or more combinations of metal silicides, and may also include other suitable materials. The material of the first interlayer insulating layer 292 is an insulating material, such as silicon oxide, silicon nitride, and one or more combinations of high dielectric constant insulating materials, or may also include other suitable insulating materials.

[0066] Peripheral device 100 may include peripheral circuitry. The peripheral circuitry is configured to control and sense the array device. The peripheral circuitry may be any suitable digital, analog, and / or mixed-signal control and sensing circuitry used to support the operation (or function) of the array device (e.g., semiconductor structure 200), including but not limited to page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), charge pumps, current or voltage references, or any active or passive components of the circuitry (e.g., transistors, diodes, resistors, or capacitors). The peripheral circuitry may also include any other circuitry compatible with advanced logic processes, including logic circuitry (e.g., processors and programmable logic devices (PLDs)) or memory circuitry (e.g., static random-access memory (SRAM)).

[0067] For example, in some embodiments, peripheral device 100 may include substrate 110, transistor 120 disposed on substrate 110, and peripheral interconnect layer 130 disposed on substrate 110. Peripheral circuitry may include transistor 120.

[0068] The substrate 110 may be made of monocrystalline silicon or other suitable materials, such as silicon-germanium, germanium or silicon-on-insulator thin film.

[0069] The peripheral interconnect layer 130 is coupled to the transistor 120 to transmit electrical signals between the transistor 120 and the peripheral interconnect layer 130. The peripheral interconnect layer 130 may include one or more second interlayer insulating layers 131, and may also include one or more second interconnect conductor layers 132. Different second interconnect conductor layers 132 may be coupled to each other via contacts. The materials of the second interconnect conductor layers 132 and the contacts may include conductive materials, such as tungsten, cobalt, copper, aluminum, and combinations of one or more metal silicides, or other suitable materials. The material of the second interlayer insulating layer 131 includes insulating materials, such as silicon oxide, silicon nitride, and combinations of one or more high dielectric constant insulating materials, or other suitable materials.

[0070] The peripheral interconnect layer 130 can be coupled to the array interconnect layer 290, enabling coupling between the semiconductor structure 200 and the peripheral device 100. In some examples, because the peripheral interconnect layer 130 is coupled to the array interconnect layer 290, peripheral circuitry in the peripheral device 100 can be coupled to the memory cell string in the semiconductor structure 200 to enable the transmission of electrical signals between the peripheral circuitry and the memory cell string. In some possible implementations, an bonding interface 500 can be provided between the peripheral interconnect layer 130 and the array interconnect layer 290, allowing the peripheral interconnect layer 130 and the array interconnect layer 290 to be bonded and coupled together.

[0071] In this embodiment, the semiconductor structure 200 may include multiple memory arrays. To facilitate partitioned read / write operations, the memory arrays are spaced apart, and each memory array includes a string of memory cell transistors arranged in an array. Currently, to increase storage capacity without changing the size of the semiconductor structure 200, or to further reduce the size of the semiconductor structure 200, adjacent memory arrays are isolated only by a gate isolation structure. When one memory array is performing a read / write operation, the conductive material between adjacent memory arrays makes coupling likely, thus affecting the read / write operations. Furthermore, as the number of memory cells in the memory array increases, the voltage of the read / write operation increases, further exacerbating the adverse effects of coupling between adjacent memory arrays.

[0072] Based on this, some embodiments of this disclosure also provide a semiconductor structure 200, which can serve as the semiconductor structure 200 in the aforementioned three-dimensional memory 10, or the semiconductor structure 200 can serve as the aforementioned three-dimensional memory 10. The following description, in conjunction with... Figures 2 to 20 The semiconductor structure 200 in some embodiments will be explained and described.

[0073] Figure 2This is a top view of a semiconductor structure provided for some embodiments of this disclosure. Figure 3 This is a cross-sectional view of a semiconductor structure provided for some embodiments of this disclosure. (See also:) Figure 2 and Figure 3 In some embodiments of this disclosure, three directions are defined, wherein the first direction X intersects with the second direction Y, and the third direction Z intersects in the plane containing the first direction X and the second direction Y. For ease of understanding, in the embodiments of this disclosure, the semiconductor structure 200 is explained by taking the example that the first direction X, the second direction Y, and the third direction Z are mutually perpendicular.

[0074] Continue to refer to Figure 2 and Figure 3 In some embodiments, the semiconductor structure 200 includes: a first gate stack structure 210, a first dielectric stack structure 220 and a second gate stack structure 230 arranged sequentially along a first direction X, and a plurality of gate isolation structures 240.

[0075] The first gate stack structure 210 includes a plurality of first gate layers 211 and a plurality of first dielectric layers 212 alternately stacked along the second direction Y. Here, "alternating stacking" means that the first gate layers 211 and the first dielectric layers 212 are stacked and arranged alternately. For example, along the direction from the bottom to the top of the first gate stack structure 210, a first dielectric layer 212 is first disposed, then a first gate layer 211 is disposed on the first dielectric layer 212, and then another first dielectric layer 212 is disposed on the first gate layer 211, and so on, alternatingly, to form the first gate stack structure 210. The specific number of stacked first gate layers 211 / first dielectric layers 212 can be set according to actual conditions.

[0076] Similarly, the second gate stack structure 230 includes a plurality of second gate layers 231 and a plurality of second dielectric layers 232 alternately stacked along the second direction Y. The first dielectric stack structure 220 includes a plurality of third dielectric layers 221 and a plurality of fourth dielectric layers 222 alternately stacked along the second direction Y.

[0077] Both the first gate layer 211 and the second gate layer 231 can be made of conductive materials, including but not limited to one or more combinations of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polycrystalline silicon, doped silicon, and silicides, or other suitable conductive materials.

[0078] The first dielectric layer 212, the second dielectric layer 232, the third dielectric layer 221, and the fourth dielectric layer 222 can all be made of insulating materials. The insulating materials can include one or more of silicon oxide, silicon nitride, silicon oxynitride, and high dielectric constant insulating materials, or other suitable insulating materials.

[0079] In some examples, reference Figure 2 and Figure 3 The third dielectric layer 221 may be adjacent to the first gate layer 211 along the first direction X, and the third dielectric layer 221 may be adjacent to the second gate layer 231 along the first direction X. The fourth dielectric layer 222 may be adjacent to the first dielectric layer 212 along the first direction X, and the fourth dielectric layer 222 may also be adjacent to the second dielectric layer 232 along the first direction X. The composition of the third dielectric layer 221 is different from that of the fourth dielectric layer 222; for example, the composition of the third dielectric layer 221 may include silicon nitride, while the composition of the fourth dielectric layer 222 may include silicon oxide.

[0080] In some examples, reference Figure 2 and Figure 3 The first dielectric layer 212, the second dielectric layer 232, and the fourth dielectric layer 222 can be made of the same material. Furthermore, the first dielectric layer 212, the second dielectric layer 232, and the fourth dielectric layer 222 can be formed in the same fabrication process. For example, a silicon oxide layer is formed by deposition. The silicon oxide layer has a layered structure, with the portion stacked with the first gate layer 211 designated as the first dielectric layer 212, the portion stacked with the second gate layer 231 designated as the second dielectric layer 232, and the portion stacked with the fifth dielectric layer 261 designated as the fourth dielectric layer 222. When the first dielectric layer 212, the second dielectric layer 232, and the fourth dielectric layer 222 are made of the same material, the steps for preparing the first dielectric layer 212, the second dielectric layer 232, and the fourth dielectric layer 222 can be combined to reduce the number of fabrication steps, simplify the fabrication process, improve the fabrication efficiency of the semiconductor structure 200, and reduce production costs.

[0081] The plurality of gate isolation structures 240 include a first gate isolation structure 2401 and a second gate isolation structure 2402 that are adjacent to each other and spaced apart along a first direction X. Since the adjacent first gate isolation structures 2401 and second gate isolation structures 2402 are spaced apart, the first gate isolation structure 2401 and the second gate isolation structure 2402 are disconnected and are not connected to each other.

[0082] The first gate isolation structure 2401 penetrates the first gate stack structure 210 along the second direction Y, and the second gate isolation structure 2402 penetrates the second gate stack structure 230 along the second direction Y. The first gate isolation structure 2401 and the second gate isolation structure 2402 are located on opposite sides of the first dielectric stack structure 220 along the first direction X. The first gate isolation structure 2401 and the first dielectric stack structure 220 are spaced apart in the first direction X, and the second gate isolation structure 2402 and the first dielectric stack structure 220 are also spaced apart in the first direction X.

[0083] Additionally, it should be noted that since the first gate stack structure 210, the first dielectric stack structure 220, and the second gate stack structure 230 are arranged sequentially along the first direction X, and since the first gate isolation structure 2401 and the second gate isolation structure 2402 are two adjacent gate isolation structures 240 along the first direction X, with the first gate isolation structure 2401 penetrating the first gate stack structure 210 and the second gate isolation structure 2402 penetrating the second gate stack structure 230, it indicates that there are no other gate isolation structures 240 between the first gate isolation structure 2401 and the second gate isolation structure 2402, and therefore no gate isolation structure 240 penetrates the first dielectric stack structure 220.

[0084] In this embodiment, reference Figure 2 and Figure 4 The first dielectric stack structure 220 penetrates the first gate stack structure 210 along the third direction Z, and the first dielectric stack structure 220 also penetrates the second gate stack structure 230 along the third direction Z. Therefore, the dimension d1 of the first dielectric stack structure 220 in the third direction Z is greater than the dimension d2 of the first gate isolation structure 2401 in the third direction Z, and the dimension d1 of the first dielectric stack structure 220 in the third direction Z is greater than the dimension d3 of the second gate isolation structure 2402 in the third direction Z. (See reference here.) Figure 2 The first dielectric stack structure 220, the first gate isolation structure 2401, and the second gate isolation structure 2402 can be observed from a top-down angle along the second direction Y. The dimension d1 of the first dielectric stack structure 220 in the third direction Z is the maximum width of the first dielectric stack structure 220 in the third direction Z; the dimension d2 of the first gate isolation structure 2401 in the third direction Z is the maximum width of the first gate isolation structure 2401 in the third direction Z; and the dimension d3 of the second gate isolation structure 2402 in the third direction Z is the maximum width of the second gate isolation structure 2402 in the third direction Z.

[0085] Continue to refer to Figure 2 and Figure 4Since the dimension d1 of the first dielectric stack structure 220 in the third direction Z is greater than the dimension d2 of the first gate isolation structure 2401 in the third direction Z, and the dimension d1 of the first dielectric stack structure 220 in the third direction Z is greater than the dimension d3 of the second gate isolation structure 2402 in the third direction Z, the first dielectric stack structure 220 protrudes from the first gate isolation structure 2401 in the third direction Z, and the first dielectric stack structure 220 also protrudes from the second gate isolation structure 2402 in the third direction Z. Here, the first dielectric stack structure 220 protruding from the first gate isolation structure 2401 in the third direction Z can be understood as the first dielectric stack structure 220 protruding from the reference surface of the first gate isolation structure 2401 in the third direction Z, along the reference surface. Similarly, the first dielectric stack structure 220 protrudes from the end surface of the second gate isolation structure 2402 in the third direction Z. Furthermore, the first gate isolation structure 2401 has two end faces in the third direction Z, and the two ends of the first dielectric stack structure 220 protrude from the two end faces of the first gate isolation structure 2401 in the third direction Z. The second gate isolation structure 2402 also has two end faces in the third direction Z, and the two ends of the first dielectric stack structure 220 protrude from the two end faces of the second gate isolation structure 2402 in the third direction Z.

[0086] Continue to refer to Figure 2 and Figure 4 The first gate isolation structure 2401 can enclose the central region of the semiconductor structure 200; that is, the region enclosed by the first gate isolation structure 2401 is defined as the central region of the semiconductor structure 200. A portion of the first dielectric stack structure 220 is located on the side of the first gate isolation structure 2401 along the third direction Z away from the central region, and the end of the first dielectric stack structure 220 along the third direction Z is located on the side of the first gate isolation structure 2401 along the third direction Z away from the central region. Further, since the first dielectric stack structure 220 is continuous along the third direction Z, it can be determined that the dimension d1 of the first dielectric stack structure 220 along the third direction Z is greater than the dimension d2 of the first gate isolation structure 2401 along the third direction Z because both ends of the first dielectric stack structure 220 along the third direction Z are located on the side of the first gate isolation structure 2401 along the third direction Z away from the central region. For the same reason, it can be determined that the size d1 of the first dielectric stack 220 in the third direction Z is greater than the size d3 of the second gate isolation structure 2402 in the third direction Z because both ends of the first dielectric stack 220 are located on the side of the second gate isolation structure 2402 away from the central region in the third direction Z.

[0087] In addition, continue to refer to Figure 2 and Figure 4 Since the first dielectric stack 220, the first gate isolation structure 2401, and the second gate isolation structure 2402 are all continuous in the third direction Z, the dimensions d1 of the first dielectric stack 220 in the third direction Z can be determined to be greater than d2 of the first gate isolation structure 2401 in the third direction Z, and the dimensions d1 of the first dielectric stack 220 in the third direction Z can be greater than d3 of the second gate isolation structure 2402 in the third direction Z, based on the positions of their ends in the third direction Z. For example, the end edge of the first gate isolation structure 2401 in the third direction Z is located inside the end edge of the first dielectric stack 220 in the third direction Z. For example, the edge of the orthographic projection of the first gate isolation structure 2401 onto the first dielectric stack 220 in the third direction Z is located inside the end edge of the first dielectric stack 220 in the third direction Z. The end edge of the second gate isolation structure 2402 in the third direction Z is located inside the end edge of the first dielectric stack structure 220 in the third direction Z.

[0088] In some examples, the semiconductor structure 200 further includes multiple channel structures 250, some of which penetrate the first gate stack structure 210 along the second direction Y, and some of which penetrate the second gate stack structure 230 along the second direction Y. The channel structures 250 penetrating the first gate stack structure 210 / second gate stack structure 230 can be arranged in an array to form a memory array for storing data. Exemplarily, the channel structure 250 can be generally columnar, for example, an oxide-nitride-oxide-polysilicon (OxiDe-NitriDe-OxiDe-Poly, ONOP) structure can be sequentially stacked. In this case, the material of the channel barrier layer can, for example, include silicon oxide, the material of the memory layer can, for example, include silicon nitride, the material of the tunneling layer can, for example, include silicon oxide, and the material of the channel layer can, for example, include polysilicon. In the above steps, thin film deposition processes such as CVD, PVD, or ALD can also be used to form a filling layer, such as silicon oxide, within the channel holes where the storage layer and channel layer are formed. The channel structure 250 with the channel barrier layer, storage layer, tunneling layer, channel layer, and filling layer can be called an "ONOPO" structure. The first gate layer 211 / second gate layer 231 is used to control the channel structure 250. For example, the semiconductor structure 200 can be divided into a core region CA and a connection region SS adjacent along the third direction Z. The channel structure 250 located in the core region CA can be used to store data. The first gate layer 211 / second gate layer 231 can be led out to the corresponding control circuit in the connection region SS, thereby realizing functions such as read, erase, write, and program.

[0089] In some other embodiments, a portion of the channel structure 250 may be located in the core region CA, and a portion of the channel structure 250 may be located in the connection region SS. The channel structure 250 located in the connection region SS may include a virtual channel structure 250. Of course, in some other embodiments, multiple virtual channel structures 250 may also be located in the core region CA, and this embodiment does not limit this. The virtual channel structure 250 may be the same as or different from the channel structure 250, and this embodiment does not limit this. It should be noted that the virtual channel structure 250 may not actually be used as a storage unit, but rather serves to provide mechanical support and / or load balancing for the semiconductor structure 200.

[0090] Continue to refer to Figure 2 and Figure 3 In this embodiment, since the first dielectric stack structure 220 penetrates the first gate stack structure along the third direction Z and also penetrates the second gate stack structure 230 along the third direction Z, the first dielectric stack structure 220 can isolate the first gate stack structure 210 and the second gate stack structure 230. The first dielectric stack structure 220 is a stack structure formed by alternating third dielectric layer 221 and fourth dielectric layer 222, both of which are made of insulating material. By setting the first dielectric stack structure 220, the use of conductive material can be reduced and the use of insulating material can be increased, which is beneficial to reducing the proportion of conductive material in the semiconductor structure 200, while the insulating material will not couple with the conductive material. When performing read and write operations on the channel structure 250 located in the first gate stack structure 210, the first gate layer 211 will not couple with the third dielectric layer 221 / fourth dielectric layer 222, which is beneficial to improve the coupling of conductive materials in other stack structures to the first gate layer 211. Similarly, when performing read / write operations on the channel structure 250 located in the second gate stack structure 230, the influence of conductive materials in other stack structures on the second gate layer 231 is reduced.

[0091] In addition, the spacing between the first gate layer 211 and the second gate layer 231 in the second direction Y can be adjusted by adjusting the size of the first dielectric stack structure 220 in the first direction X. The spacing between the first gate layer 211 and the second gate layer 231 can be designed according to the requirements, which is beneficial to improve the isolation effect of the first dielectric stack structure 220 on the first gate layer 211 and the second gate layer 231, thereby improving the storage stability of the semiconductor structure 200.

[0092] In some embodiments, reference Figure 2 , Figure 3 and Figure 4The third dielectric layer 221 is adjacent to the first gate layer 211 along the first direction X, and the third dielectric layer 221 is adjacent to the second gate layer 231 along the first direction X. The third dielectric layer 221 has an end 2211 in the third direction Z, and at least a portion of the width d4 of the third dielectric layer 221 in the first direction X is smaller than the width d5 ​​of the end 2211 in the first direction X.

[0093] In this embodiment, the third dielectric layer 221 extends along the third direction Z, and has two ends 2211 in the third direction Z. At least a portion of the width d4 of the third dielectric layer 221 in the first direction X is smaller than the width d5 ​​of the ends 2211 in the first direction X, thus a portion of the sidewall 2212 of the third dielectric layer 221 extending along the third direction Z has a recess in the first direction X. The width d4 of the third dielectric layer 221 at the recess in the first direction X is smaller than the width d5 ​​of the ends 2211 in the first direction X.

[0094] It should be noted that at least a portion of the width d4 of the third dielectric layer 221 in the first direction X is smaller than the width d5 ​​of the end portion 2211 in the first direction X. This can be understood as a portion of the width d4 of the third dielectric layer 221 in the first direction X being smaller than the width d5 ​​of the end portion 2211 in the first direction X.

[0095] Since the third dielectric layer 221 is adjacent to the first gate layer 211 along the first direction X, and the third dielectric layer 221 is adjacent to the second gate layer 231 along the first direction X, at least a portion of the third dielectric layer 221 is recessed inward in the first direction X, which is beneficial to increasing the width of a portion of the first gate layer 211 in the first direction X, and also beneficial to increasing the width of a portion of the second gate layer 231 in the first direction X, thereby improving the storage capacity of the semiconductor structure 200.

[0096] In some embodiments, reference Figure 2 and Figure 4 The third dielectric layer 221 has two sidewalls 2212 disposed opposite to each other along the first direction X, and the edges of the sidewalls 2212 include arcuate edges 22121. Here, the edges of the two sidewalls 2212 disposed opposite to each other along the first direction X of the third dielectric layer 221 can be observed by observing the orthographic projection of the third dielectric layer 221 in the second direction Y. Exemplarily, if the edge of the sidewall 2212 includes an arcuate edge 22121, and the center of the arcuate edge 22121 can be located outside the third dielectric layer 221, then the arcuate edge 22121 is concave inward. In this case, the width of the third dielectric layer 221 located at the arcuate edge 22121 in the first direction X is smaller than the width of the end portion 2211 in the first direction X.

[0097] Since the third dielectric layer 221 is adjacent to the first gate layer 211 along the first direction X, and the third dielectric layer 221 is adjacent to the second gate layer 231 along the first direction X, when the sidewall 2212 of the third dielectric layer 221 includes an arc-shaped edge 22121, and the arc-shaped edge 22121 is recessed inward, it is beneficial to increase the width of part of the first gate layer 211 in the first direction X, and also beneficial to increase the width of part of the second gate layer 231 in the first direction X, thereby improving the storage capacity of the semiconductor structure 200.

[0098] In some embodiments, reference Figure 2 and Figure 4 The third dielectric layer 221 is adjacent to the first gate layer 211 along the first direction X, and the third dielectric layer 221 is adjacent to the second gate layer 231 along the first direction X. The dimension of the third dielectric layer 221 in the first direction X is greater than 3 μm. Here, the dimension of the third dielectric layer 221 in the first direction X can be understood as the width of the third dielectric layer 221 in the first direction X, such as d4 and d5 in some embodiments above. The dimension of the third dielectric layer 221 in the first direction X at any position is greater than 3 μm, for example, d4 is greater than 3 μm and d5 is greater than 3 μm.

[0099] If the dimension of the third dielectric layer 221 in the first direction X is greater than 3 μm, then the spacing between the first gate layer 211 and the second gate layer 231 is greater than 3 μm. Experimental tests show that when the spacing between the first gate layer 211 and the second gate layer 231 is greater than 3 μm, the coupling effect between the first gate layer 211 and the second gate layer 231 is small, which helps to reduce the mutual interference between the first gate stack structure 210 and the second gate stack structure 230, and facilitates independent read and write operations for the first gate stack structure 210 / second gate stack structure 230, thereby improving the storage stability of the semiconductor structure 200.

[0100] In some embodiments, reference Figure 2 and Figure 4 The semiconductor structure 200 includes multiple gate stack structures, such as a first gate stack structure 210 and a second gate stack structure 230. The semiconductor structure 200 may also include other gate stack structures besides the first gate stack structure 210 and the second gate stack structure 230. The semiconductor structure 200 also includes multiple gate isolation structures 240 that penetrate the gate stack structures; for example, a first gate isolation structure 2401 penetrates the first gate stack structure 210, and a second gate isolation structure 2402 penetrates the second gate stack structure 230.

[0101] Continue to refer to Figure 2The gate isolation structure 240 includes a first sub-isolation structure 241, a second sub-isolation structure 242, and an isolation layer 243. The second sub-isolation structure 242 has a longer extension direction than the first sub-isolation structure 241. For example... Figure 2 As shown, the first sub-isolation structure 241 extends along the third direction Z. Therefore, the length of the first sub-isolation structure 241 along its extension direction is the length of the first sub-isolation structure 241 in the third direction Z. Part of the second sub-isolation structure 242 extends along the first direction X, and part of the second sub-isolation structure 242 extends along the third direction Z. Therefore, the length of the second sub-isolation structure 242 along its extension direction is the sum of the length of the second sub-isolation structure 242 in the first direction X and the length of the second sub-isolation structure 242 in the third direction Z.

[0102] The first sub-isolation structure 241 and the second sub-isolation structure 242 are spaced apart. The isolation layer 243 is arranged around the first sub-isolation structure 241 and around the second sub-isolation structure 242. The isolation layer 243 is also located between the first sub-isolation structure 241 and the second sub-isolation structure 242. On a plane parallel to the first direction X and the third direction Z, the first sub-isolation structure 241, the second sub-isolation structure 242 and the isolation layer 243 form a closed shape.

[0103] For example, the constituent material of the isolation layer 243 may include an insulating material, such as silicon oxide. The constituent material of the first sub-isolation structure 241 / second sub-isolation structure 242 may include a semiconductor material, such as polysilicon. The strength of the semiconductor material is greater than that of the isolation material. Distributing the isolation layer 243 around the first sub-isolation structure 241 and around the second sub-isolation structure 242 helps to improve the support strength of the gate isolation structure 240. This allows the gate isolation structure 240 to support the first gate stack structure 210 and the second gate stack structure 230, preventing bending of the first gate stack structure 210 and / or the second gate stack structure 230, thereby improving the structural stability of the semiconductor structure 200.

[0104] refer to Figure 4 It should be noted that a closed figure refers to a figure that is closed in its own dimension, such as a rectangle in a two-dimensional figure.

[0105] In this embodiment, reference Figure 2 and Figure 4 The semiconductor structure 200 includes multiple gate isolation structures 240. On the XZ plane, a first sub-isolation structure 241, a second sub-isolation structure 242, and an isolation layer 243 together enclose a closed pattern. For example, refer to... Figure 4On a plane parallel to the first direction X and the third direction Z, the first gate isolation structure 2401 and the second gate isolation structure 2402 both form a closed pattern.

[0106] With the above configuration, the closed pattern formed by the first sub-isolation structure 241, the second sub-isolation structure 242, and the isolation layer 243 can enclose a region of the gate stack structure. Multiple gate isolation structures 240 can enclose multiple regions of the gate stack structure, so that the semiconductor structure 200 can perform read and write operations in different regions, thereby improving the storage capacity and data processing capacity of the semiconductor structure 200.

[0107] In addition, in this embodiment, on the XZ plane, the first sub-isolation structure 241, the second sub-isolation structure 242, and the isolation layer 243 together enclose a closed shape. At this time, reference... Figure 2 and Figure 4 The maximum dimension d2 of the first gate isolation structure 2401 in the third direction Z is the maximum length of the closed pattern enclosed by the first gate isolation structure 2401 in the third direction Z. In the third direction Z, the first dielectric stack structure 220 is located on the side of the first gate isolation structure 2401 away from the center region of the closed pattern, and it can be determined that the dimension d1 of the first dielectric stack structure 220 in the third direction Z is greater than the maximum dimension d2 of the first gate isolation structure 2401 in the third direction Z.

[0108] In some embodiments, reference Figure 2 and Figure 4 The region within the closed pattern enclosed by the first sub-isolation structure 241, the second sub-isolation structure 242, and the isolation layer 243 may include a core region CA and a connecting region SS adjacent along the third direction Z. The core region CA and the connecting region SS can be described in the preceding embodiments and will not be repeated here.

[0109] In this embodiment, the first sub-isolation structure 241 extends along the third direction Z. Furthermore, the length of the first sub-isolation structure 241 along its extension direction (the third direction Z) is less than the length of the second sub-isolation structure 242 along its extension direction. The core region CA and the connection region SS can be divided by setting the position of the first sub-isolation structure 241. During the fabrication of the semiconductor structure 200, the first sub-isolation structure 241 also serves to isolate the core region CA and the connection region SS during partition etching.

[0110] In some embodiments, reference Figure 4The multiple gate isolation structures 240 also include a third gate isolation structure 2403, which is located on the side of the first gate isolation structure 2401 away from the second gate isolation structure 2402, and is adjacent to the first gate isolation structure 2401. The third gate isolation structure 2403 and the first gate isolation structure 2401 share a portion of the structure.

[0111] refer to Figure 4 The third gate isolation structure 2403 and the first gate isolation structure 2401 share a portion of their structure. This can be understood as a portion of the third gate isolation structure 2403 being reused as a component of the first gate isolation structure 2401, or a portion of the first gate isolation structure 2401 being reused as a component of the third gate isolation structure 2403. For example... Figure 4 The overlapping portion of the two dashed boxes represents the part of the structure shared by the third gate isolation structure 2403 and the first gate isolation structure 2401. This partial structure... Figure 4 The structure located in the two dashed boxes is part of the first gate isolation structure 2401 and also part of the third gate isolation structure 2403.

[0112] With the above configuration, both the first gate isolation structure 2401 and the third gate isolation structure 2403 can enclose a memory region, which helps to reduce the use of semiconductor materials and insulating materials, thus reducing production costs. Furthermore, the memory regions enclosed by the first gate isolation structure 2401 and the third gate isolation structure 2403 are adjacent along the first direction X, greatly compressing the space between adjacent memory regions. This helps to reduce the size of the semiconductor structure 200, or, without changing the size of the semiconductor structure 200, allows for the arrangement of more memory regions, thereby increasing the memory capacity of the semiconductor structure 200.

[0113] In some embodiments, reference Figure 4 and Figure 5 The semiconductor structure 200 further includes a second dielectric stack structure 260. The second dielectric stack structure 260 includes a plurality of fifth dielectric layers 261 and a plurality of sixth dielectric layers 262 alternately stacked along a second direction Y. A first gate stack structure 210 is disposed around the second dielectric stack structure 260, and a first gate isolation structure 2401 is disposed around the second dielectric stack structure 260. Thus, the second dielectric stack structure 260 is located within the area enclosed by the first gate isolation structure 2401, and the second dielectric stack structure 260 is surrounded by the first gate stack structure 210.

[0114] Exemplary examples show that both the fifth dielectric layer 261 and the sixth dielectric layer 262 are composed of insulating materials. The insulating materials can be referred to in the preceding embodiments and will not be repeated here. It is worth noting that the materials of the fifth dielectric layer 261 and the sixth dielectric layer 262 are different; for example, the fifth dielectric layer 261 may be composed of silicon nitride, while the sixth dielectric layer 262 may be composed of silicon oxide. In some examples, the fifth dielectric layer 261 may be adjacent to the first gate layer 211. The sixth dielectric layer 262 may be adjacent to the first dielectric layer 212, and both may have the same material composition.

[0115] In this embodiment, reference Figure 4 In the region enclosed by the first gate isolation structure 2401, not the entire region is a valid storage region. For example, at the end 2211 of the first gate isolation structure 2401 along the third direction Z, which is near the scribe line, a portion of the region enclosed by the first gate isolation structure 2401 is not considered a valid storage region. Therefore, it is not necessary to configure the entire region enclosed by the first gate isolation structure 2401 as the first gate stack structure 210. This configuration helps to reduce the use of metal materials, thereby reducing the production cost of the semiconductor structure 200.

[0116] In some embodiments, reference Figure 2 , Figure 3 , Figure 4 and Figure 5 The semiconductor structure 200 also includes a plurality of channel structures 250. Among the plurality of channel structures 250, at least one channel structure 250 penetrates the first gate stack structure 210 along the second direction Y, at least one channel structure 250 penetrates the second gate stack structure 230 along the second direction Y, and at least one channel structure 250 penetrates the first dielectric stack structure 220 along the second direction Y.

[0117] In some examples, multiple channel structures 250 penetrate the first gate stack structure 210 along the second direction Y and are arranged in an array; multiple channel structures 250 penetrate the second gate layer 231 along the second direction Y and are arranged in an array; multiple channel structures 250 penetrate the first dielectric stack structure 220 along the second direction Y and are arranged in an array.

[0118] The channel structure 250 penetrating the first gate stack structure 210 / second gate stack structure 230 can be used for data storage, while the channel structure 250 penetrating the first dielectric stack structure 220 serves as a virtual channel structure 250 and is not used for data storage. The virtual channel structure 250 and the channel structure 250 can be filled with the same film layer. Through this arrangement, the etching process can be provided with the same etching environment during the formation of the channel vias, which is beneficial for forming multiple channel vias with identical morphologies, thus facilitating the formation of an effective channel structure 250. Therefore, this arrangement helps improve the uniformity of the channel structure 250 morphology, thereby improving the yield of the channel structure 250.

[0119] In some embodiments, reference Figure 6 The semiconductor structure 200 includes multiple channel structures 250 and multiple support pillars 270. Some of the channel structures 250 penetrate the first gate stack structure 210 along the second direction Y and are arranged in an array; some of the channel structures 250 penetrate the second gate stack structure 230 along the second direction Y and are also arranged in an array; the multiple support pillars 270 are arranged in multiple rows and columns, and the support pillars 270 penetrate the first dielectric stack structure 220 along the second direction Y.

[0120] In this embodiment, the supporting pillar 270 is composed of an insulating material, which may include, for example, one or more combinations of silicon oxide, silicon nitride, and high dielectric constant insulating materials, or may include other suitable insulating materials. As described in some of the preceding embodiments, the channel structure 250 can be generally a columnar structure, for example, an oxide-nitride-oxide-polysilicon (OxiDe-NitriDe-OxiDe-Poly, ONOP) structure may be sequentially stacked. The channel structure 250 is composed of insulating and semiconductor materials, and consists of multiple material layers. The supporting pillar 270, however, is a single columnar structure, does not have multiple material layers, and is composed only of insulating material, not semiconductor material. Therefore, the material composition of the supporting pillar 270 differs from that of the channel structure 250. However, the channel holes used to form the channel structure 250 and the holes used to form the support pillars 270 can be formed in the same step, so as to provide the same etching environment for the etching process, thereby facilitating the formation of multiple channel holes with the same morphology, which in turn facilitates the formation of an effective channel structure 250. This arrangement helps to improve the uniformity of the morphology of the channel structure 250, and thus improves the yield of the channel structure 250.

[0121] Furthermore, insulating material can be filled into the holes penetrating the first dielectric stack 220 to form support pillars 270, providing support for the semiconductor structure 200. This arrangement further reduces the proportion of conductive material, which helps reduce coupling effects and their adverse impact on the first gate layer 211 / second gate layer 231. Moreover, reducing the use of semiconductor materials also helps control the production cost of the semiconductor structure 200.

[0122] This disclosure also provides a method for fabricating a semiconductor structure 200 in some embodiments, which will be described below in conjunction with... Figures 7 to 20 The preparation method of a semiconductor structure 200 is explained.

[0123] like Figure 7 As shown, the method for fabricating the semiconductor structure 200 includes: S1 to S2.

[0124] S1. A first gate stack structure, a first dielectric stack structure, and a second gate stack structure are sequentially arranged along a first direction. The first gate stack structure includes a plurality of first gate layers and a plurality of first dielectric layers alternately stacked along a second direction. The second gate stack structure includes a plurality of second gate layers and a plurality of second dielectric layers alternately stacked along a second direction. The first dielectric stack structure includes a plurality of third dielectric layers and a plurality of fourth dielectric layers alternately stacked along a second direction.

[0125] In this step, refer to Figure 8 A dielectric stack structure 300 can be formed first, comprising a plurality of dielectric layers 310 and a plurality of sacrificial layers 320 alternately stacked along a second direction Y. Exemplarily, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof can be used to alternately form the dielectric layers 310 and sacrificial layers 320 on a substrate to form the dielectric stack structure 300. The second direction Y is the stacking direction of the dielectric layers 310 and the sacrificial layers 320.

[0126] For example, the material of the dielectric layer 310 may include oxides, and the material of the sacrificial layer 320 may include nitrides.

[0127] For example, the substrate can be a single-crystal silicon (Si) substrate, a single-crystal germanium (Ge) substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate, etc. Alternatively, the substrate material can also be a compound semiconductor. For example, the substrate can be a gallium arsenide (GaAs) substrate, an indium phosphide (InP) substrate, or a silicon carbide (SiC) substrate, etc. Alternatively, the substrate can also be made of other semiconductor materials commonly used in the art, which is not limited in this embodiment.

[0128] In this embodiment, the substrate can provide support for the fabrication of the first stacked structure, and alternatively, the substrate can be removed in a subsequent fabrication process.

[0129] After the dielectric stack structure 300 is formed, for example, a dry etching process or a wet etching process can be used to remove part of the dielectric stack structure 300 to form a plurality of gate spacers 330. The plurality of gate spacers 330 are spaced apart along the first direction X, and the gate spacers 330 penetrate the dielectric stack structure 300 along the second direction Y.

[0130] In some embodiments, reference Figure 9 The method steps for forming multiple gate spacers 330 may include: S11 to S16.

[0131] S11. Multiple through holes are formed, with the multiple through holes spaced apart, and the through holes penetrate the dielectric stacked structure along the second direction.

[0132] In this step, refer to Figure 10 For example, a dry etching process or a wet etching process can be used to remove part of the dielectric stack structure 300 to form multiple vias 350. The vias 350 penetrate the dielectric stack structure 300 along the second direction Y, and the multiple vias 350 are spaced apart.

[0133] refer to Figure 10 and Figure 11 After forming multiple vias 350, a channel structure 250 can be formed within some of the vias 350 using CVD, PVD, ALD, or any combination thereof thin film deposition processes, while retaining the vias 350 for the gate spacer 330. After forming the channel structure 250, the remaining vias 350 can be filled with a first sacrificial material 361.

[0134] S12. Connect some of the through holes to form a first partition and a second partition. The first partition and the second partition are spaced apart along a third direction, and some of the through holes are located between the first partition and the second partition.

[0135] In this step, refer to Figure 11 and Figure 12Etching fluid can be injected into a portion of the through-hole 350 to enlarge the diameter of the through-hole 350, thereby connecting the through-holes 350 to form a first partition 331 and a second partition 332. The first partition 331 and the second partition 332 are spaced apart along a third direction Z, and the through-hole 350 is located between the first partition 331 and the second partition 332.

[0136] It should be noted that before injecting the etchant into part of the through hole 350, the first sacrificial material 361 in part of the through hole 350 can be removed.

[0137] In addition, in this step, multiple first partitions 331 and multiple second partitions 332 can be formed. The multiple first partitions 331 can be spaced apart along the first direction X, and the multiple second partitions 332 can be spaced apart along the first direction X. The multiple first partitions 331 and the multiple second partitions 332 are arranged in a one-to-one correspondence. At least two first partitions 331 that are adjacent along the first direction X are not connected to each other.

[0138] S13. Fill the first and second compartments with sacrificial material.

[0139] In this step, refer to Figure 12 and Figure 13 After the first septum 331 and the second septum 332 are formed, a second sacrificial material 362 can be filled into the first septum 331 and the second septum 332 using CVD, PVD, ALD or any combination thereof thin film deposition process.

[0140] S14. Connect the through hole located between the first and second partitions to form a third partition. The first, second, and third partitions form a closed pattern. The first, second, and third partitions together constitute the gate partition.

[0141] In this step, refer to Figure 12 and Figure 13After the second sacrificial material 362 is filled into the first and second partitions 331 and 332, the aperture of the through hole 350 located between the first and second partitions 331 and 332 can be enlarged, thereby connecting the through hole 350 between the first and second partitions 331 and forming a third partition 333. The third partition 333 can expose a portion of the second sacrificial material 362 filled in the first partition 331, and also expose a portion of the second sacrificial material 362 filled in the second partition 332. The first partition 331, the third partition 333, and the second partition 332 are sequentially connected, and the first partition 331, the second partition 332, and the third partition 333 together form a closed pattern and constitute a gate partition 330. Furthermore, in the preceding steps, multiple first partitions 331, multiple second partitions 332, and multiple third partitions 333 can be formed, so in this step, multiple gate partitions 330 can be formed. Moreover, at least two adjacent gate partitions 330 along the first direction X are not connected to each other.

[0142] It should be noted that the first partition 331, the second partition 332 and the third partition 333 together enclose a closed figure, meaning that on the XZ plane, the edges of the first partition 331, the second partition 332 and the third partition 333 are closed figures.

[0143] S15. Part of the sacrificial layer is removed through the gate trench to form a filling space.

[0144] In this step, refer to Figure 14 , Figure 15 , Figure 16 and Figure 17 The sacrificial layer 320 can be partially removed by passing through the gate trench 330 in different regions. For example, a first isolation layer 2431 and a first sub-isolation structure 241 can be sequentially formed in the third trench 333 using CVD, PVD, ALD or any combination thereof thin film deposition process, thereby blocking the first trench 331 and the second trench 332, so as to facilitate the subsequent removal of the sacrificial layer 320 in different regions.

[0145] refer to Figure 15 and Figure 16 A wet etching process can be used, first removing part of the sacrificial layer 320 through the first septum 331 to form the first filling space 341. (Reference) Figure 15 and Figure 16 Furthermore, a third sacrificial material 363 is filled in the first filling space 341 using, for example, CVD, PVD, ALD or any combination thereof thin film deposition processes.

[0146] refer to Figure 17 and Figure 18A wet etching process can be used to remove part of the sacrificial layer 320 through the second septum 332 to form the second filling space 342. (Continue to refer to...) Figure 17 , Figure 18 and Figure 19 The third sacrificial material 363 located in the first filling space 341 is removed, and the first filling space 341 and the second filling space 342 together constitute the filling space 340.

[0147] In this step, the same process can be performed on multiple gate spacers 330 in the same step so that the first gate layer 211 and the second gate layer 231 can be formed together in subsequent steps.

[0148] S16. Fill the filling space with conductive material to form a first gate layer and a second gate layer.

[0149] refer to Figure 19 and Figure 20 In this step, CVD, PVD, ALD or any combination thereof thin film deposition processes can be used to fill the filling space 340 with conductive material, such as metal material, to form the first gate layer 211 and the second gate layer 231.

[0150] Through the above steps, after partially replacing the sacrificial layer 320 with the first gate layer 211 and partially replacing the sacrificial layer 320 with the second gate layer 231, multiple first gate layers 211 and multiple dielectric layers are alternately stacked along the second direction Y to form a first gate stack structure 210, and multiple second gate layers 231 and multiple dielectric layers are alternately stacked along the second direction Y to form a second gate stack structure 230. In the first direction X, the dielectric stack structure located between the first gate stack structure 210 and the second gate stack structure 230 serves as the first dielectric stack structure 220, thereby isolating the first gate stack structure 210 and the second gate stack structure 230, reducing the proportion of conductive material in the semiconductor structure 200, improving the coupling effect between adjacent memory regions, and thus improving the memory stability of the semiconductor structure 200.

[0151] S2. Forming multiple gate isolation structures, including a first gate isolation structure and a second gate isolation structure that are adjacent and spaced apart along a first direction. The first gate isolation structure penetrates the first gate stack structure along a second direction, and the second gate isolation structure penetrates the second gate stack structure along the second direction. The dimension of the first dielectric stack structure in the third direction is greater than the dimension of the first gate isolation structure in the third direction, and the dimension of the first dielectric stack structure in the third direction is greater than the dimension of the second gate isolation structure in the third direction. The first direction and the second direction intersect, and the third direction intersects the plane containing the first direction and the second direction.

[0152] In this step, refer to Figure 19 and Figure 20 and combined Figure 12 and Figure 13 After the third partition 333 is formed and before the first filling space 341 is formed, a first isolation layer 2431 and a first sub-isolation structure 241 can be sequentially formed in the third partition 333 using CVD, PVD, ALD or any combination thereof thin film deposition process, with the first isolation layer 2431 surrounding the first sub-isolation structure 241.

[0153] refer to Figure 19 and Figure 20 After forming the first gate layer 211 and the second gate layer 231, the sacrificial material located in the gate spacer 330 can be removed. A second isolation layer 2432 and a second sub-isolation structure 242 can be sequentially formed in the first spacer 331 and the second spacer 332 using CVD, PVD, ALD, or any combination thereof thin film deposition processes. The second isolation layer 2432 surrounds the second sub-isolation structure 242. The first isolation layer 2431, the second isolation layer 2432, the first sub-isolation structure 241, and the second sub-isolation structure 242 together constitute the gate isolation structure 240. The first isolation layer 2431 and the second isolation layer 2432 together constitute the isolation layer 243 in some of the preceding embodiments.

[0154] It should be noted that, in some of the preceding steps, multiple gate isolation trenches 330 can be formed. Therefore, in this step, the sacrificial material in multiple gate isolation trenches 330 can be removed simultaneously, and a second isolation layer 2432 and a second sub-isolation structure 242 can be sequentially formed in multiple gate isolation trenches 330, thereby forming multiple gate isolation structures 240. Among the first gate isolation structures 2401 and the second gate isolation structures 2402 that are adjacent and spaced apart along the first direction X, the first gate isolation structure 2401 penetrates the first gate stack structure 210 along the second direction Y, and the second gate isolation structure 2402 penetrates the second gate stack structure 230 along the second direction Y.

[0155] The semiconductor structure 200 described above can be fabricated using the method described in some of the preceding embodiments. In this semiconductor structure 200, since the first dielectric stack structure 220 penetrates the first gate stack structure along the third direction Z and also penetrates the second gate stack structure 230 along the third direction Z, the first dielectric stack structure 220 can isolate the first gate stack structure 210 and the second gate stack structure 230. The first dielectric stack structure 220 is a stack structure formed by alternating third dielectric layer 221 and fourth dielectric layer 222, both of which are made of insulating material. By setting the first dielectric stack structure 220, the use of conductive material can be reduced, while the use of insulating material can be increased, which is beneficial for reducing the proportion of conductive material in the semiconductor structure 200, while the insulating material will not couple with the conductive material. When performing read / write operations on the channel structure 250 located in the first gate stack structure 210, the first gate layer 211 will not couple with the third dielectric layer 221 / fourth dielectric layer 222, which helps to improve the coupling of conductive materials in other stack structures to the first gate layer 211. Similarly, when performing read / write operations on the channel structure 250 located in the second gate stack structure 230, the influence of conductive materials in other stack structures on the second gate layer 231 is reduced.

[0156] In addition, the spacing between the first gate layer 211 and the second gate layer 231 in the second direction Y can be adjusted by adjusting the size of the first dielectric stack structure 220 in the first direction X. The spacing between the first gate layer 211 and the second gate layer 231 can be designed according to the requirements, which is beneficial to improve the isolation effect of the first dielectric stack structure 220 on the first gate layer 211 and the second gate layer 231, thereby improving the storage stability of the semiconductor structure 200.

[0157] Figure 21 This is a block diagram of a storage system according to some embodiments. Figure 22 This is a block diagram of a storage system according to some other embodiments.

[0158] Please see Figure 21 and Figure 22 Some embodiments of this disclosure also provide a storage system 1000. The storage system 1000 includes a controller 20 and a three-dimensional memory 10 as described in some of the embodiments above. The controller 20 is coupled to the three-dimensional memory 10 to control the storage of data in the three-dimensional memory 10. The three-dimensional memory 10 includes the semiconductor structure 200 described in some of the embodiments above.

[0159] The storage system 1000 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an Embedded Multi Media Card (eMMC) package). In other words, the storage system 1000 can be applied to and packaged into different types of electronic products, such as mobile phones (e.g., cell phones), desktop computers, tablets, laptops, servers, in-vehicle devices, game consoles, printers, positioning devices, wearable devices, smart sensors, power banks, virtual reality (VR) devices, augmented reality (AR) devices, or any other suitable electronic device containing storage.

[0160] In some embodiments, see Figure 21 The storage system 1000 includes a controller 20 and a three-dimensional memory 10, and the storage system 1000 can be integrated into a memory card.

[0161] Among them, memory cards include any one of the following: PC card (PCMCIA, Personal Computer Memory Card International Association), Compact Flash (CF) card, Smart Media (SM) card, memory stick, Multimedia Card (MMC), Secure Digital Memory Card (SD) card, and UFS.

[0162] In other embodiments, see Figure 22 The storage system 1000 includes a controller 20 and multiple three-dimensional storage devices 10, and the storage system 1000 is integrated into a solid state drive (SSD).

[0163] In some embodiments of the storage system 1000, the controller 20 is configured to operate in a low duty cycle environment, such as an SD card, CF card, Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, and mobile phones.

[0164] In other embodiments, controller 20 is configured to operate in a high duty cycle environment in an SSD or eMMC, which is used as data storage for mobile devices such as smartphones, tablets, and laptops, as well as enterprise storage arrays.

[0165] In some embodiments, controller 20 may be configured to manage data stored in 3D memory 10 and communicate with external devices (e.g., a host). In some embodiments, controller 20 may also be configured to control operations of 3D memory 10, such as read, erase, and program operations. In some embodiments, controller 20 may also be configured to manage various functions relating to data stored or to be stored in 3D memory 10, including at least one of bad block management, garbage collection, logical-to-physical address translation, and wear leveling. In some embodiments, controller 20 is also configured to process error correction codes relating to data read from or written to 3D memory 10.

[0166] Of course, controller 20 can also perform any other suitable functions, such as formatting the three-dimensional memory 10; for example, controller 20 can communicate with external devices (e.g., hosts) through at least one of various interface protocols.

[0167] It should be noted that the interface protocol includes at least one of the following: USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI High Speed ​​(PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronic Device (IDE) protocol, and Firewire protocol.

[0168] Since the three-dimensional memory 10 includes the semiconductor structure 200 provided in some of the above embodiments, the storage system 1000 also has good storage stability and reliability.

[0169] Some embodiments of this disclosure also provide an electronic device. The electronic device can be any of the following: mobile phone, desktop computer, tablet computer, laptop computer, server, in-vehicle equipment, wearable device (e.g., smartwatch, smart bracelet, smart glasses, etc.), power bank, game console, digital multimedia player, etc.

[0170] The electronic device may include the storage system 1000 described above, and may also include at least one of a central processing unit (CPU) and a cache. If the electronic device includes the storage system 1000 described above, then the electronic device also has good storage stability and reliability.

[0171] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A semiconductor structure, characterized by, include: A first gate stack structure, a first dielectric stack structure, and a second gate stack structure are arranged sequentially along a first direction. The first gate stack structure includes a plurality of first gate layers and a plurality of first dielectric layers that are alternately stacked along a second direction. The second gate stack structure includes a plurality of second gate layers and a plurality of second dielectric layers that are alternately stacked along the second direction. The first dielectric stack structure includes a plurality of third dielectric layers and a plurality of fourth dielectric layers that are alternately stacked along the second direction. A plurality of gate isolation structures, the plurality of gate isolation structures including a first gate isolation structure and a second gate isolation structure that are adjacent to and spaced apart along the first direction, the first gate isolation structure penetrating the first gate stack structure along the second direction, the second gate isolation structure penetrating the second gate stack structure along the second direction, the dimension of the first dielectric stack structure in the third direction being greater than the dimension of the first gate isolation structure in the third direction, and the dimension of the first dielectric stack structure in the third direction being greater than the dimension of the second gate isolation structure in the third direction; Wherein, the first direction intersects the second direction, and the third direction intersects the plane containing the first direction and the second direction.

2. The semiconductor structure of claim 1, wherein, The third dielectric layer is adjacent to the first gate layer along the first direction, and the third dielectric layer is adjacent to the second gate layer along the first direction. The third dielectric layer has an end in the third direction, and at least a portion of the width of the third dielectric layer in the first direction is smaller than the width of the end in the first direction.

3. The semiconductor structure of claim 2, wherein, The third dielectric layer has two sidewalls disposed opposite each other along the first direction, and the edges of the sidewalls include arc-shaped edges.

4. The semiconductor structure of claim 1, wherein, The third dielectric layer is adjacent to the first gate layer along the first direction, and the third dielectric layer is adjacent to the second gate layer along the first direction. The dimension of the third dielectric layer in the first direction is greater than 3 μm.

5. The semiconductor structure of claim 1, wherein, The gate isolation structure includes a first sub-isolation structure, a second sub-isolation structure, and an isolation layer. The length of the second sub-isolation structure along its extension direction is greater than the length of the first sub-isolation structure along its extension direction. The first sub-isolation structure and the second sub-isolation structure are spaced apart. The isolation layer is disposed around the first sub-isolation structure and around the second sub-isolation structure. The isolation layer is also located between the first sub-isolation structure and the second sub-isolation structure. On a plane parallel to the first direction and the third direction, the first sub-isolation structure, the second sub-isolation structure, and the isolation layer form a closed pattern.

6. The semiconductor structure of claim 5, wherein, The first sub-isolation structure extends along the third direction.

7. The semiconductor structure of claim 1, wherein, The plurality of gate isolation structures further includes a third gate isolation structure, which is located on the side of the first gate isolation structure opposite to the second gate isolation structure, and the third gate isolation structure and the first gate isolation structure share a portion of the structure.

8. The semiconductor structure of claim 1, wherein, Also includes: The second dielectric stack structure includes a plurality of fifth dielectric layers and a plurality of sixth dielectric layers alternately stacked along the second direction, the first gate stack structure is disposed around the second dielectric stack structure, and the first gate isolation structure is disposed around the second dielectric stack structure.

9. The semiconductor structure of claim 1, wherein, Also includes: Multiple channel structures, at least one of the channel structures penetrates the first gate stack structure along the second direction, at least one of the channel structures penetrates the second gate stack structure along the second direction, and at least one of the channel structures penetrates the first dielectric stack structure along the second direction.

10. The semiconductor structure of claim 1, wherein, Also includes: Multiple support columns are arranged in multiple rows and columns, and the support columns penetrate the first medium stacked structure along the second direction.

11. The semiconductor structure of claim 1, wherein, The first dielectric layer, the second dielectric layer, and the fourth dielectric layer are made of the same material.

12. A method of fabricating a semiconductor structure, characterized by, include: A first gate stack structure, a first dielectric stack structure, and a second gate stack structure are formed sequentially along a first direction. The first gate stack structure includes a plurality of first gate layers and a plurality of first dielectric layers alternately stacked along a second direction. The second gate stack structure includes a plurality of second gate layers and a plurality of second dielectric layers alternately stacked along the second direction. The first dielectric stack structure includes a plurality of third dielectric layers and a plurality of fourth dielectric layers alternately stacked along the second direction. Multiple gate isolation structures are formed, including a first gate isolation structure and a second gate isolation structure that are adjacent and spaced apart along the first direction. The first gate isolation structure penetrates the first gate stack structure along the second direction, and the second gate isolation structure penetrates the second gate stack structure along the second direction. The dimension of the first dielectric stack structure in the third direction is larger than the dimension of the first gate isolation structure in the third direction, and the dimension of the first dielectric stack structure in the third direction is larger than the dimension of the second gate isolation structure in the third direction. The first direction intersects the second direction, and the third direction intersects the plane containing the first direction and the second direction.

13. The method of claim 12, wherein the semiconductor structure is prepared by a method comprising: The formation of the first gate stack structure, the first dielectric stack structure, and the second gate stack structure arranged sequentially along the first direction includes: A dielectric stack structure is formed, the dielectric stack structure comprising a plurality of dielectric layers and a plurality of sacrificial layers alternately stacked along the second direction; Multiple gate spacers are formed, the multiple gate spacers are spaced apart along the first direction, and the gate spacers penetrate the dielectric stack structure along the second direction; A portion of the sacrificial layer is removed through the gate trench to form a filling space; The filling space is filled with conductive material to form the first gate layer and the second gate layer.

14. The method of claim 13, wherein the semiconductor structure is prepared by a method comprising: Multiple gate spacers are formed, including: Multiple through holes are formed, the multiple through holes are spaced apart, and the through holes penetrate the dielectric stack structure along the second direction; The through holes are connected to form a first partition and a second partition, the first partition and the second partition are spaced apart along the third direction, and a portion of the through holes are located between the first partition and the second partition; Sacrificial material is filled into the first and second septa. The through hole located between the first partition and the second partition is connected to form a third partition. The first partition, the second partition, and the third partition form a closed pattern. The first partition, the second partition, and the third partition together constitute the gate partition.

15. The method for preparing a semiconductor structure according to claim 14, characterized in that, The formation of multiple gate isolation structures includes: A first isolation layer and a first sub-isolation structure are sequentially formed in the third partition groove, with the first isolation layer surrounding the first sub-isolation structure; Remove the sacrificial material; A second isolation layer and a second sub-isolation structure are sequentially formed in the first and second partitions, with the second isolation layer surrounding the second sub-isolation structure. The first isolation layer, the second isolation layer, the first sub-isolation structure, and the second sub-isolation structure together constitute the gate isolation structure.

16. A storage system, characterized in that, include: The semiconductor structure according to any one of claims 1-11; A controller, the control being coupled to the semiconductor structure, to control the semiconductor structure to store data.

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