Capacitor design and method of forming the same

Abstract

This invention provides a capacitor design and its forming method. The capacitor design includes: a substrate comprising, from top to bottom along a vertical direction, a silicon nitride layer, a first silicon oxide layer, a silicon layer, and a second silicon oxide layer; an opening located within the silicon nitride layer, the first silicon oxide layer, the silicon layer, and the second silicon oxide layer; and an insulator-shaped capacitor conformally located on the surface of the opening. The opening includes a trench located along a vertical direction within the silicon nitride layer, the second silicon oxide layer, the silicon layer, and the first silicon oxide layer; and a first annular cavity and a second annular cavity located from the trench along horizontal directions perpendicular to the vertical direction within the first silicon oxide layer and the second silicon oxide layer, respectively.

Description

Technical Field

[0001] This invention relates to a capacitor design, and more particularly to a capacitor design and a method for forming the same. Background Technology

[0002] As semiconductor processes strive for higher integration, capacitors also require higher capacitance values ​​within the same layout area. This has led to the development of various capacitor technologies, such as deep trench capacitors (DTC).

[0003] However, there is still room for improvement in the capacitance of these capacitors. Summary of the Invention

[0004] To address the aforementioned problems, this invention proposes a capacitor design and formation method to improve capacitance values.

[0005] An embodiment of the present invention provides a capacitor design, comprising: a substrate comprising, from top to bottom along a vertical direction, a silicon nitride layer, a first silicon oxide layer, a silicon layer, and a second silicon oxide layer; an opening located in the silicon nitride layer, the first silicon oxide layer, the silicon layer, and the second silicon oxide layer, wherein the opening comprises: a trench located in the silicon nitride layer, the second silicon oxide layer, the silicon layer, and the first silicon oxide layer along a vertical direction; a first annular cavity and a second annular cavity located in the first silicon oxide layer and the second silicon oxide layer respectively from the trench along a horizontal direction perpendicular to the vertical direction; and an insulator-shaped capacitor conformally located on the surface of the opening.

[0006] In some embodiments, the substrate further includes an etch stop layer located below the second silicon oxide layer.

[0007] In some embodiments, the bottom of the opening exposes an etch stop layer.

[0008] In some embodiments, the insulator capacitor includes: a lower electrode layer conformally located on the surface of the opening; a dielectric layer conformally located on the lower electrode layer; and an upper electrode layer conformally located on the dielectric layer.

[0009] In some embodiments, the insulator capacitor comprises a stacked structure of metal / dielectric layer / metal.

[0010] In some embodiments, the insulator capacitor comprises a TiN-ZAZ-TiN stacked structure or a TAN / ZAZ / TAN stacked structure.

[0011] In some embodiments, the device further includes: an insulator-shaped capacitor located on the top surface of the silicon nitride layer; and a lower electrode and an upper electrode located on the insulator-shaped capacitor of the silicon nitride layer, wherein the lower electrode is electrically connected to the lower electrode layer and the upper electrode is electrically connected to the upper electrode layer.

[0012] In some embodiments, the system further includes: an additional silicon oxide layer and an additional silicon nitride layer, located between the first silicon oxide layer and the silicon layer; wherein the opening is also located in the additional silicon oxide layer and the additional silicon nitride layer, wherein the opening includes: a trench, located in the additional silicon nitride layer and the additional silicon oxide layer in a vertical direction; and a third annular cavity, located in the trench in a horizontal direction in the additional silicon oxide layer.

[0013] An embodiment of the present invention provides a method for forming a capacitor design, comprising: providing a substrate comprising a silicon nitride layer, a first silicon oxide layer, a silicon layer and a second silicon oxide layer from top to bottom in a vertical direction; forming an opening in the silicon nitride layer, the first silicon oxide layer, the silicon layer and the second silicon oxide layer, wherein forming the opening comprises: forming a trench in the silicon nitride layer, the first silicon oxide layer, the silicon layer and the second silicon oxide layer in a vertical direction; removing a portion of the first silicon oxide layer and a portion of the second silicon oxide layer from the trench in a horizontal direction perpendicular to the vertical direction to form a first annular cavity and a second annular cavity in the first silicon oxide layer and the second silicon oxide layer, respectively; and conformally forming an insulator-shaped capacitor on the surface of the opening.

[0014] In some embodiments, the substrate further includes an etch stop layer located below the second silicon oxide layer.

[0015] In some embodiments, the bottom of the opening exposes an etch stop layer.

[0016] In some embodiments, forming the first annular cavity and the second annular cavity includes an isotropic etching process or an anisotropic etching process.

[0017] In some embodiments, forming the first annular cavity and the second annular cavity includes forming them simultaneously using an isotropic etching process or an anisotropic etching process.

[0018] In some embodiments, forming an insulator-shaped capacitor includes: conformally forming a lower electrode layer on the surface of an opening; conformally forming a dielectric layer on the lower electrode layer; and conformally forming an upper electrode layer on the dielectric layer.

[0019] In some embodiments, the insulator capacitor comprises a stacked structure of metal / dielectric layer / metal.

[0020] In some embodiments, the insulator capacitor comprises a TiN-ZAZ-TiN stacked structure or a TAN / ZAZ / TAN stacked structure.

[0021] In some embodiments, the method further includes: forming an insulator-shaped capacitor on the top surface of the silicon nitride layer; and forming a lower electrode and an upper electrode on the insulator-shaped capacitor of the silicon nitride layer, wherein the lower electrode is electrically connected to the lower electrode layer and the upper electrode is electrically connected to the upper electrode layer.

[0022] In some embodiments, the method further includes: forming an additional silicon nitride layer and an additional silicon oxide layer between the first silicon oxide layer and the silicon layer, and forming an opening in the additional silicon nitride layer and the additional silicon oxide layer, wherein forming the opening includes: forming a trench in the additional silicon nitride layer and the additional silicon oxide layer in a vertical direction; and removing a portion of the additional silicon oxide layer from the trench in a horizontal direction to form a third annular cavity in the additional silicon oxide layer.

[0023] In some embodiments, forming the first annular cavity, the second annular cavity, and the third annular cavity includes an isotropic etching process or an anisotropic etching process.

[0024] In some embodiments, forming the first annular cavity, the second annular cavity, and the third annular cavity includes forming them simultaneously using an isotropic etching process or an anisotropic etching process.

[0025] Based on the above, the present invention provides a capacitor design and its formation method. By utilizing the characteristic that different material layers inside the trench have a relatively large etch selectivity, several annular cavities are formed by further lateral expansion in a special material inside the trench through etching. This gives the subsequently formed capacitor an insulator-like shape, thereby increasing the surface area of ​​the capacitor under the same layout area or the same trench aspect ratio, and thus increasing the capacitance value while maintaining the integration density of the semiconductor device.

[0026] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description

[0027] Figures 1A to 1E This is a cross-sectional schematic diagram of the capacitor design formation method according to Embodiment 1 of the present invention;

[0028] Figure 2 This is a cross-sectional schematic diagram of the capacitor design in Embodiment 2 of the present invention;

[0029] Figures 3A to 3B This is a cross-sectional schematic diagram of the method for forming a multi-wafer stacked structure according to Embodiment 3 of the present invention. Detailed Implementation

[0030] The following description provides detailed examples and accompanying drawings, but these examples are not intended to limit the scope of the invention. Furthermore, the drawings are for illustrative purposes only and are not drawn to their original dimensions. For ease of understanding, identical components will be labeled with the same symbols, and will not be repeated in the following paragraphs.

[0031] The terms “include,” “including,” and “have” used in the text are all open-ended terms, meaning “includes but not limited to.”

[0032] Furthermore, directional terms used in this document, such as "upper," "lower," "top," and "bottom," are merely for reference to the directions in the accompanying drawings and are not intended to limit the invention. Therefore, it should be understood that "upper" and "lower" can be used interchangeably, as can "top" and "bottom"; and when a layer or film is placed "on" another device, the device can be placed directly on the other device, or there may be an intermediate device. Conversely, when a device is said to be placed "directly" on another device, there is no intermediate device between them.

[0033] As used herein, “about,” “approximately,” or “substantially” includes the average of the values ​​mentioned and specific values ​​that can be determined by a person skilled in the art, within an acceptable range of deviations, taking into account the measurement under discussion and the specific number of errors associated with the measurement (i.e., limitations of the measurement system). For example, “about” may mean within one or more standard deviations of the value, or within ±30%, ±20%, ±10%, ±5%. Furthermore, the use of “about,” “approximately,” or “substantially” herein may be chosen based on the optical, etched, or other properties to select a more acceptable range of deviations or standard deviations, and may not require a single standard deviation to apply to all properties.

[0034] The terminology used herein is for illustrative purposes only and is not intended to limit the scope of the claims. In this context, the singular form includes the plural form unless otherwise defined by the context.

[0035] The various formation steps described below include deposition processes, removal processes, and patterning processes.

[0036] The deposition process refers to the process of forming one material onto another material, which may include, but is not limited to, techniques such as spin coating, sputtering, chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma-enhanced chemical vapor deposition (PE-CVD), atomic layer deposition (ALD), molecular beam deposition (MBD), pulsed laser deposition (PLD), and liquid source misted chemical deposition (LSMCD).

[0037] The removal process may include wet etching, dry etching, chemical mechanical planarization (CMP), etc., but is not limited to these.

[0038] The patterning process may include steps such as coating a photoresist according to the desired pattern, then exposing the photoresist to react, then exposing and developing the photoresist to pattern it, then using etching to transfer the shape of the photoresist onto the material, removing the material and photoresist to be removed, and finally cleaning, but is not limited to these steps.

[0039] For details regarding the capacitor design, multi-wafer stacking structure, and its formation method of the present invention, please refer to Examples 1 to 3 below, and please also refer to... Figures 1A to 3B To learn more.

[0040] Example 1

[0041] Figures 1A to 1E This is a cross-sectional schematic diagram of the method for forming a capacitor design according to Embodiment 1 of the present invention.

[0042] First, please refer to Figure 1A A substrate S is provided, which includes a silicon nitride layer 10, a first silicon oxide layer 20, a silicon layer 30 and a second silicon oxide layer 40 from top to bottom along the vertical direction Z.

[0043] In some embodiments, the silicon nitride layer 10 may include materials such as silicon oxynitride, but is not limited thereto.

[0044] In some embodiments, the first silicon oxide layer 20 may include materials such as tetraethoxysilane (TEOS), but is not limited thereto.

[0045] In some embodiments, silicon layer 30 may include silicon material, but is not limited thereto.

[0046] In some embodiments, the second silicon oxide layer 40 may include materials such as silicon oxide fillers that form STI, but is not limited thereto.

[0047] In some embodiments, the substrate S may further include an etch stop layer 50 beneath the second silicon oxide layer 40, such as... Figure 1A As shown.

[0048] In some embodiments, the substrate S may further include an etch stop layer 50, a dielectric layer 60, and a metal layer 70 below the second silicon oxide layer 40, wherein the etch stop layer 50 may be located on the interlayer dielectric layer 60, such as... Figure 1A As shown, alternatively, the etch stop layer 50 may be located in the interlayer dielectric layer 60 (not shown).

[0049] In some embodiments, the etch stop layer 50 may include materials such as silicon nitride, but is not limited thereto.

[0050] In some embodiments, the metal layer 70 may include various conductive materials, such as copper (Cu), tungsten (W), aluminum (Al), titanium (Ti), nickel (Ni), platinum (Pt), ruthenium (Ru), cobalt (Co), or alloys thereof, or other suitable and future conductive materials, but not limited thereto.

[0051] Then, please continue reading. Figure 1A Grooves 100 are formed along the vertical direction Z in the silicon nitride layer 10, the first silicon oxide layer 20, the silicon layer 30 and the second silicon oxide layer 40.

[0052] In some embodiments, various patterning processes may be used, such as photolithography and etching processes, to form the trench 100.

[0053] In some embodiments, the bottom 100B of the formed trench 100 may expose the second silicon oxide layer 40, such as Figure 1A As shown; or, the bottom 100B of the formed trench 100 may expose the etch stop layer 50 (not shown).

[0054] Next, please refer to Figure 1BAfter forming the trench 100, a portion of the first silicon oxide layer 20 and a portion of the second silicon oxide layer 40 are removed from the trench 100 along the horizontal direction X perpendicular to the vertical direction Z, so as to form a first annular cavity 102 and a second annular cavity 104 in the first silicon oxide layer 20 and the second silicon oxide layer 20, respectively, such that the opening 110 includes the trench 100, the first annular cavity 102 and the second annular cavity 104, and this opening 110 is formed in the silicon nitride layer 10, the first silicon oxide layer 20, the silicon layer 30 and the second silicon oxide layer 40.

[0055] In some embodiments, an isotropic etching process or anisotropic etching process can be used to remove a portion of the first silicon oxide layer 20 and a portion of the second silicon oxide layer 40 from the trench 100 along the horizontal direction X perpendicular to the vertical direction Z, so as to form a first annular cavity 102 and a second annular cavity 104, respectively.

[0056] In some embodiments, forming the first annular cavity 102 and the second annular cavity 104 may include forming them simultaneously using an isotropic etching process or an anisotropic etching process.

[0057] Since the first silicon oxide layer 20 and the second silicon oxide layer 40 have an etch selectivity difference of about 100 to 1000:1 relative to the silicon nitride layer 10 and the silicon layer 30, respectively, after etching the trench 100 with an appropriate etchant and etching method, the first silicon oxide layer 20 and the second silicon oxide layer 40 in the trench 100 will be removed to a certain extent, while the silicon nitride layer 10 and the silicon layer 30 will be retained, so as to form a first annular cavity 102 and a second annular cavity 104 in the first silicon oxide layer 20 and the second silicon oxide layer 40 respectively along the horizontal direction X perpendicular to the vertical direction Z.

[0058] In addition, such as Figure 1A and Figure 1B As shown, the bottom 100B of the trench 100 may also be affected by the etching of the second annular cavity 104, causing a portion of the second silicon oxide layer 40 to be removed further downwards. This results in the bottom 110B of the formed opening 110B moving towards the etch stop layer 50 compared to the bottom 100B of the trench 100, potentially even exposing the etch stop layer 50. Figure 1B As shown.

[0059] Next, please refer to Figure 1C An insulator capacitor 200 is conformally formed on the surface of the opening 110, which includes the first annular cavity 102 and the second annular cavity 104.

[0060] In some embodiments, before the insulator capacitor 200 is conformally formed on the surface of the opening 110 including the first annular cavity 102 and the second annular cavity 104, a liner (not shown) may be conformally formed on the surface of the opening 110 including the first annular cavity 102 and the second annular cavity 104. This liner may include, but is not limited to, an oxide layer.

[0061] The aforementioned insulator refers to an insulator used in overhead transmission lines for electrical insulation and mechanical fixing, which has a special shape with umbrella-shaped insulators repeatedly arranged in the same direction on a columnar insulator. The insulator-shaped capacitor 200 of this invention, which conformally forms an insulator-shaped capacitor 200 along the surface of the opening 110 including the groove 100, the first annular cavity 102, and the second annular cavity 104, has a similar shape to an insulator, hence the name.

[0062] In some embodiments, the aforementioned insulator capacitor 200 may include a metal / insulator / metal (MIM) stacked structure, such as a TiN-ZAZ-TiN stacked structure or a TAN / ZAZ / TAN stacked structure, but is not limited thereto; the insulator capacitor 200 may also include a general capacitor structure, but is not limited thereto.

[0063] In some embodiments, the aforementioned insulator capacitor 200 may include: conformally forming a lower electrode layer 210 on the surface of the opening 110; conformally forming a dielectric layer 220 on the lower electrode layer 210; and conformally forming a lower electrode layer 230 on the dielectric layer 220, such as... Figure 1C As shown.

[0064] In some embodiments, such as Figure 1C As shown, the aforementioned barrier-shaped capacitor 200 can be further formed on the top surface of the silicon nitride layer 10.

[0065] Then, as Figure 1D As shown, an insulating layer 300 is deposited on the insulator capacitor 200 to fill the opening 110 and is located above the silicon nitride layer 10.

[0066] Next, as Figure 1E As shown, a lower electrode 410 and an upper electrode 430 are formed on an insulator capacitor 200 of a silicon nitride layer 10, wherein the lower electrode 410 is electrically connected to the lower electrode layer 210 and the upper electrode 430 is electrically connected to the upper electrode layer 230.

[0067] In other words, this invention utilizes the characteristic that different material layers inside the trench have a relatively large etch selectivity to further expand laterally in a special material inside the trench by etching, thereby forming several annular cavities. This gives the capacitors formed subsequently an insulator-like shape, increasing the surface area of ​​the capacitors while maintaining the same layout area or trench aspect ratio, and thus improving the capacitance value while maintaining the integration density of the semiconductor device.

[0068] Example 2

[0069] Figure 2 This is a cross-sectional schematic diagram of the capacitor design according to Embodiment 2 of the present invention, which differs from that of Embodiment 1. Figure 1E The capacitor designs shown are similar, and the method for forming the capacitor design in Example 2 is similar to the method for forming the capacitor design in Example 1. Therefore, the following description focuses only on the differences between them.

[0070] like Figure 2 The capacitor design shown is as follows: Figure 1E The capacitor design shown has an additional silicon nitride layer 12 and an additional silicon oxide layer 22 between the first silicon oxide layer 20 and the silicon layer 30. Therefore, the trench 100 of the capacitor design in Embodiment 2 is formed in the vertical direction Z in the silicon nitride layer 10, the first silicon oxide layer 20, the additional silicon nitride layer 12, the additional silicon oxide layer 22, the silicon layer 30 and the second silicon oxide layer 40.

[0071] Please continue reading. Figure 2 After forming the trench 100, a portion of the first silicon oxide layer 20, a portion of the additional silicon oxide layer 12, and a portion of the second silicon oxide layer 40 are removed from the trench 100 along the horizontal direction X perpendicular to the vertical direction Z, to form a first annular cavity 102, a third annular cavity 106, and a second annular cavity 104 in the first silicon oxide layer 20, the additional silicon oxide layer 12, and the second silicon oxide layer 20, respectively, so that the opening 120 includes the trench 100, the first annular cavity 102, the third annular cavity 106, and the second annular cavity 104, and this opening 120 is formed in the silicon nitride layer 10, the first silicon oxide layer 20, the additional silicon nitride layer 12, the additional silicon oxide layer 22, the silicon layer 30, and the second silicon oxide layer 40.

[0072] In some embodiments, an isotropic etching process or anisotropic etching process can be used to remove a portion of the first silicon oxide layer 20, a portion of the additional silicon oxide layer 12, and a portion of the second silicon oxide layer 40 from the trench 100 along the horizontal direction X perpendicular to the vertical direction Z, so as to form a first annular cavity 102, a third annular cavity 106, and a second annular cavity 104, respectively.

[0073] In some embodiments, forming the first annular cavity 102, the third annular cavity 106, and the second annular cavity 104 may include forming them simultaneously using an isotropic etching process or an anisotropic etching process.

[0074] Next, please refer to [link / reference]. Figure 2 An insulator capacitor 200 is conformally formed on the surface of the opening 120, which includes the first annular cavity 102, the third annular cavity 106 and the second annular cavity 104.

[0075] Please also refer to Figure 1E Capacitor design and Figure 2 In the capacitor design of Embodiment 2, since an additional silicon nitride layer 12 and an additional silicon oxide layer 22 are added between the first silicon oxide layer 20 and the silicon layer 30, after the formation steps of the opening 120 and the insulator capacitor 200, a larger surface area of ​​the insulator capacitor 200 than that of Embodiment 1 is obtained, thus obtaining a capacitor design of Embodiment 2 with a higher capacitance value.

[0076] Therefore, the concept of the capacitor design formation method in Example 2 can be used to form an array of silicon oxide layers and silicon nitride layers, so that the opening forms a shape including several annular cavities, thereby increasing the capacitance of the capacitor subsequently formed.

[0077] Example 3

[0078] Figures 3A to 3B This is a cross-sectional schematic diagram of a method for forming a multi-wafer stacked structure according to Embodiment 3 of the present invention. This multi-wafer stacked structure and its formation method embed the capacitor design from Embodiment 1 into the multi-wafer stacked structure; however, the concept of the present invention is not limited to this, and the capacitor design from Embodiment 2 and similar capacitor designs formed using this concept can also be embedded into the multi-wafer stacked structure; furthermore... Figure 3A and Figure 3B The multi-wafer stacked structure described herein is merely one example to clearly illustrate various multi-wafer stacked structures, and its application in capacitor design is not limited thereto.

[0079] First, please refer to Figure 3A The device provides a bottom wafer structure 600, including a bottom wafer 610; and a top wafer structure 700, including a top wafer 710 and a top dielectric layer 730; the top wafer structure 700 and the bottom wafer structure 600 are joined in a vertical Z-direction such that the top wafer 710 and the bottom wafer 610 are far apart from each other.

[0080] In some embodiments, the bottom wafer structure 600 further includes a bottom device 620 and a bottom dielectric layer 630 on the bottom wafer 610; a bottom first interlayer dielectric layer 640 and a bottom contact plug 650 are also included on the bottom device 620 and the bottom dielectric layer 630; and a stack of a bottom first metal layer 660 and a bottom second interlayer dielectric layer 670 is sequentially included on the bottom first interlayer dielectric layer 640 and the bottom contact plug 650, as shown below. Figure 3A As shown, but not limited to.

[0081] In some embodiments, the top wafer structure 700 further includes a top device 720 and a top dielectric layer 730 on the top wafer 710; an etch stop layer 735 is also included on the top device 720 and the top dielectric layer 735; a top first interlayer dielectric layer 740 and a bottom contact plug 750 are also included on the etch stop layer 735; and a stack of a top first metal layer 760 and a top second interlayer dielectric layer 770 is sequentially included on the top first interlayer dielectric layer 740 and the bottom contact plug 750, as shown below. Figure 3A As shown, but not limited to.

[0082] In some embodiments, the top wafer structure 700 and the bottom wafer structure 600 are joined at the bonding interface BL along the vertical direction Z such that the top wafer 710 and the bottom wafer 610 are far apart from each other, as shown in the example. Figure 3A As shown, but not limited to.

[0083] In some embodiments, a through silicon via (TSV) 800 is also included located in the bottom wafer structure 600 and the top wafer structure 700, such as Figure 3A As shown, but not limited to.

[0084] Next, as Figure 3B As shown, after chemical mechanical polishing (CMP) grinding to reduce the thickness of the top wafer 710 to approximately 3–10 micrometers, a side insulating layer 900 is formed on the exposed upper surface of the bottom wafer 610 and the sidewalls of the top wafer structure 700 and the bottom wafer structure 600, as follows. Figure 3B As shown.

[0085] In some embodiments, the side insulation layer 900 may include an insulating material such as TEOS, but is not limited thereto.

[0086] Next, a first silicon oxide layer 20 is formed on the top wafer 710; then a silicon nitride layer 10 is formed on the first silicon oxide layer 20.

[0087] Next, as Figures 1A to 1EThe steps for forming the capacitor design of Example 1 shown are as follows: Figure 3B The top wafer structure 700, the bottom wafer structure 600, and the second silicon oxide layer 20 and silicon nitride layer 10 subsequently formed on the top wafer 710 are considered as the substrate S described in Example 1, especially... Figure 3B The silicon nitride layer 10, the first silicon oxide layer 20, the top wafer 710, and the top dielectric layer 730 correspond to Figures 1A to 1E The silicon nitride layer 10, the first silicon oxide layer 20, the silicon layer 30, and the second silicon oxide layer 40 are arranged in a structure to form an opening 110 in the silicon nitride layer 10, the first silicon oxide layer 20, the top wafer 710, and the top dielectric layer 730. Forming the opening 110 includes: forming a trench 100 along the vertical direction Z in the silicon nitride layer 10, the first silicon oxide layer 20, the top wafer 710, and the top dielectric layer 730; removing a portion of the first silicon oxide layer 20 and a portion of the top dielectric layer 730 from the trench 100 along the horizontal direction X perpendicular to the vertical direction Z to form a first annular cavity 102 and a second annular cavity 104 in the first silicon oxide layer 20 and the top dielectric layer 730, respectively; and conformally forming an insulator capacitor 200 on the surface of the opening 110.

[0088] Besides being able to Figure 3B The silicon nitride layer 10, the first silicon oxide layer 20, the top wafer 710, and the top dielectric layer 730 correspond to Figures 1A to 1E In addition to the silicon nitride layer 10, the first silicon oxide layer 20, the silicon layer 30, and the second silicon oxide layer 40, in some embodiments, additional layers may be used. Figure 3A and Figure 3B The etch stop layer 735, the top first interlayer dielectric layer 740, and the top first metal layer 760 correspond to Figures 1A to 1E The etching stop layer 50, the interlayer dielectric layer 60, and the metal layer 70 are included.

[0089] Then, the formation of the multi-wafer stacked structure of Embodiment 3 can be completed using the capacitor design formation method of Embodiment 1 of the present invention.

[0090] As described above, the present invention provides a capacitor design and its formation method. By utilizing the characteristic that different material layers inside the trench have a relatively large etch selectivity, several annular cavities are formed by further lateral expansion in a special material inside the trench through etching. This gives the subsequently formed capacitor an insulator-like shape, thereby increasing the surface area of ​​the capacitor while maintaining the same layout area or the same trench aspect ratio, and thus increasing the capacitance value while maintaining the integration density of the semiconductor device.

[0091] Although the present invention has been described above with reference to embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be defined by the appended claims.

Claims

1. A capacitor design, characterized in that, include: The substrate includes, from top to bottom, a silicon nitride layer, a first silicon oxide layer, a silicon layer, and a second silicon oxide layer in a vertical direction; An opening is located in the silicon nitride layer, the first silicon oxide layer, the silicon layer, and the second silicon oxide layer, wherein the opening includes: The trench is located along the vertical direction in the silicon nitride layer, the second silicon oxide layer, the silicon layer, and the first silicon oxide layer; and The first annular cavity and the second annular cavity are respectively located in the first silicon oxide layer and the second silicon oxide layer along a horizontal direction perpendicular to the vertical direction from the trench; and An insulator-shaped capacitor is conformally located on the surface of the opening.

2. The capacitor design according to claim 1, characterized in that, The substrate further includes: An etch stop layer is located below the second silicon oxide layer.

3. The capacitor design according to claim 2, characterized in that, The bottom of the opening exposes the etch stop layer.

4. The capacitor design according to claim 1, characterized in that, The insulator-type capacitor includes: The lower electrode layer is conformally located on the surface of the opening; A dielectric layer, conformally located on the lower electrode layer; and The upper electrode layer is conformally located on the dielectric layer.

5. The capacitor design according to claim 1, characterized in that, The obstruction capacitor described herein comprises a stacked structure of metal / dielectric layer / metal.

6. The capacitor design according to claim 1, characterized in that, The obstruction capacitor includes a TiN-ZAZ-TiN stacked structure or a TAN / ZAZ / TAN stacked structure.

7. The capacitor design according to claim 4, characterized in that, Also includes: The obstruction-shaped capacitor is located on the top surface of the silicon nitride layer; as well as The lower electrode and the upper electrode are located on the insulator-shaped capacitor of the silicon nitride layer, wherein the lower electrode is electrically connected to the lower electrode layer and the upper electrode is electrically connected to the upper electrode layer.

8. The capacitor design according to claim 1, characterized in that, Also includes: An additional silicon oxide layer and an additional silicon nitride layer are located between the first silicon oxide layer and the silicon layer; The opening is also located within the additional silicon oxide layer and the additional silicon nitride layer, wherein the opening comprises: The trench is also located in the additional silicon nitride layer and the additional silicon oxide layer along the vertical direction; as well as The third annular cavity is located in the trench in the additional silicon oxide layer in the horizontal direction.

9. A method for forming a capacitor design, characterized in that, include: A substrate is provided, comprising, from top to bottom in a vertical direction, a silicon nitride layer, a first silicon oxide layer, a silicon layer, and a second silicon oxide layer; An opening is formed in the silicon nitride layer, the first silicon oxide layer, the silicon layer, and the second silicon oxide layer, wherein forming the opening includes: Trenches are formed along the vertical direction in the silicon nitride layer, the first silicon oxide layer, the silicon layer, and the second silicon oxide layer; and A portion of the first silicon oxide layer and a portion of the second silicon oxide layer are removed from the trench in a horizontal direction perpendicular to the vertical direction to form a first annular cavity and a second annular cavity in the first silicon oxide layer and the second silicon oxide layer, respectively; and An indenter-shaped capacitor is conformally formed on the surface of the opening.

10. The method for forming a capacitor design according to claim 9, characterized in that, The substrate further includes: An etch stop layer is located below the second silicon oxide layer.

11. The method for forming a capacitor design according to claim 10, characterized in that, The bottom of the opening exposes the etch stop layer.

12. The method for forming a capacitor design according to claim 9, characterized in that, The formation of the first annular cavity and the second annular cavity includes an isotropic etching process or an anisotropic etching process.

13. The method for forming a capacitor design according to claim 9, characterized in that, The formation of the first annular cavity and the second annular cavity can be achieved by simultaneously forming them using an isotropic etching process or by simultaneously forming them using an anisotropic etching process.

14. The method for forming a capacitor design according to claim 9, characterized in that, The formation of the insulator-shaped capacitor includes: A lower electrode layer is conformally formed on the surface of the opening; A dielectric layer is conformally formed on the lower electrode layer; and An upper electrode layer is conformally formed on the dielectric layer.

15. The method for forming a capacitor design according to claim 9, characterized in that, The obstruction capacitor described herein comprises a stacked structure of metal / dielectric layer / metal.

16. The method for forming a capacitor design according to claim 9, characterized in that, The obstruction capacitor includes a TiN-ZAZ-TiN stacked structure or a TAN / ZAZ / TAN stacked structure.

17. The method for forming a capacitor design according to claim 14, characterized in that, Also includes: The obstruction-shaped capacitor is formed on the top surface of the silicon nitride layer; as well as A lower electrode and an upper electrode are formed on the insulator-shaped capacitor of the silicon nitride layer, wherein the lower electrode is electrically connected to the lower electrode layer and the upper electrode is electrically connected to the upper electrode layer.

18. The method for forming a capacitor design according to claim 9, characterized in that, Also includes: An additional silicon nitride layer and an additional silicon oxide layer are formed between the first silicon oxide layer and the silicon layer, and The opening is also formed in the additional silicon nitride layer and the additional silicon oxide layer, wherein forming the opening includes: Trenches are formed in the additional silicon nitride layer and the additional silicon oxide layer along the vertical direction; as well as A portion of the additional silicon oxide layer is removed from the trench along the horizontal direction to form a third annular cavity in the additional silicon oxide layer.

19. The method for forming a capacitor design according to claim 18, characterized in that, The formation of the first annular cavity, the second annular cavity, and the third annular cavity includes an isotropic etching process or an anisotropic etching process.

20. The method for forming a capacitor design according to claim 16, characterized in that, The formation of the first annular cavity, the second annular cavity, and the third annular cavity can be achieved by simultaneously forming them using an isotropic etching process or by simultaneously forming them using an anisotropic etching process.

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