Gallium nitride transistor based on ion implantation and method of manufacturing the same

Abstract

The application relates to the technical field of semiconductor devices, and relates to a gallium nitride transistor based on ion implantation and a preparation method thereof, which comprises a substrate, a buffer layer, a channel layer, a barrier layer and a p-type communication layer; a drain and a p-type gallium nitride step are arranged above the p-type communication layer in a spaced mode; a source is arranged above the p-type gallium nitride step; the sidewall of the p-type gallium nitride step facing the drain and the exposed surface of the p-type communication layer are both covered with a dielectric layer; and a gate is arranged above the dielectric layer; the p-type gallium nitride step comprises a first p-type region, an ion implantation region and a second p-type region which are sequentially arranged from bottom to top. The application further provides a preparation method of the gallium nitride transistor based on ion implantation, which comprises the following steps: S1, providing a semiconductor epitaxial wafer; S2, performing high-energy ion implantation; S3, preparing a source; S4, forming a p-type gallium nitride step; S5, preparing a drain; and S6, preparing a gate. The application realizes a stable vertical sandwich structure and does not need multiple epitaxial growths.

Description

Technical Field

[0001] This invention relates to the technical field of semiconductor devices, and more specifically, to a gallium nitride transistor based on ion implantation and a method for fabricating the same. Background Technology

[0002] With the rapid development of integrated circuit technology, wide-bandgap semiconductor materials, represented by gallium nitride (GaN), have gradually become a core research direction in the field of high-voltage, high-frequency, and low-loss power devices due to their wider bandgap, higher breakdown field strength, faster carrier saturation drift velocity, and superior high-temperature stability. In GaN-based circuit systems, p-type field-effect transistors (p-FETs) are key unit devices for constructing complementary logic circuits, high-voltage drive circuits, and various power integrated systems, and their performance directly determines the overall operating efficiency and reliability of the circuit. Meanwhile, to meet the higher requirements of high-voltage and high-power applications for device withstand voltage, current carrying capacity, and dynamic characteristics, vertical-structure gallium nitride power devices, with their advantage of fully utilizing the voltage withstand potential in the material thickness direction through vertical conductive paths, are gradually becoming an important development trend in the power semiconductor field.

[0003] The current mainstream approach to fabricating vertical gallium nitride (GaN) p-type field-effect transistors (FETs) follows the process path of silicon-based and silicon carbide-based vertical devices. This involves fabricating p-GaN / n-GaN / p-GaN vertical stacked structures through continuous epitaxial growth, relying on the PNP junction to achieve the device's normally-off characteristics and current regulation. However, GaN p-type doping primarily uses magnesium as the acceptor impurity. Magnesium exhibits a strong high-temperature memory effect during metal-organic chemical vapor deposition (MOCVD) and undergoes intense upward thermal diffusion during high-temperature epitaxial growth. When an n-type GaN layer is epitaxially grown on top of the underlying p-GaN layer, a large amount of magnesium atoms diffuse and incorporate into the intermediate n-GaN layer, severely compensating for the n-type doping. In extreme cases, this can completely reverse the n-GaN layer to p-type, causing the PN junction depletion region inside the device to completely fail, thus preventing normal blocking and switching functions. Summary of the Invention

[0004] The purpose of this invention is to overcome the shortcomings of existing technologies that use chemical vapor deposition to cause failure of the PN junction depletion region, and to provide a gallium nitride transistor based on ion implantation to achieve a stable vertical sandwich structure without the need to prepare vertical stacks through multiple epitaxial growths.

[0005] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows: A gallium nitride transistor based on ion implantation is provided, comprising a substrate, a buffer layer, a channel layer, a barrier layer and a p-type interconnect layer arranged sequentially from bottom to top; A drain and a p-type gallium nitride step are spaced apart above the p-type interconnect layer. A source is disposed above the p-type gallium nitride step. The sidewall of the p-type gallium nitride step facing the drain and the exposed surface of the p-type interconnect layer are covered with a dielectric layer. The portion of the source facing the drain is covered with the dielectric layer. A gate is disposed above the dielectric layer near the p-type gallium nitride step. The p-type gallium nitride step includes a first p-type region, an ion implantation region, and a second p-type region arranged sequentially from bottom to top; the source electrode forms an ohmic contact with the second p-type region, and the drain electrode covers the p-type interconnect layer and forms an ohmic contact; When the gate is in a zero-bias state, the ion-implanted region blocks the vertical conductive path between the second p-type region and the first p-type region, and the transistor remains in a turned-off state. When a bias voltage corresponding to a threshold is applied to the gate, a vertical conductive channel is formed in the sidewall region of the ion-implanted region near the gate. Holes start from the source, flow sequentially through the second p-type region, the ion-implanted region, the first p-type region, and the p-type interconnect layer, and then reach the drain, and the transistor enters a turned-on state.

[0006] The gallium nitride transistor based on ion implantation of the present invention comprises a p-type interconnect layer stacked from bottom to top on a substrate, a buffer layer, a channel layer, and a barrier layer. A p-type gallium nitride step and a drain are arranged laterally at intervals above the p-type interconnect layer. The p-type gallium nitride step contains a vertical sandwich structure formed in situ from bottom to top, consisting of a first p-type region, an ion-implanted isolation region, and a second p-type region. A source electrode forming an ohmic contact with the second p-type region is disposed at the top of the step. The sidewalls of the p-type gallium nitride step facing the drain, the exposed surface of the p-type interconnect layer, and the source electrode are also included. The upper surface facing the drain is covered with a dielectric layer, and a gate is disposed above the dielectric layer. During device operation, the electric field applied to the gate dynamically controls the carrier distribution on the sidewall of the ion-implanted isolation region. In the zero-bias state, the isolation region blocks the vertical path between the second p-type region and the first p-type region, maintaining the transistor in a stable normally-off blocking state. When a threshold bias voltage is applied, a vertical conductive channel is induced on the sidewall of the isolation region, allowing holes to flow from the source sequentially through the second p-type region, the vertical conductive channel, the first p-type region, and the p-type interconnect layer to reach the drain, thus achieving conduction. This invention eliminates the need for multiple epitaxial growths to prepare vertically doped stacks, fundamentally avoiding the high-temperature memory effect and doping compensation failure problems of magnesium in gallium nitride epitaxial processes. Simultaneously, relying on the electric field control mechanism of the sidewall gate, it effectively reduces conduction losses while ensuring the device's high-voltage blocking capability, combining advantages in both process feasibility and electrical performance.

[0007] Furthermore, the implanted ions in the ion implantation region are one or more combinations of fluorine ions, argon ions, helium ions, nitrogen ions, or oxygen ions, and the p-type gallium nitride steps form a PIP sandwich structure. By limiting the high-resistivity region of the ion implantation to one or more of fluorine, argon, helium, nitrogen, and oxygen ions, the p-type gallium nitride steps are constructed into a PIP sandwich structure. These ions can trap charge carriers by introducing deep-level lattice defects or combine with magnesium acceptors in p-type gallium nitride to form electrically neutral complexes, precisely achieving high-resistivity isolation in local areas, effectively reducing vertical leakage current in the off state, ensuring excellent normally-off blocking characteristics and high-voltage withstand capability of the device, while the implantation process parameters are highly controllable, accurately matching the depth and resistivity requirements of the high-resistivity region, and adapting to device designs with different withstand voltage levels.

[0008] Furthermore, the implanted ions in the ion implantation region are silicon ions, and the p-type gallium nitride steps form a PNP sandwich structure. By limiting the isolation region to silicon ion implantation, the p-type gallium nitride steps are constructed into a PNP sandwich structure. Silicon ions, as donor impurities, can achieve precise n-type doping compensation for p-type gallium nitride. The current blocking in the vertical direction is achieved by relying on the depletion effect of the reverse bias of the PN junction. Compared with high-resistance isolation, it has a higher blocking voltage and a lower reverse leakage current. At the same time, the doping concentration and thickness of the intermediate n-type region can be flexibly controlled by adjusting the silicon ion implantation dose and energy, which is suitable for power device applications with higher withstand voltage. Moreover, it can share the ion implantation process with the PIP structure, improving process compatibility.

[0009] Furthermore, the substrate is any one of a silicon substrate, a silicon carbide substrate, a sapphire substrate, or a self-supporting gallium nitride substrate; the buffer layer is an aluminum nitride layer or an aluminum gallium nitride layer, and the barrier layer is an aluminum gallium nitride layer or an indium aluminum gallium nitride layer. By limiting the selectable material systems of the substrate, buffer layer, and barrier layer, epitaxial schemes can be flexibly matched according to the device's performance positioning and cost requirements: silicon, silicon carbide, sapphire, and other substrates respectively take into account mass production costs, lattice matching, and insulation characteristics; aluminum nitride and aluminum gallium nitride buffer layers can effectively alleviate lattice mismatch and improve the quality of epitaxial crystals; aluminum gallium nitride or indium aluminum gallium nitride barrier layers can construct high-quality conductive channels through polarization effects. The entire material system is a mature commercial solution for gallium nitride devices, which can be directly compatible with existing wafer production lines, reducing the manufacturing threshold and mass production costs while ensuring the electrical performance of the device.

[0010] Furthermore, the source and drain are made of one or more of nickel, gold, palladium, platinum, titanium, and titanium nitride; the gate is made of one or more of polysilicon, titanium nitride, tungsten, nickel, gold, or aluminum. By limiting the selectable materials of the source, drain, and gate, the contact characteristics and gate control requirements of the device are adapted: the source and drain use high work function metals such as nickel, gold, and palladium, or their stacks, which can form ohmic contacts with p-type gallium nitride with low specific contact resistance, effectively reducing the conduction loss of the device and improving the current output capability; the gate uses materials such as polysilicon, titanium nitride, and tungsten, which have excellent step coverage and conductivity, can uniformly fit the sidewall structure and reduce the gate distributed resistance, improve the high-frequency switching characteristics and long-term thermal stability of the device, and are suitable for high-power and high-frequency application scenarios.

[0011] Furthermore, the dielectric layer is made of one or more of the following materials: alumina, silicon dioxide, silicon nitride, silicon oxynitride, hafnium oxide, or zirconium oxide. By limiting the choice of dielectric layer material, the gate control performance of the device can be optimized while ensuring the reliability of gate insulation: conventional dielectric materials such as alumina, silicon dioxide, and silicon nitride have wide band gaps and high breakdown field strengths, which can effectively suppress gate leakage current and improve gate withstand voltage. Moreover, conformal coverage of sidewalls and mesa can be achieved through atomic layer deposition, ensuring the uniformity of electric field control. High dielectric constant dielectrics such as hafnium oxide and zirconium oxide can also increase the equivalent gate capacitance, enhance the gate's control over the channel, optimize the device's subthreshold swing, reduce switching losses, and further improve the device's dynamic performance and switching speed.

[0012] This invention also provides a method for fabricating gallium nitride transistors based on ion implantation, comprising the following steps: S1. A semiconductor epitaxial wafer is provided, wherein the epitaxial wafer comprises, from bottom to top, a substrate, a buffer layer, a channel layer, an aluminum gallium nitride barrier layer and a top p-type gallium nitride layer; S2. Perform high-energy ion implantation on the p-type gallium nitride layer to form an ion implantation region at a specified depth in the layer thickness direction, so that the p-type gallium nitride layer forms a sandwich structure of a first p-type region, an ion implantation region, and a second p-type region from bottom to top in the vertical direction; S3. Select the source metal region through photolithography, deposit metal material in the source metal region and perform thermal annealing to form an ohmic contact source. S4. Using the source ohmic contact as a hard mask, a portion of the p-type gallium nitride layer is removed by a dry etching process. The remaining bottom p-type gallium nitride layer serves as a p-type interconnect layer. The unetched area forms a raised p-type gallium nitride step, while exposing the sidewalls of the sandwich structure. S5. Select the drain metal region through photolithography, deposit metal material in the drain metal region and perform thermal annealing to form an ohmic contact drain. S6. A dielectric layer is formed by deposition on the sidewall of the p-type gallium nitride step facing the drain, the exposed surface of the p-type interconnect layer, and the upper surface of the source facing the drain. Then, a conductive material is deposited on the dielectric layer and patterned to form a gate.

[0013] The present invention discloses a method for fabricating gallium nitride transistors based on ion implantation. First, a semiconductor epitaxial wafer is provided, comprising a substrate, a buffer layer, a channel layer, an aluminum gallium nitride barrier layer, and a top p-type gallium nitride layer from bottom to top. High-energy ion implantation is performed on the p-type gallium nitride layer to form an ion implantation isolation region at a specified depth, constructing a vertical sandwich structure of a first p-type region, an ion implantation isolation region, and a second p-type region. Then, the source metal region is defined by photolithography, and a metal deposition and annealing process is performed to form a source ohmic contact. Subsequently, dry etching is performed using the source ohmic contact as a hard mask to remove part of the p-type gallium nitride layer, forming a p-type interconnect layer and raised p-type gallium nitride steps, exposing the sidewalls of the sandwich structure. Next, the drain region is defined by photolithography, and a metal deposition and annealing process is performed to form a drain ohmic contact. Finally, a dielectric layer is deposited on the step sidewalls, the exposed surface of the interconnect layer, and the upper surface of the source portion. The gate is then fabricated by conductive material deposition and patterning. This invention eliminates the need for multiple epitaxial growth processes to prepare vertically doped stacks, avoiding the high-temperature memory effect and doping compensation failure of magnesium in gallium nitride epitaxial processes. At the same time, relying on the source self-aligned etching process, it eliminates the need for additional mask preparation and photolithography alignment steps, which simplifies the process flow, reduces manufacturing costs, reduces photolithography alignment errors, improves process accuracy, and can be directly adapted to commercial gallium nitride epitaxial wafers, thus possessing good production line compatibility and industrial promotion value.

[0014] Furthermore, in step S2, the implanted ions are selected from one or more combinations of fluoride ions, argon ions, helium ions, nitrogen ions, or oxygen ions to construct a PIP-type sandwich structure; or silicon ions are selected to construct a PNP-type sandwich structure. By limiting the two selectable ion implantation systems, the same fabrication process can flexibly construct both PIP and PNP vertical sandwich structures. When using fluoride, argon, helium, nitrogen, or oxygen ions, a high-resistivity isolation region can be formed by relying on deep-level defects or impurities for compensation. The process is easy to implement, has good thermal stability, and is suitable for medium- and low-voltage high-frequency applications. When using silicon ion implantation, an n-type region can be formed through donor doping. Relying on the PN junction depletion effect, better blocking performance and lower reverse leakage current can be achieved, making it suitable for high-voltage power applications. This design does not require changing the epitaxial wafer system; it can adapt to the fabrication of devices with different performance requirements simply by adjusting the type of implanted ions. This effectively broadens the process window and product applicability range, and improves the reuse efficiency of the production line.

[0015] Furthermore, the annealing temperature in steps S3 and S5 is 400℃~600℃, and the annealing time is 3~15 minutes. By limiting the thermal annealing temperature during the source and drain fabrication process to 400℃~600℃ and the annealing time to 3~15 minutes, it is possible to ensure that the metal layer and p-type gallium nitride undergo sufficient alloying reaction to form an ohmic contact with low specific contact resistance, thereby reducing the conduction loss and contact voltage drop of the device. At the same time, the thermal impact of the annealing process can be controlled within a safe range, avoiding significant secondary thermal diffusion of dopants in the ion-implanted isolation region and preventing the degradation of the blocking characteristics of the isolation region. Meanwhile, the mild annealing conditions can also reduce high-temperature damage and impurity redistribution on the gallium nitride surface, ensuring the consistency and stability of the device threshold voltage and electrical parameters.

[0016] Furthermore, in step S4, the difference between the dry etching depth and the ion implantation depth is greater than 10 nm. After dry etching, a tetramethylammonium hydroxide solution is used to perform wet repair treatment on the sidewalls of the p-type gallium nitride step. By limiting the dry etching depth to exceed the ion implantation depth by more than 10 nm, it can be ensured that the complete sidewall interface of the ion implantation isolation region is fully exposed on the side of the gate trench, so that the gate electric field can completely cover the isolation region along the thickness direction, giving full play to the control efficiency of the sidewall electric field, and avoiding the problem of shortened effective conductive channels and increased on-resistance due to insufficient etching. At the same time, the use of tetramethylammonium hydroxide solution to perform wet repair on the step sidewalls can effectively remove lattice damage, surface dangling bonds and etching residues introduced by dry etching, reduce the sidewall interface state density, reduce the current collapse effect caused by carrier scattering and interface traps, and further improve the conduction performance and long-term operational reliability of the device.

[0017] Compared with the prior art, the beneficial effects of the present invention are: 1. By avoiding the bottleneck of epitaxial doping, a stable vertical sandwich structure can be achieved. There is no need to prepare vertical stacks through multiple epitaxial growths. The isolation region can be formed in situ in the integrated p-type gallium nitride layer by high-energy ion implantation, which can construct PIP or PNP vertical structures. This avoids the high-temperature memory effect of magnesium and the failure of doping compensation caused by chemical vapor deposition. 2. Self-aligned etching simplifies the process and improves process accuracy and controllability. Using the source ohmic contact metal as a hard mask to perform dry etching to form a stepped structure, it eliminates the need for additional mask deposition and photolithography alignment and stripping processes, significantly simplifying the process flow. At the same time, the etching depth is precisely controlled below the implantation depth, fully exposing the sidewall modulation interface of the isolation region, ensuring the efficiency of the gate electric field in regulating the vertical conductive channel. 3. The sidewall gate control balances high voltage blocking and low conduction loss, with excellent reliability. In the zero bias state, the high resistance isolation region can achieve reliable normally closed blocking. In the conduction state, a vertical conductive channel is induced on the sidewall of the isolation region, forming a U-shaped conductive path to reduce the conduction resistance, thus achieving a balance between high voltage blocking capability and low conduction loss. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of a gallium nitride transistor based on ion implantation. Figure 2 A top view of a gallium nitride transistor based on ion implantation; Figure 3 This is a flowchart of a gallium nitride transistor fabrication method based on ion implantation.

[0019] In the attached figures: 110, substrate; 120, buffer layer; 130, channel layer; 140, barrier layer; 150, p-type connection layer; 200, drain; 300, source; 400, gate; 500, dielectric layer; 600, first p-type region; 700, ion implantation region; 800, second p-type region. Detailed Implementation

[0020] The present invention will be further described below with reference to specific embodiments. The accompanying drawings are for illustrative purposes only, representing schematic diagrams rather than actual physical objects, and should not be construed as limiting the scope of this patent. To better illustrate the embodiments of the present invention, some components in the drawings may be omitted, enlarged, or reduced, and do not represent the actual dimensions of the product. It is understandable to those skilled in the art that some well-known structures and their descriptions may be omitted in the drawings.

[0021] In the accompanying drawings of the embodiments of the present invention, the same or similar reference numerals correspond to the same or similar components. In the description of the present invention, it should be understood that if terms such as "upper," "lower," "left," "right," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, they are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, the terms used to describe positional relationships in the drawings are only for illustrative purposes and should not be construed as limiting the present patent. For those skilled in the art, the specific meaning of the above terms can be understood according to the specific circumstances.

[0022] Example 1 This embodiment is a first embodiment of a gallium nitride transistor based on ion implantation, providing a gallium nitride transistor based on ion implantation, including a substrate 110, a buffer layer 120, a channel layer 130, a barrier layer 140 and a p-type interconnect layer 150 arranged sequentially from bottom to top; A drain 200 and a p-type gallium nitride step are disposed at intervals above the p-type interconnect layer 150. A source 300 is disposed above the p-type gallium nitride step. The sidewall of the p-type gallium nitride step facing the drain 200 and the exposed surface of the p-type interconnect layer 150 are covered with a dielectric layer 500. The portion of the source 300 facing the drain 200 is covered with the dielectric layer 500. A gate 400 is disposed above the dielectric layer 500 near the p-type gallium nitride step. The p-type gallium nitride step includes a first p-type region 600, an ion implantation region 700, and a second p-type region 800 arranged sequentially from bottom to top; the source 300 forms an ohmic contact with the second p-type region 800, and the drain 200 covers the p-type interconnect layer 150 and forms an ohmic contact. When the gate 400 is in a zero-bias state, the ion implantation region 700 blocks the vertical conductive path between the second p-type region 800 and the first p-type region 600, and the transistor remains in the off state. When a bias voltage corresponding to the threshold is applied to the gate 400, the ion implantation region 700 forms a vertical conductive path in the sidewall region near the gate 400. Holes start from the source 300, flow sequentially through the second p-type region 800, the ion implantation region 700, the first p-type region 600, and the p-type interconnect layer 150, and then reach the drain 200, and the transistor enters the on state.

[0023] The gallium nitride transistor based on ion implantation of the present invention comprises a p-type interconnect layer 150 disposed on a substrate 110, a buffer layer 120, a channel layer 130, and a barrier layer 140 stacked from bottom to top. A p-type gallium nitride step and a drain 200 are arranged laterally at intervals above the p-type interconnect layer 150. The p-type gallium nitride step contains a vertical sandwich structure formed in situ from bottom to top, consisting of a first p-type region 600, an ion-implanted isolation region, and a second p-type region 800. A source 300 forming an ohmic contact with the second p-type region 800 is disposed at the top of the step. The p-type gallium nitride step faces the sidewall of the drain 200, the exposed surface of the p-type interconnect layer 150, and the source. A dielectric layer 500 covers the upper surface of the portion of the transistor facing the drain 200, and a gate 400 is disposed above the dielectric layer 500. During device operation, the electric field applied by the gate 400 dynamically controls the carrier distribution on the sidewall of the ion-implanted isolation region. In the zero-bias state, the isolation region blocks the vertical path between the second p-type region 800 and the first p-type region 600, maintaining the transistor in a stable normally-off blocking state. When a threshold bias voltage is applied, a vertical conductive channel is induced on the sidewall of the isolation region, allowing holes to flow from the source 300 sequentially through the second p-type region 800, the vertical conductive channel, the first p-type region 600, and the p-type interconnect layer 150 before reaching the drain 200 to achieve conduction. This invention eliminates the need for multiple epitaxial growths to prepare vertically doped stacks, fundamentally avoiding the high-temperature memory effect of magnesium and the failure of doping compensation in gallium nitride epitaxial processes. Simultaneously, relying on the electric field control mechanism of the sidewall gate 400, it effectively reduces conduction losses while ensuring the device's high-voltage blocking capability, combining advantages in both process feasibility and electrical performance.

[0024] The implanted ions in ion implantation region 700 are one or more combinations of fluorine ions, argon ions, helium ions, nitrogen ions, or oxygen ions, forming a PIP sandwich structure with p-type gallium nitride steps. By limiting the high-resistivity region of ion implantation to one or more of fluorine, argon, helium, nitrogen, and oxygen ions, the p-type gallium nitride steps are constructed into a PIP sandwich structure. These ions can trap charge carriers by introducing deep-level lattice defects or combine with magnesium acceptors in p-type gallium nitride to form electrically neutral complexes, precisely achieving high-resistivity isolation in local areas. This effectively reduces vertical leakage current in the off-state, ensuring excellent normally-off blocking characteristics and high-voltage withstand capability of the device. At the same time, the implantation process parameters are highly controllable, allowing for precise matching of the depth and resistivity requirements of the high-resistivity region, adapting to device designs with different withstand voltage levels.

[0025] The substrate 110 can be any one of a silicon substrate, a silicon carbide substrate, a sapphire substrate, or a self-supporting gallium nitride substrate; the buffer layer 120 is an aluminum nitride layer or an aluminum gallium nitride layer; and the barrier layer 140 is an aluminum gallium nitride layer or an indium aluminum gallium nitride layer. By limiting the selectable material systems of the substrate 110, the buffer layer 120, and the barrier layer 140, the epitaxial scheme can be flexibly matched according to the device's performance positioning and cost requirements: silicon, silicon carbide, sapphire, and other substrates 110 respectively take into account mass production cost, lattice matching degree, and insulation characteristics; aluminum nitride and aluminum gallium nitride buffer layers 120 can effectively alleviate lattice mismatch and improve the quality of epitaxial crystals; and aluminum gallium nitride or indium aluminum gallium nitride barrier layers 140 can construct a high-quality conductive channel through polarization effect. The entire material system is a mature commercial solution for gallium nitride devices, which can be directly compatible with existing wafer production lines, reducing the manufacturing threshold and mass production cost while ensuring the electrical performance of the device.

[0026] The source 300 and drain 200 are made of one or more of nickel, gold, palladium, platinum, titanium, and titanium nitride; the gate 400 is made of one or more of polysilicon, titanium nitride, tungsten, nickel, gold, or aluminum. By limiting the optional materials of the source 300, drain 200, and gate 400, the contact characteristics and gate control requirements of the device are adapted respectively: the source and drain use high work function metals such as nickel, gold, and palladium or their stacks, which can form ohmic contacts with p-type gallium nitride with low specific contact resistance, effectively reducing the conduction loss of the device and improving the current output capability; the gate 400 uses materials such as polysilicon, titanium nitride, and tungsten, which have excellent step coverage and conductivity, can uniformly fit the sidewall structure and reduce the distributed resistance of the gate 400, improve the high-frequency switching characteristics and long-term thermal stability of the device, and are suitable for high-power and high-frequency application scenarios.

[0027] The dielectric layer 500 is made of one or more of the following materials: alumina, silicon dioxide, silicon nitride, silicon oxynitride, hafnium oxide, or zirconium oxide. By limiting the optional materials of the dielectric layer 500, the gate control performance of the device can be optimized while ensuring the insulation reliability of the gate 400: conventional dielectric materials such as alumina, silicon dioxide, and silicon nitride have wide band gaps and high breakdown field strengths, which can effectively suppress the leakage current of the gate 400 and improve the withstand voltage capability of the gate 400. Furthermore, conformal coverage of the sidewalls and mesa can be achieved through atomic layer deposition, ensuring the uniformity of electric field control. High dielectric constant dielectrics such as hafnium oxide and zirconium oxide can also increase the equivalent gate 400 capacitance, enhance the gate 400's control capability over the channel, optimize the device's subthreshold swing, reduce switching losses, and further improve the device's dynamic performance and switching speed.

[0028] Example 2 This embodiment is a second embodiment of a gallium nitride transistor based on ion implantation. Similar to the first embodiment, the difference lies in that the implanted ions in the ion implantation region 700 are silicon ions, and the p-type gallium nitride steps form a PNP sandwich structure. By limiting the isolation region to silicon ion implantation, the p-type gallium nitride steps are constructed into a PNP sandwich structure. Silicon ions, as donor impurities, can achieve precise n-type doping compensation for p-type gallium nitride. Current blocking in the vertical direction is achieved through the depletion effect of the reverse bias of the PN junction. Compared to high-resistance isolation, it has a higher blocking voltage and lower reverse leakage current. Furthermore, the doping concentration and thickness of the intermediate n-type region can be flexibly controlled by adjusting the silicon ion implantation dose and energy, adapting to higher voltage-rated power device applications. It can also share the ion implantation process with PIP structures, improving process compatibility.

[0029] Example 3 This embodiment is an example of a gallium nitride transistor fabrication method based on ion implantation, including the following steps: S1. A semiconductor epitaxial wafer is provided, which includes, from bottom to top, a substrate 110, a buffer layer 120, a channel layer 130, an aluminum gallium nitride barrier layer 140, and a top p-type gallium nitride layer. S2. Perform high-energy ion implantation on the p-type gallium nitride layer to form an ion implantation region 700 at a specified depth in the layer thickness direction, so that the p-type gallium nitride layer forms a sandwich structure of a first p-type region 600, an ion implantation region 700, and a second p-type region 800 from bottom to top in the vertical direction. S3. Select the source electrode 300 metal region through photolithography, deposit metal material in the source electrode 300 metal region and perform thermal annealing to form the ohmic contact source electrode 300. S4. Using a 300-ohm source contact as a hard mask, a portion of the p-type gallium nitride layer is removed by a dry etching process. The remaining bottom p-type gallium nitride layer serves as the p-type interconnect layer 150. The unetched area forms a raised p-type gallium nitride step, while exposing the sidewalls of the sandwich structure. S5. Select the metal region of drain 200 through photolithography, deposit metal material in the metal region of drain 200 and perform thermal annealing to form the drain 200 with ohmic contact. S6. A dielectric layer 500 is formed by deposition on the sidewall of the p-type gallium nitride step facing the drain 200, the exposed surface of the p-type interconnect layer 150, and a portion of the upper surface of the source 300 facing the drain 200. Then, a conductive material is deposited on the dielectric layer 500 and patterned to form a gate 400.

[0030] The gallium nitride transistor fabrication method of the present invention first provides a semiconductor epitaxial wafer comprising, from bottom to top, a substrate 110, a buffer layer 120, a channel layer 130, an aluminum gallium nitride barrier layer 140, and a top p-type gallium nitride layer. High-energy ion implantation is performed on the p-type gallium nitride layer to form an ion implantation isolation region at a specified depth, thus constructing a vertical sandwich structure in situ of a first p-type region 600, an ion implantation isolation region, and a second p-type region 800. Then, the source metal region 300 is defined by photolithography, followed by metal deposition and annealing. A 300-ohm source contact is formed, followed by dry etching using the 300-ohm source contact as a hard mask to remove part of the p-type gallium nitride layer, forming a p-type interconnect layer 150 and raised p-type gallium nitride steps, exposing the sidewalls of the sandwich structure. Then, the drain 200 region is defined by photolithography, and metal deposition and annealing form a 200-ohm drain contact. Finally, a dielectric layer 500 is deposited on the step sidewalls, the exposed surface of the interconnect layer, and the upper surface of the source 300 portion. The gate 400 is then fabricated through conductive material deposition and patterning. This invention eliminates the need for multiple epitaxial growth processes to prepare vertically doped stacks, avoiding the high-temperature memory effect and doping compensation failure of magnesium in gallium nitride epitaxial processes. Furthermore, relying on the self-aligned etching process of the source 300 eliminates the need for additional mask preparation and photolithography alignment steps, simplifying the process flow, reducing manufacturing costs, minimizing photolithography alignment errors, improving process accuracy, and directly adapting to commercial gallium nitride epitaxial wafers, demonstrating good production line compatibility and industrial application value.

[0031] In step S2, the implanted ions are selected from one or more combinations of fluoride ions, argon ions, helium ions, nitrogen ions, or oxygen ions to construct a PIP-type sandwich structure; or silicon ions are selected to construct a PNP-type sandwich structure. By limiting the two selectable ion implantation systems, the same fabrication process can flexibly construct both PIP and PNP vertical sandwich structures. When using fluoride, argon, helium, nitrogen, or oxygen ions, a high-resistivity isolation region can be formed by relying on deep-level defects or impurities for compensation. The process is easy to implement, has good thermal stability, and is suitable for medium- and low-voltage high-frequency applications. When using silicon ion implantation, an n-type region can be formed through donor doping. Relying on the PN junction depletion effect, better blocking performance and lower reverse leakage current can be achieved, making it suitable for high-voltage power applications. This design does not require changing the epitaxial wafer system; it can adapt to the fabrication of devices with different performance requirements simply by adjusting the type of implanted ions. This effectively broadens the process window and product applicability range, and improves the reuse efficiency of the production line.

[0032] The annealing temperature in steps S3 and S5 is 400℃~600℃, and the annealing time is 3~15 minutes. By limiting the thermal annealing temperature during the preparation of the source 300 and drain 200 to 400℃~600℃ and the annealing time to 3~15 minutes, it is possible to ensure that the metal layer and p-type gallium nitride undergo sufficient alloying reaction to form an ohmic contact with low specific contact resistance, thereby reducing the conduction loss and contact voltage drop of the device. At the same time, the thermal impact of the annealing process is controlled within a safe range, avoiding significant secondary thermal diffusion of dopants in the ion-implanted isolation region and preventing the degradation of the blocking characteristics of the isolation region. Meanwhile, the mild annealing conditions can also reduce high-temperature damage and impurity redistribution on the gallium nitride surface, ensuring the consistency and stability of the device threshold voltage and electrical parameters.

[0033] In step S4, the difference between the dry etching depth and the ion implantation depth is greater than 10 nm. After dry etching, a tetramethylammonium hydroxide solution is used to perform wet repair treatment on the sidewalls of the p-type gallium nitride step. By limiting the dry etching depth to exceed the ion implantation depth by more than 10 nm, it can be ensured that the complete sidewall interface of the ion implantation isolation region is fully exposed on the side of the gate 400 trench, so that the gate 400 electric field can completely cover the isolation region along the thickness direction, giving full play to the control efficiency of the sidewall electric field, and avoiding the problems of shortened effective conductive channels and increased on-resistance due to insufficient etching. At the same time, the use of tetramethylammonium hydroxide solution to perform wet repair on the step sidewalls can effectively remove lattice damage, surface dangling bonds and etching residues introduced by dry etching, reduce the sidewall interface state density, reduce the current collapse effect caused by carrier scattering and interface traps, and further improve the device's conduction performance and long-term operational reliability. In the specific implementation of the above embodiments, the technical features can be combined in any non-contradictory way. For the sake of brevity, not all possible combinations of the above technical features are described. However, as long as the combination of these technical features is not contradictory, it should be considered to be within the scope of this specification.

[0034] Obviously, the above embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not intended to limit the implementation of the present invention. Those skilled in the art can make other variations or modifications based on the above description. It is neither necessary nor possible to exhaustively describe all embodiments here. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the claims of the present invention.

Claims

1. A gallium nitride transistor based on ion implantation, characterized in that, It includes a substrate (110), a buffer layer (120), a channel layer (130), a barrier layer (140), and a p-type interconnect layer (150) arranged sequentially from bottom to top; A drain (200) and a p-type gallium nitride step are disposed at intervals above the p-type interconnect layer (150). A source (300) is disposed above the p-type gallium nitride step. A dielectric layer (500) covers the sidewall of the p-type gallium nitride step facing the drain (200) and the exposed surface of the p-type interconnect layer (150). The dielectric layer (500) partially covers the side of the source (300) facing the drain (200). A gate (400) is disposed above the dielectric layer (500) near the p-type gallium nitride step. The p-type gallium nitride step includes a first p-type region (600), an ion implantation region (700), and a second p-type region (800) arranged sequentially from bottom to top; the source (300) forms an ohmic contact with the second p-type region (800), and the drain (200) covers the p-type interconnect layer (150) and forms an ohmic contact; When the gate (400) is in a zero-bias state, the ion implantation region (700) blocks the vertical conductive path between the second p-type region (800) and the first p-type region (600), and the transistor remains in a turned-off state. When a bias voltage corresponding to a threshold is applied to the gate (400), the ion implantation region (700) forms a vertical conductive channel in the sidewall region near the gate (400). Holes start from the source (300), flow sequentially through the second p-type region (800), the ion implantation region (700), the first p-type region (600), and the p-type interconnect layer (150) before reaching the drain (200), and the transistor enters a conducting state.

2. The gallium nitride transistor based on ion implantation according to claim 1, characterized in that, The implanted ions in the ion implantation region (700) are one or more combinations of fluorine ions, argon ions, helium ions, nitrogen ions, or oxygen ions, and the p-type gallium nitride steps form a PIP sandwich structure.

3. The gallium nitride transistor based on ion implantation according to claim 1, characterized in that, The implanted ions in the ion implantation region (700) are silicon ions, and the p-type gallium nitride steps form a PNP sandwich structure.

4. The gallium nitride transistor based on ion implantation according to any one of claims 1 to 3, characterized in that, The substrate (110) is any one of a silicon substrate, a silicon carbide substrate, a sapphire substrate, or a self-supporting gallium nitride substrate; the buffer layer (120) is an aluminum nitride layer or an aluminum gallium nitride layer; and the barrier layer (140) is an aluminum gallium nitride layer or an indium aluminum gallium nitride layer.

5. The gallium nitride transistor based on ion implantation according to any one of claims 1 to 3, characterized in that, The source (300) and drain (200) are made of one or more of nickel, gold, palladium, platinum, titanium, and titanium nitride; the gate (400) is made of one or more of polysilicon, titanium nitride, tungsten, nickel, gold, or aluminum.

6. The gallium nitride transistor based on ion implantation according to any one of claims 1 to 3, characterized in that, The material of the dielectric layer (500) is one or more of aluminum oxide, silicon dioxide, silicon nitride, silicon oxynitride, hafnium oxide, or zirconium oxide.

7. A method for fabricating gallium nitride transistors based on ion implantation, used to fabricate gallium nitride transistors based on ion implantation as described in any one of claims 1 to 6, characterized in that, Includes the following steps: S1. A semiconductor epitaxial wafer is provided, wherein the semiconductor epitaxial wafer comprises, from bottom to top, a substrate (110), a buffer layer (120), a channel layer (130), an aluminum gallium nitride barrier layer (140), and a top p-type gallium nitride layer; S2. Perform high-energy ion implantation on the p-type gallium nitride layer to form an ion implantation region (700) at a specified depth in the layer thickness direction, so that the p-type gallium nitride layer forms a sandwich structure of a first p-type region (600), an ion implantation region (700), and a second p-type region (800) from bottom to top in the vertical direction. S3. Select the source (300) metal region through photolithography, deposit metal material in the source (300) metal region and perform thermal annealing to form an ohmic contact source (300); S4. Using the source (300) ohmic contact as a hard mask, a portion of the p-type gallium nitride layer is removed by a dry etching process. The remaining bottom p-type gallium nitride layer is used as a p-type interconnect layer (150). The unetched area forms a raised p-type gallium nitride step, while exposing the sidewall of the sandwich structure. S5. Select the drain (200) metal region by photolithography, deposit metal material in the drain (200) metal region and perform thermal annealing to form an ohmic contact drain (200); S6. A dielectric layer (500) is formed by deposition on the sidewall of the p-type gallium nitride step facing the drain (200), the exposed surface of the p-type interconnect layer (150), and a portion of the upper surface of the source (300) facing the drain (200). Then, a conductive material is deposited on the dielectric layer (500) and patterned to form a gate (400).

8. The method for fabricating gallium nitride transistors based on ion implantation according to claim 7, characterized in that, In step S2, the implanted ions are selected from one or more combinations of fluoride ions, argon ions, helium ions, nitrogen ions, or oxygen ions to construct a PIP-type sandwich structure; or silicon ions are selected as the implanted ions to construct a PNP-type sandwich structure.

9. The method for fabricating gallium nitride transistors based on ion implantation according to claim 7, characterized in that, The annealing temperature in steps S3 and S5 is 400℃~600℃, and the annealing time is 3~15 minutes.

10. The method for fabricating gallium nitride transistors based on ion implantation according to claim 7, characterized in that, In step S4, the difference between the depth of dry etching and the depth of ion implantation is greater than 10 nm; after dry etching is completed, the sidewalls of the p-type gallium nitride step are wet-processed using tetramethylammonium hydroxide solution.

Images