Trench gate device inter-electrode dielectric layer forming method and device

Abstract

This invention provides a method and device for forming an inter-electrode dielectric layer in a trench gate device. The method includes: providing a substrate, the substrate including a mesa and a trench, with an active conductive layer within the trench; depositing an insulating dielectric layer on the substrate, covering the mesa and partially filling the trench; forming a planarization layer on the insulating dielectric layer to create a planarized morphology; integrally etching the planarization layer and the insulating dielectric layer, stopping at the mesa surface and retaining the insulating dielectric layer within the trench; and removing the remaining planarization layer to form the inter-electrode dielectric layer. This invention reduces the thickness of the insulating dielectric layer and utilizes the planarization layer to assist etching, eliminating the need for chemical mechanical planarization and complex hard mask processes, simplifying the process and reducing costs. Simultaneously, it reduces plasma bombardment damage, improves wafer warpage, and enhances device parameter stability and production yield.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit manufacturing, and in particular to a method and device for forming an inter-electrode dielectric layer in a trench gate device. Background Technology

[0002] In the fabrication of trench gate semiconductor devices such as ultra-high density shielded gate trench transistors (UDSGTs), the formation of the inter-electrode dielectric (IPD, often referred to in the art as IPO or IPD) is one of the core process steps. This inter-electrode dielectric layer is mainly used to isolate the source shielding electrode at the bottom of the trench from the subsequently formed gate electrode, and its morphology and quality directly affect the reliability and electrical performance of the device.

[0003] In conventional trench gate device inter-electrode dielectric layer formation methods, after etching the source conductive layer, the field dielectric layer on the trench sidewalls is typically removed to increase the aspect ratio of the high-density plasma (HDP) oxide. Subsequently, a high-density plasma oxide layer, typically up to, for example, about 22,000 angstroms thick, is deposited to completely fill the trench. Next, the high-density plasma oxide is etched back onto the silicon nitride plane of the hard mask using a chemical mechanical planarization (CMP) process. Finally, after removing the hard mask, wet etching is used for etch-back to obtain the desired morphology.

[0004] However, the above-mentioned conventional process has the following obvious drawbacks:

[0005] First, in the formation of conventional inter-electrode dielectric layers, hard masks require a complex structure of silicon oxide-silicon nitride-silicon oxide (ONO). Furthermore, due to the large amount of high-density plasma oxide filling, chemical mechanical planarization (CMP) and silicon nitride stop layers are necessary, resulting in a lengthy overall process and high manufacturing costs.

[0006] Secondly, in terms of product preparation and performance, due to the huge amount of high-density plasma oxide filling, the plasma bombardment during the filling process is extremely severe, which can easily lead to device parameter failure. At the same time, ultra-thick film deposition can cause severe wafer warping, making it difficult to process the wafers on subsequent equipment and reducing production yield.

[0007] Therefore, simplifying the process, reducing costs, and improving wafer warpage have become urgent technical problems to be solved in this field. Summary of the Invention

[0008] The problems to be solved by this invention are the following in conventional inter-electrode dielectric layer formation processes: complex hard mask structure, large amount of high-density plasma oxide filling which necessitates chemical mechanical planarization process, high manufacturing cost, severe plasma bombardment, and large wafer warpage.

[0009] A method for forming an inter-electrode dielectric layer in a trench gate device includes:

[0010] Step 1: Provide a substrate, the substrate including mesa and trenches located between the mesa, wherein an active conductive layer is formed in the trench;

[0011] Step 2: Deposit an insulating dielectric layer on the substrate, the insulating dielectric layer covering the mesa and partially filling the trench;

[0012] Step 3: Form a planarization layer on the insulating dielectric layer to form a planarization morphology;

[0013] Step 4: Perform integrated etching on the planarization layer and the insulating dielectric layer, stopping the integrated etching on the mesa surface to preserve the insulating dielectric layer within the trench;

[0014] Step 5: Remove the remaining planarization layer to form an inter-electrode dielectric layer within the trench.

[0015] Preferably, in step one, after forming the source conductive layer, the field dielectric layer of the trench sidewall is removed.

[0016] Preferably, in step two, the insulating dielectric layer material comprises a high-density plasma oxide.

[0017] Preferably, in step two, the deposition thickness of the insulating dielectric layer is 4000 angstroms to 6000 angstroms.

[0018] Preferably, in step three, the planarization layer material includes a bottom anti-reflective coating.

[0019] Preferably, in step three, the planarization layer material comprises an advanced patterned thin film.

[0020] Preferably, in step four, the planarization layer is used to protect the insulating dielectric layer within the trench.

[0021] Preferably, in step four, the integrated etching includes simultaneously etching the planarization layer and the insulating dielectric layer on the surface.

[0022] Preferably, the trench gate device includes an ultra-high density shielded gate trench transistor.

[0023] A trench gate device includes an inter-electrode dielectric layer prepared by any of the above-described methods for forming an inter-electrode dielectric layer.

[0024] As described above, the trench gate device inter-electrode dielectric layer formation method and device of the present invention have the following beneficial effects:

[0025] By reducing the deposition thickness of the insulating dielectric layer and introducing a planarization layer for integrated etching, the complex hard mask structure, chemical mechanical planarization process, and silicon nitride stop layer are eliminated, significantly simplifying the process flow and reducing manufacturing costs. The thinner insulating dielectric layer greatly reduces plasma bombardment during the deposition process, lowers the device parameter failure rate, effectively improves wafer warpage, and increases production yield. The final inter-electrode dielectric layer morphology is consistent with that of traditional processes, ensuring the electrical performance and reliability of the device. Attached Figure Description

[0026] Figure 1 The diagram shows a process flow diagram of the trench gate device inter-electrode dielectric layer formation method of the present invention;

[0027] Figure 2 The diagram shows a cross-sectional structure of the trench gate device inter-electrode dielectric layer formation method of the present invention, in which the height of the source conductive layer is defined by photoresist.

[0028] Figure 3 The diagram shows a cross-sectional structure of the field dielectric layer patterned with photoresist in the trench gate device inter-electrode dielectric layer formation method of the present invention.

[0029] Figure 4 The diagram shows a cross-sectional structure of the deposited insulating dielectric layer in the trench gate device inter-electrode dielectric layer formation method of the present invention.

[0030] Figure 5 The diagram shows a cross-sectional structure of the planarization layer formed in the trench gate device inter-electrode dielectric layer formation method of the present invention.

[0031] Figure 6 The diagram shows a cross-sectional structure after integrated etching in the trench gate device inter-electrode dielectric layer formation method of the present invention.

[0032] Figure 7 The diagram shows a cross-sectional structure after removing the planarization layer in the trench gate device inter-electrode dielectric layer formation method of the present invention. Detailed Implementation

[0033] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0034] Please refer to Figure 1 , Figure 1 A schematic diagram of the process flow of an embodiment of this disclosure is shown. A method for forming an inter-electrode dielectric layer of a trench gate device includes:

[0035] Step 1: Provide a substrate 101, which includes a mesa 102 and a trench located between the mesa 102, and form an active conductive layer 103 in the trench.

[0036] In some embodiments, step one, after forming the source conductive layer 103, further includes removing the field dielectric layer 102 from the trench sidewalls.

[0037] Please see Figure 2 , Figure 2 The diagram shows a cross-sectional structure of the source conductive layer 103 defined by photoresist 104 in step one.

[0038] Substrate 101 may include a bulk semiconductor substrate or a silicon-on-insulator (SOI) substrate. The SOI substrate includes an insulating layer beneath a thin semiconductor layer serving as the active layer. The semiconductor in the active layer and the bulk semiconductor typically include the crystalline semiconductor material silicon, but may also include one or more other semiconductor materials, such as germanium, silicon-germanium alloys, compound semiconductors (e.g., GaAs, AlAs, InAs, GaN, AlN, etc.) or alloys thereof (e.g., GaxAl1-xAs, GaxAl1-xN, InxGa1-xAs, etc.), oxide semiconductors (e.g., ZnO, SnO2, TiO2, Ga2O3, etc.), or combinations thereof. The semiconductor material may be doped or undoped. Other substrates that may be used include multilayer substrates, gradient substrates, or mixed-orientation substrates.

[0039] In actual manufacturing environments, semiconductor manufacturing equipment typically grows one or more epitaxial layers with varying doping concentrations on a base substrate 101 to meet the voltage withstand and on-resistance requirements of different power devices. Mesa areas are typically unetched protruding regions within the substrate 101, where subsequent processes form device channel regions, body regions, and source regions. Trench formation usually involves depositing a hard mask layer on the surface of the substrate 101, forming a pattern using photolithography, and then performing anisotropic etching processes, such as deep reactive ion etching, using dry etching equipment to transfer the pattern into the substrate 101. The source conductive layer 103 can include conductive materials such as in-situ doped polysilicon, undoped polysilicon, tungsten, aluminum, titanium nitride, or metal silicides. The source conductive layer 103 is typically used as a shielding gate electrode. Its formation process includes depositing conductive material in a trench using a low-pressure chemical vapor deposition device, followed by using photoresist 104 as a mask to perform an etch-back process to precisely define the etching depth of the source conductive layer 103 and reduce its height so that the top of the source conductive layer 103 is located at a preset depth.

[0040] Please see Figure 3 , Figure 3 The diagram illustrates the cross-sectional structure of the field dielectric layer 102 patterned using photoresist 105 in step one. The field dielectric layer 102 is formed on the trench sidewalls and serves to isolate the source conductive layer 103 from the substrate 101. Using photoresist 105 as a mask, isotropic etching is performed using a wet cleaning system to selectively remove the field dielectric layer 102 on the upper sidewalls of the trench. This removal of the sidewall field dielectric layer 102 effectively widens the opening size at the top of the trench, thereby increasing the aspect ratio during subsequent deposition of the insulating dielectric layer, improving the filling morphology, preventing premature closure of the trench opening and the generation of internal voids or gaps, and enhancing the structural integrity of the device.

[0041] Step 2: Deposit an insulating dielectric layer 106 on the substrate 101. The insulating dielectric layer 106 covers the mesa and partially fills the trench.

[0042] In some embodiments, in step two, the insulating dielectric layer 106 material comprises a high-density plasma oxide.

[0043] In some embodiments, in step two, the insulating dielectric layer 106 is deposited with a thickness of 4,000 to 6,000 angstroms.

[0044] Please see Figure 4 , Figure 4This diagram illustrates the completed deposition of the insulating dielectric layer 106, covering the cross-sectional structure of the mesa and trench interior. Besides high-density plasma oxides, the insulating dielectric layer 106 material can also include tetraethyl orthosilicate oxide, silane oxide, borosilicate glass, phosphosilicate glass, undoped silicate glass, or silicon-rich oxides. The deposition process can be performed using high-density plasma chemical vapor deposition (PDCVD), sub-atmospheric pressure PDCVD, flowable PDCVD, or atomic layer deposition (ALD). PDCVD features simultaneous deposition and sputtering, enabling excellent bottom-up gap filling. By strictly controlling the PDCVD thickness to approximately 5K angstroms (4000 to 6000 angstroms), a single-pass deposition is achieved, significantly reducing the PDCVD layer thickness compared to the ultra-thick deposition of up to 22K angstroms in traditional processes. This thin-film deposition method greatly reduces plasma bombardment time and intensity during deposition, minimizing physical damage and charge accumulation effects on the underlying structure, thereby reducing the device parameter failure rate. Meanwhile, the thinner deposition layer effectively reduces residual stress inside the film, improves wafer warpage, and enhances the smoothness of subsequent lithography and metrology equipment, preventing mechanical transmission failures caused by wafer deformation. In addition, the partially filled state allows the insulating dielectric layer 106 to conformally cover the mesa and trenches, reserving sufficient physical space for subsequent planarization material filling.

[0045] Step 3: A planarization layer 107 is formed on the insulating dielectric layer 106 to form a planarization morphology;

[0046] In some embodiments, in step three, the planarization layer 107 material includes a bottom anti-reflective coating.

[0047] In some embodiments, in step three, the planarization layer 107 material includes an advanced patterned thin film.

[0048] Please see Figure 5 , Figure 5A schematic diagram of the cross-sectional structure after the planarization layer 107 is formed is shown. The planarization layer 107 may also include spin-coated carbon materials, spin-coated glass materials, photoresists, carbon-containing polymers, or amorphous carbon, which are sacrificial materials with good flowability and gap-filling properties. The process for forming the planarization layer 107 can be either spin-coating or plasma-enhanced chemical vapor deposition, depending on the material characteristics. For example, when using a bottom anti-reflective coating or spin-coated carbon materials, the coating and developing equipment drops liquid polymer materials onto the surface of a rotating wafer, uses centrifugal force to distribute them evenly and allow them to flow into the trenches, and then uses a multi-step baking process to evaporate the solvent and promote cross-linking and curing of the material. When using advanced patterned thin films, chemical vapor deposition equipment deposits carbon-rich thin films at specific temperatures and pressures. The planarization layer 107 can fill the remaining space in the trenches with its own flowability or deposition characteristics, while covering the insulating dielectric layer 106 above the mesa, thereby forming a globally planarized morphology on the wafer surface. This flattened topography effectively eliminates the undulations caused by the underlying platform and trenches, allowing subsequent etching processes to be performed on a uniform and flat reference plane. This avoids local etching residues or over-etching problems caused by topographic undulations, improving process uniformity and controllability.

[0049] Step 4: Perform integrated etching on the planarization layer 107 and the insulating dielectric layer 106. The integrated etching stops at the mesa surface to preserve the insulating dielectric layer 106 in the trench.

[0050] In some embodiments, in step four, the planarization layer 107 is used to protect the insulating dielectric layer 106 in the trench.

[0051] In some embodiments, step four, the integrated etching includes simultaneously etching the surface planarization layer 107 and the insulating dielectric layer 106.

[0052] Please see Figure 6 , Figure 6A schematic diagram of the cross-sectional structure after integrated etching is shown. Integrated etching is typically performed using dry etching equipment, such as capacitively coupled plasma (CCP) etching machines or inductively coupled plasma (ICP) etching machines. During the etching process, the etching gas ratio, chamber pressure, and RF power are precisely adjusted to ensure that the planarization layer 107 and the insulating dielectric layer 106 have similar or identical etching rates. The etching gas can include a mixture of fluorocarbon-based gases (such as carbon tetrafluoride, octafluorocyclobutane, or trifluoromethane) and oxygen, argon, and helium. Because the trench is filled with a relatively thick planarization layer 107, this planarization layer 107 acts as a sacrificial mask for the insulating dielectric layer 106 within the trench when etching the insulating dielectric layer 106 above the mesa, effectively preventing excessive consumption and physical damage to the insulating dielectric layer 106 inside the trench by plasma ions. The etching equipment can be equipped with an optical emission spectrum endpoint detection system. When the etching front reaches the silicon surface of the mesa, a specific silicon byproduct emission signal is generated in the plasma, and the system accurately stops the etching process accordingly. This integrated etching solution stops directly on the mesa surface, eliminating the need for a traditional silicon nitride stop layer or a complex silicon oxide-silicon nitride-silicon oxide hard mask structure. It completely eliminates the expensive, time-consuming, and defect-prone chemical mechanical planarization process, significantly simplifying the overall process flow, shortening the production cycle, and greatly reducing manufacturing costs.

[0053] Step 5: Remove the remaining planarization layer 107 to form an interpolar dielectric layer 106 within the trench.

[0054] Please see Figure 7 , Figure 7A schematic diagram of the cross-sectional structure after removing the planarization layer 107 is shown. The process for removing the remaining planarization layer 107 can be either a dry ashing process or a wet cleaning process, depending on the specific material of the planarization layer 107. For carbon-based planarization layers 107, plasma debinding equipment is typically used, where oxygen or a hydrogen-nitrogen mixture is introduced to generate plasma, oxidizing or reducing the carbon-based material into volatile gases that are then discharged from the chamber. Subsequently, a wet cleaning device can be used, employing a mixture of sulfuric acid and hydrogen peroxide or a mixture of ammonia and hydrogen peroxide, to thoroughly remove any possible organic residues or polymer byproducts. After removing the planarization layer 107, the insulating dielectric layer 106 remaining at the bottom of the trench constitutes the inter-electrode dielectric layer 106. In some embodiments, the insulating dielectric layer 106 remaining on the upper sidewall of the trench can be directly used as the gate dielectric layer, which can further reduce deposition and thermal oxidation steps and lower the thermal budget. In other preferred embodiments, to obtain better interface characteristics, the residual insulating dielectric layer 106 on the upper sidewall of the trench can be removed first by a wet etching process, and then a high-quality gate dielectric layer can be re-formed by a thermal oxidation process, an in-situ vapor growth process, or an atomic layer deposition process. The final inter-electrode dielectric layer 106 exhibits the expected flatness or micro-concave morphology, which is highly consistent with the morphology obtained by conventional complex processes. It can effectively isolate the bottom source conductive layer 103 from the subsequently formed control gate structure, preventing leakage or breakdown between the two, and ensuring that the device has excellent withstand voltage characteristics, low parasitic capacitance, and stable electrical performance.

[0055] In some embodiments, the trench gate device includes an ultra-high density shielded gate trench transistor.

[0056] Ultra-high density shielded gate trench transistors typically include a shielded gate electrode at the bottom of the trench and a control gate electrode at the top of the trench, electrically isolated from each other by an inter-electrode dielectric layer 106. The shielded gate electrode is typically connected to the source to shield the electric field between the gate and drain, thereby reducing Miller capacitance and improving device switching speed. The method provided in this disclosure is also applicable to other types of trench-gate power semiconductor devices, such as insulated-gate bipolar transistors, metal-oxide-semiconductor field-effect transistors, or silicon carbide trench devices. These devices are widely used in power management systems in fields such as switching power supplies, motor drives, automotive electronics, photovoltaic inverters, and consumer electronics.

[0057] In some embodiments, after forming the inter-electrode dielectric layer 106, subsequent processes include forming a gate dielectric layer on the upper sidewall of the trench. The gate dielectric layer can be formed by thermal oxidation, in-situ vapor deposition, or atomic layer deposition, and its thickness is precisely adjusted according to the threshold voltage requirements of the device. Subsequently, a semiconductor manufacturing apparatus uses low-pressure chemical vapor deposition or plasma-enhanced chemical vapor deposition to fill the trench with a second conductive material to form a control gate electrode. The second conductive material may include doped polysilicon, tungsten, aluminum, cobalt, copper, titanium, tantalum, titanium nitride, tantalum nitride, metal silicides, or combinations thereof. After depositing the second conductive material, a chemical mechanical planarization process or a dry etch-back process can be performed to remove excess conductive material from the mesa surface, making the top of the control gate electrode flush with or slightly below the surface of the substrate 101.

[0058] Next, source and drain ion implantation is performed. The ion implantation equipment selects appropriate dopants based on the device type, such as phosphorus, arsenic, antimony, boron, boron fluoride, or indium. The dopants penetrate the surface of substrate 101 into the mesa region, forming the source and drain regions. To activate the dopants and repair lattice damage caused by ion implantation, thermal annealing processes are typically performed, such as rapid thermal annealing, spike annealing, or laser annealing.

[0059] Subsequently, an interlayer insulating layer is deposited over substrate 101. The material of the interlayer insulating layer can include undoped silicate glass, phosphosilicate glass, borosilicate glass, fluorine-doped silicate glass, low-dielectric-constant materials, or extremely low-dielectric-constant materials. The deposition process can employ sub-atmospheric pressure chemical vapor deposition, high-density plasma chemical vapor deposition, or flowable chemical vapor deposition. To provide a flat substrate for subsequent metallization processes, a chemical mechanical planarization (CMP) device is typically used to globally planarize the interlayer insulating layer, ensuring that the surface roughness meets the requirements of high-precision photolithography.

[0060] Finally, the metallization interconnect process is performed. This involves forming contact holes in the interlayer insulating layer using photolithography and etching processes, followed by filling the contact holes with a barrier layer material and a metal plug material. The barrier layer material can include titanium, titanium nitride, tantalum, or tantalum nitride, used to prevent metal diffusion and enhance adhesion; the metal plug material can include tungsten, cobalt, or ruthenium. Next, one or more metal wiring layers are formed over the interlayer insulating layer. The material of the metal wiring layers can include an aluminum-copper alloy or copper. For copper interconnect processes, single-damascene or double-damascene processes are typically used, including electrochemical plating and chemical mechanical planarization. Through these metallization steps, the control gate electrode, source region, and drain region of the device are electrically connected to the external circuitry, ultimately completing the fabrication of the overall device.

[0061] A trench gate device includes an inter-electrode dielectric layer 106 prepared by the inter-electrode dielectric layer formation method of any of the above embodiments.

[0062] This trench gate device, employing the simplified inter-electrode dielectric layer formation method described above, suffers less plasma damage to its internal inter-electrode dielectric layer 106, exhibiting low internal defect density and good thickness uniformity. This not only improves the consistency of wafer edge and center processes and increases the overall device production yield but also enhances the device's switching characteristics, threshold voltage stability, and long-term reliability. Furthermore, the significantly reduced wafer warpage allows for higher alignment accuracy and processing yield in subsequent high-precision photolithography, chemical mechanical planarization, and wafer-level packaging processes, reducing manufacturing costs and enhancing market competitiveness.

[0063] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0064] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for forming an inter-electrode dielectric layer in a trench gate device, characterized in that, At least including: Step 1: Provide a substrate, the substrate including mesa and trenches located between the mesa, wherein an active conductive layer is formed in the trench; Step 2: Deposit an insulating dielectric layer on the substrate, the insulating dielectric layer covering the mesa and partially filling the trench; Step 3: Form a planarization layer on the insulating dielectric layer to form a planarization morphology; Step 4: Perform integrated etching on the planarization layer and the insulating dielectric layer, stopping the integrated etching on the mesa surface to preserve the insulating dielectric layer within the trench; Step 5: Remove the remaining planarization layer to form an inter-electrode dielectric layer within the trench.

2. The method for forming an inter-electrode dielectric layer in a trench gate device according to claim 1, characterized in that: In step one, after forming the source conductive layer, the field dielectric layer of the trench sidewall is removed.

3. The method for forming an inter-electrode dielectric layer in a trench gate device according to claim 1, characterized in that: In step two, the insulating dielectric layer material includes high-density plasma oxide.

4. The method for forming an inter-electrode dielectric layer in a trench gate device according to claim 1, characterized in that: In step two, the thickness of the insulating dielectric layer is 4,000 to 6,000 angstroms.

5. The method for forming an inter-electrode dielectric layer in a trench gate device according to claim 1, characterized in that: In step three, the planarization layer material includes a bottom anti-reflective coating.

6. The method for forming an inter-electrode dielectric layer of a trench gate device according to claim 1, characterized in that: In step three, the planarization layer material includes an advanced patterned thin film.

7. The method for forming an inter-electrode dielectric layer in a trench gate device according to claim 1, characterized in that: In step four, the planarization layer is used to protect the insulating dielectric layer within the trench.

8. The method for forming an inter-electrode dielectric layer of a trench gate device according to claim 1, characterized in that: In step four, the integrated etching includes simultaneously etching the planarization layer and the insulating dielectric layer on the surface.

9. The method for forming an inter-electrode dielectric layer of a trench gate device according to claim 1, characterized in that: The trench gate device includes an ultra-high density shielded gate trench transistor.

10. A trench gate device, characterized in that, This includes an interpolar dielectric layer prepared using the interpolar dielectric layer formation method as described in any one of claims 1 to 9.

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