A semiconductor device and a manufacturing method thereof

Abstract

A semiconductor device and a manufacturing method thereof, the method comprising: providing a semiconductor substrate, including an active region and a gate structure; forming a field plate dielectric layer, the field plate dielectric layer covering part of the gate structure and part of the active region; forming a metal silicide layer on the surface of the active region and the gate structure exposed by the field plate dielectric layer; forming an etching balance layer covering the metal silicide layer and the field plate dielectric layer, the material of the etching balance layer being the same as the material of the uppermost layer of the field plate dielectric layer; forming an interlayer dielectric layer covering the etching balance layer; etching the interlayer dielectric layer, the etching balance layer and part of the field plate dielectric layer to form a field plate contact hole, a shared contact hole and / or a regular contact hole, the field plate contact hole exposing part of the field plate dielectric layer, the shared contact hole and the regular contact hole exposing the metal silicide layer; filling the field plate contact hole, the shared contact hole and / or the regular contact hole with a conductive material. The present application can increase the process window when etching multiple contact holes together.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically to a semiconductor device and a method for manufacturing the same. Background Technology

[0002] BCD (Bipolar-CMOS-DMOS) technology is an advanced process technology that can monolithically integrate bipolar transistors, CMOS (complementary metal-oxide-semiconductor) devices, and DMOS (double-diffused metal-oxide-semiconductor) devices, and is widely used in power management, power integrated circuits and other fields.

[0003] In BCD technology, DMOS devices typically employ a contact field plate (CFP) structure to improve breakdown voltage. Simultaneously, the chip integrates memory devices such as static random access memory (SRAM). During manufacturing, to save costs and simplify the process, a single photomask is often used to simultaneously form the field plate contact holes and other contact holes.

[0004] During etching, different contact holes stop etching at different etch stop layers. For example, normal contact holes (Normal CT) stop etching on the silicide layer, field plate (CFP) contact holes stop etching on the field plate dielectric layer, while shared contact holes (Share CT) not only need to stop etching on the silicide layer but also need to retain part of the gate sidewall to avoid damaging the underlying active region. Integrating multiple contact holes of different sizes with different etch stop layer requirements onto the same photomask results in a very narrow process window. This easily leads to incomplete etching of the CFP region, causing electrical performance degradation. Summary of the Invention

[0005] The summary section introduces a series of simplified concepts, which will be further explained in detail in the detailed description section. This summary section is not intended to limit the key and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0006] To address the existing problems, this application provides a method for manufacturing a semiconductor device, comprising: A semiconductor substrate is provided, the semiconductor substrate including an active region on which a gate structure is formed; A field plate dielectric layer is formed, the field plate dielectric layer covering a portion of the gate structure and a portion of the active region, the field plate dielectric layer comprising multiple layers; A metal silicide layer is formed on the surface of the active region exposed by the field plate dielectric layer and the gate structure. An etching balance layer is formed covering the metal silicide layer and the field plate dielectric layer, wherein the material of the etching balance layer is the same as the material of the topmost layer of the field plate dielectric layer; An interlayer dielectric layer is formed covering the etching balance layer; The interlayer dielectric layer, the etching balance layer, and a portion of the field plate dielectric layer are etched to form field plate contact holes, as well as shared contact holes and / or conventional contact holes. The field plate contact holes expose a portion of the field plate dielectric layer. The shared contact holes expose a portion of the metal silicide layer located on the upper surface of the gate structure and a metal silicide layer located on the upper surface of the active region adjacent to the gate structure. The conventional contact holes expose the metal silicide layer on the upper surface of the active region or the gate structure. The field plate contact holes, the shared contact holes, and / or the conventional contact holes are filled with conductive material.

[0007] In one embodiment, the field plate dielectric layer includes a silicon oxide layer and a first silicon nitride layer stacked sequentially, the etching balance layer includes a second silicon nitride layer, and the field plate contact hole exposes a portion of the silicon oxide layer of the field plate dielectric layer.

[0008] In one embodiment, the total thickness of the first silicon nitride layer and the second silicon nitride layer is 1000 Å - 1500 Å.

[0009] In one embodiment, prior to forming the interlayer dielectric layer, an etch stop layer is further formed covering the etch balance layer, the etch extending through the etch stop layer, and the material of the etch stop layer being different from the materials of the etch balance layer and the interlayer dielectric layer.

[0010] In one embodiment, forming the field plate dielectric layer includes: A metal silicide barrier layer is formed covering the semiconductor substrate and the gate structure; The metal silicide barrier layer is etched to form the field plate dielectric layer.

[0011] In one embodiment, the semiconductor substrate includes a memory device region and a power device region, the shared contact hole is located in the memory device region, and the field plate contact hole is located in the power device region.

[0012] Another aspect of the present invention provides a semiconductor device, comprising: A semiconductor substrate, the semiconductor substrate including an active region, on which a gate structure is formed; A field plate dielectric layer covers a portion of the gate structure and a portion of the active region; A metal silicide layer is located on the surface of the active region and the gate structure exposed by the field plate dielectric layer; An etching balance layer covers the field plate dielectric layer and the metal silicide layer, and the material of the etching balance layer is the same as the material of the topmost layer of the field plate dielectric layer; An interlayer dielectric layer covers the etching balance layer; The field plate contact hole penetrates the interlayer dielectric layer and the etching balance layer, and exposes a portion of the field plate dielectric layer; Shared contact holes and / or conventional contact holes penetrate the interlayer dielectric layer and the etching balance layer. The shared contact holes expose a portion of the metal silicide layer on the upper surface of the gate structure and a metal silicide layer on the upper surface of the active region adjacent to the gate structure. The conventional contact holes expose the metal silicide layer on the upper surface of the active region or the gate structure. Conductive material is filled in the field plate contact holes, the shared contact holes, and / or the conventional contact holes.

[0013] In one embodiment, the metal silicide barrier layer comprises a first silicon nitride layer, and the etching balance layer comprises a second silicon nitride layer.

[0014] In one embodiment, the total thickness of the first silicon nitride layer and the second silicon nitride layer is 1000 Å - 1500 Å.

[0015] In one embodiment, the semiconductor device further includes an etch stop layer formed between the etch balance layer and the interlayer dielectric layer, wherein the field plate contact via, the shared contact via, and the conventional contact via also penetrate the etch stop layer, and the material of the etch stop layer is different from the material of the etch balance layer and the interlayer dielectric layer.

[0016] According to the semiconductor device and manufacturing method provided in the embodiments of this application, by forming an additional etching balance layer covering the entire device after forming the field plate dielectric layer and before forming the interlayer dielectric layer, the contact field plate region retains the stacked structure of the field plate dielectric layer and the etching balance layer, while the shared contact hole region and the conventional contact hole region also retain the etching balance layer until the contact hole etching completely etches through it. Compared with the related technology, which only retains a thick dielectric layer in the contact field plate region and completely removes the dielectric layer in the shared contact hole and conventional contact hole regions, this application makes the dielectric layer thickness of each contact hole region more uniform, significantly reduces the difference in etching load, and enables a one-step etching process to simultaneously meet the etching requirements of each contact hole structure, increases the overall etching process window, and reduces over-etching of the metal silicide layer and the polysilicon gate sidewall. Attached Figure Description

[0017] The following drawings, which are incorporated herein by reference and are used to understand this application, illustrate embodiments of the invention and their descriptions to explain the principles of the invention.

[0018] In the attached image: Figures 1A-1C A cross-sectional view of a semiconductor device is shown during an implementation of a semiconductor device manufacturing method in the related art. Figure 1D This diagram illustrates the normal etching of the contact holes in the field plate in the relevant technology. Figure 1E This diagram illustrates an example of etching damage occurring at the gate sidewall at the bottom of the shared contact hole in a related technology, where the field plate contact hole is etched normally. Figure 1F This diagram illustrates the etching damage to the metal silicide at the bottom of a conventional contact hole during normal etching of the field plate contact hole in the relevant technology. Figure 2 A schematic flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of this application is shown; Figures 3A-3E A cross-sectional view of a semiconductor device during the implementation of a method for manufacturing a semiconductor device according to an embodiment of this application is shown; Figure 3F and Figure 3G This diagram shows a top view of a semiconductor device according to an embodiment of this application. Detailed Implementation

[0019] The following description provides numerous specific details to offer a more thorough understanding of this application. However, it will be apparent to those skilled in the art that this application can be practiced without one or more of these details. In other instances, certain technical features well-known in the art have not been described to avoid confusion with this application.

[0020] It should be understood that this application can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of this application to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated. The same reference numerals denote the same elements throughout.

[0021] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.

[0022] Spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0023] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0024] To fully understand this application, detailed steps and structures will be presented in the following description to illustrate the technical solutions proposed in this application. Preferred embodiments of this application are described in detail below; however, in addition to these detailed descriptions, this application may have other implementation methods.

[0025] In the BCD product field, both power devices (such as DMOS devices) and memory devices (SRAM devices) are typically present. For example... Figure 1A As shown, in related technologies, a gate structure 102 is first formed on the active region 101, and a gate sidewall 103 is formed on the sidewall of the gate structure 102. Next, a metal silicide barrier layer 104 is formed covering the gate structure 102 and the surface of the active region 101. This barrier layer includes a silicon oxide layer 1041 and a silicon nitride layer 1042, where the thickness of the silicon oxide layer 1041 is approximately 900 Å and the thickness of the silicon nitride layer 1042 is approximately 1250 Å. Then, as... Figure 1B As shown, a patterned metal silicide barrier layer 104 is formed to create a field dielectric layer 105. Next, as... Figure 1C As shown, a metal silicide layer 106 is formed in the region not covered by the field plate dielectric layer 105. Then, an interlayer dielectric layer 107 is formed covering the metal silicide layer 106, and field plate contact holes 108, shared contact holes 109, and conventional contact holes 110 are formed in the interlayer dielectric layer 107. The shared contact holes 109 are formed in the memory device region, and the field plate contact holes 110 are formed in the power device region.

[0026] At this point, a single contact hole mask is typically used to simultaneously form the field contact hole 108, the shared contact hole 109, and the conventional contact hole 110 through a single etching process. However, the etching stop layers and dimensions of each contact hole are different. For example, the etching of the conventional contact hole 110 stops on the metal silicide layer 106, the etching of the field contact hole 108 stops on the field dielectric layer 105, while the shared contact hole 109, because it spans the gate structure 102 and the active region 101, not only needs to stop on the metal silicide layer 106, but also needs to ensure that the gate sidewall 103 is not damaged after etching.

[0027] Integrating multiple contact holes with different etch stop layer requirements onto the same photomask for etching results in a very narrow process window. This can easily lead to incomplete etching of the field plate contact hole 108, causing electrical performance degradation; or it can lead to over-etching of the shared contact hole 109, damaging the active region 101 below the gate sidewall 103, resulting in leakage and yield loss. Figure 1D A schematic diagram showing normal etching of the contact holes in the mid-plate in the relevant technology is shown. Figure 1E This diagram illustrates how, while the field plate contact hole is being etched normally, the entire gate sidewall at the bottom of the shared contact hole (circled location) is etched away, thereby damaging the active region below. Figure 1F This diagram illustrates how, while the contact holes on the field plate are etched normally, the metal silicide at the bottom of the conventional contact holes (circled position) is etched too deeply, or even etched through.

[0028] To address the above problems, embodiments of this application provide a semiconductor device and a method for manufacturing the same. For example... Figure 2 As shown, the manufacturing method mainly includes the following steps: Step S201: Provide a semiconductor substrate, the semiconductor substrate including an active region, on which a gate structure is formed; Step S202: Forming a field plate dielectric layer, the field plate dielectric layer covers part of the gate structure and part of the active region, and the field plate dielectric layer includes multiple layers; Step S203: A metal silicide layer is formed on the surface of the active region and gate structure exposed by the field plate dielectric layer; Step S204: Form an etching balance layer covering the metal silicide layer and the field dielectric layer. The material of the etching balance layer is the same as the material of the topmost layer of the field dielectric layer. Step S205: Form an interlayer dielectric layer covering the etching balance layer; Step S206: Etch the interlayer dielectric layer, the etching balance layer, and part of the field plate dielectric layer to form field plate contact holes, as well as shared contact holes and / or conventional contact holes. The field plate contact holes expose part of the field plate dielectric layer. The field plate dielectric layer and the etching balance layer located above the field plate dielectric layer together constitute the field plate dielectric. The shared contact holes expose part of the metal silicide layer located on the upper surface of the gate structure and the metal silicide layer located on the upper surface of the active region adjacent to the gate structure. The conventional contact holes expose the metal silicide layer on the upper surface of the active region or the gate structure. Step S207: Fill the field plate contact holes, shared contact holes and / or conventional contact holes with conductive material.

[0029] Below, for reference Figures 3A to 3G The method for fabricating the semiconductor device in this embodiment is described in detail.

[0030] First, such as Figure 3A As shown, a semiconductor substrate is provided, the semiconductor substrate includes an active region 301, a gate structure 302 is formed on the active region 301, and a gate sidewall 303 is formed on the sidewall of the gate structure 302.

[0031] The semiconductor substrate can be a silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium substrate, or a compound semiconductor substrate (such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, etc.). In this embodiment, the semiconductor substrate is a silicon substrate.

[0032] An active region 301 and an isolation structure defining the active region are formed in a semiconductor substrate. The isolation structure can be a shallow trench isolation (STI) structure. Specifically, a patterned mask layer is formed on the semiconductor substrate. The semiconductor substrate is etched using the patterned mask layer as a mask to form isolation trenches. The isolation trenches are filled with an isolation material (such as silicon oxide) to form the isolation structure, and then the patterned mask layer is removed. The area isolated by the isolation structure is the active region 301. Subsequently, the structures required for semiconductor devices, such as well regions and drift regions, can be formed within the active region 301 using an ion implantation process.

[0033] Next, a gate structure 302 is formed on the surface of the semiconductor substrate. The gate structure 302 is located on the active region 301. Exemplarily, the method for forming the gate structure 302 includes: firstly, forming a gate dielectric layer on the semiconductor substrate. The gate dielectric layer can be formed by a thermal oxidation process, a chemical vapor deposition process, or an atomic layer deposition process, and its material can be silicon oxide, silicon oxynitride, or a high-k dielectric material. Then, forming a gate electrode layer on the gate dielectric layer. The gate electrode layer can be a polysilicon layer, a metal layer, or a combination thereof. Next, forming a patterned mask layer on the gate electrode layer, and etching the gate electrode layer and the gate dielectric layer using the patterned mask layer as a mask to form the gate structure 302. Finally, removing the patterned mask layer.

[0034] Next, a gate sidewall 303 is formed on the sidewall of the gate structure 302. Specifically, a sidewall material layer is first deposited, covering the gate structure 302 and the semiconductor substrate. The sidewall material can be silicon oxide, silicon nitride, or a combination thereof. Then, the sidewall material layer is anisotropically etched to remove the horizontal sidewall material, leaving only the sidewall material on the sidewall of the gate structure 302, forming the gate sidewall 303. The gate sidewall 303 can be a single-layer structure or a multi-layer structure (such as a three-layer structure of silicon oxide-silicon nitride-silicon oxide). In this embodiment, the gate sidewall 303 is a stacked structure of silicon oxide and silicon nitride.

[0035] Next, source and drain regions are formed on both sides of gate structure 302 by ion implantation, followed by rapid heating annealing to activate doped impurities and repair the lattice structure of the semiconductor substrate surface damaged in each ion implantation process.

[0036] For example, the semiconductor substrate includes a power device region and a memory device region. The power device region is used to form power devices, such as DMOS devices, and its layout is as follows: Figure 3G As shown. The memory device area is used to form memory devices, such as SRAM devices, and its layout is as follows. Figure 3FAs shown. In the memory device region, the gate structure 302 includes at least an adjacent first gate structure 3021 and a second gate structure 3022. The first gate structure 3021 and the second gate structure 3022 extend along a first direction and are spaced apart along a second direction. The active region includes at least a first active region 3011 and a second active region 3012, which extend along the second direction and are spaced apart along the first direction. The first gate structure 3021 spans the first active region 3011 and extends to the second active region 3012, and the second gate structure 3022 spans the second active region 3012 and extends to the first active region 3011. This arrangement allows a subsequently formed shared contact hole to extend from above the first gate structure 3021 to the second active region 3012, or from above the second gate structure 3022 to the first active region 3011, thereby enabling cross-coupling of two transistors in the SRAM cell.

[0037] Next, a metal silicide barrier layer 304 is formed covering the semiconductor substrate and the gate structure 302.

[0038] In this embodiment, the metal silicide barrier layer 304 has a stacked structure, including a silicon oxide layer 3041 and a first silicon nitride layer 3042 stacked sequentially from bottom to top. Specifically, the silicon oxide layer 3041 is deposited first. The silicon oxide layer 3041 can be a silicon-rich oxide layer. The thickness of the silicon oxide layer 3041 is 600 Å-1200 Å, for example, it can be 900 Å. Then, the first silicon nitride layer 3042 is deposited on the silicon oxide layer 3041. The thickness of the first silicon nitride layer 3042 is less than 1000 Å, specifically it can be 500 Å-1000 Å.

[0039] Next, as Figure 3B As shown, the metal silicide barrier layer 304 is etched to form a field plate dielectric layer 305, which covers part of the gate structure 302 and part of the active region.

[0040] Specifically, a patterned first mask layer (not shown in the figure) is first formed on the metal silicide barrier layer 304, defining the area to be retained. Then, using the patterned first mask layer as a mask, the metal silicide barrier layer 304 is etched to form the field dielectric layer 305. The etching process can be dry etching, performed in sections.

[0041] In this embodiment, the field plate dielectric layer 305 is located in the power device region and is used to form a capacitive coupling structure below the subsequently formed field plate contact hole to improve the breakdown voltage of the DMOS device.

[0042] Next, as Figure 3CAs shown, a metal silicide process is performed to form a metal silicide layer 306 on the surface of the active region 301 and the gate structure 302 exposed by the field plate dielectric layer 305.

[0043] Specifically, firstly, a layer of metal material, such as cobalt, nickel, titanium, or platinum, is deposited on the entire semiconductor substrate. The deposition method can be a physical vapor deposition (PVD) process, such as sputtering. Then, a first rapid thermal annealing (RTA) process is performed, causing the metal to react with silicon, forming metal silicides in the contact silicon regions. In areas not in contact with silicon (e.g., areas covered by the field plate dielectric layer 305), the metal does not react. Next, a wet etching process is used to remove the unreacted metal. The etching solution can be selected depending on the metal material; for example, a mixture of sulfuric acid and hydrogen peroxide can be used for cobalt, and a mixture of nitric acid and hydrochloric acid can be used for nickel. Finally, a second rapid thermal annealing (RTA) process is performed, transforming the metal silicide into a low-resistivity phase. For example, for cobalt silicide, CoSi2 is formed; for nickel silicide, NiSi is formed.

[0044] Through the above steps, a metal silicide layer 306 is formed on the top surface of the gate structure 302 and the exposed surface (including the source and drain regions) of the active region 301. The metal silicide layer 306 is used to reduce contact resistance and improve device performance. Due to the presence of the field plate dielectric layer 305, the silicon surface beneath it is covered and no metal silicide forms. For example, the thickness of the metal silicide layer is approximately 100 Å.

[0045] Next, as Figure 3D As shown, after forming the metal silicide layer 306, an etching balance layer 307 is formed covering the metal silicide layer 306 and the field dielectric layer 305. The material of the etching balance layer 307 is the same as the material of the topmost layer of the field dielectric layer 305.

[0046] For example, an etching balancing layer 307 is deposited on the entire semiconductor substrate using a chemical vapor deposition process. The etching balancing layer 307 is made of the same material as the topmost layer of the field dielectric layer 305, specifically, it can be a second silicon nitride layer; that is, the material of the etching balancing layer 307 is the same as the material of the first silicon nitride layer 3042. This etching balancing layer 307 covers at least the shared contact hole region and the conventional contact hole region, serving to balance the etching load between different contact hole regions during subsequent contact hole etching.

[0047] In this embodiment, the thickness of the etching balance layer 307 is set such that the sum of the thicknesses of the first silicon nitride layer 3042 and the etching balance layer 307 is substantially consistent with the thickness of the silicon nitride layer required for the field plate region. That is, the portions of the field plate dielectric layer 305 and the etching balance layer 307 located on the field plate dielectric layer 305 together constitute the final field plate dielectric required for the device. Specifically, the sum of the thicknesses of the first silicon nitride layer 3042 and the etching balance layer 307 can be between 1000 Å and 1500 Å, for example, about 1250 Å. Through this thickness distribution method, a total silicon nitride thickness comparable to that of related technologies is retained in the field plate dielectric layer 305 region, while a certain thickness of the etching balance layer 307 is also retained in the shared contact hole region and the conventional contact hole region, thereby making the etching load of each contact hole region tend to be balanced. The specific thicknesses of the first silicon nitride layer 3042 and the etching balance layer 307 can be adjusted according to the actual etching process conditions, as long as the total thickness of silicon nitride between each contact hole area can be balanced.

[0048] For example, after forming the etching balance layer 307, as Figure 3E As shown, an etch stop layer 308 is formed over the etch balance layer 307. The material of the etch stop layer 308 is different from that of the etch balance layer 307 and also different from the material of the subsequently formed interlayer dielectric layer, including but not limited to a silicon oxynitride (SiON) layer with a thickness of 300 Å to 400 Å, for example, 360 Å. The etch stop layer 308 covers the surface of the etch balance layer 307. When forming contact holes in the subsequent etch of the interlayer dielectric layer, the etch stop layer 308 can precisely control the etching depth and protect the underlying structure. The etch stop layer 308 can also serve as an anti-reflection layer, absorbing reflected light in subsequent photolithography processes to prevent photoresist pattern distortion and to prevent metal atoms in the metal silicide layer 306 from diffusing into the interlayer dielectric layer, thus avoiding contamination and leakage problems.

[0049] Next, continue to refer to Figure 3E An interlayer dielectric layer 309 is formed, covering the etch stop layer 308. The interlayer dielectric layer 309 can be formed using a chemical vapor deposition process, and its material can be silicon oxide, a low-dielectric-constant material, etc. In this embodiment, the interlayer dielectric layer 309 is a silicon oxide layer with a thickness greater than 5000 Å, for example, 6500 Å. After forming the interlayer dielectric layer, chemical mechanical polishing (CMP) can be performed to planarize the surface.

[0050] Next, the interlayer dielectric layer 309, the etch stop layer 308, and the etch balance layer 307 are etched to form field plate contact holes 310, as well as shared contact holes 311 and / or conventional contact holes 312. The field plate contact holes 310 expose a portion of the field plate dielectric layer 305 (i.e., expose the surface of the silicon oxide layer 3041), the shared contact holes 311 expose a portion of the metal silicide layer 306 located on the upper surface of the gate structure 302 and the metal silicide layer 306 located on the upper surface of the active region 301 adjacent to the gate structure 302, and the conventional contact holes 312 expose the metal silicide layer 306 on the upper surface of the active region 301 or the gate structure 302.

[0051] It should be noted that, Figure 3E In order to show the three types of contact holes at the same time, the field plate contact hole 310 and the shared contact hole 311 are drawn on the same gate. However, in reality, the shared contact hole 311 and the field plate contact hole 310 are located on different gate sides, and the shared contact hole 311 is located in the memory device area, while the field plate contact hole 310 is located in the power device area.

[0052] Specifically, a patterned second mask layer (not shown) is first formed on the interlayer dielectric layer 309. The patterned second mask layer defines the positions of the field contact hole 310, the shared contact hole 311, and the conventional contact hole 312. Then, using the patterned second mask layer as a mask, the interlayer dielectric layer 309, the etch stop layer 308, and the etch balance layer 307 are etched.

[0053] For example, the etching process includes the following stages: In the first stage, the interlayer dielectric layer 309 is etched until the surface of the etch stop layer 308 is exposed. In this stage, an etching formulation with high silicon oxide selectivity is used to ensure that the etching stops precisely on the etch stop layer 308 (SiON).

[0054] In the second stage, the etch stop layer 308 is etched, exposing the surface of the underlying etch balance layer 307 in all three contact hole regions. In this stage, an etching formulation with high selectivity for silicon oxynitride is used.

[0055] In the third stage, the etching balance layer 307 is etched. For the field plate contact hole 310 region, the etching stops at the surface of the silicon oxide layer 3041 (i.e., the surface of the field plate dielectric layer 305). For the shared contact hole 311 region and the conventional contact hole 312 region, the etching balance layer 307 is completely etched through, exposing the surface of the underlying metal silicide layer 306.

[0056] After etching is complete, the patterned second mask layer is removed.

[0057] In this embodiment, since both the shared contact hole 311 region and the conventional contact hole 312 region are covered with an etching balance layer 307 before contact hole etching, the dielectric layer thickness in these regions tends to be more uniform than that in the field plate contact hole 310 region, significantly reducing the difference in etching load. During contact hole etching, the field plate contact hole 310 stops at the surface of the field plate dielectric layer 305 (i.e., the surface of the silicon oxide layer 3041), while the shared contact hole 311 and the conventional contact hole 312 stop at the surface of the metal silicide layer 306. The etching of each contact hole can be precisely stopped at the target layer.

[0058] The final contact hole structure is as follows Figure 3E As shown: Field plate contact hole 310 exposes the surface of silicon oxide layer 3041 of field plate dielectric layer 305; shared contact hole 311 exposes part of metal silicide layer 306 on the upper surface of gate structure 302 and metal silicide layer 306 on the upper surface of active region 301; conventional contact hole 312 exposes metal silicide layer 306 on the upper surface of active region 301 or gate structure 302.

[0059] Next, conductive material is filled into the field plate contact holes 310, shared contact holes 311, and conventional contact holes 312 to form conductive plugs. Specifically, a titanium layer, a titanium nitride layer, and a tungsten layer are deposited sequentially using physical vapor deposition or chemical vapor deposition. The titanium layer serves as an adhesion layer, the titanium nitride layer as a diffusion barrier layer to prevent tungsten diffusion, and the tungsten layer serves as the main conductive filler material, with a thickness sufficient to fill the contact holes. After deposition, a chemical mechanical polishing process is used for planarization to remove excess metal material from the surface of the interlayer dielectric layer 309 until the surface of the interlayer dielectric layer 309 is exposed.

[0060] At this point, the conductive material filling the field plate contact hole 310 constitutes the field plate contact plug. The field plate contact plug penetrates the interlayer dielectric layer 309, the etch stop layer 308, and the etch balance layer 307, and its bottom contacts the silicon oxide layer 3041 of the field plate dielectric layer 305. Because the silicon-rich silicon oxide layer 3041 has a high dielectric constant and good insulation properties, the field plate modulates the electric field below through capacitive coupling, thereby increasing the breakdown voltage of the DMOS device.

[0061] The conductive material filling the shared contact hole 311 constitutes a conductive plug for the shared contact hole. It penetrates the interlayer dielectric layer 309, the etch stop layer 308, and the etch balance layer 307, extending from above the gate structure 302 to the adjacent active region 301. It contacts the metal silicide layer 306 on the upper surface of the gate structure 302 and the metal silicide layer 306 on the upper surface of the active region 301, respectively, thus achieving electrical connection between the gate and the active region. During formation, the presence of the etch balance layer 307 balances the etch load, preventing damage to the active region 301 at the bottom of the shared contact hole 311 and avoiding leakage problems.

[0062] The conductive material filling the conventional contact hole 312 constitutes a conventional contact hole conductive plug, which is electrically connected to the metal silicide layer 306 of the active region 301 or the metal silicide layer 306 of the gate structure 302, respectively.

[0063] In summary, the semiconductor device manufacturing method of this application embodiment, by forming an additional etching balance layer 307 covering the entire device after forming the field plate dielectric layer 305 and before forming the interlayer dielectric layer 309, ensures that the contact field plate region retains the stacked structure of the field plate dielectric layer 305 and the etching balance layer 307, while the shared contact hole region and the conventional contact hole region also retain the etching balance layer 307 until the contact hole etching completely etches through it. Compared with the scheme of retaining a thick dielectric layer only in the contact field plate region and completely removing the dielectric layer in the shared contact hole and conventional contact hole regions, the embodiment of this application makes the dielectric layer thickness of each contact hole region more uniform, significantly reducing the difference in etching load, enabling a one-step etching process to simultaneously meet the etching requirements of each contact hole structure, increasing the overall etching process window, and reducing over-etching of the metal silicide layer and polysilicon gate sidewalls.

[0064] This application also provides a semiconductor device that can be prepared by the method described in the first embodiment above.

[0065] Below, for reference Figures 3E-3G The semiconductor devices of this application are described in detail. It is worth mentioning that, in order to avoid repetition, only a brief description is given for the same components and structures as in the foregoing embodiments. For specific explanations and descriptions, please refer to the descriptions in the foregoing embodiments.

[0066] Specifically, such as Figure 3E As shown, the semiconductor device in this application embodiment includes: The semiconductor substrate includes an active region 301, a gate structure 302 is formed on the active region 301, and a gate sidewall 303 is formed on the sidewall of the gate structure 302. The field plate dielectric layer 305 covers part of the gate structure 302 and part of the active region 301; Metal silicide layer 306 is located on the surface of active region 301 and gate structure 302 exposed by field plate dielectric layer 305; An etching balance layer 307 covers the field plate dielectric layer 305 and the metal silicide layer 306. The material of the etching balance layer 307 is the same as the material of the top layer of the field plate dielectric layer 305. The field plate dielectric layer 305 and the etching balance layer 307 located above the field plate dielectric layer 305 together constitute the field plate dielectric. Interlayer dielectric layer 309, covering etching balance layer 307; The field plate contact hole 310 penetrates the interlayer dielectric layer 309 and the etching balance layer 307, and exposes part of the field plate dielectric layer 305; Shared contact hole 311 and / or conventional contact hole 312 penetrate the interlayer dielectric layer 309 and the etching balance layer 307. Shared contact hole 311 exposes part of the metal silicide layer 306 on the upper surface of the gate structure 302 and the metal silicide layer 306 on the upper surface of the active region 301 adjacent to the gate structure 302. Conventional contact hole 312 exposes the metal silicide layer 306 on the upper surface of the active region 301 or the gate structure 302. Conductive material is filled in the field plate contact hole 310, the shared contact hole 311 and / or the conventional contact hole 312.

[0067] In one embodiment, the field plate dielectric layer 305 includes a first silicon nitride layer 3042, and the etching balance layer 307 includes a second silicon nitride layer. In one embodiment, the total thickness of the first silicon nitride layer 3042 and the second silicon nitride layer is 1000 Å-1500 Å.

[0068] In one embodiment, the semiconductor device further includes an etch stop layer 308 formed between the etch balance layer 307 and the interlayer dielectric layer 309. The material of the etch stop layer 308 is different from the material of the field plate dielectric layer 305 and the interlayer dielectric layer 309. The field plate contact hole 310, the shared contact hole 311 and the conventional contact hole 312 also penetrate the etch stop layer 308.

[0069] The semiconductor device of this application embodiment is prepared by the above method, which can increase the process window when multiple contact holes are etched together, take into account the etching requirements of each contact hole, and avoid damage to the active area below the shared contact hole.

[0070] In another embodiment of this application, an electronic device is provided, including the aforementioned semiconductor device, which is prepared according to the aforementioned method.

[0071] The electronic device in this embodiment can be any electronic product or device such as a mobile phone, tablet computer, laptop computer, netbook, television, VCD player, DVD player, navigator, digital photo frame, camera, camcorder, voice recorder, MP3 player, MP4 player, PSP, etc., or any intermediate product including circuitry. The electronic device in this embodiment, due to the use of the aforementioned semiconductor devices, has better performance.

[0072] This application has been described through the above embodiments. However, it should be understood that the above embodiments are for illustrative purposes only and are not intended to limit this application to the scope of the described embodiments. Furthermore, those skilled in the art will understand that this application is not limited to the above embodiments, and many more variations and modifications can be made based on the teachings of this application, all of which fall within the scope of protection claimed in this application. The scope of protection of this application is defined by the appended claims and their equivalents.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, include: A semiconductor substrate is provided, the semiconductor substrate including an active region on which a gate structure is formed; A field plate dielectric layer is formed, the field plate dielectric layer covering a portion of the gate structure and a portion of the active region, the field plate dielectric layer comprising multiple layers; A metal silicide layer is formed on the surface of the active region exposed by the field plate dielectric layer and the gate structure. An etching balance layer is formed covering the metal silicide layer and the field plate dielectric layer, wherein the material of the etching balance layer is the same as the material of the topmost layer of the field plate dielectric layer; An interlayer dielectric layer is formed covering the etching balance layer; The interlayer dielectric layer, the etching balance layer, and a portion of the field plate dielectric layer are etched to form field plate contact holes, as well as shared contact holes and / or conventional contact holes. The field plate contact holes expose a portion of the field plate dielectric layer. The shared contact holes expose a portion of the metal silicide layer located on the upper surface of the gate structure and a metal silicide layer located on the upper surface of the active region adjacent to the gate structure. The conventional contact holes expose the metal silicide layer on the upper surface of the active region or the gate structure. The field plate contact holes, the shared contact holes, and / or the conventional contact holes are filled with conductive material.

2. The manufacturing method according to claim 1, characterized in that, The field plate dielectric layer includes a silicon oxide layer and a first silicon nitride layer stacked sequentially, the etching balance layer includes a second silicon nitride layer located on the first silicon nitride layer, and the field plate contact hole exposes a portion of the silicon oxide layer of the field plate dielectric layer.

3. The manufacturing method according to claim 2, characterized in that, The total thickness of the first silicon nitride layer and the second silicon nitride layer is 1000 Å - 1500 Å.

4. The manufacturing method according to claim 1, characterized in that, Before forming the interlayer dielectric layer, an etch stop layer is formed that covers the etch balance layer. The etch also penetrates the etch stop layer. The material of the etch stop layer is different from the materials of the etch balance layer and the interlayer dielectric layer.

5. The manufacturing method according to claim 1, characterized in that, The formation of the field plate dielectric layer includes: A metal silicide barrier layer is formed covering the semiconductor substrate and the gate structure; The metal silicide barrier layer is etched to form the field plate dielectric layer.

6. The manufacturing method according to claim 1, characterized in that, The semiconductor substrate includes a memory device region and a power device region, the shared contact hole is located in the memory device region, and the field plate contact hole is located in the power device region.

7. A semiconductor device, characterized in that, include: A semiconductor substrate, the semiconductor substrate including an active region, on which a gate structure is formed; A field plate dielectric layer covers a portion of the gate structure and a portion of the active region; A metal silicide layer is located on the surface of the active region and the gate structure exposed by the field plate dielectric layer; An etching balance layer covers the field plate dielectric layer and the metal silicide layer, and the material of the etching balance layer is the same as the material of the topmost layer of the field plate dielectric layer; An interlayer dielectric layer covers the etching balance layer; The field plate contact hole penetrates the interlayer dielectric layer and the etching balance layer, and exposes a portion of the field plate dielectric layer; Shared contact holes and / or conventional contact holes penetrate the interlayer dielectric layer and the etching balance layer. The shared contact holes expose a portion of the metal silicide layer on the upper surface of the gate structure and a metal silicide layer on the upper surface of the active region adjacent to the gate structure. The conventional contact holes expose the metal silicide layer on the upper surface of the active region or the gate structure. Conductive material is filled in the field plate contact holes, the shared contact holes, and / or the conventional contact holes.

8. The semiconductor device according to claim 7, characterized in that, The field plate dielectric layer includes a first silicon nitride layer as the topmost layer, and the etching balance layer includes a second silicon nitride layer located on the first silicon nitride layer.

9. The semiconductor device according to claim 8, characterized in that, The total thickness of the first silicon nitride layer and the second silicon nitride layer is 1000 Å - 1500 Å.

10. The semiconductor device according to claim 7, characterized in that, It also includes an etch stop layer formed between the etch balance layer and the interlayer dielectric layer, wherein the field plate contact hole, the shared contact hole and the conventional contact hole also penetrate the etch stop layer, and the material of the etch stop layer is different from the material of the etch balance layer and the interlayer dielectric layer.

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