Method of improving photoresist residue for image sensors

Abstract

This invention provides a method for improving photoresist residue in image sensors. The method includes: providing a semiconductor substrate with a gate material layer; forming a photoresist layer on the gate material layer; patterning the photoresist layer to form a photoresist pattern, the pattern comprising multiple independent photoresist blocks covering the gate region to be retained, and the light transmittance of the photoresist pattern being greater than a preset ratio; performing ion implantation using the photoresist pattern as a mask; and removing the photoresist pattern. This invention significantly increases the light transmittance by dividing a large area of ​​photoresist into smaller blocks, effectively solving the problems of photoresist hardening and residue removal caused by high-dose ion implantation, reducing the defect rate, and improving device performance and production yield.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit manufacturing, and in particular to a method for improving photoresist residue in image sensors. Background Technology

[0002] This invention relates to the field of semiconductor manufacturing technology, and more specifically to a design method for improving photoresist (PR) residue in floating polysilicon ion implantation (FPOIMP) of complementary metal-oxide-semiconductor image sensors (CIS).

[0003] In chip manufacturing, photoresist residue is a critical defect that requires strict control. Photoresist residue can severely impact subsequent thin film growth and etching processes, especially at critical layers such as polysilicon, where it directly affects the product's electrical performance and yield.

[0004] In the production of existing 55nm complementary metal-oxide-semiconductor (CIS) image sensors, the clear ratio of the floating polysilicon ion implantation (FPOIMP) layer is relatively low. Due to the small number of grains within the exposure field, large areas of photoresist are present in the pixel region. After high-dose ion implantation, the photoresist hardens. In this situation, conventional photoresist removal methods cannot completely remove the hardened photoresist, easily resulting in photoresist residue and consequently, product performance degradation.

[0005] Therefore, optimizing the layout design to meet ion implantation requirements and solve the problem of photoresist residue has become a pressing technical challenge in this field. Summary of the Invention

[0006] The technical problem to be solved by this invention is to provide a design method to improve the photoresist residue in complementary metal oxide semiconductor image sensors, which is caused by excessive photoresist coverage area and high implantation dose during floating polysilicon ion implantation in the prior art.

[0007] A design method for improving photoresist residue in complementary metal-oxide-semiconductor image sensors includes:

[0008] Step 1: Provide a semiconductor substrate, on which a gate material layer is formed;

[0009] Step 2: Form a photoresist layer on the gate material layer;

[0010] Step 3: Perform patterning processing on the photoresist layer to form a photoresist pattern, wherein the photoresist pattern includes multiple independent photoresist blocks, the photoresist blocks cover the gate area to be retained in the gate material layer, and the light transmittance ratio of the photoresist pattern is greater than a preset ratio.

[0011] Step 4: Perform ion implantation using the photoresist pattern as a mask;

[0012] Step 5: Remove the photoresist pattern.

[0013] Preferably, in step one, the step of providing the semiconductor substrate includes: performing an active region process, a first conductivity type trap ion implantation, and a second conductivity type trap pixel ion implantation sequentially on the semiconductor substrate.

[0014] Preferably, in step one, the first conductivity type is N-type and the second conductivity type is P-type.

[0015] Preferably, in step one, the gate material layer comprises a polycrystalline silicon layer.

[0016] Preferably, in step one, the gate material layer further includes a covering oxide layer located on the polysilicon layer.

[0017] Preferably, in step two, the thickness of the photoresist layer is greater than 3 micrometers.

[0018] Preferably, in step three, the size of the photoresist block satisfies the redundancy requirements of floating polycrystalline silicon ion implantation photolithography stacking.

[0019] Preferably, in step four, the energy of the ion implantation is 10 to 20 kiloelectron volts.

[0020] Preferably, in step four, the ion implantation dose is 5~7×10^15 atoms / square centimeter.

[0021] Preferably, after step five, the method further includes performing a contact hole process and a metallization process.

[0022] As described above, the method for improving photoresist residue in image sensors according to the present invention has the following beneficial effects:

[0023] This invention optimizes the design of a large-area photoresist into a design of multiple independent small photoresist blocks. While ensuring effective protection of the gate region, it significantly improves the light transmittance of the pixel region, disrupts the continuity of the hardened photoresist layer under high-dose ion implantation, thereby greatly reducing the difficulty of photoresist removal and completely eliminating photoresist residue defects, thus improving the manufacturing yield and electrical performance stability of the image sensor. Attached Figure Description

[0024] Figure 1 The diagram shows a process flow diagram of a design method for improving photoresist residue in complementary metal-oxide-semiconductor image sensors according to the present invention.

[0025] Figure 2 The diagram shown is a layout design schematic of a design method for improving photoresist residue in complementary metal-oxide-semiconductor image sensors according to the present invention.

[0026] Figure 3 The diagram shows a cross-sectional view of the ion implantation process of a design method for improving photoresist residue in a complementary metal-oxide-semiconductor image sensor according to the present invention. Detailed Implementation

[0027] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0028] refer to Figure 1 This document illustrates a process flow diagram of a design method for improving photoresist residue in complementary metal-oxide-semiconductor image sensors according to some embodiments of the present invention. The method includes the following steps:

[0029] Step 1: Provide a semiconductor substrate on which a gate material layer is formed.

[0030] The semiconductor substrate can be composed of elemental semiconductor materials, such as silicon or germanium. In some embodiments, the semiconductor substrate includes compound semiconductors, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide. In some embodiments, the semiconductor substrate includes alloy semiconductors, such as silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium arsenide phosphide. Furthermore, the semiconductor substrate can also be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GeOI) substrate. To enhance device performance, the semiconductor substrate may also include an epitaxial layer, such as a silicon epitaxial layer over bulk silicon. The semiconductor substrate may also include various doping configurations, such as P-type doped regions and / or N-type doped regions as required by the design.

[0031] In some embodiments, step one, providing the semiconductor substrate, includes sequentially performing an active region process, first conductivity type well ion implantation, and second conductivity type well pixel ion implantation on the semiconductor substrate. The active region process typically involves forming an isolation structure using process equipment to define the active region. This isolation structure can employ shallow trench isolation (STI) technology, accomplished by etching trenches in the substrate and filling them with insulating material. The filling process can employ chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), or high-density plasma-enhanced chemical vapor deposition (HDP-CVD). After filling, chemical mechanical planarization (CMP) is typically performed to remove excess insulating material and provide a flat surface. The first conductivity type well ion implantation and the second conductivity type well pixel ion implantation utilize photoresist as a mask, introducing dopant atoms into a specific depth of the substrate using an ion implanter. After implantation, rapid thermal annealing (RTA) or furnace tube annealing is typically performed to repair lattice damage and activate the dopant ions.

[0032] In some embodiments, in step one, the first conductivity type is N-type and the second conductivity type is P-type. (See reference) Figure 3 The semiconductor substrate contains a first conductivity type well (e.g., NW) and a second conductivity type well (e.g., PW). In an alternative embodiment, the first conductivity type can be P-type, and the second conductivity type can be N-type. N-type dopants are typically group V elements, such as phosphorus, arsenic, or antimony. P-type dopants are typically group III elements, such as boron, indium, or boron difluoride. The concentration and depth distribution of these doped regions are precisely calculated to optimize the photoelectric conversion efficiency, dark current performance, and full-well capacity of the image sensor.

[0033] In some embodiments, in step one, the gate material layer includes a polycrystalline silicon layer. This polycrystalline silicon layer can serve as a gate electrode material, and its formation method may include a low-pressure chemical vapor deposition (LPCVD) process using silane or dichlorosilane as a precursor gas. In some embodiments, the polycrystalline silicon layer may be in-situ doped during deposition or doped after deposition via ion implantation to adjust its work function. The thickness of the polycrystalline silicon layer may be approximately 1000 Å. In other embodiments, the gate material layer may also employ a metal gate structure, including a work function metal layer and a filler metal layer, such as a composite structure composed of titanium, aluminum, tantalum, tungsten, or their nitrides or silicides.

[0034] In some embodiments, in step one, the gate material layer further includes a covering oxide layer located on the polysilicon layer. (Reference) Figure 3This capping oxide layer, also known as the cover oxide, primarily functions to protect the surface of the underlying polysilicon layer during subsequent ion implantation processes, preventing irreversible damage caused by high-energy ions directly impacting the polysilicon lattice. This capping oxide layer can be formed through thermal oxidation processes, exposing the substrate to a high-temperature environment containing oxygen; it can also be formed through chemical vapor deposition (CVD) or atomic layer deposition (ALD) processes. The thickness of this capping oxide layer can be approximately 100 Å. Besides silicon dioxide, this capping oxide layer can also be composed of silicon oxynitride, silicon nitride, or high-k dielectric materials.

[0035] Step 2: Form a photoresist layer on the gate material layer. This photoresist layer is typically formed using a spin-coating process. The photoresist layer can include deep ultraviolet (DUV) photoresist, extreme ultraviolet (EUV) photoresist, or electron beam photoresist. Depending on its development characteristics, the photoresist layer can be positive or negative. After spin-coating, a soft baking process is performed to drive out the solvent and densify the photoresist film.

[0036] In some embodiments, the patterning process employs different reaction mechanisms depending on the type of photoresist selected. When a positive photoresist is used, after the exposed area is irradiated (e.g., deep ultraviolet, extreme ultraviolet, or electron beam), the photoacid in it generates acid. During subsequent post-exposure baking, the acid catalyzes a deprotection reaction in the polymer, causing the polymer in the light-exposed area to change from hydrophobic to hydrophilic, thereby significantly increasing its solubility in alkaline developer. Subsequently, by immersing or spraying the substrate with developer, the light-exposed area is dissolved and removed, while the unexposed area remains to form the photoresist retention area 101.

[0037] In other embodiments, when a negative photoresist is used for the photoresist layer, the exposed areas undergo cross-linking or polymerization reactions under radiation, thereby reducing their solubility in the developer. Subsequently, the developer (such as an organic solvent or a specific alkaline solution) dissolves and removes the unexposed areas, while the photocured areas remain on the surface of the gate material layer, forming the photoresist retention area 101. Furthermore, to optimize photolithography performance, an underlayer anti-reflective coating can be formed on the gate material layer before forming the photoresist layer to reduce interference from reflected light from the underlying interface, thereby improving the contour and fidelity of the photolithographic pattern.

[0038] In some embodiments, in step two, the thickness of the photoresist layer is greater than 3 micrometers. This thick-film process is particularly suitable for high-energy ion implantation steps. A thicker photoresist provides sufficient barrier effect to ensure that implanted ions are completely blocked from non-target areas. In some embodiments, the photoresist layer may consist of a multilayer structure, such as including a bottom anti-reflective coating (BARC), intermediate layers, and a top photoresist layer, to improve lithography resolution and critical dimension control.

[0039] Step 3: Perform patterning processing on the photoresist layer to form a photoresist pattern, wherein the photoresist pattern includes multiple independent photoresist blocks, the photoresist blocks cover the gate area to be retained in the gate material layer, and the light transmittance of the photoresist pattern is greater than a preset ratio.

[0040] refer to Figure 2 and Figure 3 The patterning process involves exposing a photoresist layer to a radiation source, through which the radiation passes through a mask with a predetermined pattern. This is followed by exposure and baking to catalyze a chemical reaction, and finally development in a developer solution. Figure 2 The optimized layout design is shown, where 101 is the photoresist retention area, i.e. the formed photoresist block; 102 represents the light-transmitting area after the photoresist is removed.

[0041] The core improvement of this invention lies in changing the design layout of the photomask. In the traditional floating polysilicon ion implantation (FPOIMP) process, the pixel area is usually covered by a large area of ​​photoresist, resulting in extremely low light transmittance.

[0042] This embodiment divides a large area of ​​photoresist into multiple discrete small blocks, namely photoresist retention areas 101, so that the photoresist only covers the polysilicon layer or its immediate vicinity. This segmentation design transforms the photoresist pattern from a continuous "surface" structure to a discrete "point" or "line" structure. This structural change increases the sidewall surface area of ​​the photoresist, allowing chemical solutions or plasma to remove the photoresist from more dimensions in subsequent resist removal processes, thereby improving resist removal efficiency.

[0043] In some embodiments, in step three, the size of the photoresist block meets the redundancy requirements of floating polysilicon ion implantation lithography stacking. This redundancy requirement can be ±45nm. This means that the photoresist-retained region 101 is designed to be slightly larger than the underlying polysilicon region to tolerate potential mechanical deviations that may occur during the alignment process. This redundancy design ensures that even if alignment misalignment occurs within the maximum permissible range, the polysilicon region can still be completely covered by the photoresist, thereby preventing doping by subsequent ion implantation.

[0044] In some embodiments, the light transmittance of the photoresist pattern in the pixel area can be increased from 2.9% to 57.87%. This increase in light transmittance means that more than half of the pixel area is exposed during injection, which eliminates the conditions for forming a large-area hardened photoresist film.

[0045] Step 4: Perform ion implantation using the photoresist pattern as a mask.

[0046] refer to Figure 3The ion implantation process is performed by an ion implanter, which implants specific impurity ions into the area not covered by the photoresist-retained area 101 to form a floating polysilicon ion implantation region.

[0047] In some embodiments, in step four, the ion implantation energy is 10 to 20 kiloelectron volts. This energy range ensures that the ions reach a preset implantation depth to form a doping distribution that meets electrical requirements.

[0048] In some embodiments, in step four, the dose of ion implantation is 5 to 7 × 10^15 atoms per square centimeter.

[0049] Step 5: Remove the photoresist pattern. This high-dose ion implantation typically causes carbonization or cross-linking of the photoresist surface, forming a hard shell. In this invention, because the photoresist is divided into small pieces, the continuity of this hardened shell is disrupted, reducing its hindering effect on the overall photoresist removal process.

[0050] Following dry ashing, wet cleaning is typically performed immediately to remove ashing residues and metallic impurities. Wet cleaning can employ a mixture of sulfuric acid and hydrogen peroxide, ammonium hydroxide and hydrogen peroxide, or hydrochloric acid and hydrogen peroxide. In some embodiments, a specialized organic stripping solution can also be used. Due to the small size of the photoresist retention area 101, the wet solution can more easily penetrate to the interface between the photoresist and the underlying material through capillary action, thereby stripping away residual photoresist fragments. This combined process ensures that no photoresist residue remains at the polysilicon edges and pixel areas after the FPOIMP process, avoiding contamination of subsequent thin film deposition processes.

[0051] In some embodiments, after step five, the method further includes performing a contact hole process and a metallization process. The contact hole process involves depositing a relatively thick interlayer dielectric, such as phosphosilicate glass or borosilicate glass, on the device surface. Contact holes are then formed using photolithography and high aspect ratio dry etching techniques. The metallization process includes filling the contact holes with a barrier layer and conductive plugs. A multilayer metal interconnect structure can then be formed, with the metal layers connected by intermetallic dielectrics and vias. The metal lines can be formed using aluminum or copper damascene processes.

[0052] This invention utilizes an innovative layout design to transform large areas of photoresist that are prone to residue buildup into a small array of easily removable particles. This design not only meets the mask blocking requirements of high-dose ion implantation but also cleverly avoids the photoresist removal challenges caused by photoresist hardening through a change in physical morphology. Experimental data shows that this method increases the light transmittance of the pixel area several times over, completely eliminating photoresist residue defects behind the FPOIMP layer. This not only improves the production yield of 55nm and more advanced node complementary metal-oxide-semiconductor image sensors but also enhances the reliability of devices during long-term operation, providing stable process assurance for the manufacture of high-performance digital imaging products. This method has strong versatility and can be widely applied to various semiconductor manufacturing processes involving high-dose implantation and large-area photoresist coverage risks.

[0053] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0054] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for improving photoresist residue in an image sensor, characterized in that, At least including: Step 1: Provide a semiconductor substrate, on which a gate material layer is formed; Step 2: Form a photoresist layer on the gate material layer; Step 3: Perform patterning processing on the photoresist layer to form a photoresist pattern, wherein the photoresist pattern includes multiple independent photoresist blocks, the photoresist blocks cover the gate area to be retained in the gate material layer, and the light transmittance ratio of the photoresist pattern is greater than a preset ratio. Step 4: Perform ion implantation using the photoresist pattern as a mask; Step 5: Remove the photoresist pattern.

2. The method for improving photoresist residue in image sensors according to claim 1, characterized in that: In step one, the step of providing the semiconductor substrate includes: performing an active region process, a first conductivity type trap ion implantation, and a second conductivity type trap pixel ion implantation sequentially on the semiconductor substrate.

3. The method for improving photoresist residue in image sensors according to claim 2, characterized in that: In step one, the first conductivity type is N-type, and the second conductivity type is P-type.

4. The method for improving photoresist residue in image sensors according to claim 1, characterized in that: In step one, the gate material layer includes a polysilicon layer.

5. The method for improving photoresist residue in an image sensor according to claim 1, characterized in that: In step one, the gate material layer further includes a covering oxide layer located on the polysilicon layer.

6. The method for improving photoresist residue in an image sensor according to claim 1, characterized in that: In step two, the thickness of the photoresist layer is greater than 3 micrometers.

7. The method for improving photoresist residue in an image sensor according to claim 1, characterized in that: In step three, the size of the photoresist block meets the redundancy requirements of floating polycrystalline silicon ion implantation photolithography stacking.

8. The method for improving photoresist residue in an image sensor according to claim 1, characterized in that: In step four, the energy of the ion implantation is 10 to 20 kiloelectron volts.

9. The method for improving photoresist residue in an image sensor according to claim 1, characterized in that: In step four, the ion implantation dose is 5~7×10^15 atoms / square centimeter.

10. The method for improving photoresist residue in an image sensor according to claim 1, characterized in that: After step five, the method further includes performing a contact hole process and a metallization process.

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