Optoelectronic chip co-packaging structure and its fabrication method

Abstract

This invention provides a co-packaging structure for optoelectronic chips and its fabrication method. A patterned dielectric layer, not corresponding to the image region, is placed between the optoelectronic chip wafer and the image sensor wafer. Adhesive applied to the surface of the patterned dielectric layer bonds the two wafers face-to-face. Simultaneously, vias are drilled and wiring is installed on the back of the image sensor wafer, and metal bumps guide the electrical signals of the image sensor chip from the front to the back, achieving wafer-to-wafer level bonding. This effectively controls the distance between the image region of the image sensor and the grating coupling region of the optoelectronic chip to within 30 μm, achieving low-cost, high-density packaging integration. Furthermore, by setting the substrate layer of the optoelectronic chip as a transparent substrate, the grating coupling region and the grating coupling region can be made non-coplanar, effectively reducing the wiring difficulty of the image sensor chip and increasing the design freedom of the grating coupling region's position and size, further reducing process complexity and package size.

Description

Technical Field

[0001] This invention relates to the field of chip packaging technology, and in particular to a co-packaging structure for optoelectronic chips and its fabrication method. Background Technology

[0002] With the development of optoelectronic fusion technology, functions such as image acquisition, optical signal transmission, optical signal modulation, and optical signal processing are widely used in fields such as intelligent sensing, optical communication, 3D imaging, machine vision, and biological detection. Image sensors, as the core component for photoelectric conversion, can convert received optical signals into electrical signals and are key devices in photoelectric detection and imaging systems; optical chips can serve as light sources, optical modulation devices, or optical signal processing devices to generate, modulate, transmit, or process optical signals.

[0003] Currently, image sensor designs on the market generally employ a highly integrated layout, placing the image area and electrical signal windows on the same plane. This design is relatively simple to manufacture and has a lower cost, thus gaining widespread application in many fields. In existing technologies, to improve signal transmission efficiency between the optical chip and the image sensor chip, a die-to-die packaging method is used to integrate the optical chip and image sensor chip face-to-face, ensuring that the image sensor chip can receive the optical signal from the optical chip at close range. While this type of packaging structure shortens the optical signal transmission path, reduces signal delay and transmission loss, and improves photoelectric conversion and signal processing efficiency, it still requires support structures, protective structures, wire bonding, and substrate structures after the optical chip and image sensor chip are face-to-face bonded. This results in a large overall packaging structure occupying significant space in the thickness or planar direction, making it difficult to further reduce the package size and increasing manufacturing costs.

[0004] Furthermore, for co-packaged structures including image sensor chips and optical chips, the optical chip, acting as a light source or optical signal processing unit, needs to couple an external light source into the optical chip and then out to the image sensor chip. If the spatial layout of existing face-to-face bonding structures is unreasonable, it can easily restrict the optical path arrangement and increase the package size. Therefore, how to further optimize the packaging layout of the image sensor chip and the optical chip, improve packaging density, reduce package volume, and lower packaging costs while ensuring a short path for the image sensor chip to receive optical signals has become a pressing technical problem to be solved in this field.

[0005] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating understanding by those skilled in the art. It should not be assumed that these technical solutions are known to those skilled in the art simply because they have been described in the background section of this application. Summary of the Invention

[0006] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a co-packaging structure for optoelectronic chips and its preparation method, so as to solve the problems of the existing optoelectronic chip co-packaging structure, which, although achieving a short path for image sensor chips to receive optical signals, has a large package size, high spatial circuit layout difficulty, is not conducive to high-density packaging integration and has high manufacturing cost.

[0007] To achieve the above and other related objectives, the present invention provides a method for fabricating a co-packaged structure for an optoelectronic chip, the method comprising the following steps:

[0008] A wafer of optical chips is provided, wherein the optical chips include a light-transmitting substrate layer and an optical path layer located on the light-transmitting substrate layer, and the two opposite surfaces of the optical path layer have a grating coupling-in region and a grating coupling-out region, the grating coupling-in region being located on the side closer to the light-transmitting substrate layer, and the grating coupling-out region being located on the side farther away from the light-transmitting substrate layer;

[0009] A patterned dielectric layer is formed on the surface of the optical chip wafer near the grating coupling region;

[0010] An image sensor wafer with multiple image sensor chips disposed thereon is provided, and the image sensor wafer is bonded to a patterned dielectric layer by an adhesive to achieve bonding between the optical chip wafer and the image sensor wafer; wherein, the front side of the image sensor chip is provided with a coplanar image area and a pad area, the grating coupling area of ​​the optical chip is directly opposite to the image area, and the patterned dielectric layer does not correspond to the image area but is at least directly opposite to a portion of the pad area;

[0011] A plurality of vias are formed by etching the back side of the image sensor wafer, the vias exposing the pads in the pad area of ​​each image sensor chip;

[0012] A first dielectric isolation layer is formed on the sidewall of the via, and the first dielectric isolation layer extends to cover the back surface of the image sensor wafer;

[0013] A metal wiring layer is formed on the bottom wall of the via and on the surface of the first dielectric isolation layer on the sidewall of the via, and the metal wiring layer extends from the inside of the via to the surface of the first dielectric isolation layer on the back side of the image sensor wafer.

[0014] A second dielectric isolation layer is formed on the back side of the image sensor wafer, and a window is made in it to expose the metal wiring layer;

[0015] Balls are implanted in the window to form metal bumps;

[0016] The obtained structure is diced along the cutting path to obtain a single optoelectronic chip co-packaged structure.

[0017] Optionally, the light-transmitting substrate layer of the optical chip is a glass substrate layer.

[0018] Optionally, the image area on the front side of the image sensor chip is located in the middle of the image sensor chip, and the pad area on the front side of the image sensor chip is located at the outer peripheral edge of the image area; after the optical chip wafer is bonded to the image sensor wafer, the patterned dielectric layer is aligned with the pad area and dicing area on the front side of each image sensor chip, forming a dike structure.

[0019] Further, the method for etching to form the via includes: performing a first etching step on the back side of the image sensor wafer to a predetermined depth to form a first etched hole, the opening of the first etched hole being directly opposite the outer periphery of the patterned dielectric layer; performing a second etching step on the back side of the image sensor wafer to a predetermined depth based on the first etched hole to form a second etched hole, the second etched hole exposing the pads in the pad area and the dicing track directly opposite the patterned dielectric layer, the second etched hole exposing the pads and the first etched hole constituting the via.

[0020] Optionally, the material of the patterned dielectric layer is a photosensitive material; the method of forming the patterned dielectric layer includes: first forming a dielectric layer on the entire surface of the optical chip wafer near the grating coupling region; then performing a preset exposure and development on the dielectric layer, and the remaining dielectric layer is formed as the patterned dielectric layer.

[0021] Optionally, the material of the first dielectric isolation layer is a photosensitive material; the method of forming the first dielectric isolation layer includes: first forming the first dielectric isolation layer on the entire back surface of the image sensor wafer, the sidewall and bottom wall of the via; and then performing a preset exposure and development on the first dielectric isolation layer to remove the first dielectric isolation layer from the bottom wall of the via and the dicing channel.

[0022] Optionally, the method for forming the metal wiring layer includes: firstly forming a seed layer on the surface of the first dielectric isolation layer and the surface of the pad on the bottom wall of the via using a sputtering process; then forming a metal layer on the surface of the seed layer using an electroplating process; and finally performing a preset patterned etching on the metal layer and the seed layer to form the metal wiring layer.

[0023] The present invention also provides a co-packaging structure for optoelectronic chips, the co-packaging structure for optoelectronic chips comprising:

[0024] An optical chip; the optical chip includes a light-transmitting substrate layer and an optical path layer located on the light-transmitting substrate layer, the optical path layer having a grating coupling-in region and a grating coupling-out region on two opposite surfaces, the grating coupling-in region being located on the side closer to the light-transmitting substrate layer, and the grating coupling-out region being located on the side farther away from the light-transmitting substrate layer;

[0025] An image sensor chip; the front side of the image sensor chip has a coplanar image area and a pad area; the back side of the image sensor chip has a through-hole that exposes the pad area; a first isolation dielectric layer is formed on the sidewall surface of the through-hole, and the first dielectric isolation layer extends to cover the back surface of the image sensor chip; a metal wiring layer is formed on the bottom wall of the through-hole and on the surface of the first dielectric isolation layer on the sidewall of the through-hole, and the metal wiring layer extends from the inside of the through-hole to the surface of the first dielectric isolation layer on the back side of the image sensor chip;

[0026] The second dielectric isolation layer is disposed on the metal wiring layer on the back side of the image sensor chip and on the first dielectric isolation layer;

[0027] Metal bumps that penetrate the second dielectric isolation layer and contact the metal wiring layer;

[0028] A patterned dielectric layer is disposed on the surface of the optical chip near the grating coupling region, and the patterned dielectric layer does not correspond to the image region of the image sensor chip but is at least directly opposite a portion of the pad region of the image sensor chip;

[0029] The image sensor chip is bonded to the patterned medium layer by an adhesive, thereby achieving the bonding between the optical chip and the image sensor chip, and the grating coupling region of the optical chip is directly opposite the image region of the image sensor chip.

[0030] Optionally, the light-transmitting substrate layer of the optical chip is a glass substrate layer, the material of the patterned medium layer is a photosensitive material, and the material of the first medium isolation layer is a photosensitive material.

[0031] Optionally, the image area on the front side of the image sensor chip is located in the middle of the image sensor chip, and the pad area on the front side of the image sensor chip is located at the outer peripheral edge of the image area.

[0032] As described above, the optoelectronic chip co-packaging structure and its fabrication method of the present invention, by setting a patterned dielectric layer that does not correspond to the image area between the optoelectronic chip wafer and the image sensor wafer, and bonding the two wafers face to face by applying adhesive to the surface of the patterned dielectric layer, simultaneously drilling holes and wiring from the back of the image sensor wafer and guiding the electrical signals of the image sensor chip from the front to the back through metal bumps, achieves wafer-to-wafer level bonding, and can effectively control the distance between the image area of ​​the image sensor and the grating coupling area of ​​the optoelectronic chip to within 30μm, realizing short-distance and efficient transmission of optical signals between the optoelectronic chip and the image sensor chip, and significantly reducing the packaging volume, packaging difficulty and packaging manufacturing cost, achieving low-cost, high-density packaging integration, and according to calculations, compared with die to ... Compared to the package volume of a die, under the same conditions, the package volume obtained by the preparation method of the present invention can be reduced by up to 80%. In addition, by setting the substrate layer of the optical chip in the optical chip wafer as a light-transmitting substrate layer, the grating coupling region and the grating coupling region can be set as non-coplanar, with the grating coupling region closer to the light-transmitting substrate layer and the grating coupling region farther away from the light-transmitting substrate layer. The grating coupling region does not restrict the wiring of the image sensor chip, which can effectively reduce the wiring difficulty of the image sensor chip and improve the design freedom of the position and size of the grating coupling region, further reducing the process difficulty and package volume. Attached Figure Description

[0033] The accompanying drawings, which form part of this specification, are used to provide a further understanding of the embodiments of this application and to illustrate the implementation of this application, together with the textual description, to explain the principles of this application. Obviously, the drawings described below are merely some embodiments of this application.

[0034] Figure 1 The diagram shown is a simplified planar structure of the optical chip wafer in the method for fabricating the optoelectronic chip co-packaging structure according to Embodiment 1 of the present invention.

[0035] Figure 5 The diagram shown is a simplified planar structure of the image sensor wafer in the fabrication method of the optoelectronic chip co-packaging structure according to Embodiment 1 of the present invention.

[0036] Figures 2 to 4 , Figures 6 to 18 The diagram shows a cross-sectional view of each step in the fabrication method of the optoelectronic chip co-packaging structure according to Embodiment 1 of the present invention.

[0037] Figure 19 The diagram shown is a cross-sectional view of the optoelectronic chip co-packaging structure according to Embodiment 2 of the present invention.

[0038] Component designation explanation

[0039] 10 Optical chip wafer 100 optical chip 101 Transparent substrate layer 102 Optical path layer 103 Grating coupling region 104 Grating coupling area 11 Patterned media layer 110 Dielectric layer 12 Image sensor wafer 120 Image sensor chip 121 Image region 122 solder pad area 123 solder pads 13 Through hole 130 First etching hole 131 Second etching hole 14 First dielectric isolation layer 15 Metal wiring layer 16 Second dielectric isolation layer 160 window 17 metal bumps 18 Cutting channel 19 Optoelectronic chip packaging structure Detailed Implementation

[0040] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0041] It should be emphasized that the term "including / comprises" as used herein refers to the presence of a feature, whole, step, or component, but does not exclude the presence or addition of one or more other features, wholes, steps, or components.

[0042] Features described and / or illustrated for one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.

[0043] In the detailed description of embodiments of the present invention, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged and not to scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0044] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include directions other than those depicted in the drawings for devices in use or operation. Furthermore, when a layer is referred to as being “between” two layers, it may be the only layer between the two layers, or there may be one or more layers in between.

[0045] In the context of this application, the structure described above the first feature may include embodiments in which the first and second features are formed in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0046] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0047] Example 1

[0048] This embodiment provides a method for fabricating a co-packaged structure for an optoelectronic chip, the method comprising the following steps:

[0049] S1, providing an optical chip wafer on which multiple optical chips are arranged; wherein, the optical chip includes a light-transmitting substrate layer and an optical path layer located on the light-transmitting substrate layer, the two opposite surfaces of the optical path layer have a grating coupling-in region and a grating coupling-out region, the grating coupling-in region is located on the side close to the light-transmitting substrate layer, and the grating coupling-out region is located on the side away from the light-transmitting substrate layer;

[0050] S2, a patterned dielectric layer is formed on the surface of the optical chip wafer near the grating coupling region;

[0051] S3, an image sensor wafer with multiple image sensor chips disposed thereon is provided, and the image sensor wafer is bonded to the patterned dielectric layer by adhesive to achieve bonding between the optical chip wafer and the image sensor wafer; wherein, the front side of the image sensor chip is provided with a coplanar image area and a pad area, the grating coupling area of ​​the optical chip is directly opposite to the image area, and the patterned dielectric layer does not correspond to the image area but is at least directly opposite to a portion of the pad area;

[0052] S4, etching a plurality of vias is performed on the back side of the image sensor wafer, the vias exposing the pads in the pad area of ​​each image sensor chip;

[0053] S5, a first dielectric isolation layer is formed on the sidewall of the through hole, and the first dielectric isolation layer extends to cover the back surface of the image sensor wafer;

[0054] S6, a metal wiring layer is formed on the bottom wall of the through hole and on the surface of the first dielectric isolation layer on the side wall of the through hole, and the metal wiring layer extends from the inside of the through hole to the surface of the first dielectric isolation layer on the back side of the image sensor wafer.

[0055] S7, a second dielectric isolation layer is formed on the back side of the image sensor wafer, and a window is made in it to expose the metal wiring layer;

[0056] S8, a ball is placed in the window to form a metal bump;

[0057] S9. The obtained structure is diced along the cutting path to obtain a single optoelectronic chip co-packaged structure.

[0058] The method for fabricating the optoelectronic chip co-packaging structure in this embodiment involves setting a patterned dielectric layer with a non-corresponding image area between the optoelectronic chip wafer and the image sensor wafer, and bonding the two wafers face-to-face using an adhesive applied to the surface of the patterned dielectric layer. Simultaneously, holes are drilled and wiring is installed on the back of the image sensor wafer, and the electrical signals of the image sensor chip are guided from the front to the back using metal bumps, achieving wafer-to-wafer level bonding. This effectively controls the distance between the image area of ​​the image sensor and the grating coupling area of ​​the optoelectronic chip to within 30 μm, enabling short-range, efficient transmission of optical signals between the optoelectronic chip and the image sensor chip. Furthermore, it significantly reduces packaging size, packaging difficulty, and packaging manufacturing costs, achieving low-cost, high-density packaging integration. Calculations show that this method is comparable to die-to-die packaging. Compared to the package volume of a die, under the same conditions, the package volume obtained by the preparation method in this embodiment can be reduced by up to 80%. In addition, by setting the substrate layer of the optical chip in the optical chip wafer as a light-transmitting substrate layer, the grating coupling region and the grating coupling region can be set as non-coplanar, with the grating coupling region closer to the light-transmitting substrate layer and the grating coupling region farther away from the light-transmitting substrate layer. The grating coupling region does not restrict the wiring of the image sensor chip, which can effectively reduce the wiring difficulty of the image sensor chip and increase the design freedom of the position and size of the grating coupling region, further reducing the process difficulty and package volume.

[0059] The fabrication method of the optoelectronic chip co-packaging structure of this embodiment will be described in detail below with reference to the specific accompanying drawings.

[0060] like Figure 1 and Figure 2 As shown, step S1 is performed first, providing an optical chip wafer 10 on which multiple optical chips 100 are arranged; wherein, the optical chip 100 includes a light-transmitting substrate layer 101 and an optical path layer 102 located on the light-transmitting substrate layer 101, the two opposite surfaces of the optical path layer 102 have a grating coupling-in region 103 and a grating coupling-out region 104, the grating coupling-in region 103 is located on the side close to the light-transmitting substrate layer 101, and the grating coupling-out region 104 is located on the side away from the light-transmitting substrate layer 101.

[0061] like Figure 1 As shown, the optical chips 100 on the optical chip wafer 10 are connected by dicing channels 18. After subsequent packaging and integration, the wafers will be diced along the dicing channels 18 to obtain a single-chip package structure. Subsequently, the optical chips 100 in the optical chip wafer 10 will be bonded one-to-one with the image sensor chips 120 in the image sensor wafer 12. Therefore, the dicing channels 18 in the image sensor wafer 12 and the dicing channels 18 in the optical chip wafer 10 are located in the same area.

[0062] like Figure 2The diagram shows a cross-sectional view of the optical chip 100. The optical path layer 102 of the optical chip 100 has two opposing surfaces with a grating coupling region 103 and a grating coupling region 104. The grating coupling region 103 couples light rays entering through the transparent substrate layer 101 into the optical path layer 102. The grating coupling region 104 couples image light rays transmitted within the optical path layer 102 into the image sensor chip 120. An optical waveguide formed by optical wire bonding technology is disposed between the grating coupling region 103 and the grating coupling region 104, so that the signal transmission path between adjacent grating coupling regions 103 and grating coupling regions 104 is no longer metal, but an optical waveguide. Optionally, the shape of the optical waveguide can be linear, curved, or other shapes, depending on different design requirements.

[0063] The light-transmitting substrate layer 101 primarily functions as a support and light-transmitting material. Therefore, the material of the light-transmitting substrate layer 101 can be selected as a material that provides both support and light transmission. In this embodiment, the light-transmitting substrate layer 101 is preferably a glass substrate layer. On the one hand, glass substrate layers provide both support and light transmission; on the other hand, glass has good flatness and an adjustable coefficient of thermal expansion (CTE), thereby reducing stress, warpage, and reliability risks during thermal cycling. This makes it highly suitable for wafer-level packaging, which requires parameters such as flatness, stress, and warpage, thus improving packaging quality.

[0064] like Figure 4 As shown, step S2 is then performed, forming a patterned dielectric layer 11 on the surface of the optical chip wafer 10 near the grating coupling region 104. Subsequently, the image sensor wafer 12 will be bonded to the optical chip wafer 10 based on this patterned dielectric layer 11. Therefore, to reduce the occlusion of the image region 121 in the image sensor chip 120 by the patterned dielectric layer 11, the area of ​​the patterned dielectric layer 11 is set such that it does not directly face the image region 121 in the image sensor chip 120 after bonding, thus ensuring that it at least faces a portion of the pad region 122 in the image sensor chip 120. Preferably, the patterned dielectric layer 11 can also be set to face all the pad regions 122 in the image sensor chip 120 to increase the area of ​​the patterned dielectric layer 11 and improve bonding strength.

[0065] As an example, a method for forming the patterned medium layer 11 includes: Figure 3 As shown, a dielectric layer 110 is first formed across the entire surface of the optical chip wafer 10 near the grating coupling region 104; as Figure 4As shown, the dielectric layer 110 is then patterned to form the remaining dielectric layer 110 as the patterned dielectric layer 11. In a further preferred embodiment, the material of the patterned dielectric layer 11 is selected as a photosensitive material, such as photoresist or photosensitive PI material. Therefore, after forming a photosensitive dielectric layer 110 over the entire surface, the dielectric layer 110 can be directly patterned by exposure, avoiding etching processes. Thus, the patterned dielectric layer 11 can be obtained without damaging the optical chip 100, improving packaging quality.

[0066] The thickness of the patterned dielectric layer 110 will subsequently be a factor affecting the optical signal transmission distance between the optical chip 100 and the image sensor chip 120. Therefore, its thickness is selected according to design requirements. In order to ensure complete isolation after the optical chip 100 and the image sensor chip 120 are bonded, the thickness of the patterned dielectric layer 110 is generally greater than 5 μm.

[0067] like Figures 5 to 7 As shown, step S3 is then performed, providing an image sensor wafer 12 on which multiple image sensor chips 120 are arranged, and bonding the image sensor wafer 12 to the patterned dielectric layer 11 with adhesive, thereby achieving bonding between the optical chip wafer 10 and the image sensor wafer 12; wherein, the front side of the image sensor chip 120 is provided with a coplanar image region 121 and a pad region 122, the grating coupling region 104 of the optical chip 100 is directly opposite to the image region 121, and the patterned dielectric layer 11 does not correspond to the image region 121 but is at least directly opposite to a portion of the pad region 122.

[0068] The type of adhesive applied to the patterned dielectric layer 11 is not overly restricted, as long as it enables the image sensor wafer 12 to be bonded. Furthermore, solid, paste-like, or less fluid adhesives can be selected to prevent overflow into areas outside the patterned dielectric layer 11 during application.

[0069] As an example, the image sensor chip 120 can be any existing suitable image sensor chip, as long as the chip layout in which the image area 121 and the pad area 122 are coplanar is satisfied, such as CMOS image sensor, CCD, etc.

[0070] As a specific example, such as Figure 6As shown, the image region 121 on the front of the image sensor chip 120 is located in the middle of the image sensor chip 120, and the pad region 122 on the front of the image sensor chip 120 is located at the outer periphery of the image region 121. This structure is a highly integrated layout commonly used in current image sensor chips 120. It should also be noted that the image region 121 is mainly used to set the device structure of the image sensor, and the pad region 122 is mainly used to set the pads 123 of the image sensor. However, the setting of the pads 123 in the pad region 122 can be configured according to actual needs. It can be set only in a portion of the outer periphery of the image region 121, or the pads 123 can be set on the entire outer periphery of the image region 121. Regardless of whether the pad region 122 on the outer periphery is set with pads 123, it is always defined as the pad region 122. Based on this, since the pad area 122 is located at the outer edge of each image sensor chip 120, in order to further improve the adhesion, the patterned dielectric layer 11 can be extended to face the entire pad area 122 and the cut track 18. That is, the periphery of each image sensor chip 120 and the cut track 18 on its outer periphery are all facing the patterned dielectric layer 11, forming a dam structure.

[0071] As an example, such as Figure 8 As shown, after bonding the optical chip wafer 10 to the image sensor wafer 12, the process further includes grinding and planarizing the image sensor wafer 12 to maintain a suitable thickness, which helps to reduce the volume of the subsequently formed optoelectronic chip co-packaging structure and improve the packaging quality of the optoelectronic chip co-packaging structure.

[0072] like Figure 10 As shown, step S4 is then performed to etch a plurality of vias 13 on the back side of the image sensor wafer, the vias 13 exposing the pads 123 in the pad area 122 of each image sensor chip 120.

[0073] It should be noted here that... Figure 10 The illustration shows a cross-sectional structure example where the patterned dielectric layer 11 extends to face the entire pad area 122 and the cut track 18, exposing the pad 123 and the cut track 18 at the same time as forming the via 13.

[0074] As a specific example, when the patterned dielectric layer 11 extends to cover the entire pad area 122 and the cutaway 18, the method for forming the via 13 includes: Figure 9As shown, a first etching step of a preset depth is performed on the back side of the image sensor wafer 12 to form a first etched hole 130. The opening of the first etched hole 130 is directly opposite the outer periphery of the patterned dielectric layer 11. This means that the opening of the first etched hole 130 on each image sensor chip 120 is directly opposite the outer periphery of the patterned dielectric layer 11. Figure 10 As shown, a second etching step is performed on the back side of the image sensor wafer 12 based on the first etching hole 130 to a preset depth, forming a second etching hole 131. The second etching hole 131 exposes the pads 123 of the pad area 122 and the dicing track 18 opposite the patterned dielectric layer 11. The second etching hole 131 that exposes the pads 123 and the first etching hole 130 constitute the through hole 13. At the same time, this process also exposes the corresponding dicing track 18, which can reduce the difficulty of subsequent dicing and improve the dicing quality.

[0075] like Figure 12 As shown, step S5 is then performed, in which a first dielectric isolation layer 14 is formed on the sidewall of the via 130, and the first dielectric isolation layer 14 extends to cover the back surface of the image sensor wafer 12.

[0076] As an example, a method for forming the first dielectric isolation layer 14 includes: Figure 11 As shown, the first dielectric isolation layer 14 is first formed on the entire back surface of the image sensor wafer 12, the sidewalls of the via 130, and the bottom wall. Of course, if the dicing channel 18 is exposed at this time, the first dielectric isolation layer 14 is also simultaneously formed on the sidewalls and bottom walls of the exposed via 130. Figure 12 As shown, the first dielectric isolation layer 14 is then patterned to remove the first dielectric isolation layer 14 on the bottom wall of the via 130 on the pad 123. At this time, the first dielectric isolation layer 14 on the bottom wall of the via 18 on the dicing channel 18 can also be removed. In a further preferred embodiment, the material of the first dielectric isolation layer 14 is selected as a photosensitive material, such as photoresist or photosensitive PI material. Therefore, after forming a first dielectric isolation layer 14 on the entire surface, the first dielectric isolation layer 14 can be directly patterned by exposure, avoiding the use of etching processes. Thus, the required first dielectric isolation layer 14 can be obtained without damaging the image sensor chip 12, improving packaging quality.

[0077] like Figure 14As shown, step S6 is then performed, where a metal wiring layer 15 is formed on the bottom wall of the via 130 and on the surface of the first dielectric isolation layer 14 on the sidewall of the via 130, and the metal wiring layer 15 extends from the interior of the via 130 to the surface of the first dielectric isolation layer 14 on the back side of the image sensor wafer 12. This enables the pads 123 of each image sensor chip 120 to be led out from the corresponding back surface of the image sensor chip 120.

[0078] As a specific example, the method for forming the metal wiring layer 15 includes: Figure 13 As shown, a seed layer (not shown in the figure) is first formed on the surface of the first dielectric isolation layer 14 and the surface of the pad 123 on the bottom wall of the through hole 130 using a sputtering process, and then a metal layer is formed on the surface of the seed layer using an electroplating process; as Figure 14 As shown, the metal layer and the seed layer are finally patterned and etched to form the metal wiring layer 15. If the corresponding dicing path 18 is exposed, the metal layer and the seed layer on the dicing path 18 are removed during the patterning etching. Furthermore, the principle for patterning the metal layer and the seed layer is that the remaining metal layer and seed layer must extend continuously from the surface of the pad 123 to the back surface of the image sensor chip 120. Therefore, the metal layer and seed layer can be fully retained in the via 130, or partially retained (e.g., ...). Figure 14 (As shown).

[0079] The material of the metal wiring layer 15 is not excessively limited; any suitable metal material for metal wiring can be used, such as one or a combination of copper, aluminum, nickel, gold, silver, and titanium. As a specific example, titanium-copper material can be used as the seed layer material as described above, and copper material can be used as the metal layer material as described above.

[0080] like Figure 15 and Figure 16 As shown, step S7 is then performed, in which a second dielectric isolation layer 16 is formed on the back side of the image sensor wafer 12, and a window 160 is formed thereon, the window 160 exposing the metal wiring layer 15.

[0081] As a specific example, such as Figure 16 As shown, the window 160 exposes the metal wiring layer 15 located on the back surface of the image sensor chip 120.

[0082] As a preferred example, the second insulating dielectric layer 16 is preferably an organic dielectric material, such as an epoxy resin layer, polyimide, and silicone, etc. Figure 15As shown, the process for forming the second insulating dielectric layer 16 of the organic dielectric material includes one of a liquid sealant curing process, a vacuum lamination process, and a spin coating process. After forming the second insulating dielectric layer 16, a planarization process is also included. The planarization process enables the optoelectronic chip co-packaging structure to maintain a suitable thickness, further reducing the volume of the packaging structure and improving the packaging quality.

[0083] Specifically, in this embodiment, the process of forming the second dielectric isolation layer 16 and creating the window 160 is as follows: after screen printing solder resist ink on the back surface of the image sensor chip 120, it undergoes pre-curing, exposure, development, and thermal curing processes to cure the solder resist ink into the second dielectric isolation layer 16. Further, a windowing process is performed on the second dielectric isolation layer 16 to expose the metal wiring layer 15 on the back of the image sensor chip 120. The second dielectric isolation layer 16 provides a permanent electrical environment and a chemically resistant protective layer for the image sensor chip 120, while also enhancing its appearance.

[0084] Further, the method for forming the window 160 by opening a window in the second dielectric isolation layer 16 includes: forming a photoresist layer on the second dielectric isolation layer 16; exposing and developing the photoresist layer to form a patterned photoresist layer; etching the second dielectric isolation layer 16 based on the patterned photoresist layer to form the window 160 in the second dielectric isolation layer 16, the window 160 exposing the metal wiring layer 15 on the back side of the image sensor wafer 12; and then removing the photoresist layer. The process conditions used for photolithography and etching of the second dielectric isolation layer 16 are well known in the art, and those skilled in the art can adjust them according to actual needs, and will not be described in further detail here.

[0085] like Figure 17 As shown, step S8 is then performed, in which a ball is placed in the window 160 to form a metal bump 17.

[0086] As an example, the metal bump 17 includes one of gold-tin solder balls, silver-tin solder balls, and copper-tin solder balls; or, the metal bump 17 includes a metal pillar and solder balls formed on the metal pillar. Preferably, the metal pillar is a copper pillar or a nickel pillar. In this embodiment, the metal bump 17 is a gold-tin solder ball, and its manufacturing steps include: firstly forming a gold-tin layer in the window 160, then using a high-temperature reflow process to reflow the gold-tin layer into a spherical shape, and then cooling it to form a gold-tin solder ball; or using a ball-planting process to form the gold-tin solder ball.

[0087] like Figure 18 and Figure 19As shown, in step S9, the obtained structure is diced along the dicing path 18 to obtain a single optoelectronic chip co-packaged structure 19. The dicing paths 18 of the optical chip wafer 10 and the image sensor wafer 12 correspond one-to-one. Therefore, the two bonded wafers can be separated by dicing along the preset dicing path 18 to form several individual optoelectronic chip co-packaged structures 19.

[0088] Example 2

[0089] This embodiment provides a co-packaged structure for an optoelectronic chip. This co-packaged structure can be prepared using the method described in Embodiment 1. Therefore, the materials and fabrication processes of the co-packaged structure can be found in Embodiment 1. Of course, other fabrication processes can also be used to prepare the co-packaged structure as needed, as long as the co-packaged structure can be formed. The beneficial effects of this co-packaged structure can be found in Embodiment 1, and will not be repeated below.

[0090] like Figure 19 As shown, the optoelectronic chip co-packaging structure includes:

[0091] Optical chip 100; the optical chip 100 includes a light-transmitting substrate layer 101 and an optical path layer 102 located on the light-transmitting substrate layer 101. The optical path layer 102 has a grating coupling-in region 103 and a grating coupling-out region 104 on two opposite surfaces. The grating coupling-in region 103 is located on the side closer to the light-transmitting substrate layer 101, and the grating coupling-out region 104 is located on the side away from the light-transmitting substrate layer 101.

[0092] Image sensor chip 120; the image sensor chip 120 has a coplanar image area 121 and a pad area 122 (e.g., ...) on its front side. Figure 6 As shown); the image sensor chip 120 has through holes 13 formed on its back side that expose the pads 123 of the pad area 122 (as shown). Figure 10 As shown in the figure, a first dielectric isolation layer 14 is formed on the sidewall surface of the through hole 13, and the first dielectric isolation layer 14 extends to cover the back surface of the image sensor chip 120; a metal wiring layer 15 is formed on the bottom wall of the through hole 13 and on the surface of the first dielectric isolation layer 14 on the sidewall of the through hole 13, and the metal wiring layer 15 extends from the inside of the through hole 13 to the surface of the first dielectric isolation layer 14 on the back of the image sensor chip 120;

[0093] The second dielectric isolation layer 16 is disposed on the metal wiring layer 15 on the back side of the image sensor chip 120 and on the first dielectric isolation layer 14.

[0094] Metal bump 17, the metal bump 17 penetrates the second dielectric isolation layer 16 and contacts the metal wiring layer 15;

[0095] A patterned dielectric layer 11 is disposed on the surface of the optical chip 100 near the grating coupling region 104, and the patterned dielectric layer 11 does not correspond to the image region 121 of the image sensor chip 120 but is at least directly opposite a portion of the pad region 122 of the image sensor chip 120.

[0096] The image sensor chip 120 is bonded to the patterned medium layer 11 by an adhesive (not shown in the figure), thereby achieving the bonding between the optical chip 100 and the image sensor chip 120, and the grating coupling region 104 of the optical chip 100 is directly opposite to the image region 121 of the image sensor chip 120.

[0097] like Figure 19 As shown in the figure, the optical path of the optoelectronic chip co-package structure 19 in this embodiment is as indicated by the arrow direction in the figure: the two opposite surfaces of the optical path layer 102 of the optical chip 100 have a grating coupling region 103 and a grating coupling out region 104. An external light source enters the grating coupling region 103 through the light-transmitting substrate layer 101 and is coupled into the optical path layer 102. After the preset light signal is processed in the optical path layer 102 to form image light rays, the light rays are coupled out from the grating coupling out region 104 into the image region 121 of the image sensor chip 120.

[0098] As a preferred example, the light-transmitting substrate layer 101 of the optical chip 100 is a glass substrate layer, the patterned dielectric layer 11 is made of a photosensitive material, and the first dielectric isolation layer 14 is made of a photosensitive material, such as photoresist or photosensitive PI material.

[0099] As a specific example, the image area 121 on the front side of the image sensor chip 120 is located in the middle of the image sensor chip 120, and the pad area 122 on the front side of the image sensor chip 120 is located at the outer peripheral edge of the image area 121.

[0100] In summary, this invention provides a co-packaging structure for optoelectronic chips and its fabrication method. By setting a patterned dielectric layer with a non-corresponding image region between the optoelectronic chip wafer and the image sensor wafer, and bonding the two wafers face-to-face using an adhesive applied to the surface of the patterned dielectric layer, simultaneously, vias are drilled and wiring is performed on the back of the image sensor wafer, and electrical signals from the image sensor chip are guided from the front to the back using metal bumps. This achieves wafer-to-wafer level bonding and effectively controls the distance between the image region of the image sensor and the grating coupling region of the optoelectronic chip to within 30 μm. This enables short-range, efficient transmission of optical signals between the optoelectronic chip and the image sensor chip, significantly reducing packaging size, packaging difficulty, and packaging manufacturing costs. It achieves low-cost, high-density packaging integration, and is comparable to die-to-die packaging. Compared to the package volume of a die, under the same conditions, the package volume obtained by the method of this invention can be reduced by up to 80%. Furthermore, by setting the substrate layer of the optical chip in the optical chip wafer as a transparent substrate layer, the grating coupling region and the grating coupling region can be made non-coplanar, with the grating coupling region closer to the transparent substrate layer and the grating coupling region farther away. The grating coupling region does not restrict the wiring of the image sensor chip, effectively reducing the wiring difficulty of the image sensor chip and increasing the design freedom of the position and size of the grating coupling region, further reducing the process difficulty and package volume. Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0101] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for fabricating a co-packaged structure for an optoelectronic chip, characterized in that, The preparation method comprises the following steps: providing a light chip wafer arranged with a plurality of light chips; wherein the light chip comprises a light-transmitting substrate layer and a light path layer located on the light-transmitting substrate layer, and opposite surfaces of the light path layer have grating coupling-in areas and grating coupling-out areas, the grating coupling-in areas are located on one side close to the light-transmitting substrate layer, and the grating coupling-out areas are located on one side away from the light-transmitting substrate layer; forming a patterned dielectric layer on the surface of the light chip wafer close to the grating coupling-out areas; providing an image sensor wafer arranged with a plurality of image sensor chips, and bonding the image sensor wafer on the patterned dielectric layer through an adhesive to realize bonding of the light chip wafer and the image sensor wafer; wherein the front surface of the image sensor chip is provided with coplanar image areas and pad areas, the grating coupling-out areas of the light chip are directly opposite in the image areas, and the patterned dielectric layer does not correspond to the image areas but at least directly opposite part of the pad areas; etching the back surface of the image sensor wafer to form a plurality of through holes, and the through holes expose pads in the pad areas of each image sensor chip; forming a first dielectric isolation layer on the sidewall of the through hole, and the first dielectric isolation layer also extends to cover the back surface of the image sensor wafer; forming a metal wiring layer on the bottom wall of the through hole and the surface of the first dielectric isolation layer on the sidewall of the through hole, and the metal wiring layer extends from the inside of the through hole to the surface of the first dielectric isolation layer on the back surface of the image sensor wafer; forming a second dielectric isolation layer on the back surface of the image sensor wafer, and windowing the second dielectric isolation layer to form a window, and the window exposes the metal wiring layer; ball planting in the window to form a metal bump; scribing the obtained structure along a scribe lane to obtain a single optoelectronic chip co-packaging structure.

2. The method of claim 1, wherein: The light-transmitting substrate layer of the light chip is a glass substrate layer.

3. The method of claim 1, wherein: The image areas on the front surface of the image sensor chip are located at the middle position of the image sensor chip, and the pad areas on the front surface of the image sensor chip are located at the outer peripheral edge of the image areas; after bonding of the light chip wafer and the image sensor wafer, the patterned dielectric layer directly opposite the pad areas on the front surface of each image sensor chip and the scribe lane area forms a cofferdam structure.

4. The method of claim 3, wherein the method further comprises: The method for etching the through hole comprises: first-step etching the back surface of the image sensor wafer to a preset depth to form a first etching hole, and the opening of the first etching hole is directly opposite the outer periphery of the patterned dielectric layer; second-step etching the back surface of the image sensor wafer to a preset depth based on the first etching hole to form a second etching hole, and the second etching hole exposes the pads of the pad areas and exposes the scribe lane directly opposite the patterned dielectric layer, and the second etching hole exposing the pads and the first etching hole constitute the through hole.

5. The method of claim 1, wherein the method further comprises: The material of the patterned dielectric layer is a photosensitive material; The method for forming the patterned dielectric layer comprises: forming a dielectric layer on the surface of the optical chip wafer near the grating out-coupling region; and performing preset exposure and development on the dielectric layer, so that the remaining dielectric layer forms the patterned dielectric layer.

6. The method of claim 1, wherein the method further comprises: The first dielectric isolation layer is made of a photosensitive material. The method for forming the first dielectric isolation layer comprises: forming the first dielectric isolation layer on the back surface of the image sensor wafer, the sidewall and the bottom wall of the through hole. Then, the first dielectric isolation layer is subjected to preset exposure and development to remove the first dielectric isolation layer on the bottom wall of the through hole and the cutting path.

7. The method of claim 1, wherein the method further comprises: The method for forming the metal wiring layer comprises: forming a seed layer on the surface of the first dielectric isolation layer and the surface of the pad on the bottom wall of the through hole by sputtering; forming a metal layer on the surface of the seed layer by electroplating; and performing preset patterned etching on the metal layer and the seed layer to form the metal wiring layer.

8. An optoelectronic chip co-packaging structure, comprising: The optoelectronic chip co-packaging structure comprises: an optical chip, which comprises a light-transmitting substrate layer and a light path layer on the light-transmitting substrate layer, and the light path layer has a grating in-coupling region and a grating out-coupling region on opposite surfaces thereof, the grating in-coupling region is located on a side close to the light-transmitting substrate layer, and the grating out-coupling region is located on a side away from the light-transmitting substrate layer; an image sensor chip, which has a co-planar image region and a pad region on the front surface thereof, and has a through hole with a pad of the pad region exposed on the back surface thereof, a first dielectric isolation layer on the sidewall surface of the through hole, and a metal wiring layer on the bottom wall of the through hole and the surface of the first dielectric isolation layer on the sidewall of the through hole, the metal wiring layer extending from the inside of the through hole to the surface of the first dielectric isolation layer on the back surface of the image sensor chip; a second dielectric isolation layer on the metal wiring layer on the back surface of the image sensor chip and on the first dielectric isolation layer; a metal bump, which penetrates the second dielectric isolation layer and contacts the metal wiring layer; a patterned dielectric layer on the surface of the optical chip near the grating out-coupling region, the patterned dielectric layer not corresponding to the image region of the image sensor chip but at least facing part of the pad region of the image sensor chip. The image sensor chip is bonded to the patterned dielectric layer by an adhesive, the optical chip and the image sensor chip are bonded, and the grating out-coupling region of the optical chip faces the image region of the image sensor chip.

9. The optoelectronic chip co-package structure of claim 8, wherein: The light-transmitting substrate layer of the optical chip is a glass substrate layer, the patterned dielectric layer is made of a photosensitive material, and the first dielectric isolation layer is made of a photosensitive material.

10. The optoelectronic chip co-package structure of claim 8, wherein: The image region on the front surface of the image sensor chip is located at the middle position of the image sensor chip, and the pad region on the front surface of the image sensor chip is located at the outer peripheral edge of the image region.

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