Display device, display device manufacturing method, and electronic device including display device

Abstract

This application relates to a display device, a method of manufacturing a display device, and an electronic device including a display device. The display device includes: a substrate including a display area; a thin-film transistor on the substrate and in the display area; a first insulating layer on the thin-film transistor and including a via exposing a source electrode or drain electrode of the thin-film transistor; a second insulating layer on the first insulating layer and including a first via and a second via spaced apart from each other; and a pixel electrode on the second insulating layer and electrically connected to the thin-film transistor via a via, wherein the first via overlaps with the via, and the second via does not overlap with the via.

Description

[0001] Cross-reference of related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2025-0030872, filed on March 10, 2025, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] Some aspects of this disclosure relate to display devices, methods of manufacturing display devices, and electronic devices including display devices. Background Technology

[0004] Display devices display images and include liquid crystal displays (LCDs), organic light-emitting diodes (OLEDs), etc. Display devices are used in various electronic devices such as mobile phones, navigation devices, digital cameras, e-books, portable game consoles, and various terminals.

[0005] Organic light-emitting diode (OLED) displays employ an active matrix scheme using thin-film transistors (TFTs), connecting the TFTs to pixel electrodes and driving them based on a voltage maintained by the capacitance of the TFTs. In OLED devices, multiple apertures are used between wiring and electrodes, as well as in areas where connections are needed between electrodes, thus reducing the aperture ratio.

[0006] The information disclosed in this background section is only intended to enhance the understanding of the background art, and therefore the information discussed in this background section does not necessarily constitute prior art. Summary of the Invention

[0007] Some aspects of embodiments of this disclosure relate to display devices, methods of manufacturing display devices, and electronic devices including display devices, and, for example, to display devices, methods of manufacturing display devices, and electronic devices including display devices with relatively improved reliability.

[0008] Some aspects of embodiments of this disclosure include display devices and electronic devices capable of improving the aperture ratio of pixels.

[0009] However, this feature is merely an example, and the scope of implementations according to this disclosure is not limited thereto.

[0010] According to some embodiments of the present disclosure, a display device includes: a substrate including a display area; a thin-film transistor disposed on the display area; a first insulating layer disposed on the thin-film transistor and including a via exposing a source electrode or a drain electrode of the thin-film transistor; a second insulating layer disposed on the first insulating layer and including a first via and a second via spaced apart from each other; and a pixel electrode disposed on the second insulating layer and electrically connected to the thin-film transistor via a via, wherein the first via overlaps with the via and the second via does not overlap with the via.

[0011] According to some embodiments of the present disclosure, the display device may further include: an initialization voltage line extending in a first direction on a substrate, wherein a second via overlaps with the initialization voltage line.

[0012] According to some embodiments of this disclosure, the second via may not overlap with the pixel electrode.

[0013] According to some embodiments of this disclosure, the second via may not overlap with the source or drain electrode exposed by the via.

[0014] According to some embodiments of this disclosure, the width of the second via may be less than or equal to the width of the first via.

[0015] According to some embodiments of this disclosure, the width of the first via may be less than or equal to the width of the through hole.

[0016] According to some embodiments of this disclosure, the width of the first via can be at most twice the width of the through hole.

[0017] According to some embodiments of this disclosure, the source electrode or drain electrode of a thin-film transistor may include copper (Cu).

[0018] According to some embodiments of this disclosure, the second via may expose a portion of the first insulating layer.

[0019] According to some embodiments of this disclosure, the second via can be formed in multiple ways.

[0020] According to some embodiments of the present disclosure, a method of manufacturing a display device includes: forming a thin-film transistor including a source electrode and a drain electrode on a display area of ​​a substrate; forming a first insulating layer including a via exposing the source electrode or the drain electrode on the thin-film transistor; forming a second insulating layer including a first via and a second via on the first insulating layer; and forming a pixel electrode electrically connected to the source electrode or the drain electrode via the via on the second insulating layer, wherein the first via overlaps with the via, and the second via does not overlap with the via.

[0021] According to some embodiments of this disclosure, the method may further include: forming an initialization voltage line extending in a first direction on a substrate, wherein a second via overlaps with the initialization voltage line.

[0022] According to some embodiments of this disclosure, the second via may not overlap with the pixel electrode.

[0023] According to some embodiments of this disclosure, the width of the second via may be less than or equal to the width of the first via.

[0024] According to some embodiments of this disclosure, the width of the first via may be less than or equal to the width of the through hole.

[0025] According to some embodiments of this disclosure, the width of the first via can be at most twice the width of the through hole.

[0026] According to some embodiments of this disclosure, the source electrode or drain electrode of a thin-film transistor may include copper (Cu).

[0027] According to some embodiments of this disclosure, the second via may expose a portion of the first insulating layer.

[0028] According to some embodiments of this disclosure, the second via can be formed in multiple ways.

[0029] According to some embodiments of this disclosure, an electronic device includes: a processor configured to generate a scan input signal; a power supply module configured to generate a scan input voltage; and a display device configured to receive the scan input signal and the scan input voltage, and output a scan signal to a pixel circuit, wherein the display device includes: a substrate including a display area; a thin-film transistor disposed on the display area; a first insulating layer disposed on the thin-film transistor and including a via exposing a source electrode or a drain electrode of the thin-film transistor; a second insulating layer disposed on the first insulating layer and including a first via and a second via spaced apart from each other; and a pixel electrode disposed on the second insulating layer and electrically connected to the thin-film transistor via a via, wherein the first via overlaps with the via, and the second via does not overlap with the via.

[0030] Other aspects, features, and characteristics, in addition to those described above, will become apparent from the accompanying drawings, claims, and detailed embodiments of this disclosure. Attached Figure Description

[0031] The above and other aspects, features and characteristics of certain embodiments of this disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, wherein: Figure 1 This is a schematic plan view of a display device according to some embodiments of the present disclosure; Figure 2This is a schematic diagram illustrating wiring included in a display device according to some embodiments of the present disclosure; Figure 3 This is an equivalent circuit diagram of a pixel according to some embodiments of this disclosure; Figure 4 It is shown in Figure 1 A layout diagram of a portion of the display area of ​​a display device, including the area of ​​pixel units; Figure 5 It is shown schematically. Figure 4 A cross-sectional view of the display device shown in the figure; Figure 6 yes Figure 4 An enlarged plan view of part A; Figures 7 to 9 It is shown schematically layer by layer. Figure 4 The layout diagram of the display device shown includes components such as thin-film transistors and storage capacitors; Figure 10 This is a block diagram of an electronic device according to some embodiments of the present disclosure; and Figure 11 This is a block diagram of an electronic device according to various embodiments of the present disclosure. Detailed Implementation

[0032] Various modifications and implementations are possible with respect to embodiments of this disclosure, and therefore specific embodiments will be shown in the accompanying drawings and described in detail in the specific embodiments. The effects and features of this disclosure, as well as the methods for implementing them, will become clear with reference to the embodiments described in detail below in conjunction with the accompanying drawings. However, embodiments of this disclosure are not limited to those disclosed below and can be implemented in various forms.

[0033] In the following implementation, terms such as first, second, etc., are used to distinguish one component from other components, rather than to limit them.

[0034] In the following implementation, unless otherwise explicitly indicated in the context, the singular form includes the plural form.

[0035] In the following implementation, the terms "comprising," "having," etc., are intended to indicate the presence of the features or components described herein, but do not preclude the possibility of adding one or more other features or components.

[0036] In the following embodiments, when a portion such as a membrane, region, component, etc. exists on or above another portion, this situation can include not only the case where it is directly on the other portion, but also the case where another membrane, region, component, etc. is arranged between the portion and the other portion.

[0037] In the accompanying drawings, the dimensions of components may be exaggerated or reduced for ease of description. For example, since the dimensions and thicknesses of each component shown in the drawings are arbitrarily depicted for ease of description, the embodiments according to this disclosure are not necessarily limited to the illustrations.

[0038] When a particular implementation can be carried out in a different order, the specific process sequence may be performed differently than the order in which it is described. For example, two processes described consecutively may be performed simultaneously (or substantially simultaneously), or they may be performed in the reverse order of their description.

[0039] In the following description, some aspects of embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings, and in the description with reference to the drawings, the same or corresponding parts are given the same reference numerals, and some redundant descriptions may be omitted.

[0040] Figure 1 This is a schematic plan view of a display device 1 according to some embodiments of the present disclosure.

[0041] refer to Figure 1 The display device 1 can be applied to various electronic devices, including: small to medium-sized electronic devices such as tablet PCs, smartphones, car navigation units, cameras, central information displays (CIDs) installed in vehicles, wrist-worn electronic devices, personal digital assistants (PDAs), portable multimedia players (PMPs), and game consoles; and medium to large-sized electronic devices such as televisions, billboards, monitors, PCs, and laptops. However, these are presented as embodiments, and it is apparent that this disclosure can be used with other electronic devices without departing from the concept of this disclosure.

[0042] Display device 1 may include a display panel that provides a display screen. Examples of display panels may include inorganic light-emitting diode (LED) display panels, organic light-emitting diode (OLED) display panels, quantum dot (QD) display panels, plasma display panels, field emission display panels, etc. In the following description, organic light-emitting diodes are used as an example of a display panel; however, embodiments according to this disclosure are not limited thereto, and other display panels may be used, provided that the same technical concept is applicable.

[0043] The shape of the display device 1 can be changed in various ways. According to some embodiments, the display device 1 can have shapes such as a rectangle with a long width, a rectangle with a long length, a square, a rectangle with rounded corners (vertices), other polygons, a circle, etc. The shape of the display area DA of the display device 1 can also be similar to the overall shape of the display device 1. Figure 1 The image shows a display device 1 with a rectangular shape and a display area DA.

[0044] The display device 1 may include two first sides extending in one direction and two second sides extending in another direction intersecting the first side. The corners where the first and second sides of the display device 1 intersect may be right angles, but embodiments of the present disclosure are not limited to this, and they may also form curved surfaces. According to some embodiments, the first side may be shorter than the second side, but embodiments of the present disclosure are not limited to this. The planar shape of the display device 1 is not limited to that shown in the figures and may be circular or other shapes.

[0045] Display device 1 may include a display area DA and a non-display area NDA. The display area DA may be an area where a screen or image can be displayed, and the non-display area NDA may be an area where a screen or image is not displayed. The display area DA may also be referred to as the active area, and the non-display area NDA may also be referred to as the inactive area. This can be understood to mean that the substrate SUB included in display device 1 (see...) Figure 5 The display device 1 includes a display area DA and a non-display area NDA. The display area DA may occupy the center of the display device 1 substantially. The non-display area NDA may surround the display area DA (e.g., outside the display area DA or outside its space).

[0046] The display area DA may include multiple pixels PX. The multiple pixels PX can be arranged in a matrix direction. The shape of each pixel PX in the plane can be rectangular or square, but is not limited to this according to embodiments of this disclosure, and can also be a rhombus with each side inclined in the direction. Each pixel PX can be arranged alternately in a strip or penTile pattern. ® type.

[0047] Each pixel PX can represent a subpixel and can include a light-emitting element and pixel circuitry connected thereto. Each pixel PX can include one or more light-emitting elements that emit light of a specific wavelength to display a specific color. The display device 1 can use the light emitted from the pixel PX to display an image.

[0048] The non-display area NDA can be arranged around the display area DA (e.g., outside the display area DA or outside its space). The non-display area NDA can completely or partially surround the display area DA (e.g., outside the display area DA or outside its space). The display area DA can have a rectangular shape, and the non-display area NDA can be arranged adjacent to the four sides of the display area DA. The non-display area NDA can form the frame of the display device 1. In each non-display area NDA, wiring or circuit driving units included in the display device 1 can be placed, or external devices can be mounted.

[0049] Figure 2This is a schematic diagram illustrating wiring included in a display device 1 according to some embodiments of the present disclosure.

[0050] refer to Figure 2 The display device 1 may include multiple wirings. These wirings may include scan lines (SCL), sensing lines (SSL) (see...). Figure 3 The display device 1 may include data lines DTL, operation control lines ECL, initialization voltage lines VIL, first voltage lines VDL, second voltage lines VSL, etc. According to some embodiments, the display device 1 may also include other wiring. Figure 2 Only a schematic arrangement of multiple wirings is shown.

[0051] Scan line SCL and sensing line SSL can extend along the first direction DR1. Scan line SCL and sensing line SSL can be connected to a scan driving unit SDR. The scan driving unit SDR can include driving circuitry. The scan driving unit SDR can be arranged on one side of the first direction DR1 of the display area DA, but embodiments according to this disclosure are not limited thereto. The scan driving unit SDR can be connected to a signal connection line CWL, and at least one end of the signal connection line CWL can form a pad WPD_CW on the non-display area NDA for connection to an external device.

[0052] Here, "connection" can mean not only that one component is connected to another component through physical contact, but also that one component is connected through another component. "Connection" can also be understood as a single, unified component through which any part is connected to another part. The connection between any component and another component can be interpreted as including not only direct contact connection, but also electrical connection through other components.

[0053] The data line DTL and the initialization voltage line VIL can extend along a second direction DR2, which intersects with the first direction DR1. The initialization voltage line VIL can include a portion extending along the second direction DR2 and a portion extending from that portion along the first direction DR1. The first voltage line VDL and the second voltage line VSL can also include a portion extending along the second direction DR2 and a portion connected thereto and extending along the first direction DR1. The first voltage line VDL and the second voltage line VSL can have a mesh structure, but embodiments according to this disclosure are not limited thereto.

[0054] The data line DTL, initialization voltage line VIL, first voltage line VDL, and second voltage line VSL can be electrically connected to at least one wiring pad WPD. Each wiring pad WPD can be arranged in a non-display area NDA. According to some embodiments, the wiring pad WPD_DT of the data line DTL (hereinafter referred to as the "data pad") can be arranged in the pad area PDA on one side of the second direction DR2 of the display area DA, and the wiring pad WPD_Vint of the initialization voltage line VIL (hereinafter referred to as the "initialization voltage pad"), the wiring pad WPD_VDD of the first voltage line VDL (hereinafter referred to as the "first power pad"), and the wiring pad WPD_VSS of the second voltage line VSL (hereinafter referred to as the "second power pad") can be arranged in the pad area PDA on the other side of the second direction DR2 of the display area DA. As another example, the data pad WPD_DT, the initialization voltage pad WPD_Vint, the first power pad WPD_VDD, and the second power pad WPD_VSS can all be arranged in the same area, for example, the non-display area NDA located above the display area DA. External devices can be mounted on the wiring pads WPD. External devices can be mounted on the wiring pads WPD via anisotropic conductive films, ultrasonic bonding, etc.

[0055] Each pixel PX of the display device 1 may include a pixel driving circuit. The wiring described above can apply a driving signal to each pixel driving circuit while passing through each pixel PX or its periphery. The pixel driving circuit may include transistors and capacitors. The number of transistors and capacitors in each pixel driving circuit can vary. According to some embodiments, each pixel PX of the display device 1 may have a 4T1C structure in which the pixel driving circuit includes four transistors and one capacitor. Although the 4T1C structure is used as an example to describe the pixel driving circuit, the embodiments according to this disclosure are not limited thereto, and various other modified pixel PX structures such as 2T1C structure, 3T1C structure, 7T1C structure, etc., can be applied.

[0056] Figure 3 This is an equivalent circuit diagram of a pixel according to some implementation methods. Although Figure 3 Various components in a pixel circuit according to some embodiments are shown, but the embodiments of this disclosure are not limited thereto, and according to some embodiments, the pixel circuit may include additional or fewer components without departing from the spirit and scope of the embodiments of this disclosure.

[0057] refer to Figure 3According to some embodiments, a pixel PX of the display device 1 may include a pixel driving circuit PC connected to a scan line SCL and a data line DTL, and a light-emitting diode LD connected to the pixel driving circuit PC.

[0058] The pixel driving circuit PC may include four thin-film transistors T1, T2, T3, and T4, and a storage capacitor Cst. The thin-film transistors T1, T2, T3, and T4, and the storage capacitor Cst may be connected to signal lines SCL, ECL, and DTL, initialization voltage line VIL, first voltage line VDL, and second voltage line VSL.

[0059] A light-emitting diode (LED) can emit light according to the current supplied through a first transistor T1. The LED may include a pixel electrode, a counter electrode, and at least one light-emitting element disposed therebetween. The light-emitting element can emit light within a specific wavelength range via electrical signals transmitted from the pixel electrode and the counter electrode. The pixel electrode of the LED may be connected to the source electrode of the first transistor T1, and the counter electrode may be connected to a second voltage line VSL supplied with a low potential voltage (hereinafter, the second power supply voltage) lower than the high potential voltage (hereinafter, the first power supply voltage) of the first voltage line VDL.

[0060] The signal lines may include the scan line SCL for transmitting the scan signal Sn, the operation control line ECL for transmitting the operation control signal EM, and the data line DTL for transmitting the data signal Dm. The initialization voltage line VIL can transmit the initialization voltage Vint for initializing the pixel electrode of the light-emitting diode LD, and the first voltage line VDL can transmit the first power supply voltage ELVDD, which serves as the driving voltage for the driving transistor T1.

[0061] The first transistor T1 can control the current flowing from the first voltage line VDL, to which the first power supply voltage ELVDD is supplied, to the light-emitting diode LD based on the voltage difference between its gate electrode and source electrode. For example, the first transistor T1 can be a driver transistor for driving the light-emitting diode LD. The gate electrode of the first transistor T1 can be connected to the source electrode of the second transistor T2 via a first node N1, the source electrode can be connected to the pixel electrode of the light-emitting diode LD, and the drain electrode can be connected to the first voltage line VDL, to which the first power supply voltage ELVDD is applied, via a fourth transistor T4.

[0062] The second transistor T2 can be turned on by the scan signal Sn of the scan line SCL to connect the data line DTL to the gate electrode of the first transistor T1. The gate electrode of the second transistor T2 can be connected to the scan line SCL, the source electrode can be connected to the gate electrode of the first transistor T1, and the drain electrode can be connected to the data line DTL.

[0063] The third transistor T3 can be turned on by the sensing signal SSn of the sensing line SSL to connect the initialization voltage line VIL to the pixel electrode of the light-emitting diode LD. The gate electrode of the third transistor T3 can be connected to the sensing line SSL, the drain electrode can be connected to the initialization voltage line VIL, and the source electrode can be connected to the pixel electrode of the light-emitting diode LD or the source electrode of the first transistor T1 through the second node N2.

[0064] The fourth transistor T4 can be turned on by the operation control signal EM on the operation control line ECL to transmit the first power supply voltage ELVDD (drive voltage) to the light-emitting diode LD, so that drive current can flow to the light-emitting diode LD. The gate electrode of the fourth transistor T4 can be connected to the operation control line ECL, the drain electrode can be connected to the first voltage line VDL, and the source electrode can be connected to the drain electrode of the first transistor T1.

[0065] According to some implementations, the source and drain electrodes of each transistor T1, T2, T3 or T4 are not limited to those described above, and vice versa.

[0066] A storage capacitor Cst can be formed between the gate electrode and the source electrode of the first transistor T1. The storage capacitor Cst may include a first capacitor electrode CE1 and a second capacitor electrode CE2. The first capacitor electrode CE1 can be connected to the source region of the first transistor T1 through a second node N2, and the second capacitor electrode CE2 can be connected to the gate electrode of the first transistor T1 through a first node N1. The storage capacitor Cst can store the differential voltage between the gate voltage and the source voltage of the first transistor T1.

[0067] Each of transistors T1, T2, T3, and T4 may include a thin-film transistor. Figure 3 The description is primarily based on the fact that each transistor T1, T2, T3, or T4 comprises an N-type metal-oxide-semiconductor field-effect transistor (MOSFET), but embodiments of this disclosure are not limited thereto. That is, each of transistors T1, T2, and T3 may be formed as a P-type MOSFET, or some of them may be formed as N-type MOSFETs and others may be formed as P-type MOSFETs.

[0068] In the following description, the structure of a pixel PX of the display device 1 according to some embodiments will be further described in detail with reference to other accompanying drawings.

[0069] Figure 4 It is shown in Figure 1 A layout diagram of a portion of the display area of ​​a display device, including the area of ​​pixel units (PXU). Figure 5 It is shown schematically. Figure 4 A cross-sectional view of the display device shown, and Figure 6 yes Figure 4 A magnified plan view of part A. Figures 7 to 9 It is shown schematically layer by layer. Figure 4 The diagram shows a layout of components of the display device, including thin-film transistors, storage capacitors, etc.

[0070] In each of the following figures, the opposite sides of the first direction DR1 may be referred to as the left and right sides, respectively, and the opposite sides of the second direction DR2 may be referred to as the upper and lower sides, respectively.

[0071] refer to Figure 4 A pixel unit PXU may include at least one pixel PX. According to some implementations, a pixel unit PXU may include three pixels PX1, PX2 and PX3, but the number of pixels PX included in the pixel unit PXU is not limited to this, and the pixel unit PXU may include fewer or more pixels PX.

[0072] Multiple pixels PXn (n being an integer from 1 to 3) included in a pixel unit PXU can emit light of different colors. According to some embodiments, the first pixel PX1 can emit red light, the second pixel PX2 can emit green light, and the third pixel PX3 can emit blue light. However, embodiments according to this disclosure are not limited to this, and each pixel PX1, PX2, or PX3 can emit light of the same color.

[0073] Although the multiple pixels PX included in the pixel unit PXU are arranged in a strip shape or arrangement, according to some embodiments, they can be arranged as PenTile. ® Shape. For ease of description, Figure 4 The portions of other pixels located below the first pixel PX1, the second pixel PX2, and the third pixel PX3 are also shown. For example... Figure 4 The structure shown can be repeated in the first direction DR1 and / or the second direction DR2. Between pixels PX, there can be regions that do not belong to any pixel PX. According to some embodiments, an initialization voltage line VIL, a first voltage line VDL, or a second voltage line VSL can exist between adjacent pixels PX.

[0074] As described above, each pixel PX1, PX2, or PX3 included in the pixel unit PXU may include a plurality of transistors T1 to T4 as pixel circuit elements and a storage capacitor Cst, and may be connected to the scan line SCL, the data line DTL, the operation control line ECL, the sensing line SSL, the first voltage line VDL, the second voltage line VSL, and the initialization voltage line VIL.

[0075] Scan lines SCL can extend along a first direction DR1 and can span multiple pixels PX arranged along the first direction DR1. Multiple scan lines SCL can span the entire display area DA and be spaced apart from each other along a second direction DR2. According to some embodiments, the scan lines SCL can be located on the upper side relative to the center of each pixel PX. The scan lines SCL can be electrically connected to the gate electrode of a second transistor T2, and a scan signal can be applied to the second transistor T2.

[0076] Sensing lines SSL can extend along a first direction DR1 and can span multiple pixels PX arranged along the first direction DR1. Multiple sensing lines SSL can span the entire display area DA and be spaced apart from each other along a second direction DR2. According to some embodiments, the sensing lines SSL can be located on the lower side relative to the center of each pixel PX. The sensing lines SSL can be electrically connected to the gate electrode of a third transistor T3 and can apply a sensing signal to the third transistor T3.

[0077] The scan line SCL and the sensing line SSL may include a third conductive layer as described below.

[0078] Data lines DTL can extend along the second direction DR2 and can span multiple pixels PX arranged along the second direction DR2. Multiple data lines DTL can span the entire display area DA, spaced apart from each other along the first direction DR1. According to some embodiments, the data lines DTL can be located on the right or left side of each pixel PX. The data lines DTL can be electrically connected to the source or drain electrode of the second transistor T2 and can apply data signals to the second transistor T2.

[0079] The initialization voltage line VIL can extend along the second direction DR2 and can span multiple pixel PX arrangements along the second direction DR2. Multiple initialization voltage lines VIL can span the entire display area DA and be spaced apart from each other along the first direction DR1.

[0080] According to some embodiments, the initialization voltage line VIL can be arranged for every three pixels PX or for each pixel unit PXU. According to some embodiments, the initialization voltage line VIL can be arranged on the upper left side relative to the center of each pixel unit PXU, and can be arranged on the left side of the lower capacitor electrode included in any pixel (e.g., the first pixel PX1). The initialization voltage line VIL can be electrically connected to the source or drain electrode of the third transistor T3, and an initialization voltage can be applied to the third transistor T3.

[0081] The data line DTL and the initialization voltage line VIL may include a first conductive layer as described below.

[0082] The first voltage line VDL and the second voltage line VSL can extend along the second direction DR2 and can be arranged across multiple adjacent pixels PX along the second direction DR2. Multiple first voltage lines VDL or multiple second voltage lines VSL can be spaced apart from each other across the entire display area DA along the first direction DR1. According to some embodiments, the first voltage line VDL can be arranged on the upper right side relative to the center of each pixel unit PXU, and the second voltage line VSL can be arranged on the upper left side relative to the center of each pixel unit PXU.

[0083] The first voltage line VDL can be electrically connected to the source or drain electrode of the fourth transistor T4, and the first power supply voltage ELVDD can be applied to the first transistor T1 via the fourth transistor T4. The second voltage line VSL can be electrically connected to the counter electrode of the light-emitting diode LD to apply the second power supply voltage ELVSS to the light-emitting diode LD. The first voltage line VDL and the second voltage line VSL may include a first conductive layer.

[0084] A first voltage line VDL can be electrically connected via a contact hole to a first upper voltage line VDL' extending in the first direction DR1. A second voltage line VSL can be electrically connected via a contact hole to a second upper voltage line VSL' extending in the first direction DR1. The first upper voltage line VDL' and the second upper voltage line VSL' may include a third conductive layer, such as... Figure 9 As shown in the image.

[0085] The layout diagram and the cross-sectional structure of each pixel PX will be described in detail. For ease of description, some components will be described based on the first pixel PX1, but these components can also be arranged in the second pixel PX2 and the third pixel PX3.

[0086] The display device 1 may include a substrate SUB, and pixel circuit elements may be arranged on the substrate SUB. The substrate SUB may include an insulating material such as glass, quartz, polymer resin, etc. The substrate SUB may be a rigid substrate, but it may also be a flexible substrate that can be bent, folded, rolled, etc.

[0087] A lower metal layer BML can be disposed on the substrate SUB. The lower metal layer BML may include a first voltage line VDL, a second voltage line VSL, an initialization voltage line VIL, a first lower capacitor electrode BML1, and a first data line DTL1. Among them, the first voltage line VDL, the second voltage line VSL, the initialization voltage line VIL, and the first data line DTL1 can extend in the second direction DR2.

[0088] The lower capacitor electrode can have an isolated shape in each pixel PX. The first lower capacitor electrode BML1 can be electrically connected to the first capacitor electrode CE1-1 located thereon via a contact hole. The first lower capacitor electrode BML1 can be arranged to overlap with the active layer of the first transistor T1. The first lower capacitor electrode BML1 can prevent or reduce light entering the first transistor T1 by including a light-blocking material.

[0089] The lower metal layer (BML) may be a first conductive layer comprising a first conductive material. The first conductive material may include metals, alloys, conductive metal oxides, etc. According to some embodiments, the lower metal layer (BML) may include silver (Ag), Ag-containing alloys, molybdenum (Mo), Mo-containing alloys, aluminum (Al), Al-containing alloys, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), etc. The lower metal layer (BML) may have a multilayer structure. According to some embodiments, the lower metal layer (BML) may have a two-layer structure comprising an aluminum layer with a thickness of 3500 Å and a titanium layer with a thickness of 300 Å.

[0090] As described above, the lower metal layer BML (i.e., the first conductive layer) can be applied as a signal line of a pixel PX, such as a first voltage line VDL, a second voltage line VSL, an initialization voltage line VIL, and a data line DTL. The lower metal layer BML may include a low-resistance material to reduce the resistance of the signal line and can be formed to have a selected thickness.

[0091] The buffer layer 111 can cover the underlying metal layer BML and can be disposed on the entire surface of the substrate SUB. The buffer layer 111 can be formed on the substrate SUB to protect the thin-film transistors of the pixel PX from moisture or impurities penetrating the moisture-permeable substrate SUB, and can perform surface planarization functions.

[0092] Buffer layer 111 may include an insulating material. Buffer layer 111 may include multiple inorganic layers stacked alternately. According to some embodiments, buffer layer 111 may be formed as a silicon oxide layer (SiO2). x ), silicon nitride layer (SiN) x A multilayer structure consisting of alternating layers of inorganic materials, such as silicon oxide (SiON) and silicon nitride (SiON).

[0093] Semiconductor layer 210 may be disposed on buffer layer 111. Semiconductor layer 210 may include the active layer of each transistor T1, T2, T3 or T4.

[0094] According to some embodiments, the semiconductor layer 210 may include polycrystalline silicon, monocrystalline silicon, oxide semiconductors, etc. Polycrystalline silicon can be formed by crystallizing amorphous silicon. The oxide semiconductor may be an oxide semiconductor containing indium (In). According to some embodiments, the oxide semiconductor may include indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium oxide (IGO), indium zinc tin oxide (IZTO), indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), indium gallium zinc tin oxide (IGZTO), etc.

[0095] Semiconductor layer 210 may include a plurality of semiconductor patterns AP spaced apart from each other. According to some embodiments, semiconductor layer 210 may include a first semiconductor pattern AP1-1, a second semiconductor pattern AP2-1, and a third semiconductor pattern AP3-1 spaced apart from each other, such as... Figure 8 As shown in the figure, the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 can be arranged along the semiconductor pattern AP of the semiconductor layer 210.

[0096] The first semiconductor pattern AP1-1 can be electrically connected to the data line DTL. The source region, active region, and drain region of the second transistor T2 can be arranged on the first semiconductor pattern AP1-1. The first semiconductor pattern AP1-1 can be referred to as the switching semiconductor layer.

[0097] The second semiconductor pattern AP2-1 can be electrically connected to the first voltage line VDL. The source, active, and drain regions of the first transistor T1 and the source, active, and drain regions of the fourth transistor T4 can be arranged on the second semiconductor pattern AP2-1. The second semiconductor pattern AP2-1 can be referred to as a driving semiconductor layer or an operation control semiconductor layer.

[0098] The sensing line SSL can be electrically connected to the third semiconductor pattern AP3-1. The source region, active region, and drain region of the third transistor T3 can be arranged on the third semiconductor pattern AP3-1. The third semiconductor pattern AP3-1 can be referred to as the sensing semiconductor layer.

[0099] The semiconductor patterns AP of each pixel PX1, PX2, or PX3 included in the pixel unit PXU can be formed identically or symmetrically. According to some embodiments, the semiconductor patterns AP1-1, AP2-1, and AP3-1 of the first pixel PX1 and the semiconductor patterns AP3-1, AP2-3, and AP3-3 of the third pixel PX3 can be arranged symmetrically with respect to the virtual line.

[0100] A gate insulating layer 113 may be placed on the semiconductor layer 210. The gate insulating layer 113 may include an insulating material. According to some embodiments, the gate insulating layer 113 may include an inorganic insulating layer such as silicon oxide, silicon nitride, silicon nitride, aluminum oxide, etc. According to some embodiments, the gate insulating layer 113 may be patterned into a shape corresponding to the gate electrode 220, but embodiments of this disclosure are not limited thereto, and the gate insulating layer 113 may be formed to cover both the buffer layer 111 and the semiconductor layer 210.

[0101] Gate electrode 220 may be disposed on gate insulating layer 113. Gate electrode 220 may include a second conductive layer comprising a second conductive material. Gate electrode 220 may include a plurality of gate electrode patterns GP spaced apart from each other. Figure 8 As shown, according to some embodiments, the gate electrode 220 may include a first gate electrode pattern GP1-1, a second gate electrode pattern GP2-1, a third gate electrode pattern GP3-1, and a fourth gate electrode pattern GP4-1 spaced apart from each other. Figure 8 In the image, for convenience, the gate electrode pattern GP is shown together with the underlying metal layer BML and the semiconductor pattern AP.

[0102] The first gate electrode pattern GP1-1 may have an isolated shape, and a portion of the first gate electrode pattern GP1-1 may overlap with the first semiconductor pattern AP1-1 located below the first gate electrode pattern GP1-1. The overlapping portion of the first gate electrode pattern GP1-1 (i.e., the portion overlapping with the active region of the semiconductor layer 210) may be used as the gate electrode of the second transistor T2.

[0103] The second gate electrode pattern GP2-1 may have an isolated shape, and a portion of the second gate electrode pattern GP2-1 may overlap with the second semiconductor pattern AP2-1 located below the second gate electrode pattern GP2-1. The portion of the second gate electrode pattern GP2-1 that overlaps with the second semiconductor pattern AP2-1 may serve as the gate electrode of the first transistor T1. The second gate electrode pattern GP2-1 may overlap with the first capacitor electrode CE1-1, which will be described later, to serve as the second capacitor electrode CE2 of the storage capacitor Cst.

[0104] The second semiconductor pattern AP2-1 may overlap with the fourth gate electrode pattern GP4-1 and a portion of the second gate electrode pattern GP2-1. The fourth gate electrode pattern GP4-1 may have an isolated shape, and the portion of the fourth gate electrode pattern GP4-1 that overlaps with the second semiconductor pattern AP2-1 may be used as the gate electrode of the fourth transistor T4.

[0105] The third gate electrode pattern GP3-1 may have an isolated shape, and a portion of the third gate electrode pattern GP3-1 may overlap with the third semiconductor pattern AP3-1 located below the third gate electrode pattern GP3-1. The portion of the third gate electrode pattern GP3-1 that overlaps with the third semiconductor pattern AP3-1 may be used as the gate electrode of the third transistor T3.

[0106] The gate electrode patterns GP of each pixel PX1, PX2, or PX3 included in the pixel unit PXU can be formed identically or symmetrically. According to some embodiments, the gate electrode patterns GP1-1, GP2-1, GP3-1, and GP4-1 of the first pixel PX1 and the gate electrode patterns GP1-3, GP2-3, GP3-3, and GP4-3 of the third pixel PX3 can be arranged symmetrically with respect to the virtual line.

[0107] The gate electrode pattern GP may include a second conductive layer comprising a second conductive material. The second conductive material may include metals, alloys, conductive metal oxides, transparent conductive materials, etc. According to some embodiments, the gate electrode pattern GP may include Ag, Ag-containing alloys, Mo, Mo-containing alloys, Al, Al-containing alloys, AlN, W, WN, Cu, Ni, Cr, CrN, Ti, Ta, Pt, Sc, ITO, IZO, etc. The gate electrode pattern GP may have a multilayer structure; for example, the gate electrode pattern GP may have a two-layer structure comprising a titanium layer with a thickness of 300 Å and a molybdenum layer with a thickness of 2500 Å.

[0108] Interlayer insulating layer 115 may be disposed on buffer layer 111, covering gate electrode 220. Interlayer insulating layer 115 may include inorganic insulating material, organic insulating material, or a combination thereof. Examples of inorganic insulating materials that can be used as interlayer insulating layer 115 may include silicon oxide, silicon nitride, silicon nitride, etc. Examples of organic insulating materials that can be used as interlayer insulating layer 115 may include polyimide, polyamide, acrylic resin, phenolic resin, benzocyclobutene (BCB), etc. Interlayer insulating layer 115 can insulate source electrode 230 and drain electrode 240 from gate electrode 220.

[0109] like Figure 5 As shown, the first contact hole CNT1, the second contact hole CNT2, and the third contact hole CNT3 can be formed by etching portions of the interlayer insulating layer 115 or the buffer layer 111, respectively. The first contact hole CNT1 can electrically connect the lower metal layer BML to the third conductive layer SP, which will be described later, by passing through the interlayer insulating layer 115 and the buffer layer 111. The second contact hole CNT2 can expose the source region of the semiconductor layer 210, and the third contact hole CNT3 can expose the drain region of the semiconductor layer 210.

[0110] The third conductive layer SP may be located on the interlayer insulating layer 115. The third conductive layer SP may include a scan line SCL, an operation control line ECL, a first upper voltage line VDL', a second upper voltage line VSL', a sensing line SSL, a first capacitor electrode CE1-1, a first connection electrode BE1-1, a second connection electrode BE2-1, a third connection electrode BE3-1, a fourth connection electrode BE4, a fifth connection electrode BE5, a sixth connection electrode BE6, and a seventh connection electrode BE7. The third conductive layer SP may include the source electrode 230 and the drain electrode 240 of the thin-film transistor TFT.

[0111] The scan line SCL can partially overlap with the first gate electrode pattern GP1-1 and can be electrically connected to the first gate electrode pattern GP1-1 via a contact hole. That is, the scan line SCL can be connected to the gate electrode of the second transistor T2.

[0112] The operation control line ECL can partially overlap with the fourth gate electrode pattern GP4-1 and can be electrically connected to the fourth gate electrode pattern GP4-1 via a contact hole. That is, the operation control line ECL can be connected to the gate electrode of the fourth transistor T4.

[0113] The first upper voltage line VDL' may partially overlap with the first voltage line VDL and may be electrically connected to the first voltage line VDL via a contact hole. The first upper voltage line VDL' may partially overlap with the second semiconductor pattern AP2-1 and may be electrically connected to the fourth transistor T4 via a contact hole.

[0114] The second upper voltage line VSL' may partially overlap with the second voltage line VSL and may be electrically connected to the second voltage line VSL via a contact hole. The sensing line SSL may partially overlap with the third semiconductor pattern AP3-1 and may be electrically connected to the third transistor T3 via a contact hole.

[0115] The first capacitor electrode CE1-1 may have an isolated shape and may be located on the first lower capacitor electrode BML1 and the second gate electrode pattern GP2-1. The first capacitor electrode CE1-1 may form a storage capacitor Cst together with the second capacitor electrode CE2.

[0116] The first capacitor electrode CE1-1 can be electrically connected via a contact hole CNT to a first lower capacitor electrode BML1 located below the first capacitor electrode CE1-1. In this case, the first lower capacitor electrode BML1 can be used together with the first capacitor electrode CE1-1 as the capacitor electrode of the storage capacitor Cst. The first capacitor electrode CE1-1 can partially overlap with the second semiconductor pattern AP2-1 located below the first capacitor electrode CE1-1, and can be electrically connected via a contact hole to the first transistor T1.

[0117] The first connecting electrode BE1-1, the second connecting electrode BE2-1, and the third connecting electrode BE3-1 can be arranged in each of the first pixel PX1, the second pixel PX2, and the third pixel PX3. The first to third connecting electrodes of each pixel can be formed identically or symmetrically. According to some embodiments, the first connecting electrodes BE1-1, BE2-1, and BE3-1 of the first pixel PX1 and the first connecting electrodes BE1-3, BE2-3, and BE3-3 of the third pixel PX3 can be arranged symmetrically with respect to the virtual line. The fourth connecting electrode BE4, the fifth connecting electrode BE5, the sixth connecting electrode BE6, and the seventh connecting electrode BE7 can be arranged in each pixel unit PXU.

[0118] One side of the first connecting electrode BE1-1 can be connected to the first semiconductor pattern AP1-1 via the contact hole CNT. The other side of the first connecting electrode BE1-1 can be connected to the second gate electrode pattern GP2-1 via the contact hole CNT. The first connecting electrode BE1-1 can be understood as serving to electrically connect the first transistor T1 to the first node N1 of the second transistor T2 (see...). Figure 3 The role of ).

[0119] One side of the second connection electrode BE2-1 can be connected to the data line DTL1 via the contact hole CNT, and the other side of the second connection electrode BE2-1 can be connected to the first semiconductor pattern AP1-1 via the contact hole CNT. The second connection electrode BE2-1 can electrically connect the data line DTL1 to the second transistor T2.

[0120] One side of the third connecting electrode BE3-1 can be connected to the lower capacitor electrode BML1 via the contact hole CNT, and the other side of the third connecting electrode BE3-1 can be connected to the third semiconductor pattern AP3-1 via the contact hole CNT. The third connecting electrode BE3-1 can be understood as serving to electrically connect the third transistor T3 to the second node N2 of the storage capacitor Cst (see...). Figure 3 The role of ).

[0121] The fourth connecting electrode BE4 and the fifth connecting electrode BE5 may each have an isolated shape and may have a selected length in the second direction DR2. The fourth connecting electrode BE4 and the fifth connecting electrode BE5 may completely or partially overlap with the second voltage line VSL and may be electrically connected to the second voltage line VSL via a contact hole CNT. The fourth connecting electrode BE4 and the fifth connecting electrode BE5 may be spaced apart from each other in the second direction DR2. An operation control line ECL or a first upper voltage line VDL' may be arranged between the fourth connecting electrode BE4 and the fifth connecting electrode BE5.

[0122] The sixth connecting electrode BE6 can extend along the first direction DR1 and overlap with the first pixel PX1, the second pixel PX2, and the third pixel PX3. One side of the sixth connecting electrode BE6 can be electrically connected to the initialization voltage line VIL via the contact hole CNT. The sixth connecting electrode BE6 can be electrically connected to the third gate electrode pattern GP3-1 of each pixel PX1, PX2, or PX3 via the contact hole CNT. The sixth connecting electrode BE6 can electrically connect the initialization voltage line VIL to the third transistor T3. The sixth connecting electrode BE6 can be arranged to avoid overlap of the light-emitting areas EA1, EA2, and EA3 of each pixel PX1, PX2, and PX3.

[0123] The seventh connecting electrode BE7 may have an isolated shape and may have a selected length in the second direction DR2. The seventh connecting electrode BE7 may completely or partially overlap with the first voltage line VDL and may be electrically connected to the first voltage line VDL via the contact hole CNT.

[0124] The third conductive layer SP may include a third conductive material. The third conductive material may include metals, alloys, conductive metal oxides, transparent conductive materials, etc. According to some embodiments, the gate electrode pattern GP may include Ag, Ag-containing alloys, Mo, Mo-containing alloys, Al, Al-containing alloys, AlN, W, WN, Cu, Ni, Cr, CrN, Ti, Ta, Pt, Sc, ITO, IZO, etc. According to some embodiments, the third conductive layer SP may have a multilayer structure including a titanium layer with a thickness of 700 Å, an aluminum layer with a thickness of 6000 Å, and a titanium layer with a thickness of 300 Å. This third conductive layer SP may also be referred to as a source / drain layer.

[0125] The first insulating layer 117 may cover the third conductive layer SP and may be located on the interlayer insulating layer 115. The first insulating layer 117 may include an insulating material. According to some embodiments, the gate insulating layer 113 may include an inorganic insulating material such as silicon oxide, silicon nitride, silicon nitride, aluminum oxide, etc. The first insulating layer 117 may include a material with a stronger bonding strength to the third conductive layer SP compared to the second insulating layer 118 described later.

[0126] A via OP3 exposing a portion of the source electrode 230 or drain electrode 240 may be formed in the first insulating layer 117. The via OP3 may overlap with the second contact hole CNT2 of the source electrode 230, but embodiments according to this disclosure are not limited thereto.

[0127] The second insulating layer 118 may be located on the first insulating layer 117. The second insulating layer 118 may include an insulating material different from the insulating material of the first insulating layer 117. According to some embodiments, the second insulating layer 118 may include an organic insulating material. As specific examples, the second insulating layer 118 may include photoresist, benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), polymethyl methacrylate (PMMA), polystyrene, phenolic polymer derivatives, acrylate polymers, imide polymers, aryl ether polymers, amide polymers, fluorinated polymers, p-xylene polymers, vinyl alcohol polymers, mixtures thereof, etc. According to some embodiments, the second insulating layer 118 forms a planarization layer, which may include a polyimide layer with a thickness of 1.6 micrometers (μm) (or approximately 1.6 μm).

[0128] A first via OP1 and a second via OP2, spaced apart from each other, can be formed in the second insulating layer 118. The first via OP1 can be arranged to overlap with the through-hole OP3 of the first insulating layer 117 and can expose a portion of the source electrode 230 or the drain electrode 240 of the thin-film transistor TFT.

[0129] The width W1 of the first via OP1 can be equal to or less than the width W3 of the via OP3. In this way, the first via OP1 can expose a portion of the source electrode 230 or drain electrode 240 of the thin-film transistor TFT without exposing the second insulating layer 118. However, the invention is not limited thereto, and the width W1 of the first via OP1 can be formed to be greater than the width W3 of the via OP3, such that the first via OP1 can expose a portion of the second insulating layer 118. In this case, the width W1 of the first via OP1 can have a value selected within a range not exceeding twice the width W3 of the via OP3.

[0130] Through-hole OP3 and first via OP1 can be formed for each pixel PX1, PX2, or PX3, and can be used to connect the pixel electrode 310 of each pixel to the source electrode 230 or drain electrode 240 of the thin-film transistor TFT. See also Figure 4 The pixel electrode 310 may include a first pixel electrode 310R corresponding to a first pixel PX1 that can emit red light, a second pixel electrode 310G corresponding to a second pixel PX2 that can emit green light, and a third pixel electrode 310B corresponding to a third pixel PX3 that can emit blue light.

[0131] like Figure 5As shown, when the width W1 of the first via OP1 is formed to be small enough to correspond to the size of the width W3 of the through hole OP3, the edges of the first via OP1 and the edges of the through hole OP3 may overlap or be too close to each other, making it difficult to identify the edge of the first via OP1 with a measuring device.

[0132] Conversely, according to embodiments of this disclosure, a second via OP2 spaced apart from the first via OP1 can be formed in the second insulating layer 118 to facilitate measurement using a measuring device, thereby obtaining a measurement result corresponding to the measurement value of the first via OP1 through the second via OP2.

[0133] The second via OP2 may not overlap with the through hole OP3 of the first insulating layer 117. The second via OP2 can expose the top surface of the first insulating layer 117 by not overlapping with the through hole OP3. The width W2 of the second via OP2 may be equal to the width W1 of the first via OP1, but the embodiments of this disclosure are not limited thereto.

[0134] The second via OP2 can be produced using the same photoresist process with the same mask as the first via OP1. Since the second via OP2 undergoes the same photoresist process as the first via OP1, it can include process errors within the same range as the first via OP1. As a result, even if the width W2 of the second via OP2 is formed differently from the width W1 of the first via OP1, the measured value of the first via OP1 can be accurately estimated based on the measured value of the second via OP2. However, to improve the design freedom of the display device 1, the width W2 of the second via OP2 can be formed to be equal to or smaller than the width W1 of the first via OP1.

[0135] The position of the second via OP2 is not particularly restricted as long as it does not overlap with the through-hole OP3. According to some embodiments, for ease of measurement, the second via OP2 can be arranged to overlap with the first voltage line VDL, the second voltage line VSL, or the initialization voltage line VIL constituting the first conductive layer. As another example, the second via OP2 can be arranged to overlap with the sixth connection electrode BE6 constituting the third conductive layer SP, such that the second via OP2 does not overlap with the light-emitting area of ​​each pixel.

[0136] According to some embodiments, the second via OP2 can be formed to avoid overlapping with the pixel electrode 310. In this case, the pixel electrode 310 may not be bent by the second via OP2.

[0137] The number of second vias OP2 is not particularly limited. Multiple second vias OP2 can be formed, but the embodiments of this disclosure are not limited thereto. According to some embodiments, a selected number of second vias OP2 can be formed for each pixel unit PXU or for each pixel PX. In another example, in the process of forming the first via OP1 and the second via OP2 in the second insulating layer 118, one second via OP2 can be formed throughout the entire second insulating layer 118.

[0138] The light-emitting diode (LD) may be located on the second insulating layer 118. According to some embodiments, the LD may be an organic light-emitting diode (OLED). The LD may include a pixel electrode 310, an intermediate layer 320 including a light-emitting layer, and a counter electrode 330.

[0139] The pixel electrode 310 can be a (semi-)transmissive electrode or a reflective electrode. According to some embodiments, the pixel electrode 310 may include a reflective layer comprising Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, and their compounds, and a transparent or semi-transparent electrode layer located on the reflective layer. The transparent or semi-transparent electrode layer may include at least one selected from the group consisting of ITO, IZO, zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide, and aluminum zinc oxide (AZO). According to some embodiments, the pixel electrode 310 may have a three-layer structure of ITO / Ag / ITO.

[0140] The pixel defining film 119 can be placed on the second insulating layer 118. The pixel defining film 119 can prevent or reduce arcing and other phenomena at the edge of the pixel electrode 310 by increasing the distance between the edge of the pixel electrode 310 and the counter electrode 330 above the pixel electrode 310. The pixel defining film 119 can be formed from one or more organic insulating materials selected from the group consisting of polyimide, polyamide, acrylic resin, benzocyclobutene, and phenolic resin using methods such as spin coating.

[0141] At least a portion of the intermediate layer 320 of the light-emitting diode (LD) may be located within an opening formed by the pixel defining film 119. The light-emitting region EA of the LD may be defined by the opening.

[0142] The intermediate layer 320 may include a light-emitting layer. The light-emitting layer may include an organic material containing a fluorescent or phosphorescent material that emits red, green, blue, or white light. The light-emitting layer may be a low-molecular-weight organic material or a high-molecular-weight organic material, and functional layers such as hole transport layer (HTL), hole injection layer (HIL), electron transport layer (ETL), and electron injection layer (EIL) may be selectively arranged below and above the light-emitting layer.

[0143] The light-emitting layer can have a patterned shape corresponding to each of the pixel electrodes 310. The layers included in the intermediate layer 320, other than the light-emitting layer, can be modified in various ways, such as being formed across multiple pixel electrodes 310 as a whole.

[0144] The counter electrode 330 can be a light-transmitting electrode or a reflective electrode. According to some embodiments, the counter electrode 330 can be a transparent or translucent electrode and can include a thin metal film with a low work function comprising Li, Ca, LiF, Al, Ag, Mg, and their compounds. The counter electrode 330 may also include a transparent conductive oxide (TCO) film such as ITO, IZO, ZnO, or In2O3 located on the metal film. The counter electrode 330 can be integrally formed over the entire display area DA and placed on top of the intermediate layer 320 and the pixel defining film 119.

[0145] The embodiments of this disclosure can achieve precise control over the formation of the first via OP1 by simultaneously forming a second via OP2 that is spaced apart from the first via OP1 and does not overlap with the through hole OP3 during the process of forming the first via OP1. The embodiments of this disclosure can improve the aperture ratio of the light-emitting region EA of each pixel PX by reducing the aperture ratio of the first via OP1. The embodiments of this disclosure can improve the design freedom of the display device 1 by achieving accurate measurement while forming the small first via OP1.

[0146] In the following, a method of manufacturing a display device according to some embodiments of the present disclosure will be described, and any descriptions that overlap with the foregoing description will be omitted.

[0147] A lower metal layer BML can be formed on a substrate SUB. The lower metal layer BML can be formed by applying a first conductive material to the substrate SUB and then patterning a first voltage line VDL, a second voltage line VSL, an initialization voltage line VIL, and a data line DTL included in the lower metal layer BML. The lower metal layer BML can be formed by photolithography, and embodiments according to this disclosure are not limited thereto.

[0148] A buffer layer 111 can be formed on the substrate SUB to cover the underlying metal layer BML, and then a semiconductor layer 210 can be formed on the buffer layer 111. The semiconductor layer 210 can be formed by forming a silicon layer on the buffer layer 111 and then etching the silicon layer using photolithography or the like.

[0149] A gate insulating layer 113 can be formed on the semiconductor layer 210, and a gate electrode 220 can be formed on the gate insulating layer 113. The gate electrode 220 can be formed by applying a second conductive material to the substrate SUB and then patterning a plurality of gate electrode patterns GP that partially overlap with the semiconductor layer 210.

[0150] Ions can be partially implanted into the semiconductor layer 210 to form source and drain regions. The portion of the semiconductor layer 210 overlapping with the gate electrode 220 can remain undoped, thus forming an active region. The active region can be formed between the source and drain regions, and the ions can be N-type or P-type impurities. The ion-doped portions of the semiconductor layer 210 can have increased conductivity and thus possess conductor properties, thereby allowing the formation of source and drain regions.

[0151] An interlayer insulating layer 115 may be formed on the gate electrode 220. The interlayer insulating layer 115 may be formed to cover the entirety of the buffer layer 111, the semiconductor layer 210, and the gate electrode 220. The interlayer insulating layer 115 may insulate the source electrode 230 and the drain electrode 240 from the gate electrode 220.

[0152] The first contact hole CNT1, the second contact hole CNT2, and the third contact hole CNT3 can be formed by etching portions of the interlayer insulating layer 115 and the buffer layer 111, respectively. The second contact hole CNT2 can expose the source region of the semiconductor layer 210, and the third contact hole CNT3 can expose the drain region of the semiconductor layer 210.

[0153] A source electrode 230 and a drain electrode 240 may be formed on the interlayer insulating layer 115. The source electrode 230 may be connected to the source region of the semiconductor layer 210, and the drain electrode 240 may be connected to the drain region of the semiconductor layer 210. Each of the source electrode 230 and the drain electrode 240 may include a third conductive material. The semiconductor layer 210, the gate electrode 220, the source electrode 230, and the drain electrode 240 may form a thin-film transistor (TFT).

[0154] A first insulating layer 117 can be formed on the source electrode 230 and the drain electrode 240. The first insulating layer 117 can be formed by applying an inorganic insulating material to the interlayer insulating layer 115 and then etching the via OP3 using a first mask. The via OP3 can expose a portion of the source electrode 230 or the drain electrode 240.

[0155] A second insulating layer 118 can be formed on the first insulating layer 117. The second insulating layer 118 can be formed by applying an organic insulating material to the first insulating layer 117 and then etching the first via OP1 and the second via OP2 using a second mask. The first via OP1 may overlap with the through-hole OP3, and the second via OP2 may not overlap with the through-hole OP3.

[0156] The pixel electrode 310 can contact the source electrode 230 or the drain electrode 240 via a via OP3 formed by removing a portion of the first insulating layer 117 and a first via OP1 formed by removing a portion of the second insulating layer 118.

[0157] A pixel defining film 119 may be formed on the second insulating layer 118, and an intermediate layer 320 may be formed on the pixel electrode 310. An opening may be formed in the pixel defining film 119 to expose a portion of the pixel electrode 310. A counter electrode 330 may be formed on the intermediate layer 320 and the pixel defining film 119. The counter electrode 330 may include a common electrode of the display device 1. The pixel electrode 310, the intermediate layer 320, and the counter electrode 330 may form a light-emitting diode (LED). The LED may emit light based on a driving current transmitted from a thin-film transistor (TFT).

[0158] The display device 1 according to some embodiments can be applied to various electronic devices. The electronic device according to some embodiments may include the display device 1 described above, and may also include modules or devices having additional functions besides the display device 1.

[0159] Figure 10 This is a block diagram of an electronic device 10 according to some embodiments of the present disclosure.

[0160] refer to Figure 10 According to some embodiments, the electronic device 10 may include a display module 11, a processor 12, a memory 13, and a power module 14.

[0161] The processor 12 may include at least one of a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0162] The memory 13 can store data information required for the operation of the processor 12 or the display module 11. When the processor 12 executes the application stored in the memory 13, image data signals and / or input control signals can be sent to the display module 11, and the display module 11 can process the received signals and output image information through the display screen.

[0163] The power module 14 may include a power supply module such as a power adapter, a battery device, etc., and a power conversion module that converts the power supplied by the power supply module to generate the power required for the operation of the electronic device 10.

[0164] At least one of the components of the electronic device 10 may be included in the display device according to the embodiments described above. Some of the individual modules that are functionally included in modules may be included in the display device, and other modules may be provided separately from the display device. According to some embodiments, the display device may include a display module 11, and the processor 12, memory 13, and power module 14 may be provided in the form of other devices in the electronic device 10 besides the display device.

[0165] Figure 11 Schematic diagrams of electronic devices according to various embodiments are shown.

[0166] refer to Figure 11 The various electronic devices that utilize the display device according to the embodiments may include not only image display electronic devices such as smartphones 10_1a, tablet PCs 10_1b, laptop computers 10_1c, TVs 10_1d, and desktop monitors 10_1e, but also wearable electronic devices including display modules such as smart glasses 10_2a, head-mounted displays 10_2b, and smartwatches 10_2c, as well as vehicle electronic devices 10_3 including display modules such as vehicle dashboards, center consoles, central information displays (CIDs) arranged on the dashboard, and interior mirror displays.

[0167] The display device and electronic device according to the embodiments of the present disclosure can accurately measure the size of the via overlapping with the contact hole of the insulating layer and form vias with smaller size, thereby relatively improving the aperture ratio of the pixel.

[0168] Furthermore, the method for manufacturing a display device according to embodiments of the present disclosure can reduce the defect rate caused by vias by accurately measuring the size of vias that overlap with the contact holes of the insulating layer.

[0169] However, the scope of the embodiments according to this disclosure is not limited to the foregoing effects and can be extended in various ways without departing from the spirit and scope of the embodiments according to this disclosure.

[0170] While some aspects of this disclosure have been described with reference to the embodiments illustrated in the accompanying drawings, those skilled in the art will understand that various modifications and changes can be made to the embodiments without departing from the spirit and scope of the embodiments according to this disclosure. Therefore, the true technical scope of the embodiments according to this disclosure should be defined by the appended claims and their equivalents.

Claims

1. A display device, comprising: Substrate, including the display area; Thin-film transistor, on the substrate, in the display area; A first insulating layer is provided on the thin-film transistor and includes a via that exposes the source or drain electrode of the thin-film transistor. A second insulating layer is provided on the first insulating layer and includes a first via and a second via spaced apart from each other. as well as The pixel electrode is located on the second insulating layer and is electrically connected to the thin-film transistor via the via. Wherein, the first via overlaps with the through hole, and the second via does not overlap with the through hole.

2. The display device according to claim 1, further comprising: An initial voltage line extends on the substrate in a first direction. The second via overlaps with the initialization voltage line.

3. The display device according to claim 1, wherein, The second via does not overlap with the pixel electrode.

4. The display device according to claim 1, wherein, The second via does not overlap with the source electrode or the drain electrode exposed by the via.

5. The display device according to claim 1, wherein, The width of the second via is less than or equal to the width of the first via.

6. The display device according to claim 1, wherein, The width of the first via is less than or equal to the width of the through hole.

7. The display device according to claim 1, wherein, The width of the first via is at most twice the width of the through hole.

8. The display device according to claim 1, wherein, The source electrode or the drain electrode of the thin-film transistor comprises copper.

9. The display device according to claim 1, wherein, The second via exposes a portion of the first insulating layer.

10. The display device according to claim 1, wherein, The second via is formed in multiple ways.

Images