Display panel and display device

Abstract

This application provides a display panel and a display device. The display panel has a display area and a peripheral area, the peripheral area including a driving circuit area and an edge area located outside it. The display panel includes a substrate, an array functional layer, a display functional layer, a first dam, and an encapsulation layer. The array functional layer includes a first insulating layer, a first conductive layer, and a second insulating layer, with multiple through slots formed on the second insulating layer. The display functional layer includes a first electrode layer and a second electrode layer located on the side of the array functional layer away from the substrate. The second electrode layer is located in both the display area and the peripheral area. The encapsulation layer covers the first dam and encapsulates the edge of the second electrode layer. The first electrode layer contacts the first conductive layer in the edge area and is electrically contacted with the first conductive layer through multiple through slots in the driving circuit area. This application optimizes the static discharge path during film manufacturing and can effectively reduce the bezel size of the display panel.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0002] OLED (Organic Light-Emitting Diode) is a self-emissive display technology based on organic materials. Its structure is extremely thin and can be made into curved, foldable, and rollable forms. It has a fast display response speed and almost no dynamic ghosting. It also maintains brightness and color accuracy at large viewing angles.

[0003] However, the product structure and manufacturing process of OLED display panels still need improvement. Summary of the Invention

[0004] This application provides a display panel, a display device, and a method for manufacturing the display panel, aiming to improve electrostatic damage and reduce bezel size.

[0005] An embodiment of the first aspect of this application provides a display panel; the display panel has a display area and a peripheral area, the peripheral area including a driving circuit area and an edge area located outside thereto. The display panel includes a substrate, an array functional layer, a display functional layer, a first dam, and an encapsulation layer.

[0006] A substrate is located in the display area and the peripheral area. An array functional layer is located on one side of the substrate in the display area and the peripheral area. The array functional layer has a gate driving circuit structure located in the driving circuit area. The array functional layer includes a first insulating layer on one side of the substrate, a first conductive layer on the side of the first insulating layer away from the substrate, and a second insulating layer on the side of the first conductive layer away from the substrate and located in the driving circuit area. A plurality of through slots are formed on the second insulating layer. The display functional layer includes a first electrode layer on the side of the array functional layer away from the substrate, a light-emitting functional layer on the side of the first electrode layer away from the substrate and located in the display area, and a second electrode layer on the side of the light-emitting functional layer away from the substrate. The second electrode layer is located in the display area and the peripheral area. A first dam is located on the array functional layer in the edge area. An encapsulation layer is located on the side of the display functional layer away from the substrate and in the display area and the peripheral area. The encapsulation layer covers the first dam and the edge of the second electrode layer. The encapsulation layer includes an organic encapsulation layer. The edge of the first insulating layer is located at the boundary between the driving circuit region and the edge region. The first conductive layer is located in the driving circuit region and the edge region. The edge of the second electrode layer is at least partially located in the driving circuit region. The second insulating layer does not cover or only partially covers the first conductive layer in the edge region. The first electrode layer is in contact with the first conductive layer in the edge region and is in electrical contact with the first conductive layer in the driving circuit region through multiple through slots.

[0007] Furthermore, a touch function layer is provided on the side of the second electrode layer away from the substrate.

[0008] The first insulating layer includes an organic layer, and the first conductive layer has a first vent hole. The projection of the first vent hole on the substrate does not overlap with the projection of the through groove on the substrate.

[0009] Furthermore, the multiple through slots on the second insulating layer are connected to form a mesh, and the position of the first vent hole corresponds to the grid position on the mesh.

[0010] Furthermore, the first conductive layer includes a first sublayer, a second sublayer, and a third sublayer stacked together, the second sublayer being made of aluminum, and the second insulating layer filling the first vent hole and covering the edge of the first vent hole.

[0011] Furthermore, the second insulating layer includes an organic layer, the first electrode layer has a second vent hole in the driving circuit area, the first electrode layer includes a fourth sub-layer, a fifth sub-layer and a sixth sub-layer stacked together, the material of the fifth sub-layer includes silver, and the edge of the second vent hole is covered with a sealing structure.

[0012] Preferably, the sealing structure covers the entire second vent.

[0013] Furthermore, a pixel defining layer is provided in the display area and the driving circuit area. The pixel defining layer is located on the side of the array functional layer away from the substrate. The pixel defining layer defines multiple pixel openings in the display area. The first electrode layer is located between the pixel defining layer and the array functional layer. The light emitting functional layer is located on the side of the pixel defining layer away from the substrate and is at least partially located in the pixel openings. The sealing structure is of the same layer and material as the pixel defining layer.

[0014] Furthermore, the array functional layer also includes a second conductive layer located between the first conductive layer and the substrate. The second conductive layer is located in the driving circuit region and the edge region. At least a portion of the second conductive layer located in the driving circuit region is used to form a gate driving circuit structure, and the second conductive layer located in the edge region is in contact with the first conductive layer.

[0015] Furthermore, an overflow groove is formed on the side of the first dam facing the display area in the edge region, and the distance between the edge of the second electrode layer and the first dam is greater than the width of the overflow groove.

[0016] Preferably, the entire edge of the second electrode layer is located in the driving circuit area.

[0017] Furthermore, a first optical functional layer and a second optical functional layer are sequentially disposed on the side of the second electrode layer in the display area and the peripheral area away from the substrate. The orthographic projection of the edge of the second electrode layer in the driving circuit area onto the substrate is located within the orthographic projection of the first optical functional layer onto the substrate, and the orthographic projection of the edge of the first optical functional layer onto the substrate is located within the orthographic projection of the second optical functional layer onto the substrate.

[0018] This application also provides a display device, including the aforementioned display panel.

[0019] The display panel and display device provided in this application embodiment, by opening a through groove in the second insulating layer, allow the first electrode layer to contact the first conductive layer in the edge area and to make electrical contact with the first conductive layer in the driving circuit area through the through groove. On the one hand, this optimizes the static discharge path during the film manufacturing process and avoids product damage caused by a long static discharge path and high resistance. On the other hand, the edge of the second electrode layer does not need to extend to the edge area to reduce the resistance of the static discharge path. Correspondingly, the distance between the encapsulation layer covering the edge of the second electrode layer and the first dam to the driving circuit area can be reduced accordingly, thereby effectively reducing the bezel size of the display panel. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments or exemplary embodiments of this application, the drawings used in the description of the embodiments or exemplary embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a schematic diagram of an overall display panel; Figure 2 A cross-sectional view of a display panel corresponding to the peripheral area, provided for some embodiments of this application; Figure 3 A cross-sectional view of a display panel corresponding to the display area, provided for some embodiments of this application; Figure 4 A top view of a portion of the film layer corresponding to the display area of ​​a display panel, provided in some embodiments of this application; Figure 5 A top view of a portion of the film layer corresponding to the display area of ​​another display panel provided in some embodiments of this application; Figure 6 A schematic diagram of the film structure of the first conductive layer in a display panel provided in some embodiments of this application; Figure 7 This is a schematic diagram of the film structure of the first electrode layer in a display panel, provided for some embodiments of this application.

[0022] Explanation of reference numerals in the attached figures: Display area AA, peripheral area NA, driving circuit area NA1, edge area NA2, substrate 20, array functional layer 300, gate driving circuit structure 30, first insulating layer 31, first conductive layer 32, first sub-layer 321, second sub-layer 322, third sub-layer 323, first vent hole 320, second insulating layer 33, through groove 330, island structure 331, second conductive layer 35, display functional layer 50, first electrode layer 51, fourth sub-layer 511, and so on. Fifth sublayer 512, sixth sublayer 513, second vent 510, light-emitting functional layer 52, second electrode layer 53, pixel limiting layer 61, pixel opening 610, sealing structure 66, encapsulation layer 65, organic encapsulation layer 651, first inorganic encapsulation layer 652, second inorganic encapsulation layer 653, first dam 81, second dam 82, touch functional layer 83, first optical functional layer 84, second optical functional layer 85, overflow groove 87, pixel circuit 88, support pillar 89 Detailed Implementation To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings. Preferred embodiments of this application are shown in the drawings. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of this application.

[0023] It should be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, this does not indicate any order, quantity, or importance, but is merely used to distinguish different components. These terms are used only to distinguish one element from another. For example, without departing from the scope of this application, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. Words such as “comprising” or “including” mean that the element or object preceding the word covers the element or object listed after the word and its equivalents, without excluding other elements or objects.

[0024] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0025] The following is in conjunction with the attached figure. Figures 1-7 The technical solution of this application will be described in detail.

[0026] In the manufacturing process of OLED and other display panels, static electricity is easily generated in many processes, especially in some vapor deposition processes, and static discharge is a critical issue. After in-depth analysis, the inventors of this application discovered the electrostatic breakdown problem found in the fabrication of the light-emitting layer, the second electrode, and subsequent film layers. The cause is as follows: the second electrode needs to extend to the bottom of the overflow tank and overlap with the first electrode. To cover the edge of the second electrode layer, the encapsulation layer and the overflow tank need a large outward extension dimension. This results in a long static discharge path and high resistance, preventing timely static discharge and causing product damage. Furthermore, this structure limits further narrowing of the panel bezel, which is detrimental to the development trend of display panel technology.

[0027] To address the aforementioned problems, firstly, some embodiments of this application provide a display panel; please refer to... Figure 1 , Figure 2 , Figure 3 and Figure 4 The display panel has a display area AA and a peripheral area NA. The peripheral area NA includes a driving circuit area NA1 and an edge area NA2 located outside the driving circuit area NA1. The display panel includes a substrate 20, an array functional layer 300, a display functional layer 50, a first dam 81, and an encapsulation layer 65.

[0028] The substrate 20 is located in the display area AA and the peripheral area NA. An array functional layer 300 is located on one side of the substrate 20 in the display area AA and the peripheral area NA. The array functional layer 300 forms a gate driving circuit structure 30 located in the driving circuit area NA1. The array functional layer 300 includes a first insulating layer 31 on one side of the substrate 20, a first conductive layer 32 on the side of the first insulating layer 31 away from the substrate 20, and a second insulating layer 33 on the side of the first conductive layer 32 away from the substrate 20 and located in the driving circuit area NA1. A plurality of through slots 330 are formed on the second insulating layer 33. The display functional layer 50 includes a first electrode layer 51 on the side of the array functional layer 300 away from the substrate 20, a light-emitting functional layer 52 on the side of the first electrode layer 51 away from the substrate 20 and located in the display area AA, and a second electrode layer 53 on the side of the light-emitting functional layer 52 away from the substrate 20. The second electrode layer 53 is located in the display area AA and the peripheral area NA. A first dam 81 is located on the array functional layer 300 in the edge area NA2. The encapsulation layer 65 is located on the side of the display functional layer 50 away from the substrate 20 and is located in the display area AA and the peripheral area NA. The encapsulation layer 65 covers the first dam 81 and encapsulates the edge of the second electrode layer 53. The encapsulation layer 65 includes an organic encapsulation layer 651. The edge of the first insulating layer 31 is located at the boundary between the driving circuit area NA1 and the edge area NA2. The first conductive layer 32 is located in the driving circuit area NA1 and the edge area NA2. The edge of the second electrode layer 53 is at least partially located in the driving circuit area NA1. The second insulating layer 33 does not cover or only partially covers the first conductive layer 32 in the edge area NA2. The first electrode layer 51 is in contact with the first conductive layer 32 in the edge area NA2 and is in electrical contact with the first conductive layer 32 in the driving circuit area NA1 through multiple through-slots 330.

[0029] In some embodiments of this application, the display panel has a through groove 330 formed on the second insulating layer 33. The first electrode layer 51 contacts the first conductive layer 32 in the edge region NA2 and is electrically contacted with the first conductive layer 32 in the driving circuit region NA1 through the through groove 330. On the one hand, this optimizes the static discharge path of the film material and the mask during the film manufacturing process, avoiding the problem of product damage caused by the difficulty in timely release of static electricity due to the long static discharge path and high resistance. On the other hand, the edge of the second electrode layer 53 does not need to extend to the edge region NA2 to reduce the resistance of the static discharge path. Correspondingly, the boundary of the encapsulation layer 65 covering the edge of the second electrode layer 53 and the distance from the first dam 81 to the driving circuit region NA1 can be reduced accordingly, thereby effectively reducing the bezel size of the display panel.

[0030] It should be noted that, as a preferred embodiment, the first insulating layer 31 can be a planarization layer formed of organic material, and may be referred to as the first planarization layer. Similarly, the second insulating layer 33 can be a planarization layer formed of organic material, and may be referred to as the second planarization layer.

[0031] Please refer to Figure 4 In some embodiments of the display panel provided in this application, the through slot 330 is in the shape of a hole. Specifically, the hole-shaped outline of the through slot 330 can be rectangular (as shown in the figure), or it can be circular, elliptical, oblong, pentagonal, octagonal, etc.

[0032] Please refer to Figure 2 , Figure 3 and Figure 4 In some embodiments of the present application, a touch function layer 83 is provided on the side of the second electrode layer 53 away from the substrate 20; the first insulating layer 31 includes an organic layer; a first vent hole 320 is provided on the first conductive layer 32; the projection of the first vent hole 320 on the substrate 20 does not overlap with the projection of the through groove 330 on the substrate 20.

[0033] In some embodiments of this application, a touch function layer 83 is provided on the side of the second electrode layer 53 away from the substrate 20; the first insulating layer 31 includes an organic layer, and a first vent hole 320 is formed on the first conductive layer 32. The projection of the first vent hole 320 on the substrate 20 does not overlap with the projection of the through groove 330 on the substrate 20. On the one hand, when the first insulating layer 31 includes an organic layer, the first vent hole 320 allows the first insulating layer 31 to discharge the gas released by the first insulating layer 31 in subsequent process steps, so as to prevent gas from being released. Body pressure can cause defects such as film detachment; on the other hand, when the touch function layer 83 is provided on the side of the second electrode layer 53 away from the substrate 20, the projection of the first vent hole 320 on the substrate 20 and the projection of the through groove 330 on the substrate 20 do not overlap, so that the second electrode layer 53 and the first conductive layer 32 can cover each other's holes (first vent hole 320 or through groove 330), thereby avoiding electromagnetic signals from the upper touch function layer 83 and electromagnetic signals from the lower gate drive circuit structure 30, thereby improving the performance of the product.

[0034] It should be noted that the touch function layer 83 may include a mutual capacitance touch structure or a self-capacitance touch structure. Specifically, the mutual capacitance touch structure may include a first touch electrode (such as TX) extending along a first direction and a second touch electrode (RX) extending along a second direction and insulated from the first touch electrode. The second direction intersects with the first direction.

[0035] Please refer to Figure 2 , Figure 3 and Figure 6 In some embodiments of the present application, the first conductive layer 32 includes a first sub-layer 321, a second sub-layer 322 and a third sub-layer 323 stacked together. The material of the second sub-layer 322 includes aluminum. The second insulating layer 33 fills the first vent hole 320 and covers the edge of the first vent hole 320.

[0036] In some embodiments of this application, the display panel includes a first conductive layer 32 comprising a first sub-layer 321, a second sub-layer 322, and a third sub-layer 323 stacked together. The material of the second sub-layer 322 is aluminum. The second insulating layer 33 fills the first vent hole 320 and covers the edge of the first vent hole 320, thereby sealing the exposed edge of the aluminum second sub-layer 322 in the first vent hole 320. This prevents the aluminum in the second sub-layer 322 from contacting and reacting with the etching solution in subsequent etching processes, thus avoiding damage to the first conductive layer 32.

[0037] It should be noted that the materials of the first sub-layer 321 and the third sub-layer 323 of the first conductive layer 32 can be titanium, which can protect the aluminum second sub-layer 322. The second insulating layer 33 can completely cover the first vent 320, and not just the edge of the first vent 320.

[0038] Please refer to Figure 2 , Figure 3 and Figure 7 In some embodiments of the present application, the display panel provided includes a second insulating layer 33 comprising an organic layer, a first electrode layer 51 having a second vent 510 in the driving circuit area NA1, the first electrode layer 51 comprising a fourth sub-layer 511, a fifth sub-layer 512 and a sixth sub-layer 513 stacked together, the material of the fifth sub-layer 512 comprising silver, and a sealing structure 66 at the edge of the second vent 510.

[0039] In some embodiments of the display panel provided in this application, when the second insulating layer 33 includes an organic layer, the first electrode layer 51 has a second vent hole 510 in the driving circuit area NA1, which allows the second insulating layer 33 to release the gas that has been released during subsequent process steps, thus preventing defects such as film detachment caused by gas pressure. On the other hand, when the material of the fifth sub-layer 512 in the first electrode layer 51 includes silver, the sealing structure 66 at the edge of the second vent hole 510 can prevent the silver in the fifth sub-layer 512 from being dissolved in liquid and precipitated at other locations during subsequent etching processes, thus preventing silver particles formed at other locations from causing product defects such as short circuits, thereby improving product yield.

[0040] Please refer to Figure 2 , Figure 3 and Figure 5In some embodiments of this application, the display panel has a display area AA and a peripheral area NA. The peripheral area NA includes a driving circuit area NA1 and an edge area NA2 located outside the driving circuit area NA1. The display panel includes a substrate 20, an array functional layer 300, a display functional layer 50, a first dam 81, and an encapsulation layer 65. The array functional layer 300 is located on one side of the substrate 20, encompassing the display area AA and the peripheral area NA. The array functional layer 300 forms a gate driving circuit structure 30 located in the driving circuit area NA1. The array functional layer 300 includes a first insulating layer 31 on one side of the substrate 20, a first conductive layer 32 on the side of the first insulating layer 31 away from the substrate 20, and a second insulating layer 33 on the side of the first conductive layer 32 away from the substrate 20 and located in the driving circuit area NA1. Multiple through-slots 330 are formed on the second insulating layer 33. The display functional layer 50 includes a first electrode layer 51 on the side of the array functional layer 300 away from the substrate 20, a light-emitting functional layer 52 on the side of the first electrode layer 51 away from the substrate 20 and located in the display area AA, and a second electrode layer 53 on the side of the light-emitting functional layer 52 away from the substrate 20. The second electrode layer 53 is located in both the display area AA and the peripheral area NA. A first dam 81 is located on the array functional layer 300 in the edge area NA2. The encapsulation layer 65 is located on the side of the display functional layer 50 away from the substrate 20 and is situated between the display area AA and the peripheral area NA. The encapsulation layer 65 covers the first dam 81 and encapsulates the edge of the second electrode layer 53. The encapsulation layer 65 includes an organic encapsulation layer 651. The edge of the first insulating layer 31 is located at the boundary between the driving circuit area NA1 and the edge area NA2. The first conductive layer 32 is located between the driving circuit area NA1 and the edge area NA2. The edge of the second electrode layer 53 is at least partially located in the driving circuit area NA1. The second insulating layer 33 does not cover or only partially covers the first conductive layer 32 in the edge area NA2. The first electrode layer 51 contacts the first conductive layer 32 in the edge area NA2 and is electrically contacted with the first conductive layer 32 in the driving circuit area NA1 through multiple through-slots 330. The multiple through-slots 330 on the second insulating layer 33 are interconnected and form a mesh; in other words, the second insulating layer 33 forms multiple island-like structures 331 separated by the interconnected multiple through-slots 330.

[0041] In some embodiments of this application, the display panel has through slots 330 formed on the second insulating layer 33, and multiple through slots 330 are connected to form a mesh. The first electrode layer 51 contacts the first conductive layer 32 in the edge region NA2 and is electrically contacted with the first conductive layer 32 through the through slots 330 in the driving circuit region NA1. On the one hand, the short electrical contact path and large contact area between the first electrode layer 51 and the first conductive layer 32 optimize the static discharge path of the film material and the mask during the film manufacturing process and reduce the contact resistance, avoiding the problem of product damage caused by the long static discharge path and high resistance, which makes it difficult to release static electricity in time. On the other hand, the edge of the second electrode layer 53 does not need to extend to the edge region NA2 to reduce the resistance of the static discharge path. Correspondingly, the boundary of the encapsulation layer 65 covering the edge of the second electrode layer 53 and the distance from the first dam 81 to the driving circuit region NA1 can be reduced accordingly, thereby effectively reducing the bezel size of the display panel.

[0042] Please refer to Figure 2 , Figure 3 , Figure 5 and Figure 7 In some embodiments of the display panel provided in this application, the first conductive layer 32 includes a first sub-layer 321, a second sub-layer 322, and a third sub-layer 323 stacked together (the materials of the first sub-layer 321 and the third sub-layer 323 of the first conductive layer 32 can be titanium), the material of the second sub-layer 322 includes aluminum, and the second insulating layer 33 fills the first vent hole 320 and covers the edge of the first vent hole 320. A plurality of through-slots 330 on the second insulating layer 33 are interconnected to form a mesh; in other words, the second insulating layer 33 forms a plurality of island-like structures 331 separated by the interconnected through-slots 330. The position of the first vent hole 320 corresponds to the grid position on the mesh, and the orthographic projection of the first vent hole 320 on the substrate 20 lies within the orthographic projection of these island-like structures 331 on the substrate 20. That is, the island-like structures on the second insulating layer 33 simultaneously cover the first vent hole 320.

[0043] In some embodiments of this application, the display panel covers the first vent hole 320 with an island-shaped structure 331. On the one hand, this can prevent the second sub-layer 322 from reacting with the etching solution in the subsequent etching process and causing damage to the first conductive layer 32. On the other hand, while covering the first vent hole 320, it can ensure that the first electrode layer 51 and the first conductive layer 32 have a large contact area. This optimizes the static electricity release path on the film material and mask during the film manufacturing process and reduces the contact resistance. It avoids the problem of product damage caused by the long static electricity release path and high resistance, which makes it difficult to release static electricity in time.

[0044] Please refer to Figure 2 , Figure 3 , Figure 5 and Figure 7 In some embodiments of the display panel provided in this application, a plurality of through-slots 330 on the second insulating layer 33 are connected to form a mesh, and the position of the first vent 320 corresponds to the grid position on the mesh. In other words, the second insulating layer 33 forms a plurality of island-like structures 331 separated by a plurality of interconnected through-slots 330. The second insulating layer 33 includes an organic layer, and the first electrode layer 51 has a second vent 510 formed in the driving circuit region NA1. The first electrode layer 51 includes a fourth sub-layer 511, a fifth sub-layer 512, and a sixth sub-layer 513 stacked together. The material of the fifth sub-layer 512 includes silver. A sealing structure 66 covering the edge of the second vent 510 is provided at the second vent 510 of the first electrode layer 51 (i.e., the edge of the second vent 510 is covered by the sealing structure 66; more preferably, the sealing structure 66 covers the entire second vent 510). The orthographic projection of the second vent 510 on the substrate 20 lies within the orthographic projection of these island-like structures 331 on the substrate 20. That is to say, the orthographic projection of the second vent 510 on the substrate 20 and the corresponding orthographic projection of the second vent 510 on the substrate 20 can be located within the orthographic projection of the same island structure 331 on the substrate 20.

[0045] In some embodiments of this application, the display panel is connected in a mesh-like manner by multiple through-slots 330 on the second insulating layer 33. The second insulating layer 33 forms multiple island-like structures 331 separated by the multiple interconnected through-slots 330. The orthographic projection of the second vent hole 510 on the substrate 20 and the orthographic projection of the corresponding second vent hole 510 on the substrate 20 can be located within the orthographic projection of the same island-like structure 331 on the substrate 20. On the one hand, when the material of the fifth sub-layer 512 includes silver, it can prevent silver particles formed at other locations after precipitation in the fifth sub-layer 512 during subsequent etching processes, which could lead to short circuits and other defects. On the other hand, the multiple through-slots 330 connected in a mesh-like manner can ensure a large contact area between the first electrode layer 51 and the first conductive layer 32, optimize the static discharge path of the film material and the mask during film manufacturing, and reduce the contact resistance. This avoids the problem of product damage caused by long static discharge paths and high resistance, which make it difficult to release static electricity in time.

[0046] Please refer to Figure 2 and Figure 3In some embodiments of the present application, a pixel limiting layer 61 is provided in the display area AA and the driving circuit area NA1. The pixel limiting layer 61 is located on the side of the array functional layer 300 away from the substrate 20. The pixel limiting layer 61 defines a plurality of pixel openings 610 in the display area AA. The first electrode layer 51 is located between the pixel limiting layer 61 and the array functional layer 300. The light emitting functional layer 52 is located on the side of the pixel limiting layer 61 away from the substrate 20 and is at least partially located in the pixel openings 610. The sealing structure 66 is of the same layer and material as the pixel limiting layer 61.

[0047] In some embodiments of this application, the display panel is formed simultaneously with the pixel limiting layer 61 because the sealing structure 66 and the pixel limiting layer 61 are made of the same material and layer, which simplifies the manufacturing process and reduces manufacturing costs.

[0048] Please refer to Figure 2 and Figure 3 In some embodiments of the present application, the array functional layer 300 further includes a second conductive layer 35 located between the first conductive layer 32 and the substrate 20. The second conductive layer 35 is located in the driving circuit region NA1 and the edge region NA2. At least a portion of the second conductive layer 35 located in the driving circuit region NA1 is used to form a gate driving circuit structure 30. The second conductive layer 35 located in the edge region NA2 is in contact with the first conductive layer 32.

[0049] In some embodiments of the present application, the display panel utilizes the second conductive layer 35 of the array functional layer 300 located between the first conductive layer 32 and the substrate 20. This allows the second conductive layer 35 to release static electricity and transmit ELVSS signals together with the first conductive layer 32, thereby further reducing the resistance on the static discharge path and better preventing static damage.

[0050] Please refer to Figure 2 and Figure 3 In some embodiments of this application, the display panel has a display area AA and a peripheral area NA. The peripheral area NA includes a driving circuit area NA1 and an edge area NA2 located outside the driving circuit area NA1. The display panel includes a substrate 20, an array functional layer 300, a display functional layer 50, a first dam 81, and an encapsulation layer 65.

[0051] The substrate 20 is located in the display area AA and the peripheral area NA.

[0052] The array functional layer 300 is located on one side of the substrate 20, which is the display area AA and the peripheral area NA. The array functional layer 300 forms a gate driving circuit structure 30 located in the driving circuit area NA1. The array functional layer 300 includes a first insulating layer 31 located on one side of the substrate 20, a first conductive layer 32 located on the side of the first insulating layer 31 away from the substrate 20, and a second insulating layer 33 located on the side of the first conductive layer 32 away from the substrate 20 and located in the driving circuit area NA1. A plurality of through slots 330 are formed on the second insulating layer 33.

[0053] The display functional layer 50 includes a first electrode layer 51 located on the side of the array functional layer 300 away from the substrate 20, a light-emitting functional layer 52 located on the side of the first electrode layer 51 away from the substrate 20 and located in the display area AA, and a second electrode layer 53 located on the side of the light-emitting functional layer 52 away from the substrate 20. The second electrode layer 53 is located in the display area AA and the peripheral area NA.

[0054] The first dam 81 is located on the array functional layer 300 of the edge region NA2. At the edge region NA2, an overflow channel 87 is formed on the side of the first dam 81 facing the display area AA.

[0055] The encapsulation layer 65 is located on the side of the display functional layer 50 away from the substrate 20 and is located in the display area AA and the peripheral area NA. The encapsulation layer 65 covers the first dam 81 and covers the edge of the second electrode layer 53. The encapsulation layer 65 includes an organic encapsulation layer 651.

[0056] The edge of the first insulating layer 31 is located at the boundary between the driving circuit region NA1 and the edge region NA2. The first conductive layer 32 is located in the driving circuit region NA1 and the edge region NA2. The edge of the second electrode layer 53 is at least partially located in the driving circuit region NA1. The second insulating layer 33 does not cover or only partially covers the first conductive layer 32 in the edge region NA2. The first electrode layer 51 is in contact with the first conductive layer 32 in the edge region NA2 and is in electrical contact with the first conductive layer 32 in the driving circuit region NA1 through multiple through slots 330. The distance between the edge of the second electrode layer 53 and the first dam 81 is greater than the width of the overflow trough 87.

[0057] The distance between the edge of the second electrode layer 53 and the first dam 81 is greater than the width of the overflow trough 87, and the edge of the second electrode layer 53 is located in the drive circuit area NA1.

[0058] In some embodiments of this application, the display panel has a through groove 330 formed on the second insulating layer 33. The first electrode layer 51 contacts the first conductive layer 32 in the edge region NA2 and is electrically contacted with the first conductive layer 32 through the through groove 330 in the driving circuit region NA1. This optimizes the static discharge path of the film material and the mask during the film manufacturing process, avoiding product damage caused by the long static discharge path and high resistance, which makes it difficult to release static electricity in time. On the other hand, the edge of the second electrode layer 53 does not need to extend to the edge region NA2 to reduce the resistance of the static discharge path. Furthermore, since the distance between the edge of the second electrode layer 53 and the first dam 81 is greater than the width of the overflow groove 87, the edge of the second electrode layer 53 is located in the driving circuit region NA1. That is, the edge of the second electrode layer 53 is recessed inward towards the center of the display panel. As a result, the boundary of the encapsulation layer 65 covering the edge of the second electrode layer 53 and the distance between the first dam 81 and the driving circuit region NA1 can be reduced accordingly, thereby effectively reducing the bezel size of the display panel.

[0059] Please refer to Figure 2 and Figure 3 In some embodiments of the present application, a first optical functional layer 84 and a second optical functional layer 85 are sequentially disposed on the side of the second electrode layer 53 in the display area AA and the peripheral area NA away from the substrate 20. The orthographic projection of the edge of the second electrode layer 53 in the driving circuit area NA1 onto the substrate 20 is located within the orthographic projection of the first optical functional layer 84 onto the substrate 20, and the orthographic projection of the edge of the first optical functional layer 84 onto the substrate 20 is located within the orthographic projection of the second optical functional layer 85 onto the substrate 20.

[0060] It should be noted that the first optical functional layer 84 can be a lithium fluoride (LiF) layer, and the second optical functional layer 85 can be a light extraction layer.

[0061] In some embodiments of this application, the display panel is provided such that the orthographic projection of the edge of the second electrode layer 53 onto the substrate 20 is located within the orthographic projection of the first optical functional layer 84 onto the substrate 20, and the orthographic projection of the edge of the first optical functional layer 84 onto the substrate 20 is located within the orthographic projection of the second optical functional layer 85 onto the substrate 20. This achieves double-layer coverage of the edge of the second electrode layer 53, thereby protecting the edge structure of the second electrode layer 53 together with the encapsulation layer.

[0062] It should be noted that the array functional layer 300 has pixel circuits 88 formed in the display area AA, and support pillars 89 are provided on the pixel defining layer corresponding to the display area. The encapsulation layer may include a stacked first inorganic encapsulation layer 652, an organic encapsulation layer 651, and a second inorganic encapsulation layer 653. The substrate 20 may include multiple sublayers of different materials. In addition to the first dam 81, the display panel may also include a second dam 82, which may be located on the first conductive layer 32 and further include layer structures corresponding to the second insulating layer 33, the first electrode layer 51, the pixel defining layer 61, and the support pillars 89.

[0063] On the other hand, please refer to Figure 1 Some embodiments of this application provide a display device, which includes the display panel described above.

[0064] It should be noted that the different technical features in the aforementioned different embodiments can all be used as features in the same embodiment scheme if there is no conflict.

[0065] When using the terms “including,” “having,” and “comprising” as described herein, another component may be added unless explicitly qualifying terms such as “only,” “consisting of,” etc. are used. Unless otherwise stated, singular terms may include plural forms and should not be construed as having a quantity of one.

[0066] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0067] The above embodiments merely illustrate several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A display panel having a display area and a peripheral area, the peripheral area including a driving circuit area and an edge area located outside the driving circuit area, characterized in that, The display panel includes: A substrate is located in the display area and the peripheral area; An array functional layer is located on one side of the substrate, comprising the display area and the peripheral area. The array functional layer has a gate driving circuit structure located in the driving circuit area. The array functional layer includes a first insulating layer located on one side of the substrate, a first conductive layer located on the side of the first insulating layer away from the substrate, and a second insulating layer located on the side of the first conductive layer away from the substrate and located in the driving circuit area. A plurality of through slots are formed on the second insulating layer. The display functional layer includes a first electrode layer located on the side of the array functional layer away from the substrate, a light-emitting functional layer located on the side of the first electrode layer away from the substrate and located in the display area, and a second electrode layer located on the side of the light-emitting functional layer away from the substrate, wherein the second electrode layer is located in the display area and the peripheral area; The first dam is located on the array functional layer of the edge region; An encapsulation layer is located on the side of the display functional layer away from the substrate and in the display area and the peripheral area. The encapsulation layer covers the first dam and encapsulates the edge of the second electrode layer. The encapsulation layer includes an organic encapsulation layer. Wherein, the edge of the first insulating layer is located at the boundary between the driving circuit region and the edge region, the first conductive layer is located in the driving circuit region and the edge region, the edge of the second electrode layer is at least partially located in the driving circuit region, the second insulating layer does not cover or only partially covers the first conductive layer in the edge region, the first electrode layer is in contact with the first conductive layer in the edge region and is in electrical contact with the first conductive layer in the driving circuit region through a plurality of the through slots.

2. The display panel according to claim 1, characterized in that, A touch function layer is provided on the side of the second electrode layer away from the substrate. The first insulating layer includes an organic layer, and the first conductive layer has a first vent hole. The projection of the first vent hole on the substrate does not overlap with the projection of the through groove on the substrate.

3. The display panel according to claim 2, characterized in that, The multiple through slots on the second insulating layer are connected to form a mesh, and the position of the first vent hole corresponds to the grid position on the mesh.

4. The display panel according to claim 2, characterized in that, The first conductive layer includes a first sub-layer, a second sub-layer, and a third sub-layer stacked together. The material of the second sub-layer includes aluminum. The second insulating layer fills the first vent hole and covers the edge of the first vent hole.

5. The display panel according to claim 1, characterized in that, The second insulating layer includes an organic layer, the first electrode layer has a second vent hole in the driving circuit area, the first electrode layer includes a fourth sub-layer, a fifth sub-layer and a sixth sub-layer stacked together, the material of the fifth sub-layer includes silver, and the edge of the second vent hole is covered with a sealing structure; Preferably, the sealing structure covers the entire second vent.

6. The display panel according to claim 5, characterized in that, A pixel defining layer is provided in the display area and the driving circuit area. The pixel defining layer is located on the side of the array functional layer away from the substrate. The pixel defining layer defines a plurality of pixel openings in the display area. The first electrode layer is located between the pixel defining layer and the array functional layer. The light-emitting functional layer is located on the side of the pixel defining layer away from the substrate and is at least partially located within the pixel openings. The sealing structure is of the same layer and material as the pixel defining layer.

7. The display panel according to claim 1, characterized in that, The array functional layer further includes a second conductive layer located between the first conductive layer and the substrate. The second conductive layer is located between the driving circuit region and the edge region. At least a portion of the second conductive layer located in the driving circuit region is used to form the gate driving circuit structure. The second conductive layer located in the edge region is in contact with the first conductive layer.

8. The display panel according to claim 1, characterized in that, An overflow groove is formed in the edge area on the side of the first dam facing the display area, and the distance between the edge of the second electrode layer and the first dam is greater than the width of the overflow groove; Preferably, the entire edge of the second electrode layer is located within the driving circuit region.

9. The display panel according to claim 1, characterized in that, A first optical functional layer and a second optical functional layer are sequentially disposed on the side of the second electrode layer in the display area and the peripheral area away from the substrate. The orthographic projection of the edge of the second electrode layer in the driving circuit area onto the substrate is located within the orthographic projection of the first optical functional layer onto the substrate, and the orthographic projection of the edge of the first optical functional layer onto the substrate is located within the orthographic projection of the second optical functional layer onto the substrate.

10. A display device, characterized in that, Includes the display panel according to any one of claims 1-9.

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