Poi substrate and method of making same, acoustic device

Abstract

The application relates to the technical field of semiconductors, and particularly discloses a POI substrate, a preparation method thereof and an acoustic device. α Ga β O γ layer, and gamma=2alpha+1.5beta. The application can improve the thermal matching performance between the substrate and the piezoelectric layer, improve the yield of the device, prolong the service life of the device, and optimize the acoustic performance of the acoustic device based on the POI substrate.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a POI substrate, its preparation method, and an acoustic device. Background Technology

[0002] POI (Piezoelectric on Insulator) substrates are crucial foundational materials for manufacturing high-performance filters, resonators, and other acoustic devices in modern radio frequency (RF) front-end modules. Traditional POI structures typically use thermally oxidized silicon dioxide as the bonding layer, its primary function being to achieve insulation and acoustic isolation between the piezoelectric film and the supporting substrate. However, traditional structures suffer from the following technical limitations: First, there is a significant difference in the coefficient of thermal expansion between the silicon dioxide bonding layer and commonly used piezoelectric materials (such as lithium niobate and lithium tantalate). This can easily generate significant thermal stress during high-temperature processes or temperature cycling, leading to problems such as film warping and cracking, severely impacting device reliability and production yield. Second, the acoustic properties of a pure silicon dioxide layer are fixed and cannot be optimized according to device performance requirements, limiting further improvements in device Q-value and operating frequency. Furthermore, traditional bonding layers have a single function and lack additional electrical control capabilities, making it difficult to meet the demands of modern communication systems for reconfigurable and multifunctional acoustic devices. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to provide a POI substrate and its preparation method, which can improve the thermal matching between the substrate and the piezoelectric layer, improve reliability, and increase production yield.

[0004] Another technical problem that the present invention needs to solve is to provide an acoustic device.

[0005] To address the above problems, the present invention provides a POI substrate comprising: Substrate; A transition layer disposed above the substrate; and A piezoelectric layer disposed on the transition layer; The transition layer is Si. α Ga β O γ Layer, γ=2α+1.5β.

[0006] As an improvement to the above technical solution, in the direction from the substrate to the piezoelectric layer, α in the transition layer increases and β decreases; and / or The thickness of the transition layer is 10~500nm.

[0007] As an improvement to the above technical solution, a gallium-rich oxide layer is also included, which is disposed between the substrate and the transition layer; The gallium-rich oxide layer is a Ga2O3 layer or a GaO layer. x Layer, doped Ga2O3 layer, doped GaO x One or more of the layers; The doped Ga2O3 layer, doped GaO x Each layer is doped with acceptor impurities; The thickness of the gallium-rich oxide layer is 20~500nm.

[0008] As an improvement to the above technical solution, an ε-Ga2O3 layer and a GaO layer are sequentially disposed between the substrate and the transition layer. x layer; The thickness of the ε-Ga2O3 layer is 20~400nm; The GaO x The thickness of the layer is 100~300nm, and its O / Ga ratio is 2~2.5.

[0009] As an improvement to the above technical solution, an ε-doped Ga₂O₃ layer and a GaO-doped layer are sequentially disposed between the substrate and the transition layer. x layer; The doped ε-Ga2O3 layer is doped with Mg, Zn, or N, and the doping concentration is 5 × 10⁻⁶. 17 cm -3 ~1×10 19 cm -3 The thickness is 20~400nm; The doped GaO x The layer is doped with Mg, Zn, or N, with a doping concentration of 1 × 10⁻⁶. 17 cm -3 ~1×10 18 cm -3 The thickness is 100~300nm, and the O / Ga ratio is 2~2.5.

[0010] As an improvement to the above technical solution, a silicon-rich oxide layer is also included, which is disposed between the transition layer and the piezoelectric layer; The silicon-rich oxide layer is a silicon oxide layer or a silicon oxynitride layer, with a thickness of 10~500nm.

[0011] Accordingly, the present invention also discloses a method for preparing a POI substrate, which includes: Provide substrate; A transition layer is formed on the substrate, and the transition layer is activated to obtain a first intermediate product; Ions are implanted into the surface of the piezoelectric material to form a peeling defect layer, thus obtaining the second intermediate product; The first intermediate product is bonded to the second intermediate product; The piezoelectric material is split along the peeling defect layer to form a piezoelectric layer.

[0012] As an improvement to the above technical solution, the step of forming a transition layer on the substrate and activating the transition layer to obtain the first intermediate product includes: A gallium-rich oxide layer is formed on the substrate; A transition layer is formed on the gallium-rich oxide layer to obtain a third intermediate product; The third intermediate product is annealed. The annealed transition layer is activated to obtain the first intermediate product; The annealing temperature is 500~700℃.

[0013] As an improvement to the above technical solution, the step of forming a transition layer on the substrate and activating the transition layer to obtain the first intermediate product includes: A transition layer is formed on the substrate; A silicon-rich oxide layer is formed on the transition layer to obtain a fourth intermediate product; The fourth intermediate product is annealed. The annealed silicon-rich oxide layer was activated to obtain the first intermediate product. The annealing temperature is 500~700℃.

[0014] Accordingly, the present invention also discloses an acoustic device comprising the aforementioned POI substrate.

[0015] Implementing this invention has the following beneficial effects: In one embodiment of the present invention, the POI substrate includes a substrate, a transition layer disposed above the substrate, and a piezoelectric layer disposed on the transition layer, wherein the transition layer is Si. α Ga β O γThe transition layer, γ=2α+1.5β, has several key advantages. Firstly, this transition layer is a composite structure of Ga2O3 and SiO2 layers. It forms a thermal buffer structure between the substrate and the piezoelectric layer, mitigating structural warping and interface cracking caused by material thermal mismatch, thus improving device yield and lifespan. Secondly, this transition layer provides equivalent acoustic properties, transforming the SiO2 bonding layer in the original POI substrate from a simple acoustic isolation layer into a functional layer with a certain degree of active electro-acoustic coupling capability. This creates conditions for introducing additional electrical control ports at the substrate level, offering potential application value for developing next-generation acoustic devices with reconfigurable frequencies and tunable performance. Thirdly, by controlling the components in the transition layer, the equivalent acoustic impedance can be designed, thereby optimizing the localization of acoustic wave energy and enabling the fabrication of acoustic devices with higher Q values, better filtering performance, and wider bandwidths. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the structure of a POI substrate in one embodiment of the present invention; Figure 2 This is a schematic diagram of the POI substrate structure in another embodiment of the present invention; Figure 3 This is a schematic diagram of the POI substrate structure in another embodiment of the present invention; Figure 4 This is a schematic diagram of the POI substrate structure in another embodiment of the present invention; Figure 5 This is a schematic diagram of the POI substrate structure in another embodiment of the present invention; Figure 6 This is a cross-sectional TEM and EDS elemental analysis result diagram of the POI substrate obtained in Example 4. Detailed Implementation

[0017] To facilitate understanding of the present invention, it will be described in more detail below. However, it should be understood that the present invention can be implemented in many different forms and is not limited to the embodiments or examples described herein. Rather, these embodiments or examples are provided to make the disclosure of the present invention more thorough and complete.

[0018] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the specification of this invention is for the purpose of describing particular embodiments or examples only and is not intended to limit the invention. The optional range of the term "and / or" as used herein includes any one of two or more of the related listed items, as well as any and all combinations of the related listed items, including any two related listed items, any more related listed items, or a combination of all related listed items.

[0019] Please see Figure 1 As a first aspect of the present invention, the present invention provides a POI substrate, which includes a substrate 100, a transition layer 200 disposed above the substrate 100, and a piezoelectric layer 300 disposed on the transition layer 200, wherein the transition layer 200 is Si α Ga β O γ The transition layer 200, with γ = 2α + 1.5β, has several key advantages. Firstly, this transition layer 200 is a composite structure of Ga2O3 and SiO2 layers. It forms a thermal buffer structure between the substrate 100 and the piezoelectric layer 300, mitigating structural warping and interface cracking caused by material thermal mismatch, thus improving device yield and lifespan. Secondly, the transition layer 200 achieves equivalent acoustic properties, transforming the SiO2 bonding layer in the original POI substrate from a simple acoustic isolation layer into a functional layer with a certain degree of active electro-acoustic coupling capability. This creates conditions for introducing additional electrical control ports at the substrate 100 level, providing potential application value for developing next-generation acoustic devices with reconfigurable frequencies and tunable performance. Thirdly, by controlling the components in the transition layer 200, the equivalent acoustic impedance of the transition layer 200 can be designed, thereby optimizing the localization of acoustic wave energy and making it possible to manufacture acoustic devices with higher Q values, better filtering performance, and wider bandwidth.

[0020] Specifically, the substrate 100 may be a sapphire substrate, a silicon substrate, a silicon carbide substrate, a quartz substrate, or a spinel substrate (MgAl2O4), but is not limited thereto. Preferably, in some embodiments, the substrate 100 is a sapphire substrate, a silicon substrate, or a silicon carbide substrate, but is not limited thereto. More preferably, the substrate 100 is a high-resistivity silicon substrate with a resistivity ≥1 kΩ·cm.

[0021] Specifically, the thickness of the transition layer 200 is 10-500 nm. If its thickness is too small, the thermal buffering and acoustic modulation effects will be limited; if the thickness is too large, it may introduce additional acoustic wave loss and reduce the overall electromechanical coupling coefficient of the device. For example, the thickness of the transition layer 200 is 40 nm, 80 nm, 100 nm, 150 nm, 200 nm, 250 nm, 300 nm, 350 nm, 400 nm, or 450 nm. Preferably, in some embodiments, the thickness of the transition layer 200 is 100-500 nm. More preferably, it is 100-300 nm.

[0022] Specifically, the transition layer 200 (Si) α Ga β O γ In the layer, the value of α ranges from 0.3 to 0.8, exemplarily 0.4, 0.5, 0.6, or 0.7, but is not limited thereto. Preferably, in some embodiments, the value of α ranges from 0.4 to 0.8. The value of β ranges from 0.2 to 0.7, exemplarily 0.3, 0.4, 0.5, or 0.6, but is not limited thereto. Preferably, the value of β ranges from 0.2 to 0.6.

[0023] Specifically, the piezoelectric layer 300 is a lithium niobate layer, a lithium tantalate layer, an aluminum nitride layer, or a zinc oxide layer, but is not limited thereto. Preferably, in some embodiments, the piezoelectric layer 300 is a lithium niobate layer, a lithium tantalate layer, or an aluminum nitride layer. More preferably, the piezoelectric layer 300 is a monocrystalline lithium niobate thin film or a monocrystalline lithium tantalate layer.

[0024] Specifically, the thickness of the piezoelectric layer 300 is 0.3~3μm, exemplarily 0.4μm, 0.8μm, 1.2μm, 1.6μm, 2.0μm, 2.4μm or 2.8μm, but not limited thereto. Preferably, it is 0.3~2.5μm.

[0025] Preferably, in some embodiments, in the direction from the substrate 100 to the piezoelectric layer 300, α in the transition layer 200 exhibits an increasing variation, while β exhibits a decreasing variation. Based on this arrangement, gradient release of thermal stress and gradual matching of acoustic impedance can be achieved, thereby significantly suppressing acoustic wave reflection at the interface and reducing the risk of microcracks caused by thermal mismatch; simultaneously, it improves the power carrying capacity and long-term operational stability of the device in the high-frequency range. More specifically, the increasing and decreasing variations can be linear or gradient variations, but are not limited to these. Linear variations are more preferred.

[0026] Preferably, please refer to Figure 2 In some embodiments, the POI substrate further includes a gallium-rich oxide layer 400 disposed between the substrate 100 and the transition layer 200. This gallium-rich oxide layer 400 is a Ga₂O₃ layer or a GaO₂ layer. xLayer, doped Ga2O3 layer, doped GaO x One or more of the layers, but not limited to these. The gallium-rich oxide layer 400 can further reduce the thermal mismatch between the substrate 100 and the transition layer 200 and enhance the interfacial bonding strength.

[0027] Specifically, doped Ga2O3 layers, doped GaO x Each layer is doped with an acceptor impurity. Exemplarily, the acceptor impurity is Mg, Zn, Ni, or N, but is not limited thereto. Preferably, the acceptor impurity is Mg, Zn, or N.

[0028] Specifically, the thickness of the gallium-rich oxide layer 400 is 20~500nm, exemplarily 70nm, 130nm, 190nm, 250nm, 310nm, 370nm or 430nm, but not limited thereto. Preferably, the thickness of the gallium-rich oxide layer 400 is 50~400nm.

[0029] Preferably, please refer to Figure 3 In some embodiments, an ε-Ga₂O₃ layer 410 and a GaO layer are sequentially disposed between the POI substrate and the transition layer 200. x Layer 420; Based on this, ε-Ga₂O₃ layer 410 can serve as a lattice-matching buffer layer, significantly improving the subsequent GaO… x Layer 420 exhibits consistent epitaxial orientation; while GaO x The high oxygen vacancy concentration in layer 420 allows for better adjustment of the coefficient of thermal expansion. The synergy between the two can significantly reduce stress accumulation and improve the overall thermomechanical stability and acoustic performance of the structure.

[0030] Specifically, the thickness of the ε-Ga2O3 layer 410 is 20~400nm, exemplary of 50nm, 100nm, 150nm, 200nm, 250nm, 300nm or 350nm, but not limited thereto; preferably, the thickness of the ε-Ga2O3 layer 410 is 50~300nm. More preferably, it is 100~300nm.

[0031] Specifically, GaO x The thickness of layer 420 is 100~300nm, exemplarily 140nm, 180nm, 220nm, 260nm or 280nm, but not limited thereto. Preferably, GaO x The thickness of layer 420 is 150~250nm.

[0032] Specifically, GaO x In layer 420, the O / Ga ratio (the ratio of the number of atoms of the two) is 2 to 2.5, exemplarily 2.0, 2.1, 2.2, 2.3 or 2.4, but not limited thereto.

[0033] Preferably, please refer to Figure 4 In some embodiments, the POI substrate has an ε-doped Ga₂O₃ layer 430 and a GaO₂ layer 430 sequentially disposed between it and the transition layer 200. x Layer 440; wherein, the ε-Ga₂O₃ doped layer 430 can serve as a lattice-matching buffer layer, significantly improving the subsequent GaO… x The epitaxial orientation of layer 420 is consistent, and the doping elements can also control the carrier concentration and suppress the interface defect state density; doped GaO x The high oxygen vacancy concentration in layer 440 allows for better adjustment of the coefficient of thermal expansion, while the doping elements also enhance the charge migration capability within the layer, further optimizing the acoustic performance.

[0034] Specifically, the thickness of the doped ε-Ga2O3 layer 430 is 20~400 nm, exemplary of 50 nm, 100 nm, 150 nm, 200 nm, 250 nm, 300 nm or 350 nm, but not limited thereto; preferably, the thickness of the doped ε-Ga2O3 layer 430 is 50~300 nm. More preferably, it is 100~300 nm.

[0035] Specifically, the doping element of the ε-Ga₂O₃ layer 430 is Mg, Zn, or N, but is not limited to these. Preferably, it is Mg. The doping concentration of the ε-Ga₂O₃ layer 430 is 5 × 10⁻⁶. 17 cm -3 ~1×10 19 cm -3 For example, 7.5 × 10 17 cm -3 9.5×10 17 cm -3 1.3×10 18 cm -3 4.2×10 18 cm -3 8.5×10 18 cm -3 Or 9.5×10 18 cm -3 However, it is not limited to this. Preferably, the doping concentration is 1×10⁻⁶. 18 cm -3 ~1×10 19 cm -3 .

[0036] Specifically, doped GaO x The thickness of layer 440 is 100~300nm, exemplarily 140nm, 180nm, 220nm, 260nm or 280nm, but not limited thereto. Preferably, in some embodiments, GaO is doped. x The thickness of layer 440 is 150~250nm.

[0037] Specifically, doped GaO x In layer 440, the O / Ga ratio (the ratio of the number of atoms of the two) is 2 to 2.5, exemplarily 2.0, 2.1, 2.2, 2.3 or 2.4, but not limited thereto.

[0038] Specifically, doped GaO x The doping element of layer 440 is Mg, Zn, or N, but is not limited to these. Preferably, it is Mg. Doped GaO x The doping concentration of layer 440 is 1×10 17 cm -3 ~1×10 18 cm -3 For example, 2.5 × 10 17 cm -3 4.5×10 17 cm -3 6.5×10 17 cm -3 8×10 17 cm -3 Or 9.5×10 17 cm -3 However, it is not limited to this.

[0039] Preferably, please refer to Figure 5 In some embodiments, the POI substrate further includes a silicon-rich oxide layer 500 disposed between the transition layer 200 and the piezoelectric layer 300. The silicon-rich oxide layer 500 is a silicon oxide layer or a silicon oxynitride layer. The silicon-rich oxide layer 500 can further reduce dangling bonds, surface defects, and passivate interface states, thereby improving the stability of acoustic wave propagation.

[0040] Specifically, the thickness of the silicon-rich oxide layer 500 is 10~500nm, exemplarily 50nm, 90nm, 130nm, 170nm, 210nm, 250nm, 300nm, 400nm or 450nm, but not limited thereto. Preferably, the thickness of the silicon-rich oxide layer 500 is 100~300nm.

[0041] Accordingly, as a second aspect of the present invention, a method for preparing a POI substrate is also disclosed, comprising the following steps: S1: Provides a substrate; S2: A transition layer is formed on the substrate, and the transition layer is activated to obtain the first intermediate product; The transition layer can be formed through methods such as metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE), mist chemical vapor deposition (Mist-CVD), and pulsed laser deposition (PLD), but is not limited to these methods.

[0042] Preferably, in some embodiments, a transition layer is formed by MOCVD. By adjusting the flow rates of the gallium source (TMGa or TEGa), silicon source (SiH4, TEOS), and oxygen source (O2, N2O, or H2O), the composition and thickness of the transition layer can be precisely controlled. Specifically, the growth temperature of the transition layer is 500~800℃, and the growth pressure is 20~300 torr.

[0043] Specifically, the activation treatment can be plasma bombardment, thermal annealing, ultraviolet irradiation, or high-energy electron beam irradiation, but is not limited to these. Preferably, in some embodiments, plasma bombardment is used for activation treatment, and the bombardment gas is Ar, N2, or O2, but is not limited to these.

[0044] S3: Ions are implanted into the surface of the piezoelectric material to form a peeling defect layer, thus obtaining the second intermediate product; Specifically, hydrogen ions and / or helium ions can be injected into the surface of the piezoelectric material to form a peeling defect layer, but this is not the only possibility.

[0045] S4: Bond the first intermediate product to the second intermediate product; S5: Split the piezoelectric material along the peeling defect layer to form a piezoelectric layer.

[0046] Based on the above preparation method, Si is formed between the piezoelectric layer and the substrate. α Ga β O γ The transition layer serves as a composite of Ga2O3 and SiO2 layers. This transition layer forms a thermal buffer structure between the substrate and the piezoelectric layer, mitigating structural warping and interface cracking caused by material thermal mismatch, thus improving device yield and lifespan. This transition layer also provides equivalent acoustic properties, transforming the SiO2 bonding layer in the original POI substrate from a simple acoustic isolation layer into a functional layer with a certain degree of active electro-acoustic coupling capability. This creates conditions for introducing additional electrical control ports at the substrate level, offering potential application value for developing next-generation acoustic devices with reconfigurable frequencies and tunable performance.

[0047] Preferably, in some embodiments, step S2 includes: S211: A gallium-rich oxide layer is formed on the substrate; Gallium-rich oxide layers can be formed using methods such as metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE), mist chemical vapor deposition (Mist-CVD), and pulsed laser deposition (PLD), but are not limited to these methods. Preferably, in some embodiments, gallium-rich oxide layers are formed using MOCVD. S212: A transition layer is formed on a gallium-rich oxide layer to obtain a third intermediate product; S213: Anneal the third intermediate product; The annealing process takes place at a temperature of 500~700℃. Annealing promotes atomic-level interdiffusion between the gallium-rich oxide layer and the transition layer, thereby improving the interfacial bonding strength and thermal stability.

[0048] S214: Activate the annealed transition layer to obtain the first intermediate product.

[0049] Preferably, in some other embodiments, step S2 includes: S221: A transition layer is formed on the substrate; S222: A silicon-rich oxide layer is formed on the transition layer to obtain the fourth intermediate product; S223: Anneal the fourth intermediate product; The annealing temperature is 500~700℃.

[0050] S224: The annealed silicon-rich oxide layer is activated to obtain the first intermediate product; The present invention will be further described below with reference to specific embodiments: Example 1 This embodiment provides a POI substrate structure, which includes a substrate, a transition layer and a piezoelectric layer sequentially stacked on the substrate. The substrate is a high-resistivity silicon substrate. The transition layer is Si. α Ga β O γ The first layer has α=0.4, β=0.6, γ=2α+1.5β, and a thickness of 100nm. The piezoelectric layer is a single-crystal lithium tantalate layer with a thickness of 600nm.

[0051] Example 2 This embodiment provides a POI substrate structure, which includes a substrate, a transition layer and a piezoelectric layer sequentially stacked on the substrate. The substrate is a high-resistivity silicon substrate. The transition layer is Si. α Ga β O γ The first layer is 100 nm thick; the second layer is a single-crystal lithium tantalate layer with a thickness of 600 nm.

[0052] In the direction from the substrate to the piezoelectric layer, α in the transition layer increases linearly from 0.3 to 0.5, β decreases linearly from 0.7 to 0.5, and γ changes continuously from 2α+1.5β accordingly.

[0053] Example 3 This embodiment provides a POI substrate structure, which includes a substrate, a gallium-rich oxide layer, a transition layer, and a piezoelectric layer sequentially stacked on the substrate. The substrate is a high-resistivity silicon substrate; the gallium-rich oxide layer is an ε-Ga₂O₃ layer with a thickness of 200 nm; and the transition layer is Si. α Ga β O γ The first layer is 100 nm thick; the second layer is a single-crystal lithium tantalate layer with a thickness of 600 nm.

[0054] In the direction from the substrate to the piezoelectric layer, α in the transition layer increases linearly from 0.3 to 0.5, β decreases linearly from 0.7 to 0.5, and γ changes continuously from 2α+1.5β accordingly.

[0055] Example 4 This embodiment provides a POI substrate structure, which includes a substrate, and an ε-Ga₂O₃ layer and a GaO layer sequentially stacked on the substrate. x The system consists of a ε-Ga₂O₃ layer, a transition layer, and a piezoelectric layer. The substrate is a high-resistivity silicon substrate; the ε-Ga₂O₃ layer has a thickness of 200 nm; and the GaO₂ layer... x The layer is 150 nm thick with a Ga / O ratio of 2; the transition layer is Si. α Ga β O γ The first layer is 100 nm thick; the second layer is a single-crystal lithium tantalate layer with a thickness of 600 nm.

[0056] In the direction from the substrate to the piezoelectric layer, α in the transition layer increases linearly from 0.3 to 0.5, β decreases linearly from 0.7 to 0.5, and γ changes continuously from 2α+1.5β accordingly.

[0057] The TEM image of the sample obtained in this embodiment is as follows: Figure 6 As shown.

[0058] Example 5 This embodiment provides a POI substrate structure, which includes a substrate, a transition layer, a silicon-rich oxide layer, and a piezoelectric layer sequentially stacked on the substrate. The substrate is a high-resistivity silicon substrate; the transition layer is Si. α Ga β O γ The first layer is 100 nm thick; the second layer is a SiO2 layer with a thickness of 200 nm. The third layer is a single-crystal lithium tantalate layer with a thickness of 600 nm.

[0059] In the direction from the substrate to the piezoelectric layer, α in the transition layer increases linearly from 0.3 to 0.5, β decreases linearly from 0.7 to 0.5, and γ changes continuously from 2α+1.5β accordingly.

[0060] Comparative Example 1 This comparative example provides a POI substrate, which includes a substrate, an insulating layer, and a piezoelectric layer sequentially stacked on the substrate. The substrate is a high-resistivity silicon substrate; the insulating layer is a SiO2 layer with a thickness of 200 nm; and the piezoelectric layer is a single-crystal lithium tantalate layer with a thickness of 600 nm.

[0061] Comparative Example 2 This comparative example provides a POI substrate, which includes a substrate, an ε-Ga₂O₃ layer, an insulating layer, and a piezoelectric layer sequentially stacked on the substrate. The substrate is a high-resistivity silicon substrate; the ε-Ga₂O₃ layer has a thickness of 200 nm; the insulating layer is a SiO₂ layer with a thickness of 200 nm; and the piezoelectric layer is a single-crystal lithium tantalate layer with a thickness of 600 nm.

[0062] The POI substrates obtained in Examples 1-5 and Comparative Examples 1-2 were tested, and the specific test data are as follows:

[0063] The above description is a preferred embodiment of the invention. It should be noted that, for those skilled in the art, several improvements and modifications can be made without departing from the principle of the invention, and these improvements and modifications are also considered to be within the scope of protection of the invention.

Claims

1. A POI substrate, characterized in that, include: Substrate; A transition layer disposed above the substrate; as well as A piezoelectric layer disposed on the transition layer; The transition layer is Si. α Ga β O γ Layer, γ=2α+1.5β.

2. The POI substrate as described in claim 1, characterized in that, In the direction from the substrate to the piezoelectric layer, α in the transition layer increases and β decreases; and / or The thickness of the transition layer is 10~500nm.

3. The POI substrate as described in claim 1, characterized in that, It also includes a gallium-rich oxide layer disposed between the substrate and the transition layer; The gallium-rich oxide layer is a Ga2O3 layer or a GaO layer. x Layer, doped Ga2O3 layer, doped GaO x One or more of the layers; The doped Ga2O3 layer, doped GaO x Each layer is doped with acceptor impurities; The thickness of the gallium-rich oxide layer is 20~500nm.

4. The POI substrate as described in claim 1, characterized in that, An ε-Ga₂O₃ layer and a GaO layer are sequentially disposed between the substrate and the transition layer. x layer; The thickness of the ε-Ga2O3 layer is 20~400nm; The GaO x The thickness of the layer is 100~300nm, and its O / Ga ratio is 2~2.

5.

5. The POI substrate as described in claim 1, characterized in that, An ε-Ga₂O₃ doped layer and a GaO doped layer are sequentially disposed between the substrate and the transition layer. x layer; The doped ε-Ga2O3 layer is doped with Mg, Zn, or N, and the doping concentration is 5 × 10⁻⁶. 17 cm -3 ~1×10 19 cm -3 The thickness is 20~400nm; The doped GaO x The layer is doped with Mg, Zn, or N, with a doping concentration of 1 × 10⁻⁶. 17 cm -3 ~1×10 18 cm -3 The thickness is 100~300nm, and the O / Ga ratio is 2~2.

5.

6. The POI substrate according to any one of claims 1 to 5, characterized in that, It also includes a silicon-rich oxide layer disposed between the transition layer and the piezoelectric layer; The silicon-rich oxide layer is a silicon oxide layer or a silicon oxynitride layer, with a thickness of 10~500nm.

7. A method for preparing a POI substrate, used to prepare the POI substrate as described in any one of claims 1 to 6, characterized in that, include: Provide substrate; A transition layer is formed on the substrate, and the transition layer is activated to obtain a first intermediate product; Ions are implanted into the surface of the piezoelectric material to form a peeling defect layer, thus obtaining the second intermediate product; The first intermediate product is bonded to the second intermediate product; The piezoelectric material is split along the peeling defect layer to form a piezoelectric layer.

8. The method for preparing a POI substrate as described in claim 7, wherein the step of forming a transition layer on the substrate and activating the transition layer to obtain a first intermediate product comprises: A gallium-rich oxide layer is formed on the substrate; A transition layer is formed on the gallium-rich oxide layer to obtain a third intermediate product; The third intermediate product is annealed. The annealed transition layer is activated to obtain the first intermediate product; The annealing temperature is 500~700℃.

9. The method for preparing a POI substrate as described in claim 7, characterized in that, The step of forming a transition layer on the substrate and activating the transition layer to obtain the first intermediate product includes: A transition layer is formed on the substrate; A silicon-rich oxide layer is formed on the transition layer to obtain a fourth intermediate product; The fourth intermediate product is annealed. The annealed silicon-rich oxide layer was activated to obtain the first intermediate product. The annealing temperature is 500~700℃.

10. An acoustic device, characterized in that, Including the POI substrate as described in any one of claims 1 to 6.

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