Chip product preparation method, system, and superconducting chip

Abstract

This disclosure provides a chip fabrication method, system, and superconducting chip. The method includes: fabricating a bottom circuit on a substrate; fabricating a conductive block in a connection region on the surface of the bottom circuit; fabricating an independent Josephson junction on the substrate to obtain a first chip product, wherein the material of the conductive block is the same as the material of the first end of the Josephson junction; spin-coating a first photoresist onto the first chip product; removing the first photoresist located in a transition region of the first chip product to expose the first end and the conductive block located in the transition region; removing the native oxide layer on the exposed first end and the conductive block; depositing a superconducting connection film in the transition region, wherein the superconducting connection film is used to connect the first end and the conductive block; and peeling off the first photoresist to obtain a second chip product. This disclosure can improve the connection quality between the bottom circuit and the Josephson junction while ensuring successful connection between them.

Description

Technical Field

[0001] This disclosure relates to the field of micro-nano fabrication technology, and in particular to a method, system, and superconducting chip for chip product fabrication. Background Technology

[0002] Currently, in the fabrication of chip products, to avoid damaging the substrate, a patching method is commonly used to connect the underlying circuitry and the Josephson junction. First, the native oxide layer of the underlying circuitry connection area and the Josephson junction connection area is completely removed. Then, a superconducting connection film for connecting the underlying circuitry and the Josephson junction is deposited. However, since the removal of the native oxide layer of the underlying circuitry is usually more difficult than the removal of the native oxide layer of the Josephson junction connection area, the superconducting layer of the Josephson junction connection area is often over-etched when the native oxide layer of the underlying circuitry connection area is completely removed. This affects the connection quality between the underlying circuitry and the Josephson junction, and in some cases, the superconducting layer of the Josephson junction connection area is completely etched, leading to connection failure between the underlying circuitry and the Josephson junction. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.

[0004] This disclosure provides a chip product fabrication method, system, and superconducting chip that can improve the connection quality between the underlying circuit and the Josephson junction while ensuring successful connection between the underlying circuit and the Josephson junction.

[0005] On one hand, this disclosure provides a method for manufacturing a chip product, including:

[0006] A bottom circuit is fabricated on a substrate, a conductive block is fabricated in the connection region on the surface of the bottom circuit, and an independent Josephson junction is fabricated on the substrate to obtain a first chip product, wherein the material of the conductive block is the same as the material of the first end of the Josephson junction.

[0007] A first photoresist is spin-coated onto the first chip product, and the first photoresist located in the transition region of the first chip product is removed to expose the first end and the conductive block located in the transition region, wherein the transition region is used to connect the first end and the conductive block;

[0008] Remove the exposed first end and the native oxide layer on the conductive block, and deposit a superconducting connection film in the transition region, wherein the superconducting connection film is used to connect the first end and the conductive block;

[0009] The first photoresist is peeled off to obtain the second chip product.

[0010] On the other hand, this disclosure also provides a chip product fabrication system, the system including: a spin coater, a photolithography machine, a developing machine, an etching machine, a vapor deposition machine, and a resist stripper;

[0011] The evaporation machine, the spin coater, the photolithography machine, the developing machine, the etching machine, and the resist remover are used to fabricate a bottom layer circuit on a substrate, fabricate a conductive block in the connection area on the surface of the bottom layer circuit, and fabricate an independent Josephson junction on the substrate to obtain a first chip product, wherein the material of the conductive block is the same as the material of the first end of the Josephson junction.

[0012] The spin coater, the photolithography machine, and the developing machine are used to spin coat the first photoresist onto the first chip product and remove the first photoresist located in the transition region of the first chip product to expose the first end and the conductive block located in the transition region, wherein the transition region is used to connect the first end and the conductive block.

[0013] The vapor deposition machine is used to remove the exposed first end and the native oxide layer on the conductive block, and to deposit a superconducting connection film in the transition region, wherein the superconducting connection film is used to connect the first end and the conductive block;

[0014] The photoresist stripper is used to peel off the first photoresist to obtain the second chip product.

[0015] In one possible implementation, the spin coater, the photolithography machine, and the developing machine are further configured to spin coat a second photoresist onto the substrate to remove the second photoresist located in the connection area on the surface of the underlying circuit.

[0016] The vapor deposition machine is also used to deposit conductive blocks in the connection area;

[0017] The photoresist stripper is also used to strip the second photoresist to obtain the substrate having the underlying circuit and the conductive block.

[0018] In one possible implementation, the second photoresist is a negative photoresist;

[0019] The lithography machine is also used to expose the second photoresist located outside the connection area on the surface of the underlying circuit.

[0020] The developing machine is also used to place the substrate in a developing solution corresponding to the second photoresist for development, so as to remove the second photoresist located in the connection area and form an undercut structure composed of the remaining second photoresist.

[0021] In one possible implementation, the chip product fabrication system further includes a computing device, and the evaporation machine is equipped with an ion source;

[0022] The computing device is used to determine the first ion milling parameters based on the material of the underlying circuit.

[0023] The ion source is used to perform ion milling on the substrate having the underlying circuit according to the first ion milling parameters to remove the natural oxide layer on the connection region.

[0024] In one possible implementation, the chip manufacturing system further includes measuring instruments;

[0025] The measuring instrument and the computing device are used to determine a first distance between the surface of the conductive block and the substrate, and to determine a first thickness range based on the first distance, wherein the lower limit of the first thickness range is greater than twice the first distance;

[0026] The spin coater is further configured to determine spin coating parameters based on the first thickness range, and spin coat a first photoresist onto the first chip product based on the spin coating parameters, wherein the second distance between the surface of the first photoresist and the substrate is within the first thickness range.

[0027] In one possible implementation, the computing device is further configured to determine a distance difference between a second distance and a first distance, and to determine a second thickness range based on the first distance and the distance difference, wherein the lower limit of the second thickness range is greater than the first distance, and the upper limit of the second thickness range is less than the distance difference;

[0028] The vapor deposition machine is further configured to determine deposition parameters based on the second thickness range, and deposit a superconducting connection film in the transition region based on the deposition parameters, wherein the thickness of the superconducting connection film is within the second thickness range.

[0029] In one possible implementation, the underlying circuitry includes a capacitor, the capacitor comprising independently distributed first electrode structures and second electrode structures, the connection region being located on the surface of the first electrode structure, and the chip product fabrication system further including design equipment;

[0030] The design device is used to determine a fabrication area on the substrate surface based on the first electrode structure and the second electrode structure, wherein the fabrication area is located between the first electrode structure and the second electrode structure;

[0031] The vapor deposition machine, the spin coater, the photolithography machine, the developing machine, and the resist remover are used to prepare independent Josephson junctions in the preparation area using an angled deposition method.

[0032] In one possible implementation, the design device is further configured to define a region to be processed on the substrate surface, in addition to the underlying circuitry and the Josephson junction;

[0033] The design device is further configured to determine a transition sub-region in the area to be processed based on the conductive block and the first end, wherein the projection of the conductive block on the substrate and the projection of the first end on the substrate are both connected to the transition sub-region.

[0034] The design device is further configured to determine the transition region of the first chip product based on the connection region, the first end, and the transition sub-region.

[0035] In one possible implementation, the design device is further configured to determine a plurality of candidate regions on the surface of the first electrode structure according to a preset region shape, wherein the shape of each candidate region is the region shape;

[0036] The design device is also used to determine a first distance between each of the candidate regions and the first end;

[0037] The design device is further configured to sort the plurality of candidate regions according to the first distance, and determine a connection region among the plurality of candidate regions according to the sorting result.

[0038] In one possible implementation, the design device is further configured to determine a second distance between each of the candidate regions and the second electrode structure;

[0039] The design device is further configured to sort the multiple candidate regions according to the weighted result of the first distance and the second distance, wherein the weight of the first distance is greater than the weight of the second distance.

[0040] In one possible implementation, the computing device is further configured to determine second ion milling parameters based on the material of the conductive block;

[0041] The ion source is also used to perform ion milling on the product having the first chip according to the second ion milling parameters, to remove the exposed first end and the natural oxide layer on the conductive block.

[0042] In one possible implementation, the first photoresist is a negative photoresist, and the photolithography machine is further used to expose the first photoresist located outside the transition region of the first chip product.

[0043] The developing machine is further configured to place the first chip product in a developing solution corresponding to the first photoresist for development, so as to remove the first photoresist located in the transition area and form an undercut structure composed of the remaining first photoresist.

[0044] In one possible implementation, the vapor deposition machine is also used to remove the native oxide layer on the substrate and deposit a circuit layer on the substrate;

[0045] The spin coater, the photolithography machine, and the developing machine are also used to spin coat a third photoresist on the substrate and expose and develop the etching area corresponding to the underlying circuit in the third photoresist using an exposure method such as electron beam exposure, laser direct writing, or ultraviolet exposure, wherein the etching area is located in the circuit layer.

[0046] The etching machine and the photoresist stripper are also used to etch the etched area and strip the third photoresist to obtain the substrate having the underlying circuit.

[0047] On the other hand, this disclosure also provides a superconducting chip, including:

[0048] A substrate, an underlying circuitry on the substrate, and a separate Josephson junction on the substrate;

[0049] A conductive block located in the connection area on the surface of the underlying circuit, wherein the material of the conductive block is the same as the material of the first end of the Josephson junction;

[0050] A superconducting connecting membrane is used to connect the first end and the conductive block.

[0051] The embodiments disclosed herein include at least the following beneficial effects: By fabricating an underlying circuit and an independent Josephson junction on a substrate, and fabricating a conductive block in the connection region on the surface of the underlying circuit, a first chip product is obtained. Then, by spin-coating a first photoresist onto the first chip product and removing the first photoresist located in the transition region of the first chip product, the first end and the conductive block located in the transition region can be exposed. Then, the native oxide layer on the exposed first end and the conductive block is removed. Since the material of the conductive block is the same as the material of the first end of the Josephson junction, native oxide layers of the same thickness and composition will be formed on the surface of the first end and the surface of the conductive block, indicating that the removal difficulty of the native oxide layers on the surfaces of the two is the same. During the removal of the native oxide layer, when the native oxide layer on the surface of the conductive block is completely removed, the native oxide layer on the surface of the first end is also completely removed. This allows for the complete removal of the native oxide layer without damaging the first end of the Josephson junction. Then, a superconducting interconnect film is deposited in the transition region, and the first photoresist is stripped off to obtain the second chip product. In the second chip product, the first end of the Josephson junction is connected to the conductive block through the superconducting interconnect film. Since the first end of the Josephson junction is not over-etched during the removal of the native oxide layer, the connection quality between the underlying circuit and the Josephson junction can be improved while ensuring successful connection between the underlying circuit and the Josephson junction, thereby improving chip performance.

[0052] Other features and advantages of this disclosure will be set forth in the following description and will be apparent in part from the description or may be learned by practicing this disclosure. Attached Figure Description

[0053] The accompanying drawings are provided to further understand the technical solutions of this disclosure and constitute a part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure.

[0054] Figure 1 This is a schematic diagram of an optional structure of the superconducting chip provided in an embodiment of the present disclosure;

[0055] Figure 2 This is a schematic diagram of an optional process for a chip product fabrication method provided in an embodiment of this disclosure;

[0056] Figure 3 A schematic cross-sectional view of an optional substrate with capacitance provided in an embodiment of this disclosure;

[0057] Figure 4 This is an optional cross-sectional view provided in an embodiment of the present disclosure after removing the second photoresist;

[0058] Figure 5This is an optional schematic diagram illustrating ion milling of the connecting region according to an embodiment of this disclosure;

[0059] Figure 6 This is an optional schematic diagram of depositing a connection region according to an embodiment of this disclosure;

[0060] Figure 7 This is an optional cross-sectional view of a conductive block formed in a connection region, provided as an embodiment of the present disclosure.

[0061] Figure 8 This is an optional cross-sectional view of the area after the second photoresist has been removed, as provided in an embodiment of this disclosure.

[0062] Figure 9 A schematic diagram of an optional structure of a substrate with conductive blocks provided in an embodiment of this disclosure;

[0063] Figure 10 A schematic cross-sectional view of a substrate having a capacitor and a Josephson junction provided for an embodiment of this disclosure;

[0064] Figure 11 This is an optional schematic diagram of ion milling treatment of a transition region provided by an embodiment of this disclosure;

[0065] Figure 12 This is an optional schematic diagram of depositing in a transition region according to an embodiment of the present disclosure;

[0066] Figure 13 This is an optional cross-sectional schematic diagram of a second chip product provided in an embodiment of this disclosure;

[0067] Figure 14 This is a schematic diagram of an optional structure of the second chip product provided in an embodiment of the present disclosure;

[0068] Figure 15 This is an optional schematic diagram of a chip product fabrication system provided in an embodiment of this disclosure;

[0069] Figure 16 This is an optional schematic diagram illustrating an application scenario of the solution provided in the embodiments of this disclosure. Detailed Implementation

[0070] To make the objectives, technical solutions, and advantages of this disclosure clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0071] It should be noted that in the various specific embodiments of this disclosure, when processing is required based on data related to the characteristics of the target object, such as target object attribute information or a set of attribute information, the permission or consent of the target object will be obtained first. Furthermore, the collection, use, and processing of this data will comply with relevant laws, regulations, and standards. The target object can be a user. In addition, when embodiments of this disclosure require obtaining target object attribute information, separate permission or consent from the target object will be obtained through pop-ups or redirection to a confirmation page. Only after obtaining the target object's separate permission or consent will the necessary target object-related data for the normal operation of the embodiments of this disclosure be obtained.

[0072] In this disclosure, the terms "module" or "unit" refer to a computer program or part of a computer program that has a predetermined function and works with other related parts to achieve a predetermined goal, and can be implemented wholly or partially using software, hardware (such as processing circuitry or memory), or a combination thereof. Similarly, a processor (or multiple processors or memory) can be used to implement one or more modules or units. Furthermore, each module or unit can be part of an overall module or unit that includes the functionality of that module or unit.

[0073] To facilitate understanding of the technical solutions provided in the embodiments of this disclosure, some key terms used in the embodiments of this disclosure will be explained below:

[0074] Superconductor: A material whose electrical resistance abruptly drops to 0 below a certain temperature and which exhibits complete diamagnetism.

[0075] Stripping: The underlying photoresist is dissolved in the stripper solution, and the thin film on top of the photoresist is also removed.

[0076] In situ: A multi-step process performed in a single vacuum chamber or multiple interconnected vacuum chambers without exposure to the atmospheric environment.

[0077] Ion milling: Argon ions are generated using an ion source and bombarded on a metal surface in a vacuum to remove the natural oxide layer on the metal surface.

[0078] Undercut: A structure in which the opening on the upper surface of the photoresist is smaller than the opening at the bottom of the photoresist after development.

[0079] Currently, in the fabrication of chip products, to avoid damaging the substrate, a patching method is commonly used to connect the underlying circuitry and the Josephson junction. First, the native oxide layer of the underlying circuitry connection area and the Josephson junction connection area is completely removed. Then, a superconducting connection film for connecting the underlying circuitry and the Josephson junction is deposited. However, since the removal of the native oxide layer of the underlying circuitry is usually more difficult than the removal of the native oxide layer of the Josephson junction connection area, the superconducting layer of the Josephson junction connection area is often over-etched when the native oxide layer of the underlying circuitry connection area is completely removed. This affects the connection quality between the underlying circuitry and the Josephson junction, and in some cases, the superconducting layer of the Josephson junction connection area is completely etched, leading to connection failure between the underlying circuitry and the Josephson junction.

[0080] Taking the connection of the capacitor in the underlying circuit to the Josephson junction as an example, refer to... Figure 1 , Figure 1 This is a schematic diagram of an optional structure of the superconducting chip provided in an embodiment of this disclosure.

[0081] Specifically, a capacitor is first obtained by laser direct writing exposure followed by etching on the substrate 100. The capacitor includes a first electrode structure 101 and a second electrode structure 102. Then, a Josephson junction 103 with a cross structure is prepared by electron beam exposure. Then, a transition region for connecting the capacitor connection region and the Josephson junction 103 connection region is exposed. Then, the native oxide layer of the capacitor connection region and the Josephson junction 103 connection region is removed by ion milling. Then, the first electrode structure 101 and the Josephson junction 103 are connected by depositing a superconducting connection film.

[0082] For example, the superconducting connection film includes a first connection film 104 and a second connection film 105. The first connection film 104 connects the first electrode structure 101 to the first end of the Josephson junction 103, and the second connection film 105 connects the second electrode structure 102 to the second end of the Josephson junction 103. There can be multiple transition regions. The regions where the first connection film 104 and the second connection film 105 are located are different transition regions. The first intersection region 106 between the first connection film 104 and the first electrode structure 101 is a capacitive connection region. The second intersection region 107 between the first connection film 104 and the Josephson junction 103 is a Josephson junction 103 connection region. The third intersection region 108 between the second connection film 105 and the second electrode structure 102 is also a capacitive connection region. The fourth intersection region 109 between the second connection film 105 and the Josephson junction 103 is also a Josephson junction 103 connection region.

[0083] It is understandable that, since removing the natural oxide layer of the underlying circuit is more difficult than removing the natural oxide layer of the Josephson junction connection region, when the natural oxide layer of the capacitor connection region is completely removed, the superconducting layer of the Josephson junction 103 connection region is often over-etched, affecting the connection quality between the capacitor and the Josephson junction 103, and even completely etching the superconducting layer of the Josephson junction 103 connection region, resulting in the failure of the connection between the capacitor and the Josephson junction 103.

[0084] To address the aforementioned issues, subsequent embodiments of this disclosure propose a chip product fabrication method, system, and superconducting chip that can improve the connection quality between the underlying circuit and the Josephson junction while ensuring successful connection between the underlying circuit and the Josephson junction.

[0085] Reference Figure 2 , Figure 2 This is an optional flowchart illustrating a chip product fabrication method provided in an embodiment of the present disclosure. The chip product fabrication method includes, but is not limited to, the following steps 201 to 204.

[0086] Step 201: Fabricate the underlying circuit on the substrate, fabricate conductive blocks in the connection area on the surface of the underlying circuit, fabricate independent Josephson junctions on the substrate, and obtain the first chip product.

[0087] The substrate is the supporting material for the chip product. In superconducting chips, the substrate is usually made of sapphire or high-resistivity silicon. The material of the bottom circuit can be a superconducting material such as tantalum or niobium. The thickness of the bottom circuit can range from 200nm to 400nm. The bottom circuit can include underlying structures such as resonant cavities, transmission lines, and capacitors. Specifically, the bottom circuit can be prepared in a variety of ways, such as through processes like film deposition-photolithography-etching, photolithography-development-deposition, or nanoimprint lithography.

[0088] The connection region on the surface of the underlying circuit refers to the area on the surface of the underlying circuit used to connect the Josephson junction. In order to obtain a complete superconducting chip, it is usually necessary to connect the underlying circuit with the Josephson junction, so a connection region is required on the surface of the underlying circuit. The connection region is usually only a part of the surface of the underlying circuit. For example, when it is necessary to connect the capacitor of the underlying circuit to the Josephson junction, the area on the capacitor surface used to connect the Josephson junction is used as the connection region.

[0089] It should be noted that fabricating conductive blocks in the connection region on the surface of the underlying circuit means that the side of the conductive block closest to the underlying circuit is connected to the surface of the underlying circuit, i.e., the conductive block is connected to the underlying circuit. Furthermore, the conductive blocks are typically thin; for example, the thickness of the conductive block can range from 50 nm to 200 nm, so it can be considered that the conductive block is in the form of a thin film.

[0090] A Josephson junction is a device comprising two electrodes and a thin insulating barrier layer separating them. The materials of the electrodes exhibit superconductivity at or below their critical temperature. Simply put, a Josephson junction is a sandwich structure consisting of a superconductor, an insulator, and another superconductor. The first electrode of the Josephson junction can be considered its first end, and the second electrode can be considered its second end.

[0091] For example, both electrodes of the Josephson junction are strip-shaped. When fabricating the Josephson junction, the first electrode of the Josephson junction can be fabricated on the substrate first, and then the second electrode of the Josephson junction can be fabricated on the substrate. The intersection of the two electrodes of the Josephson junction is isolated by an oxide layer to form the Josephson junction. The oxide layer of the Josephson junction is equivalent to an insulating barrier layer. Both electrodes of the Josephson junction can be called strip-shaped superconducting layers. The feature size of the Josephson junction can be selected as 200 nm.

[0092] It should be noted that in order to form an oxide layer at the intersection of the two electrodes of the Josephson junction during the fabrication of the junction, the first electrode of the Josephson junction needs to be made of a superconducting material that can undergo oxidation. This allows the surface of the first electrode to form a natural oxide layer as an insulating barrier after the first electrode is fabricated. In other words, the material of the first end of the Josephson junction is a superconducting material that can undergo oxidation. For example, the material of the first end of the Josephson junction can be a superconducting material such as aluminum or niobium.

[0093] The conductive block is made of the same material as the first end of the Josephson junction. Since the first end of the Josephson junction is made of a superconducting material that can be oxidized, the conductive block is also made of a superconducting material that can be oxidized, which allows the conductive block to exhibit superconducting properties in a specific environment. In addition, after the conductive block is fabricated, a natural oxide layer is formed on its surface. The natural oxide layer on the surface of the first end is the same as the natural oxide layer on the surface of the conductive block. Since both the first end and the conductive block are located within the first chip product, they are under the same environmental conditions. Therefore, when the natural oxide layer on the surface of the first end and the natural oxide layer on the surface of the conductive block reach a stable state, the thickness of the natural oxide layer on the surface of the first end is the same as the thickness of the natural oxide layer on the surface of the conductive block.

[0094] For example, suppose that the material of the first end of the Josephson junction and the material of the conductive block are both aluminum, and aluminum oxide can be formed on the surface of the first end and the surface of the conductive block. When the aluminum oxide on the surface of the first end and the aluminum oxide on the surface of the conductive block reach a stable state, the thickness of the aluminum oxide on the surface of the first end is the same as the thickness of the aluminum oxide on the surface of the conductive block.

[0095] It should be noted that in the first chip product, the fabrication order of the underlying circuit, conductive block, and Josephson junction can be adjusted according to actual needs. For example, the underlying circuit, conductive block, and Josephson junction can be fabricated in sequence, or the underlying circuit, Josephson junction, and conductive block can be fabricated in sequence, or the Josephson junction, underlying circuit, and conductive block can be fabricated in sequence. It is only necessary to ensure that the fabrication order of the conductive block is after the fabrication order of the underlying circuit. The specific fabrication order of the first chip product is not limited in the embodiments of this disclosure.

[0096] It is worth noting that before fabricating the underlying circuit, conductive blocks, and Josephson junctions, the underlying circuit, conductive blocks, and Josephson junctions can be positioned. Then, based on the positional layout results, the underlying circuit is fabricated on the substrate, conductive blocks are fabricated in the connection areas on the surface of the underlying circuit, and independent Josephson junctions are fabricated on the substrate. Ensuring that the underlying circuit, conductive blocks, and Josephson junctions are in the appropriate positions helps to optimize the performance of the chip product.

[0097] It should be noted that choosing to fabricate independent Josephson junctions on the substrate can effectively improve chip performance. The following describes the disadvantages of fabricating Josephson junctions that are directly connected to the underlying circuitry on the substrate, taking the example that both electrodes of the Josephson junction are made of aluminum.

[0098] Specifically, the Josephson junction, which is directly connected to the underlying circuit, is fabricated on the substrate. This can be achieved by photolithography of the photoresist to form an undercut structure, exposing the connection area of ​​the underlying circuit and the fabrication area on the substrate surface used to fabricate the Josephson junction. To avoid the presence of an oxide layer in the contact area between the Josephson junction and the underlying circuit, which could affect the superconducting contact, the natural oxide layer on the connection area of ​​the underlying circuit needs to be removed by ion milling. Then, through steps such as positive aluminum plating, oxidation, and oblique aluminum plating, the Josephson junction directly connected to the underlying circuit is fabricated on the substrate. However, while the connection area of ​​the underlying circuit is being ion milled, the fabrication area of ​​the substrate is also being ion milled, which will significantly damage the substrate portion within the fabrication area. This will result in a deterioration in the morphology of the aluminum film obtained by positive and oblique aluminum plating, affecting chip performance.

[0099] Compared to fabricating Josephson junctions directly connected to the underlying circuitry on the substrate, fabricating independent Josephson junctions on the substrate can effectively improve chip performance. This is because independent Josephson junctions are not directly connected to the underlying circuitry. Therefore, there is no need to use ion milling to remove the natural oxide layer on the connection area of ​​the underlying circuitry, nor is ion milling performed on the fabrication area of ​​the substrate. This avoids damage to the substrate and allows for better aluminum film morphology for both positive and oblique aluminum plating, thereby improving chip performance.

[0100] For example, fabricating an independent Josephson junction on a substrate can be achieved by photolithography to form an undercut structure, exposing the substrate surface for the Josephson junction fabrication area. Then, through steps such as positive aluminum plating, oxidation, and oblique aluminum plating, an independent Josephson junction is fabricated on the substrate. It is worth noting that when the Josephson junction is fabricated after the underlying circuitry, the remaining photoresist after photolithography covers the underlying circuitry to ensure it is not exposed. This prevents the aluminum film obtained through positive and oblique aluminum plating from directly connecting to the underlying circuitry, effectively separating the Josephson junction from the underlying circuitry, allowing it to form independently on the substrate surface. Conversely, when the Josephson junction is fabricated before the underlying circuitry, subsequent fabrication of the underlying circuitry also employs specific methods to prevent direct connection between the underlying circuitry and the Josephson junction, similarly allowing the Josephson junction to form independently on the substrate surface.

[0101] Step 202: Spin-coat the first photoresist onto the first chip product, and remove the first photoresist located in the transition area of ​​the first chip product to expose the first end and conductive block located in the transition area.

[0102] The transition region is used to connect the first end and the conductive block. This means that the connection formed in the transition region can connect the first end and the conductive block. Therefore, the underlying circuit can be connected to the first end through the conductive block and the connection formed in the transition region. In addition, since the independent Josephson junction is not directly connected to the underlying circuit, there is an isolation region between the independent Josephson junction and the underlying circuit. The transition region can connect the first end of the Josephson junction and the conductive block, which means that the transition region can cross the isolation region between the Josephson junction and the underlying circuit.

[0103] It is understandable that the first photoresist is first spin-coated onto the first chip product. Since the transition area is used to connect the first end and the conductive block, after removing the first photoresist in the transition area, the first end and the conductive block located in the transition area can be exposed, which facilitates the formation of a connection part in the transition area for connecting the first end and the conductive block.

[0104] It is worth noting that there can be one or more transition regions, and different transition regions do not intersect. For the transition region used to connect the first terminal and the underlying circuit, the area on the surface of the underlying circuit that does not need to be connected to the first terminal is located outside the transition region, ensuring that the area on the surface of the underlying circuit that does not need to be connected to the first terminal will not be connected to the first terminal, thus ensuring that the chip can operate normally. For example, assuming that the first electrode structure of the capacitor in the underlying circuit needs to be connected to the first terminal of the Josephson junction, and the second electrode structure does not need to be connected to the first terminal of the Josephson junction, then for the transition region used to connect the first terminal and the first electrode structure, the area on the surface of the second electrode structure is located outside the transition region.

[0105] It is worth noting that exposing the first end and the conductive block within the transition region refers to exposing the surface of the first end and the surface of the conductive block. Specifically, the transition region can cover all or part of the surface of the first end, and the transition region can cover all or part of the surface of the conductive block. Several coverage scenarios of the transition region are described below.

[0106] In the first case, the areas on the surface of the underlying circuit, except for the connection areas, are located outside the transition area.

[0107] In the second scenario, other regions on the surface of the underlying circuit that share the same structure as the connection region can be located within the transition region. When removing the natural oxide layer on the exposed first end and the conductive block, it is only necessary to consider completely removing the natural oxide layer on the surface of the first end and the conductive block. There is no need to concern ourselves with whether the natural oxide layer on the surface of other regions on the surface of the underlying circuit that share the same structure as the connection region has been completely removed. Moreover, since the removal difficulty of the natural oxide layer on the underlying circuit is usually greater than that of the natural oxide layer on the Josephson junction connection region, when the natural oxide layer on the surface of the first end and the conductive block is completely removed, the natural oxide layer on the surface of other regions on the surface of the underlying circuit that share the same structure as the connection region has not yet been completely removed, and will not cause damage to other regions on the surface of the underlying circuit that share the same structure as the connection region.

[0108] In the third case, the portion of the processing area on the side of the connection region away from the first end can be located in the transition region. Similarly, the portion of the processing area on the side of the first end away from the connection region can also be located in the transition region. The processing area refers to the area on the substrate other than the underlying circuit and the Josephson junction. By extending the transition region, the stability of the superconducting connection film can be enhanced.

[0109] For example, suppose the first electrode structure of the capacitor in the underlying circuit needs to be connected to the first end of the Josephson junction, the connection area is a part of the surface of the first electrode structure, and the other areas of the surface of the first electrode structure other than the connection area can be located in the transition area.

[0110] It should be noted that photoresists can be classified into positive and negative photoresists based on whether the exposed areas are removed or retained during the development process. For positive photoresists, the exposed areas undergo a chemical reaction and dissolve in the developer, while the unexposed areas remain insoluble. For negative photoresists, the exposed areas solidify due to cross-linking and remain insoluble in the developer, while the unexposed areas dissolve.

[0111] Specifically, a first photoresist is spin-coated onto the first chip product. This can be achieved by spin-coating a layer of the first photoresist onto the first chip product using a spin coater, followed by baking the first chip product on a hot plate to cure the first photoresist. The first photoresist can be either a positive or negative photoresist. Removal of the first photoresist located in the transition area of ​​the first chip product can be achieved by: If the first photoresist is positive, exposing the photoresist area corresponding to the transition area in the first photoresist using a photolithography machine, and then developing the exposed first photoresist using a developing machine to remove the first photoresist located in the transition area of ​​the first chip product; or, if the first photoresist is negative, exposing the area outside the photoresist area corresponding to the transition area in the first photoresist using a photolithography machine, and then developing the exposed first photoresist using a developing machine to remove the first photoresist located in the transition area of ​​the first chip product. The photolithography machine can be an electron beam exposure device, a laser direct writing device, or an ultraviolet exposure device, etc.

[0112] Step 203: Remove the exposed first end and the native oxide layer on the conductive block, and deposit a superconducting connection film in the transition region.

[0113] In this design, the superconducting connecting film connects the first end and the conductive block. This means the superconducting connecting film can bridge the isolation region between the Josephson junction and the underlying circuitry, allowing the first end of the Josephson junction to be connected to the conductive block via the superconducting connecting film. Because the thickness of the superconducting connecting film is typically small, it is classified as a superconducting thin film. The material of the superconducting connecting film can be superconducting materials such as tantalum or niobium.

[0114] Understandably, before depositing the superconducting interconnect film in the transition region, a natural oxide layer forms on the surface of the first end of the Josephson junction because the first end has been exposed to the atmosphere. Since the natural oxide layer is not superconducting, it is necessary to remove the natural oxide layer on the exposed first end to achieve good superconducting contact. This allows a good superconducting contact surface to be formed between the superconducting interconnect film and the first end. Similarly, a natural oxide layer also forms on the surface of the conductive block. In addition to removing the natural oxide layer on the exposed first end, it is also necessary to remove the natural oxide layer on the exposed conductive block to achieve a good superconducting contact surface between the superconducting interconnect film and the conductive block, effectively improving chip performance. Since the conductive block is connected to the underlying circuit, depositing the superconducting interconnect film in the transition region can sequentially connect the underlying circuit, the conductive block, the superconducting interconnect film, and the first end. The superconducting interconnect film is equivalent to a patch connecting the conductive block and the first end.

[0115] Then, since the natural oxide layers on the first end surface and the conductive block surface have the same thickness and composition, it means that the difficulty of removing the natural oxide layers on both surfaces is the same. During the natural oxide layer removal process, when the natural oxide layer on the conductive block surface is completely removed, the natural oxide layer on the first end surface will also be completely removed. This allows for the complete removal of the natural oxide layer without damaging the first end of the Josephson junction. Taking the removal of the natural oxide layer by ion milling as an example, precise control of the intensity and time of ion milling can completely remove the natural oxide layer without damaging the first end of the Josephson junction. Then, by depositing a superconducting connection film to connect the first end of the Josephson junction to the conductive block, the connection quality between the underlying circuit and the Josephson junction can be improved while ensuring successful connection between the underlying circuit and the Josephson junction. In addition, since the process of removing the natural oxide layer does not significantly damage the first end of the Josephson junction, the thickness of the first end can be limited to a smaller range during the fabrication of the first end of the Josephson junction, thereby improving chip performance.

[0116] Specifically, the exposed first end and the native oxide layer on the conductive block are removed, and a superconducting connection film is deposited in the transition region. This can be achieved by ion milling the first chip product using the ion source of an evaporation machine to remove the native oxide layer from the exposed first end and the conductive block. Then, the first chip product is kept in situ within the evaporation machine, without exposure to the atmosphere, and a first deposition layer formed of superconducting material is deposited on it. A vacuum environment is maintained within the evaporation machine to ensure that the exposed first end and the conductive block are not re-oxidized. The evaporation machine can be an electron beam evaporation coating device or a magnetron sputtering coating device, etc. The first deposition layer is located in the transition region and on the surface of the remaining first photoresist, serving as the superconducting connection film.

[0117] Step 204: Remove the first photoresist to obtain the second chip product.

[0118] Specifically, the first photoresist is stripped, which can be achieved by placing the first chip product in a photoresist stripping solution for cleaning. Since the photoresist stripping solution can dissolve the photoresist, after placing the first chip product in the solution and immersing it for a preset first time, the photoresist stripping solution can dissolve the first photoresist, thereby removing the first deposited layer on the surface of the first photoresist during the stripping process. Since the superconducting interconnect film is in contact with the first end of the Josephson junction and with the conductive block, the superconducting interconnect film will not be carried away by the first photoresist. This results in the second chip product including a substrate, a bottom circuit, a Josephson junction, a conductive block, and a superconducting interconnect film. The second chip product can be a superconducting chip, or a superconducting chip can be fabricated based on the second chip product.

[0119] Based on this, a first chip product is obtained by fabricating an underlying circuit and an independent Josephson junction on a substrate, and by fabricating a conductive block in the connection region on the surface of the underlying circuit. Then, by spin-coating a first photoresist onto the first chip product and removing the first photoresist located in the transition region of the first chip product, the first end and the conductive block located in the transition region can be exposed. Then, the native oxide layer on the exposed first end and the conductive block is removed. Since the material of the conductive block is the same as the material of the first end of the Josephson junction, native oxide layers of the same thickness and composition will form on the surface of the first end and the surface of the conductive block. This indicates that the difficulty of removing the native oxide layers on both surfaces is the same. During the etching process, when the native oxide layer on the surface of the conductive block is completely removed, the native oxide layer on the surface of the first end is also completely removed. This allows for the complete removal of the native oxide layer without damaging the first end of the Josephson junction. Then, a superconducting interconnect film is deposited in the transition region, and the first photoresist is stripped off to obtain the second chip product. In the second chip product, the first end of the Josephson junction is connected to the conductive block through the superconducting interconnect film. Since the first end of the Josephson junction is not over-etched during the removal of the native oxide layer, the connection quality between the underlying circuit and the Josephson junction can be improved while ensuring successful connection between the underlying circuit and the Josephson junction, thereby improving chip performance.

[0120] In one possible implementation, the process of fabricating the underlying circuitry on the substrate may include steps 201a to 201c (not shown in the figure):

[0121] Step 201a: Remove the native oxide layer on the substrate and deposit a circuit layer on the substrate;

[0122] Step 201b: Spin-coat a third photoresist onto the substrate and expose and develop the etching area corresponding to the underlying circuit in the third photoresist using an exposure method such as electron beam exposure, laser direct writing or ultraviolet exposure. The etching area is located in the circuit layer.

[0123] Step 201c: Etch the etched area and peel off the third photoresist to obtain a substrate with the underlying circuitry.

[0124] The circuit layer can be made of superconducting materials such as tantalum or niobium. The circuit layer is deposited on the substrate, specifically by depositing a circuit layer made of superconducting material on the first chip product using an evaporation machine.

[0125] It should be noted that since the thickness of the circuit layer is usually small, for example, the thickness of the circuit layer can range from 200nm to 400nm, and the material of the circuit layer is a superconducting material, the circuit layer belongs to the superconducting thin film. Depositing the circuit layer on the substrate is equivalent to growing a superconducting thin film on the substrate.

[0126] It is understandable that removing the natural oxide layer on the substrate allows the circuit layer to directly contact the substrate, thereby improving electrical performance. By spin-coating a third photoresist onto the substrate and then exposing and developing the etched areas corresponding to the underlying circuit in the third photoresist, the etched areas are used to indicate the etched portions in the circuit layer. Under the masking effect of the third photoresist, when etching the etched areas, only the portions of the circuit layer located within the etched areas can be removed, while the portions of the circuit layer covered by the third photoresist are retained. The retained portions of the circuit layer form the underlying circuit. Then, the third photoresist is peeled off to obtain a substrate with the underlying circuit. Using the third photoresist as a mask ensures the integrity of the unetched portions and improves the yield.

[0127] Specifically, the natural oxide layer on the substrate is removed, and a circuit layer is deposited on the substrate. This can be achieved by using an ion source built into the evaporation machine to perform ion milling on the substrate to remove the natural oxide layer. Then, without exposing the substrate to the atmosphere, the circuit layer is deposited in situ in the evaporation machine. The evaporation machine maintains a vacuum environment to ensure that the exposed substrate is not oxidized again.

[0128] Specifically, a third photoresist is spin-coated onto the substrate. This can be achieved by spin-coating a layer of the third photoresist onto the substrate using a spin coater, followed by baking the substrate on a hot plate to cure the third photoresist. The third photoresist can be either positive or negative. The etching areas corresponding to the underlying circuitry are then exposed and developed within the third photoresist. Specifically, when the third photoresist is positive, the photoresist area corresponding to the etching area is exposed using a photolithography machine, and then the exposed third photoresist is developed using a developing machine to remove the third photoresist within the etching area. Alternatively, when the third photoresist is negative, the area outside the photoresist area corresponding to the etching area is exposed using a photolithography machine, and then the exposed third photoresist is developed using a developing machine to remove the third photoresist within the etching area. The photolithography machine can be an electron beam exposure device, a laser direct-write device, or an ultraviolet exposure device, etc.

[0129] In one possible implementation, the process of fabricating a conductive block in the connection region on the surface of the underlying circuit may include steps 201d to 201f (not shown in the figure):

[0130] Step 201d: Spin-coat the second photoresist onto the substrate and remove the second photoresist located in the connection area on the surface of the bottom circuit.

[0131] Step 201e: Deposit conductive blocks within the connection region;

[0132] Step 201f: Remove the second photoresist to obtain a substrate with underlying circuitry and conductive blocks.

[0133] It is understandable that by spin-coating a second photoresist onto the substrate and then removing the second photoresist located in the connection area on the surface of the underlying circuit, the connection area on the surface of the underlying circuit can be exposed. Then, conductive blocks are deposited in the connection area. Finally, by peeling off the second photoresist, a substrate with the underlying circuit and conductive blocks is obtained, which can accurately form conductive blocks in the connection area on the surface of the underlying circuit and improve the yield.

[0134] Specifically, a second photoresist is spin-coated onto the substrate. This can be achieved by spin-coating a layer of the second photoresist onto the substrate using a spin coater, followed by baking the substrate on a hot plate to cure the second photoresist. The second photoresist can be either a positive or negative photoresist. Removing the second photoresist from the connection areas on the surface of the underlying circuit can be achieved by: If the second photoresist is positive, exposing the photoresist area corresponding to the connection area using a photolithography machine, followed by developing the exposed second photoresist to remove the second photoresist from the connection areas on the surface of the underlying circuit; or, if the second photoresist is negative, exposing the area outside the photoresist area corresponding to the connection area using a photolithography machine, followed by developing the exposed second photoresist to remove the second photoresist from the connection areas on the surface of the underlying circuit.

[0135] Specifically, a conductive block is deposited in the connection area. This can be achieved by depositing a second deposition layer formed of superconducting material on the substrate using an evaporation machine. The second deposition layer is located in the connection area and on the surface of the remaining first photoresist. The second deposition layer in the connection area serves as the conductive block. Then, the second photoresist is peeled off. Specifically, the substrate can be cleaned in a photoresist remover. Since the photoresist remover can dissolve the photoresist, after the substrate is placed in the photoresist remover and immersed for a preset second time, the photoresist remover can dissolve the second photoresist, thus removing the second deposition layer on the surface of the second photoresist during the peeling off process. Since the conductive block is in contact with the surface of the underlying circuit, the conductive block will not be carried away by the second photoresist, resulting in a substrate with the underlying circuit and the conductive block.

[0136] In one possible implementation, the second photoresist is a negative photoresist, and the process of removing the second photoresist located in the connection area on the surface of the underlying circuit may include steps 201d1 to 201d2 (not shown in the figure):

[0137] Step 201d1: Expose the second photoresist located outside the connection area on the surface of the bottom circuit;

[0138] Step 201d2: The substrate is placed in the developer corresponding to the second photoresist for development to remove the second photoresist located in the connection area and form an undercut structure composed of the remaining second photoresist.

[0139] Understandably, since the second photoresist is a negative photoresist, by exposing the second photoresist located outside the connection area on the surface of the underlying circuit, and then placing the substrate in the developer corresponding to the second photoresist for development, the photoresist in the exposed area of ​​the second photoresist will be retained, while the second photoresist in the connection area will be dissolved, thereby forming an inverted trapezoidal undercut structure. The formation of the undercut structure is very important for good peeling, because the sidewalls of the inverted trapezoidal undercut structure are concave inward. When depositing the conductive block, the conductive block cannot climb up to the surface of the second photoresist along the concave sidewalls, ensuring that the conductive block is separated from the second deposition layer on the remaining surface of the second photoresist. That is, the conductive block will not stick to the second deposition layer on the remaining surface of the second photoresist, and a complete conductive block can be obtained when peeling off the second photoresist.

[0140] In one possible implementation, the first photoresist is a negative photoresist, and the process of removing the first photoresist located in the transition region of the first chip product may include steps 202a to 202b (not shown in the figure):

[0141] Step 202a: Expose the first photoresist located outside the transition area of ​​the first chip product;

[0142] Step 202b: The first chip product is placed in the developer corresponding to the first photoresist for development to remove the first photoresist located in the transition area and form an undercut structure composed of the remaining first photoresist.

[0143] Understandably, since the first photoresist is a negative photoresist, by exposing the first photoresist located outside the transition area of ​​the first chip product, and then placing the first chip product in the developer corresponding to the first photoresist for development, the photoresist in the exposed area of ​​the first photoresist will be retained, while the first photoresist in the transition area will be dissolved, thus forming an inverted trapezoidal undercut structure. The formation of the undercut structure is very important for good peeling, because the sidewalls of the inverted trapezoidal undercut structure are concave inward. When depositing the superconducting connection film, the superconducting connection film cannot climb along the concave sidewalls to the surface of the first photoresist, ensuring that the superconducting connection film is separated from the first deposited layer on the remaining surface of the first photoresist. That is, the superconducting connection film and the first deposited layer on the remaining surface of the first photoresist will not adhere to each other, and a complete superconducting connection film can be obtained when peeling off the first photoresist.

[0144] In one possible implementation, before depositing conductive blocks in the connection region, the chip product fabrication method further includes: determining first ion milling parameters based on the material of the underlying circuit; and performing ion milling on the substrate having the underlying circuit based on the first ion milling parameters to remove the native oxide layer on the connection region.

[0145] It is understandable that before depositing the conductive block in the connection region, a natural oxide layer will form on the connection region of the underlying circuit surface due to its exposure to the atmosphere. Since the natural oxide layer is not superconducting, it is necessary to remove the exposed natural oxide layer in order to achieve good superconducting contact. This allows a good superconducting contact surface to be formed between the conductive block and the connection region, further improving the connection quality between the underlying circuit and the Josephson junction. Therefore, when using ion milling to remove the natural oxide layer, since the natural oxide layers of different materials are different, and the removal difficulty of different natural oxide layers usually varies, it is necessary to determine the first ion milling parameters for the natural oxide layer of the underlying circuit based on its material. For example, the first ion milling parameters include the intensity and time of the ion milling. Then, based on the first ion milling parameters, the substrate with the underlying circuit is targeted for ion milling. This allows for precise removal of the natural oxide layer of the underlying circuit without damaging it, avoiding any impact on chip performance.

[0146] Specifically, the native oxide layer on the connection area is removed. This can be achieved by configuring the ion source of the evaporation machine according to the first ion milling parameters, and then performing ion milling on the substrate to remove the native oxide layer on the exposed connection area. The substrate is then kept in situ within the evaporation machine, without being exposed to the atmosphere, and a second deposition layer formed of superconducting material is deposited on the substrate. A vacuum environment is maintained within the evaporation machine to ensure that the exposed connection area is not re-oxidized. The second deposition layer is located on the surface of the connection area and the remaining surface of the second photoresist, with the second deposition layer on the surface of the connection area serving as a conductive block.

[0147] In one possible implementation, removing the exposed first end and the native oxide layer on the conductive block can be achieved by determining second ion milling parameters based on the material of the conductive block; and then performing ion milling on the product having the first chip based on the second ion milling parameters to remove the exposed first end and the native oxide layer on the conductive block.

[0148] Therefore, when using ion milling to remove the native oxide layer, since the native oxide layers of different materials are different, and the removal difficulty of different native oxide layers usually varies, it is necessary to determine the second ion milling parameters for the native oxide layer of the conductive block based on the material of the conductive block. For example, the second ion milling parameters include the intensity and time of ion milling. Then, based on the second ion milling parameters, the first chip product is subjected to targeted ion milling treatment, which can accurately remove the native oxide layer of the conductive block without damaging the bottom conductive block. Since the material of the conductive block is the same as the material of the first end of the Josephson junction, the removal difficulty of the native oxide layer of the conductive block and the native oxide layer of the first end is the same. Therefore, during the process of removing the native oxide layer, when the native oxide layer on the surface of the conductive block is completely removed, the native oxide layer on the surface of the first end will also be completely removed. This can also achieve accurate removal of the native oxide layer of the first end without damaging the first end of the Josephson junction. This can improve the connection quality between the bottom circuit and the Josephson junction while ensuring successful connection between the bottom circuit and the Josephson junction, thereby improving chip performance.

[0149] Specifically, removing the exposed first end and the natural oxide layer on the conductive block can be achieved by configuring the ion source of the vapor deposition machine according to the second ion milling parameters, and then performing ion milling on the first chip product through the ion source to remove the exposed first end and the natural oxide layer on the conductive block.

[0150] In one possible implementation, a first photoresist is spin-coated onto the first chip product. Specifically, a first distance between the surface of the conductive block and the substrate is determined, and a first thickness range is determined based on the first distance. Spin-coating parameters are determined based on the first thickness range, and the first photoresist is spin-coated onto the first chip product based on the spin-coating parameters.

[0151] Wherein, the lower limit of the first thickness range is greater than twice the first distance, and the second distance between the surface of the first photoresist and the substrate is within the first thickness range.

[0152] It should be noted that, since there is an isolation region between the independent Josephson junction and the underlying circuit, the superconducting connection film used to connect the first end and the conductive block needs to span the isolation region between the Josephson junction and the underlying circuit. This means that the portion of the superconducting connection film covering the conductive block, the portion covering the isolation region, and the portion covering the first end are connected sequentially. Since the bottom of the portion of the superconducting connection film covering the isolation region is in contact with or close to the substrate, while the bottom of the portion of the superconducting connection film covering the conductive block is in contact with the conductive block, in order to ensure that the portion of the superconducting connection film covering the conductive block and the portion covering the isolation region can be connected, the thickness of the portion of the superconducting connection film covering the isolation region needs to be greater than the first distance. Since the various parts of the superconducting connection film are deposited simultaneously, the thickness of each part of the superconducting connection film is consistent, that is, the thickness of the portion of the superconducting connection film covering the conductive block needs to be greater than the first distance.

[0153] Based on this, during the subsequent stripping of the first photoresist, to ensure that the superconducting interconnect film and the first deposited layer on the remaining surface of the first photoresist are separated, i.e., that the superconducting interconnect film and the first deposited layer on the remaining surface of the first photoresist do not adhere to each other, the second distance between the surface of the first photoresist and the substrate must be greater than the distance between the surface of the superconducting interconnect film and the substrate. Therefore, the first thickness range of the second distance can be determined based on the distance between the surface of the superconducting interconnect film and the substrate. Since the thickness of the portion of the superconducting interconnect film covering the conductive block needs to be greater than the first distance, and the distance between the surface of the conductive block and the substrate is the first distance, the distance between the surface of the portion of the superconducting interconnect film covering the conductive block and the substrate is greater than twice the first distance. Therefore, the lower limit of the first thickness range can be determined to be greater than twice the first distance. Then, the spin coating parameters are determined based on the first thickness range. For example, the spin coating parameters may include the rotation speed of the spin coater and the spin coating time. Then, the first photoresist is spin-coated on the first chip product according to the spin coating parameters, so that the second distance between the surface of the first photoresist and the substrate is within the first thickness range. This allows the first deposited layer on the surface of the first photoresist to be removed during the stripping of the first photoresist, thus obtaining a complete superconducting interconnect film.

[0154] In one possible implementation, a superconducting connecting film is deposited in the transition region. Specifically, this can involve determining a distance difference between a second distance and a first distance, determining a second thickness range based on the first distance and the distance difference, determining deposition parameters based on the second thickness range, and depositing the superconducting connecting film in the transition region based on the deposition parameters, wherein the thickness of the superconducting connecting film is within the second thickness range.

[0155] The lower limit of the second thickness range is greater than the first distance, and the upper limit of the second thickness range is less than the distance difference.

[0156] Understandably, since the thickness of the portion covering the isolation area in the superconducting connection film needs to be greater than the first distance, it can be determined that the lower limit of the second thickness range of the superconducting connection film is greater than the first distance. Furthermore, during the subsequent stripping of the first photoresist, to ensure that the superconducting connection film and the first deposited layer on the remaining first photoresist surface are separated (i.e., that the superconducting connection film and the first deposited layer on the remaining first photoresist surface do not adhere), the distance between the surface of the portion of the superconducting connection film covering the conductive block and the substrate must be less than the second distance. The thickness of the superconducting connection film is equal to the surface thickness of the portion covering the conductive block. The difference between the distance between the surface and the substrate and the first distance determines that the second thickness range of the superconducting connection film is smaller than the difference between the second distance and the first distance. By limiting the thickness of the superconducting connection film to the second thickness range, it is possible to ensure that the portion of the superconducting connection film covering the conductive block is connected to the portion covering the isolation area, while ensuring that the superconducting connection film does not adhere to the first deposition layer on the remaining first photoresist surface. This enables the removal of the first deposition layer on the first photoresist surface when the first photoresist is peeled off, resulting in a complete superconducting connection film, and successful connection between the underlying circuit and the Josephson junction.

[0157] In one possible implementation, the underlying circuit includes a capacitor, which includes independently distributed first electrode structures and second electrode structures. The connection region is located on the surface of the first electrode structure. Independent Josephson junctions are fabricated on the substrate. Specifically, the fabrication region can be determined on the substrate surface based on the first electrode structure and the second electrode structure. An angled deposition method is used to fabricate independent Josephson junctions within the fabrication region.

[0158] The fabrication region is located between the first electrode structure and the second electrode structure, and there are gaps between the first electrode structure and the fabrication region, which can prevent the Josephson junction fabricated later from directly contacting the capacitor of the underlying circuit and ensure that the Josephson junction is independently distributed on the substrate.

[0159] Understandably, when the connection area is located on the surface of the first electrode structure, the first electrode structure, representing the capacitor in the underlying circuit, needs to be connected to the first end of the Josephson junction. In this case, when fabricating the Josephson junction, it is necessary to determine the fabrication area on the substrate surface according to the first electrode structure and the second electrode structure, so that the fabrication area is located between the first electrode structure and the second electrode structure. Then, by using the tilting deposition method, an independent Josephson junction is fabricated in the fabrication area, which can limit the Josephson junction to be located between the first electrode structure and the second electrode structure, thereby effectively reducing parasitic capacitance and parasitic inductance, avoiding electromagnetic interference, and improving the stability of the chip.

[0160] In one possible implementation, before removing the first photoresist located in the transition region of the first chip product, the chip product fabrication method further includes: determining a region to be processed on the substrate surface, excluding the underlying circuitry and the Josephson junction; determining a transition sub-region in the region to be processed based on the conductive block and the first terminal; and determining the transition region of the first chip product based on the connection region, the first terminal, and the transition sub-region.

[0161] The projection of the conductive block onto the substrate and the projection of the first end onto the substrate are both connected to the transition region.

[0162] Understandably, since the independent Josephson junction is not directly connected to the underlying circuit, there is an isolation region between the independent Josephson junction and the underlying circuit. This isolation region is located within the processing area. A transition sub-region is determined based on the conductive block and the first end in the processing area, such that the transition sub-region is connected to both the projection of the conductive block on the substrate and the projection of the first end on the substrate. Therefore, the transition sub-region can cross the isolation region between the Josephson junction and the underlying circuit. Then, based on the connection area, the first end, and the transition sub-region, the transition area of ​​the first chip product is determined, ensuring that the transition area can connect the first end and the conductive block.

[0163] In one possible implementation, before fabricating conductive blocks in the connection region on the surface of the underlying circuit, the chip product fabrication method further includes: determining multiple candidate regions on the surface of the first electrode structure according to a preset region shape; determining a first distance between each candidate region and the first end; sorting the multiple candidate regions according to the first distance; and determining a connection region in the multiple candidate regions according to the sorting result.

[0164] In this embodiment, the shape of each candidate region is a region shape, which can be set according to actual needs. For example, the region shape can be a rectangle, a circle, a trapezoid, etc., and this embodiment does not limit it. For example, the region shape is set to a rectangle, and the length of the region shape can be 5um to 10um, so that the bottom surface shape of the conductive block is also rectangular.

[0165] Understandably, the region shape is set according to actual needs. The region shape is used to characterize the bottom shape of the conductive block. Then, based on the region shape, multiple candidate regions are determined on the surface of the first electrode structure, so that each candidate region is a region shape. Each candidate region indicates a region that can be used to prepare the conductive block. Then, the first distance between each candidate region and the first end is determined. The multiple candidate regions are sorted according to the first distance. The connection region is determined among the multiple candidate regions according to the sorting result. For example, the multiple candidate regions are sorted in ascending order of the first distance. The first candidate region in the sorting result is taken as the connection region to ensure that the distance between the connection region and the first end is small, which can improve chip performance.

[0166] In one possible implementation, multiple candidate regions are sorted according to a first distance. Specifically, a second distance between each candidate region and the second electrode structure may be determined. The multiple candidate regions are then sorted according to a weighted result of the first and second distances.

[0167] The weight of the first distance is greater than the weight of the second distance. The weights of the first distance and the second distance can be set according to actual needs. For example, the weight of the first distance can be set to 0.8 and the weight of the second distance can be set to 0.2.

[0168] Understandably, while determining the first distance between each candidate region and the first end, it is also necessary to determine the second distance between each candidate region and the second electrode structure. Then, based on the weighted result of the first and second distances, the candidate regions are sorted. For example, the candidate regions are sorted in ascending order of the weighted result. Subsequently, the first candidate region in the sorted result can be used as the connection region. This ensures that the distance between the connection region and the first end is small, and also ensures that the distance between the connection region and the second electrode structure is small, which can improve chip performance. In addition, since the weight of the first distance is greater than that of the second distance, the first distance has a greater impact on the weighted result, and the candidate region with the smaller distance to the first end can be preferentially selected as the connection region.

[0169] The following details the complete process of chip product manufacturing.

[0170] First, the native oxide layer on the substrate is removed, and a circuit layer is deposited on the substrate. Then, a third photoresist is spin-coated onto the substrate, and the etching area corresponding to the underlying circuit is exposed and developed in the third photoresist using an electron beam exposure, laser direct writing, or ultraviolet exposure method. The etching area is located in the circuit layer. The etching area is then etched, and the third photoresist is stripped off to obtain a substrate with the underlying circuit.

[0171] Then, based on the preset region shape, multiple candidate regions are determined on the surface of the first electrode structure, wherein the shape of each candidate region is a region shape; a first distance between each candidate region and the first end is determined; a second distance between each candidate region and the second electrode structure is determined; the multiple candidate regions are sorted according to the weighted result of the first distance and the second distance, wherein the weight of the first distance is greater than the weight of the second distance; and a connection region is determined among the multiple candidate regions according to the sorting result.

[0172] Then, a second photoresist is spin-coated onto the substrate, and the second photoresist located outside the connection area on the surface of the underlying circuit is exposed; the substrate is placed in the developer corresponding to the second photoresist for development to remove the second photoresist located in the connection area, forming an undercut structure composed of the remaining second photoresist, wherein the second photoresist is a negative photoresist; the first ion milling parameters are determined according to the material of the underlying circuit; according to the first ion milling parameters, the substrate with the underlying circuit is subjected to ion milling to remove the native oxide layer on the connection area; conductive blocks are deposited in the connection area; the second photoresist is stripped off to obtain a substrate with the underlying circuit and conductive blocks; wherein the underlying circuit includes a capacitor, the capacitor includes independently distributed first electrode structure and second electrode structure, and the connection area is located on the surface of the first electrode structure.

[0173] Then, based on the first electrode structure and the second electrode structure, a fabrication area is determined on the substrate surface, wherein the fabrication area is located between the first electrode structure and the second electrode structure; using an angled deposition method, an independent Josephson junction is fabricated within the fabrication area to obtain a first chip product, wherein the material of the conductive block is the same as the material of the first end of the Josephson junction;

[0174] Then, a first distance between the surface of the conductive block and the substrate is determined, and a first thickness range is determined based on the first distance, wherein the lower limit of the first thickness range is greater than twice the first distance; spin coating parameters are determined based on the first thickness range, and a first photoresist is spin-coated onto the first chip product based on the spin coating parameters, wherein a second distance between the surface of the first photoresist and the substrate is within the first thickness range.

[0175] Then, the area to be processed, excluding the underlying circuitry and Josephson junction, is determined on the substrate surface; a transition sub-region is determined based on the conductive block and the first end in the area to be processed, wherein the projection of the conductive block on the substrate and the projection of the first end on the substrate are both connected to the transition sub-region; and a transition region of the first chip product is determined based on the connection region, the first end, and the transition sub-region.

[0176] Then, the first photoresist located outside the transition area of ​​the first chip product is exposed; the first chip product is placed in the developer corresponding to the first photoresist for development to remove the first photoresist located in the transition area, forming an undercut structure composed of the remaining first photoresist to expose the first end and the conductive block located in the transition area, wherein the transition area is used to connect the first end and the conductive block; wherein the first photoresist is a negative photoresist.

[0177] Then, based on the material of the conductive block, the second ion milling parameters are determined; based on the second ion milling parameters, the product with the first chip is subjected to ion milling to remove the exposed first end and the natural oxide layer on the conductive block.

[0178] Then, the distance difference between the second distance and the first distance is determined, and a second thickness range is determined based on the first distance and the distance difference, wherein the lower limit of the second thickness range is greater than the first distance, and the upper limit of the second thickness range is less than the distance difference; deposition parameters are determined based on the second thickness range, and a superconducting connection film is deposited in the transition region based on the deposition parameters, wherein the thickness of the superconducting connection film is within the second thickness range, and wherein the superconducting connection film is used to connect the first end and the conductive block.

[0179] Then, the first photoresist is peeled off to obtain the second chip product.

[0180] Based on this, a first chip product is obtained by fabricating an underlying circuit and an independent Josephson junction on a substrate, and by fabricating a conductive block in the connection region on the surface of the underlying circuit. Then, by spin-coating a first photoresist onto the first chip product and removing the first photoresist located in the transition region of the first chip product, the first end and the conductive block located in the transition region can be exposed. Then, the native oxide layer on the exposed first end and the conductive block is removed. Since the material of the conductive block is the same as the material of the first end of the Josephson junction, native oxide layers of the same thickness and composition will form on the surface of the first end and the surface of the conductive block. This indicates that the difficulty of removing the native oxide layers on both surfaces is the same. During the etching process, when the native oxide layer on the surface of the conductive block is completely removed, the native oxide layer on the surface of the first end is also completely removed. This allows for the complete removal of the native oxide layer without damaging the first end of the Josephson junction. Then, a superconducting interconnect film is deposited in the transition region, and the first photoresist is stripped off to obtain the second chip product. In the second chip product, the first end of the Josephson junction is connected to the conductive block through the superconducting interconnect film. Since the first end of the Josephson junction is not over-etched during the removal of the native oxide layer, the connection quality between the underlying circuit and the Josephson junction can be improved while ensuring successful connection between the underlying circuit and the Josephson junction, thereby improving chip performance.

[0181] It should be noted that when multiple Josephson junctions need to be connected to the underlying circuit, the above-described chip fabrication method can be used to connect each Josephson junction to the underlying circuit simultaneously, or the fabrication can be completed in multiple rounds, with each round using the above-described chip fabrication method to connect a portion of the Josephson junctions to the underlying circuit.

[0182] Similarly, when it is necessary to connect the two ends of the Josephson junction to the underlying circuit, the above-described chip fabrication method can be used to connect the two ends of the Josephson junction to the underlying circuit simultaneously, or the fabrication can be completed in two separate rounds. In the first round, the above-described chip fabrication method is used to connect the first end of the Josephson junction to the underlying circuit, and then in the second round, the above-described chip fabrication method is used to connect the second end of the Josephson junction to the underlying circuit.

[0183] The following example, which connects both ends of a Josephson junction to the underlying circuitry, will be used to illustrate the chip fabrication method in detail. Specifically, the first end of the Josephson junction needs to be connected to the first electrode structure of the capacitor in the underlying circuitry, and the second end of the Josephson junction needs to be connected to the second electrode structure of the capacitor in the underlying circuitry.

[0184] First, refer to Figure 3 , Figure 3 This is an optional cross-sectional schematic diagram of a substrate with capacitance provided in an embodiment of this disclosure.

[0185] Specifically, a circuit layer is fabricated on the substrate 100. For example, the substrate 100 is made of high-resistivity silicon, and the circuit layer can be a tantalum film. Then, by etching the circuit layer, a capacitor can be obtained. The capacitor includes a first electrode structure 101 and a second electrode structure 102.

[0186] Then, refer to Figure 4 , Figure 4 This is an optional cross-sectional view provided in an embodiment of the present disclosure after removing the second photoresist.

[0187] Specifically, a second photoresist 201 is spin-coated on the substrate 100, and then the second photoresist 201 located in the first connection region 301 on the surface of the first electrode structure 101 is removed, and the second photoresist 201 located in the second connection region 302 on the surface of the second electrode structure 102 is removed.

[0188] Then, refer to Figure 5 , Figure 5 This is an optional schematic diagram of ion milling of the connecting region provided in an embodiment of this disclosure.

[0189] Specifically, the connection area is subjected to ion milling treatment using the ion source of the vapor deposition machine, that is, the natural oxide layer in the first connection area 301 and the second connection area 302 is removed using accelerated plasma.

[0190] Then, refer to Figure 6 , Figure 6 This is an optional schematic diagram of depositing a connecting region according to an embodiment of this disclosure.

[0191] Specifically, after removing the natural oxide layer, superconducting materials are deposited in the first connection region 301 and the second connection region 302 in situ in the vapor deposition machine. For example, aluminum is deposited in the first connection region 301 and the second connection region 302 in the vapor deposition machine.

[0192] Then, refer to Figure 7 , Figure 7 This is an optional cross-sectional view of a conductive block formed in a connection region, provided as an embodiment of the present disclosure.

[0193] Specifically, after depositing the superconducting material, a deposition layer is formed. Specifically, a first conductive block 402 is formed in the first connection region 301, a second conductive block 403 is formed in the first connection region 301, and a second deposition layer 401 is formed on the surface of the second photoresist 201.

[0194] Then, refer to Figure 8 and Figure 9 , Figure 8 This is an optional cross-sectional view after the second photoresist has been stripped, according to an embodiment of this disclosure. Figure 9 This is a schematic diagram of an optional structure of a substrate with conductive blocks provided in an embodiment of this disclosure.

[0195] Specifically, after the second photoresist 201 is stripped off, the second photoresist 201 will take away the second deposited layer 401 on the surface, the first conductive block 402 will remain in the first connection area 301, and the second conductive block 403 will remain in the second connection area 302.

[0196] Then, refer to Figure 10 , Figure 10 This is an optional cross-sectional schematic diagram of a substrate having a capacitor and a Josephson junction, provided for an embodiment of this disclosure.

[0197] Specifically, using tilting deposition technology, a Josephson junction 103 is fabricated on a substrate to obtain a first chip product. To ensure that the material of the first conductive block 402 is the same as the material of the first end of the Josephson junction 103, both the first conductive block 402 and the first end of the Josephson junction 103 can be made of aluminum. To ensure that the material of the second conductive block 403 is the same as the material of the second end of the Josephson junction 103, both the second conductive block 403 and the second end of the Josephson junction 103 can be made of aluminum.

[0198] Then, refer to Figure 11 , Figure 11 This is an optional schematic diagram of ion milling of a transition region provided by an embodiment of this disclosure.

[0199] Specifically, a first photoresist 202 is spin-coated onto the first chip product, and then the first photoresist 202 located in the first transition region 501 and the first photoresist 202 in the first transition region 502 are removed. The first transition region 501 is used to connect the first electrode structure 101 and the first end of the Josephson junction 103, and the second transition region 502 is used to connect the second electrode structure 102 and the second end of the Josephson junction 103. Then, the first transition region 501 and the second transition region 502 are subjected to ion milling by the ion source of the vapor deposition machine, that is, the natural oxide layer in the first transition region 501 and the second transition region 502 is removed by using accelerated plasma.

[0200] Then, refer to Figure 12 , Figure 12 This is an optional schematic diagram of depositing in a transition region, provided as an embodiment of the present disclosure.

[0201] Specifically, after removing the natural oxide layer, superconducting materials are deposited in situ in the vapor deposition machine into the first transition region 501 and the second transition region 502, for example, tantalum is deposited by vapor deposition machine.

[0202] Then, refer to Figure 13 and Figure 14 , Figure 13 This is an optional cross-sectional schematic diagram of a second chip product provided in an embodiment of this disclosure. Figure 14 This is a schematic diagram of an optional structure of a second chip product provided in an embodiment of this disclosure.

[0203] Specifically, after depositing the superconducting material, a deposition layer is formed. Specifically, a first superconducting connection film 601 is formed in the first transition region 501, and a second superconducting connection film 602 is formed in the second transition region 502. After peeling off the first photoresist 202, the first photoresist 202 will carry away the deposited superconducting material on the surface. The first superconducting connection film 601 remains in the first transition region 501, and the second superconducting connection film 602 remains in the second transition region 502. The first electrode structure 101 and the first end of the Josephson junction 103 are connected through the first superconducting connection film 601, and the second electrode structure 102 and the second end of the Josephson junction 103 are connected through the second superconducting connection film 602.

[0204] Figure 15 This is an optional schematic diagram of a chip product fabrication system provided in an embodiment of this disclosure. This chip product fabrication system can be implemented as production line equipment; such as... Figure 15 As shown, the chip product fabrication system includes: a spin coater 1501, a photolithography machine 1502, a developer 1503, an etching machine 1504, a vapor deposition machine 1505, and a resist remover 1506.

[0205] Evaporation machine 1505, spin coater 1501, lithography machine 1502, developer 1503, etching machine 1504, and resist remover 1506 are used to prepare a bottom layer circuit on a substrate, prepare a conductive block in the connection area on the surface of the bottom layer circuit, prepare an independent Josephson junction on the substrate, and obtain a first chip product, wherein the material of the conductive block is the same as the material of the first end of the Josephson junction.

[0206] Spin coater 1501, photolithography machine 1502 and developer 1503 are used to spin coat a first photoresist onto a first chip product, remove the first photoresist located in a transition area of ​​the first chip product, so as to expose a first end and a conductive block located in the transition area, wherein the transition area is used to connect the first end and the conductive block.

[0207] Evaporation machine 1505 is used to remove the natural oxide layer on the exposed first end and the conductive block, and to deposit a superconducting connection film in the transition region, wherein the superconducting connection film is used to connect the first end and the conductive block;

[0208] The photoresist stripper 1506 is used to strip the first photoresist to obtain the second chip product.

[0209] In one possible implementation, the spin coater 1501, the photolithography machine 1502, and the developer 1503 are also used to spin coat a second photoresist onto the substrate and remove the second photoresist located in the connection area on the surface of the underlying circuit.

[0210] The vapor deposition machine 1505 is also used to deposit conductive blocks in the connection area;

[0211] The photoresist stripper 1506 is also used to strip the second photoresist to obtain a substrate with underlying circuitry and conductive blocks.

[0212] In one possible implementation, the second photoresist is a negative photoresist;

[0213] The lithography machine 1502 is also used to expose a second photoresist located outside the connection area on the surface of the underlying circuit.

[0214] The developing machine 1503 is also used to place the substrate in the developing solution corresponding to the second photoresist for development, so as to remove the second photoresist located in the connection area and form an undercut structure composed of the remaining second photoresist.

[0215] In one possible implementation, the chip fabrication system also includes a computing device (not shown in the figure), and the vapor deposition machine 1505 is equipped with an ion source;

[0216] A computing device for determining the first ion milling parameters based on the material of the underlying circuitry;

[0217] An ion source is used to perform ion milling on a substrate with underlying circuitry according to first ion milling parameters to remove the native oxide layer on the connection area.

[0218] In one possible implementation, the chip fabrication system also includes measuring instruments (not shown in the figure);

[0219] Measuring instruments and computing devices are used to determine a first distance between the surface of the conductive block and the substrate, and to determine a first thickness range based on the first distance, wherein the lower limit of the first thickness range is greater than twice the first distance;

[0220] The spin coater 1501 is also used to determine spin coating parameters according to a first thickness range, and spin coat a first photoresist onto a first chip product according to the spin coating parameters, wherein the second distance between the surface of the first photoresist and the substrate is within the first thickness range.

[0221] In one possible implementation, the computing device is further configured to determine a distance difference between a second distance and a first distance, and to determine a second thickness range based on the first distance and the distance difference, wherein the lower limit of the second thickness range is greater than the first distance, and the upper limit of the second thickness range is less than the distance difference;

[0222] The vapor deposition machine 1505 is also used to determine deposition parameters based on a second thickness range, and to deposit a superconducting connection film in a transition region based on the deposition parameters, wherein the thickness of the superconducting connection film is within the second thickness range.

[0223] In one possible implementation, the underlying circuitry includes a capacitor, which includes independently distributed first electrode structures and second electrode structures. The connection region is located on the surface of the first electrode structure. The chip product fabrication system also includes design equipment (not shown in the figure).

[0224] Design equipment for determining a fabrication region on a substrate surface based on a first electrode structure and a second electrode structure, wherein the fabrication region is located between the first electrode structure and the second electrode structure;

[0225] Evaporation machine 1505, spin coater 1501, photolithography machine 1502, developer 1503, and resist remover 1506 are used to prepare independent Josephson junctions in the preparation area using an angled coating method.

[0226] In one possible implementation, the device is also designed to define the area to be processed on the substrate surface, in addition to the underlying circuitry and the Josephson junction.

[0227] The design equipment is also used to determine a transition sub-region based on the conductive block and the first end in the area to be processed, wherein the projection of the conductive block on the substrate and the projection of the first end on the substrate are both connected to the transition sub-region.

[0228] The design equipment is also used to determine the transition region of the first chip product based on the connection region, the first end, and the transition sub-region.

[0229] In one possible implementation, the device is designed to further determine multiple candidate regions on the surface of the first electrode structure according to a preset region shape, wherein the shape of each candidate region is a region shape.

[0230] The design equipment is also used to determine the first distance between each candidate region and the first end;

[0231] The design device is also used to sort multiple candidate regions based on a first distance, and to determine a connected region among the multiple candidate regions based on the sorting result.

[0232] In one possible implementation, the device is designed to further determine a second distance between each candidate region and the second electrode structure;

[0233] The design device is also used to sort multiple candidate regions based on a weighted result of a first distance and a second distance, wherein the weight of the first distance is greater than the weight of the second distance.

[0234] In one possible implementation, the computing device is also used to determine the second ion milling parameters based on the material of the conductive block;

[0235] The ion source is also used to perform ion milling on the product with the first chip according to the second ion milling parameters, to remove the exposed first end and the natural oxide layer on the conductive block.

[0236] In one possible implementation, the first photoresist is a negative photoresist, and the photolithography machine 1502 is also used to expose the first photoresist located outside the transition area of ​​the first chip product.

[0237] The developing machine 1503 is also used to place the first chip product in the developing solution corresponding to the first photoresist for development, so as to remove the first photoresist located in the transition area and form an undercut structure composed of the remaining first photoresist.

[0238] In one possible implementation, the vapor deposition machine 1505 is also used to remove the native oxide layer on the substrate and deposit a circuit layer on the substrate;

[0239] The spin coater 1501, the photolithography machine 1502, and the developer 1503 are also used to spin coat a third photoresist on a substrate. The third photoresist is exposed and developed to reveal the etching area corresponding to the underlying circuit, using an exposure method such as electron beam exposure, laser direct writing, or ultraviolet exposure. The etching area is located in the circuit layer.

[0240] The etching machine 1504 and the photoresist remover 1506 are also used to etch the etched area and remove the third photoresist to obtain a substrate with the underlying circuitry.

[0241] Optionally, the system also includes a control chip, which can be electrically connected to at least one of the aforementioned spin coater 1501, lithography machine 1502, developer 1503, etching machine 1504, vapor deposition machine 1505, and resist remover 1506, to control the spin coater 1501, lithography machine 1502, developer 1503, etching machine 1504, vapor deposition machine 1505, and resist remover 1506, etc.

[0242] Optionally, the production line equipment also includes a power supply to provide power to electrical equipment such as control chips, spin coater 1501, lithography machine 1502, developer 1503, etching machine 1504, vapor deposition machine 1505, and resist remover 1506.

[0243] Optionally, the machines can be spatially connected via conveyor belts, or the movement of the prepared material between the machines can be accomplished using robotic arms.

[0244] Optionally, the production line equipment also includes a memory that can be used to store at least one computer instruction. The processor executes the at least one computer instruction to cause the production line equipment to perform the chip product manufacturing method described above.

[0245] In summary, the scheme shown in this disclosure obtains a first chip product by fabricating an underlying circuit and an independent Josephson junction on a substrate, and fabricating a conductive block in the connection region on the surface of the underlying circuit. Then, by spin-coating a first photoresist onto the first chip product and removing the first photoresist located in the transition region of the first chip product, the first end and the conductive block located in the transition region can be exposed. Then, the native oxide layer on the exposed first end and the conductive block is removed. Since the material of the conductive block is the same as the material of the first end of the Josephson junction, native oxide layers of the same thickness and composition will be formed on the surface of the first end and the surface of the conductive block, indicating that the removal difficulty of the native oxide layers on both surfaces is the same. During the removal of the native oxide layer, when the native oxide layer on the surface of the conductive block is completely removed, the native oxide layer on the surface of the first end is also completely removed. This allows for the complete removal of the native oxide layer without damaging the first end of the Josephson junction. Then, a superconducting interconnect film is deposited in the transition region, and the first photoresist is stripped off to obtain the second chip product. In the second chip product, the first end of the Josephson junction is connected to the conductive block through the superconducting interconnect film. Since the first end of the Josephson junction is not over-etched during the removal of the native oxide layer, the connection quality between the underlying circuit and the Josephson junction can be improved while ensuring successful connection between the underlying circuit and the Josephson junction, thereby improving chip performance.

[0246] Please refer to Figure 16 , Figure 16 This is an optional schematic diagram illustrating an application scenario of the solution provided in the embodiments of this disclosure. For example... Figure 16 As shown, the application scenario can be a superconducting computing platform, which includes: computing device 1601, dilution refrigerator 1602, control device 1603 and computer 1604.

[0247] The computing device 1601 is a circuit operating on physical bits. The computing device 1601 can be implemented as a chip, such as a superconducting chip located near absolute zero. This superconducting chip can be prepared using the methods described in the above embodiments of this disclosure. The dilution refrigerator 1602 is used to provide an absolute zero environment for the superconducting chip.

[0248] Control device 1603 controls computing device 1601, and computer 1604 controls control device 1603. For example, a written program is compiled into instructions by software in computer 1604 and sent to control device 1603 (e.g., an electronic / microwave control system). Control device 1603 converts these instructions into electronic / microwave control signals, which are then input to dilution refrigerator 1602 to control the superconducting bit at a temperature below 10 mK. The reading process is the reverse; the read waveform is sent to computing device 1601.

[0249] In one exemplary embodiment, a computer-readable storage medium is also provided, which stores at least one computer instruction that is executed by a processor in a chip product fabrication system to cause the chip product fabrication system to perform the chip product fabrication method described above.

[0250] In an exemplary embodiment, a computer program product or computer program is also provided, which includes computer instructions stored in a computer-readable storage medium. A processor of a chip product fabrication system reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the chip product fabrication system to perform the described chip product fabrication method.

[0251] This disclosure also provides a superconducting chip, which includes:

[0252] Substrate, underlying circuitry on the substrate, and independent Josephson junctions on the substrate;

[0253] A conductive block located in the connection area on the surface of the underlying circuit, wherein the material of the conductive block is the same as the material of the first end of the Josephson junction;

[0254] A superconducting connecting membrane is used to connect the first end and the conductive block.

[0255] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the claims.

[0256] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.

Claims

1. A method for manufacturing a chip product, characterized in that, include: A bottom circuit is fabricated on a substrate, a conductive block is fabricated in the connection region on the surface of the bottom circuit, and an independent Josephson junction is fabricated on the substrate to obtain a first chip product, wherein the material of the conductive block is the same as the material of the first end of the Josephson junction. A first photoresist is spin-coated onto the first chip product, and the first photoresist located in the transition region of the first chip product is removed to expose the first end and the conductive block located in the transition region, wherein the transition region is used to connect the first end and the conductive block; Remove the exposed first end and the native oxide layer on the conductive block, and deposit a superconducting connection film in the transition region, wherein the superconducting connection film is used to connect the first end and the conductive block; The first photoresist is peeled off to obtain the second chip product.

2. The chip product manufacturing method according to claim 1, characterized in that, The process of fabricating conductive blocks in the connection region on the surface of the underlying circuit includes: A second photoresist is spin-coated onto the substrate to remove the second photoresist located in the connection area on the surface of the underlying circuit. A conductive block is deposited within the connection region; The second photoresist is stripped off to obtain the substrate having the underlying circuitry and the conductive block.

3. The chip product manufacturing method according to claim 2, characterized in that, The second photoresist is a negative photoresist, and the removal of the second photoresist located in the connection area on the surface of the underlying circuit includes: The second photoresist located outside the connection area on the surface of the underlying circuit is exposed; The substrate is placed in the developer corresponding to the second photoresist for development to remove the second photoresist located in the connection area, forming an undercut structure composed of the remaining second photoresist.

4. The chip product manufacturing method according to claim 2, characterized in that, Before depositing the conductive block in the connection region, the chip product fabrication method further includes: The first ion milling parameters are determined based on the material of the underlying circuit. According to the first ion milling parameters, the substrate having the underlying circuit is subjected to ion milling to remove the natural oxide layer on the connection region.

5. The chip product manufacturing method according to claim 1, characterized in that, The spin coating of the first photoresist onto the first chip product includes: A first distance is determined between the surface of the conductive block and the substrate, and a first thickness range is determined based on the first distance, wherein the lower limit of the first thickness range is greater than twice the first distance; Spin coating parameters are determined based on the first thickness range, and a first photoresist is spin-coated onto the first chip product according to the spin coating parameters, wherein the second distance between the surface of the first photoresist and the substrate is within the first thickness range.

6. The chip product manufacturing method according to claim 5, characterized in that, The deposition of the superconducting connection film in the transition region includes: Determine the distance difference between the second distance and the first distance, and determine a second thickness range based on the first distance and the distance difference, wherein the lower limit of the second thickness range is greater than the first distance, and the upper limit of the second thickness range is less than the distance difference; Deposition parameters are determined based on the second thickness range, and a superconducting connection film is deposited in the transition region according to the deposition parameters, wherein the thickness of the superconducting connection film is within the second thickness range.

7. The chip product manufacturing method according to claim 1, characterized in that, The underlying circuit includes a capacitor, the capacitor comprising independently distributed first electrode structures and second electrode structures, the connection region being located on the surface of the first electrode structure, and the fabrication of independent Josephson junctions on the substrate comprising: Based on the first electrode structure and the second electrode structure, a fabrication region is defined on the substrate surface, wherein the fabrication region is located between the first electrode structure and the second electrode structure; Independent Josephson junctions are fabricated within the fabrication area using an angled coating method.

8. The chip product manufacturing method according to claim 7, characterized in that, Before removing the first photoresist located in the transition region of the first chip product, the chip product fabrication method further includes: A processing area is defined on the substrate surface, excluding the underlying circuitry and the Josephson junction; A transition sub-region is determined in the area to be processed based on the conductive block and the first end, wherein the projection of the conductive block on the substrate and the projection of the first end on the substrate are both connected to the transition sub-region. The transition region of the first chip product is determined based on the connection region, the first end, and the transition sub-region.

9. The chip product manufacturing method according to claim 7, characterized in that, Before fabricating conductive blocks in the connection region on the surface of the underlying circuit, the chip product fabrication method further includes: According to a preset region shape, multiple candidate regions are determined on the surface of the first electrode structure, wherein the shape of each candidate region is the same as the region shape; Determine the first distance between each of the candidate regions and the first end; The candidate regions are sorted according to the first distance, and a connecting region is determined among the candidate regions based on the sorting result.

10. The chip product manufacturing method according to claim 9, characterized in that, The step of sorting the candidate regions according to the first distance includes: Determine the second distance between each of the candidate regions and the second electrode structure; Based on the weighted result of the first distance and the second distance, the candidate regions are sorted, wherein the weight of the first distance is greater than the weight of the second distance.

11. The chip product manufacturing method according to claim 1, characterized in that, The removal of the exposed first end and the native oxide layer on the conductive block includes: The second ion milling parameters are determined based on the material of the conductive block; According to the second ion milling parameters, the product with the first chip is subjected to ion milling to remove the exposed first end and the natural oxide layer on the conductive block.

12. The chip product manufacturing method according to claim 1, characterized in that, The first photoresist is a negative photoresist, and the removal of the first photoresist located in the transition region of the first chip product includes: The first photoresist located outside the transition region of the first chip product is exposed; The first chip product is placed in the developer corresponding to the first photoresist for development to remove the first photoresist located in the transition area, forming an undercut structure composed of the remaining first photoresist.

13. The chip product manufacturing method according to claim 1, characterized in that, The fabrication of the underlying circuit on the substrate includes: Remove the native oxide layer on the substrate and deposit a circuit layer on the substrate; A third photoresist is spin-coated on the substrate, and an etching region corresponding to the underlying circuit is exposed and developed in the third photoresist using an electron beam exposure, laser direct writing, or ultraviolet exposure method. The etching region is located in the circuit layer. The etched area is etched, and the third photoresist is stripped off to obtain the substrate having the underlying circuit.

14. A chip product fabrication system, characterized in that, The system includes: a spin coater, a photolithography machine, a developing machine, an etching machine, a vapor deposition machine, and a resist remover; The evaporation machine, the spin coater, the photolithography machine, the developing machine, the etching machine, and the resist remover are used to fabricate a bottom layer circuit on a substrate, fabricate a conductive block in the connection area on the surface of the bottom layer circuit, and fabricate an independent Josephson junction on the substrate to obtain a first chip product, wherein the material of the conductive block is the same as the material of the first end of the Josephson junction. The spin coater, the photolithography machine, and the developing machine are used to spin coat the first photoresist onto the first chip product and remove the first photoresist located in the transition region of the first chip product to expose the first end and the conductive block located in the transition region, wherein the transition region is used to connect the first end and the conductive block. The vapor deposition machine is used to remove the exposed first end and the native oxide layer on the conductive block, and to deposit a superconducting connection film in the transition region, wherein the superconducting connection film is used to connect the first end and the conductive block; The photoresist stripper is used to peel off the first photoresist to obtain the second chip product.

15. A superconducting chip, characterized in that, include: A substrate, an underlying circuitry on the substrate, and a separate Josephson junction on the substrate; A conductive block located in the connection area on the surface of the underlying circuit, wherein the material of the conductive block is the same as the material of the first end of the Josephson junction; A superconducting connecting membrane is used to connect the first end and the conductive block.

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