Tsv integration process method and semiconductor device

Abstract

The application discloses a TSV integrated process method and a semiconductor device. The TSV integrated process method comprises the following steps: 1) completing a front-end device FEOL process; 2) etching to form a TSV deep groove; 3) performing tungsten filling on a conventional WCVD machine, and removing tungsten on a wafer surface through tungsten etching back to form a V-shaped groove on a TSV top; 4) adopting electrochemical deposition ECP and copper chemical mechanical polishing Cu CMP to fill the V-shaped groove; and 5) performing a back-end interconnection BEOL process. The application can solve the technical problems of high stress leading to wafer warping, incapability of adapting to subsequent damascene processes, and dependence of Cu TSV on advanced special equipment and high cost existing in the prior art.

Description

Technical Field

[0001] This invention relates to the field of semiconductors, and in particular to a TSV integration process method and a semiconductor device manufactured using the TSV integration process method. Background Technology

[0002] Through-SiliconVia (TSV) is a key interconnect technology for advanced 3D integrated circuits and system-in-package (SoC). By forming vertical conductive channels within the silicon substrate, it overcomes the physical limitations of traditional planar chip interconnects, enabling vertical 3D integration and significantly improving integration density, shortening signal transmission paths, and reducing parasitic parameters. Compared to traditional wire bonding and flip-chip bonding, TSV offers the shortest electrical transmission path, significantly reducing line resistance-capacitance (RC) delay and improving chip signal transmission speed. It also boasts excellent electromagnetic shielding and anti-interference performance, meeting the application requirements of high-frequency, high-speed, and high-reliability semiconductor devices.

[0003] Metallization is a core technology in the TSV front-side fabrication process that determines conductivity, structural stability, and process compatibility, directly affecting the TSV's on-resistance, mechanical stress, and subsequent process adaptability. Depending on the filler metal material, the current mainstream TSV metallization processes are divided into two technical routes: copper-based TSV (Cu TSV) and tungsten-based TSV (W TSV). These two routes differ significantly in material properties, equipment requirements, process difficulty, and application scenarios.

[0004] In the Cu TSV technology route, copper (Cu) possesses advantages such as low resistivity, low hardness, and low residual stress, enabling low-loss, high-reliability vertical interconnects, making it suitable for high aspect ratio TSV structures. However, this route places stringent requirements on process equipment, necessitating the introduction of various advanced dedicated process equipment, including barrier / seed deposition equipment adapted to high aspect ratio structures, electrochemical deposition (ECP) equipment, and Cu anneal equipment. The high costs of equipment procurement, maintenance, and process development significantly increase chip manufacturing costs, hindering low-cost, large-scale semiconductor product applications.

[0005] In the W TSV technology route, tungsten (W) can be filled using conventional tungsten chemical vapor deposition (WCVD) equipment without the need for additional dedicated equipment. This makes it highly compatible with existing semiconductor production lines, and the equipment investment and process modification costs are significantly lower than CuTSV. However, tungsten material has high intrinsic stress, which can easily generate significant residual stress after deep trench filling in TSV. Stress accumulation can directly lead to wafer warpage, structural deformation, and even silicon wafer cracking, severely affecting yield and device reliability. At the same time, due to the challenges of high stress and surface morphology control, the industry has not yet developed mature and stable 12-inch W TSV mass production products and integrated solutions. Summary of the Invention

[0006] The summary of this invention introduces a series of simplified concepts, all of which are simplifications of existing technologies in the field, and will be further explained in detail in the detailed description section. This summary is not intended to limit the key features and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0007] The technical problem to be solved by this invention is to address the shortcomings of existing W TSV processes, such as high stress leading to wafer warpage and incompatibility with subsequent Damascus processes, as well as the high cost of Cu TSV which requires advanced dedicated equipment. This invention provides a TSV integration process method that does not rely on advanced dedicated equipment, can solve the problem of high stress warpage in W TSV, and is compatible with Damascus processes.

[0008] To solve the above-mentioned technical problems, the present invention provides a TSV integration process method, which includes the following steps: 1) Complete the FEOL process for the front-end devices; 2) Etching forms a deep TSV trench; 3) Tungsten filling is performed on a conventional WCVD machine, and tungsten on the wafer surface is removed by tungsten etch-back, forming a V-groove on the top of the TSV; 4) The V-groove was filled using electrochemical deposition (ECP) followed by copper chemical mechanical polishing (Cu CMP). 5) Perform back-end interconnection BEOL process.

[0009] Optionally, the TSV integration process method can be further improved, wherein the tungsten back etching is used to eliminate the high stress caused by tungsten filling and avoid wafer warping.

[0010] Optionally, the TSV integration process method can be further improved, wherein the copper chemical mechanical polishing (Cu CMP) is used to achieve global planarization of the wafer surface, providing a smooth surface for subsequent damascus processes.

[0011] Optionally, the TSV integration process method can be further improved to adapt to W TSV manufacturing of 12-inch wafers.

[0012] Optionally, the TSV integration process method can be further improved to integrate the TSV process between FEOL and BEOL.

[0013] The present invention provides a semiconductor device manufactured using any one of the above-described TSV integrated process methods, wherein the semiconductor device is a MOSFET, BJT, DRAM, SRAM, Flash, or 3D NAND.

[0014] The working principle of the present invention is explained below based on the above technical solution; The core working principle of this invention is a TSV integrated mechanism combining stepwise stress regulation and surface morphology reconstruction. First, the tungsten (W) filling of the TSV deep trench is completed using conventional tungsten chemical vapor deposition (WCVD) equipment in semiconductor production lines, while retaining the compatibility advantages of W TSV equipment and avoiding the introduction of high-end equipment dedicated to Cu TSV. Subsequently, the excess tungsten layer covering the wafer surface is precisely removed using the tungsten etch-back process, releasing the high residual stress generated by the tungsten material filling from the source and eliminating the risk of wafer warpage caused by stress accumulation. This etch-back process naturally forms a V-groove structure at the top of the TSV opening. Finally, a combination of electrochemical deposition (ECP) and copper chemical mechanical polishing (CuCMP) processes is used to fill and globally planarize the V-groove, transforming the uneven morphology into a flat silicon wafer surface that can be directly connected to subsequent processes. This makes the tungsten-based TSV structure seamlessly compatible with standard damascus interconnect processes, ultimately achieving stable and reliable TSV process integration between front-end devices (FEOL) and back-end interconnects (BEOL).

[0015] Based on the above technical solution and working principle, the present invention can achieve at least the following technical effects; 1. This invention can significantly reduce equipment investment and manufacturing costs; Existing Cu TSV routes rely on complete sets of specialized equipment, resulting in high costs and hindering low-cost, large-scale production.

[0016] This invention completely eliminates the need for dedicated high aspect ratio barrier / seed equipment, ECP equipment, and Cu annealing equipment required for Cu TSV. The core tungsten filling step can be completed using only conventional WCVD equipment. The process route has a high degree of compatibility with existing production lines, and the costs of equipment investment, modification, and maintenance are significantly reduced.

[0017] 2. This invention can fundamentally solve the problem of high stress warpage in WTSV wafers and is suitable for mass production of 12-inch wafers; Traditional W TSV process only performs full filling without stress release steps. High stress cannot be discharged, which can easily cause excessive warping of large-size wafers. To date, there is no mature 12-inch W TSV product in the industry.

[0018] This invention actively removes the tungsten layer on the wafer surface through the W Etch Back process, directly releasing the high internal stress generated by tungsten filling. It suppresses wafer warping, deformation, and even breakage caused by stress accumulation from a mechanistic perspective, and can be stably applied to TSV manufacturing of 12-inch wafers.

[0019] 3. This invention can achieve perfect compatibility with the Damascus process, and integrate the entire process from FEOL to BEOL. Traditional W TSV processes cannot control surface morphology and are incompatible with damascus processes, making it difficult to integrate into standard CMOS manufacturing processes.

[0020] This invention uses ECP+Cu CMP to precisely fill the V-shaped groove formed by W Etch Back, obtaining a globally planarized surface that can be directly connected to the standard damascus process, ensuring the smooth progress of back-end interconnect layer deposition, photolithography, etching and other processes, and achieving stable embedding of TSV process between FEOL and BEOL.

[0021] 4. This invention combines the advantages of two technical routes and is easy to industrialize; Existing technologies can only choose between Cu TSV and W TSV, which cannot balance cost, stress and process compatibility.

[0022] This invention retains the advantages of conventional equipment compatibility and low cost of W TSV, as well as the advantages of low stress and strong process adaptability of Cu TSV, while avoiding the inherent defects of high cost of Cu TSV and high stress of W TSV. The process steps are simple, the parameters are adjustable, and the reproducibility is strong, which can quickly realize industrialization. Attached Figure Description

[0023] The accompanying drawings are intended to illustrate the general characteristics of the methods, structures, and / or materials used in specific exemplary embodiments of the invention, supplementing the description in the specification. However, the drawings are schematic diagrams not drawn to scale and may not accurately reflect the precise structural or performance characteristics of any of the given embodiments. The drawings should not be construed as limiting or restricting the range of numerical values ​​or properties covered by exemplary embodiments of the invention. The invention will now be described in further detail with reference to the accompanying drawings and specific embodiments.

[0024] Figure 1 This is a schematic diagram of the intermediate structure of the present invention. Figure 1 .

[0025] Figure 2 This is a schematic diagram of the intermediate structure of the present invention. Figure 2 .

[0026] Figure 3 This is a schematic diagram of the intermediate structure of the present invention. Figure 3 .

[0027] Figure 4 This is a schematic diagram of the intermediate structure of the present invention. Figure 4 .

[0028] Figure 5 This is a schematic diagram of the intermediate structure of the present invention. Figure 5 .

[0029] Figure 6 This is a schematic diagram of the intermediate structure of the present invention. Figure 6 . Detailed Implementation

[0030] The following specific embodiments illustrate the implementation of the present invention. Those skilled in the art can fully understand other advantages and technical effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through different specific embodiments, and various details in this specification can also be applied based on different viewpoints, with various modifications or changes made without departing from the overall design concept of the invention. It should be noted that, in the absence of conflict, the following embodiments and features in the embodiments can be combined with each other. The following exemplary embodiments of the present invention can be implemented in many different forms and should not be construed as being limited to the specific embodiments set forth herein. It should be understood that these embodiments are provided to make the disclosure of the present invention thorough and complete, and to fully convey the technical solutions of these exemplary embodiments to those skilled in the art. It should be understood that when an element is referred to as "connected" or "combined" to another element, the element can be directly connected or combined to the other element, or there may be intermediate elements. The difference is that when an element is referred to as "directly connected" or "directly combined" to another element, there are no intermediate elements. Throughout the drawings, the same reference numerals always denote the same elements. Example

[0031] This invention provides a TSV integration process method, comprising the following steps: 1) Complete the front-end device FEOL process to fabricate front-end device structures such as BiCMOS, BJT, and SRAM on a silicon substrate; 2) Etching to form TSV trenches: Through-trace TSV trenches are formed in designated areas of the substrate, such as... Figure 1 As shown 3) Tungsten filling is performed on a conventional WCVD machine, and the tungsten on the wafer surface is removed by tungsten etch-back, forming a V-groove on the top of the TSV, such as... Figure 2and Figure 3 As shown; 4) Copper is deposited on the V-groove and wafer surface using ECP process; excess copper is removed using Cu CMP process to completely fill the V-groove and obtain a smooth surface, such as... Figure 4 and Figure 5 As shown; 5) Perform the Damascus process to complete the M1 interconnect and M1 Cu CMP, and continue with the BEOL process until the device is complete. Figure 6 As shown; The TSV integration process can be used to manufacture MOSFETs, BJTs, DRAM, SRAM, Flash, or 3D NAND.

[0032] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It will also be understood that, unless explicitly defined herein, terms such as those defined in a general dictionary shall be interpreted as having the meaning consistent with their meaning in the relevant field context, and not as having an idealized or overly formal meaning.

[0033] The present invention has been described in detail above through specific embodiments and examples, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.

Claims

1. A TSV integration process method, characterized in that, Includes the following steps: 1) Complete the FEOL process for the front-end devices; 2) Etching forms a deep TSV trench; 3) Tungsten filling is performed on a conventional WCVD machine, and tungsten on the wafer surface is removed by tungsten etch-back, forming a V-groove on the top of the TSV; 4) The V-groove was filled using electrochemical deposition (ECP) and copper chemical mechanical polishing (Cu CMP). 5) Perform back-end interconnection BEOL process.

2. The TSV integration process method according to claim 1, characterized in that: The tungsten back etching is used to eliminate the high stress caused by tungsten filling and avoid wafer warping.

3. The TSV integration process method according to claim 1, characterized in that: The copper chemical mechanical polishing (Cu CMP) is used to achieve global planarization of the wafer surface, providing a smooth surface for subsequent damascus processes.

4. The TSV integration process method according to claim 1, characterized in that: It is compatible with W TSV manufacturing of 12-inch wafers.

5. The TSV integration process method according to claim 1, characterized in that: It is used to integrate the TSV process between FEOL and BEOL.

6. A semiconductor device manufactured using the TSV integrated process method according to any one of claims 1-5, characterized in that: The semiconductor device is a MOSFET, BJT, DRAM, SRAM, Flash, or 3D NAND.

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