A post-etching process

Abstract

This application discloses a post-etching process, belonging to the technical field of semiconductor integrated circuit manufacturing. It includes: S1: providing a semiconductor device after undergoing a fully integrated etching process, the semiconductor device comprising a front layer, a metal barrier layer, a dielectric layer, and a buffer layer distributed sequentially from bottom to top. Metal interconnects are formed in the front layer, and trenches and vias for forming metal interconnect structures are formed in the dielectric layer, the bottom of the vias being connected to the metal interconnects; S2: performing a post-etching process on the surface of the semiconductor device using a plasma formed from a mixture of nitrogen and hydrogen gases. This application, through the above solution, can reduce the accumulation of etching residues and improve the PPM-level failure problem of vias.

Description

Technical Field

[0001] This application relates to the technical field of semiconductor integrated circuit manufacturing, and more specifically to a post-etching process. Background Technology

[0002] As semiconductor chip process nodes continue to shrink and chip integration increases, the width of metal interconnects in back-end processes narrows accordingly. Dense, small-size vias (Via) are widely used for the conductive connections of multilayer metal interconnects. The industry typically uses via chains with millions of parts per mille (PPM) for specific testing of via contact resistance. In this process scenario, a PPM-level failure of a via will cause the via chain resistance to exceed specifications.

[0003] During all-in-one (AIO) etching and subsequent post-etch treatment (PET) processes, etching residues easily accumulate inside the process chamber and via structure. Some of these residues react with the titanium nitride (TiN) layer on the via surface, forming insoluble polymers. These polymers are difficult to remove completely using conventional wet cleaning processes, ultimately leading to titanium oxyfluoride (TiOF) defects. Another portion of the etching residues oxidizes the copper layer at the bottom of the via. The oxidized copper layer undergoes selective corrosion during subsequent wet cleaning, resulting in copper layer loss defects. These defects manifest as tiny residue (Tiny Residue) abnormal via images during inspection, severely impacting the electrical performance, long-term reliability, and chip mass production yield of semiconductor devices. Summary of the Invention

[0004] This application provides a post-etching process that can reduce the accumulation of etching residues and improve the PPM-level failure problem of vias.

[0005] This application provides a post-etching processing technology, including: S1: Provides a semiconductor device processed by a fully integrated etching process, the semiconductor device comprising a front layer, a metal barrier layer, a dielectric layer and a buffer layer distributed from bottom to top, wherein metal interconnects are formed in the front layer, and trenches and vias for forming metal interconnect structures are formed in the dielectric layer, the bottom of the vias being connected to the metal interconnects; S2: A post-etching process for the surface of the semiconductor device using a plasma formed by a mixture of nitrogen and hydrogen gases.

[0006] In some embodiments, in the nitrogen and hydrogen gas mixture, the gas flow rate of hydrogen ranges from 100 sccm to 300 sccm, and the gas flow rate of nitrogen ranges from 200 sccm to 600 sccm.

[0007] In some embodiments, the processing time of the post-etching process ranges from 10s to 50s.

[0008] In some embodiments, the processing temperature of the post-etching process is less than 50°C.

[0009] In some embodiments, the radio frequency power range of the plasma processing device in the post-etching process is 100W to 500W.

[0010] In some embodiments, prior to step S1, the following processing is also included: Provide a front layer with metal interconnects formed thereon; A metal barrier layer, a dielectric layer, a buffer layer, a hard mask layer, and a top capping layer are deposited sequentially on the front layer; A patterned photoresist layer is formed on the top cover layer, and the openings in the photoresist layer define trench regions and via regions. Using the photoresist layer as a mask, the top cover layer and hard mask layer in the trench region and via region are etched to expose the underlying buffer layer. Through a fully integrated etching process, trenches and vias for forming metal interconnect structures are formed in the dielectric layer.

[0011] In some embodiments, the process of forming trenches and vias for forming metal interconnect structures in the dielectric layer using a fully integrated etching process includes: Using the hard mask layer as a mask, the buffer layer and part of the dielectric layer in the via region are initially etched to form the preliminary outline of the via; Simultaneous partial etching is performed on the trench area and the via area so that the bottom of the via connects to the metal barrier layer, and a preliminary outline of the trench is formed. Simultaneous main etching is performed on the trench region and the via region to shape the morphology of both the via and the trench. Remove the metal barrier layer at the bottom of the through hole to connect the through hole to the metal wiring below.

[0012] The technical solution of this application has at least the following advantages: 1. By changing the post-etching process gas from a mixture of carbon monoxide and nitrogen to a mixture of hydrogen and nitrogen, the reducing properties of the processing atmosphere are improved, effectively inhibiting the oxidation of the metal interconnect structure in subsequent processes and reducing the residue of etching by-products. This improves defects such as poor conductivity of vias, high contact resistance, and via failure, ultimately improving the PPM-level failure problem of vias. Attached Figure Description

[0013] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0014] Figure 1 This is a flowchart of an exemplary embodiment of the etching post-processing procedure provided in this application; Figure 2 This is a schematic diagram of the structure of the semiconductor device after being processed by the fully integrated etching process, provided in step S1 of this application; Figure 3.1 This is a statistical comparison chart provided by an exemplary embodiment of this application to illustrate the compliance rate of wafer-level via chain resistance before and after using this method; Figure 3.2 This is a comparative chart of statistical results provided by an exemplary embodiment of this application to illustrate the compliance rate of test point-level hole chain resistance before and after using this method; Figure 4 This is a comparison diagram provided by an exemplary embodiment of this application, illustrating the distribution of defects in the hole chain structure of a wafer before and after employing this method; Figures 5-9 This is a schematic diagram of the device structure during the implementation of the post-etching process provided in an exemplary embodiment of this application.

[0015] Explanation of reference numerals in the attached diagram: 1. Front layer; 11. Metal interconnect; 2. Metal barrier layer; 3. Dielectric layer; 31. Trench; 301. Trench area; 32. Through-hole; 302. Through-hole area; 4. Buffer layer; 5. Hard mask layer; 6. Top cover layer. Detailed Implementation

[0016] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0017] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0018] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0019] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.

[0020] This application provides a post-etching processing method, referring to... Figure 1 The post-etching process includes the following steps: S1: Provides a semiconductor device processed by a fully integrated etching process, the semiconductor device comprising a front layer, a metal barrier layer, a dielectric layer and a buffer layer distributed from bottom to top, wherein metal interconnects are formed in the front layer, and trenches and vias for forming metal interconnect structures are formed in the dielectric layer, the bottom of the vias being connected to the metal interconnects.

[0021] For example, refer to Figure 2 A semiconductor device processed by a fully integrated etching process is provided. The semiconductor device includes a front layer 1, a metal barrier layer 2, a dielectric layer 3, and a buffer layer 4 stacked sequentially from bottom to top. Metal interconnects 11 are formed in the front layer 1. Trench 31 and via 32 for forming a metal interconnect structure are formed in the dielectric layer 3, and the bottom of the via 32 is connected to the metal interconnect 11. The front layer 1 can be a pre-dip dielectric layer 3 formed in a pre-processing step, and its material can be silicon dioxide. The metal barrier layer 2 can be a silicon carbonitride layer, the dielectric layer 3 can be a low-dielectric-constant dielectric layer, and the buffer layer 4 can be a silicon oxynitride layer.

[0022] S2: A post-etching process for the surface of the semiconductor device using a plasma formed by a mixture of nitrogen and hydrogen gases.

[0023] For example, plasma generated by a mixture of nitrogen and hydrogen is used to perform post-etching treatment on the surface of the semiconductor device to remove residual etching byproducts on the inner walls of vias 32 and trenches 31. Simultaneously, a reducing atmosphere is used to suppress oxidation on the surface of the metal interconnects 11, improving interface contact characteristics and enhancing the reliability of the interconnect structure. In this step, by changing the post-etching process gas from a mixture of carbon monoxide and nitrogen to a mixture of hydrogen and nitrogen, the reducing properties of the processing atmosphere are enhanced. This effectively suppresses oxidation on the copper interconnect surface, reduces the generation and residue of etching byproducts on the inner walls of vias 32 and trenches 31, and improves problems such as poor contact, abnormal resistance, and failure of vias 32 caused by oxidation and foreign matter residue. This enhances the conductivity reliability of the interconnect structure, ultimately enabling the device to stably pass the PPM-level via 32 chain reliability test, improving product yield and process stability.

[0024] Reference Figure 3.1 The figure shows a statistical comparison of wafer-level via chain resistance compliance rates before and after using this method. (Refer to...) Figure 3.2 The graph shows a comparison of statistical results for the compliance rate of the test point-level via chain resistance before and after using this method. Through... Figure 3.1 and Figure 3.2 It can be observed that the compliance rate of the via chain resistor is significantly improved after using the etching post-processing technology described in this application. (Refer to...) Figure 4 The figures show the distribution of hole chain structure defects in the wafer before and after using this method. The left figure is before using this method, and the right figure is after using this method. It can be seen that the hole chain structure defects are significantly reduced.

[0025] Furthermore, in the nitrogen and hydrogen mixed gas used in the post-etching process, the gas flow rate of hydrogen ranges from 100 sccm to 300 sccm, and the gas flow rate of nitrogen ranges from 200 sccm to 600 sccm.

[0026] Furthermore, the processing time for the post-etching treatment ranges from 10s to 50s.

[0027] Furthermore, the processing temperature of the post-etching treatment process is less than 50°C.

[0028] Furthermore, in the post-etching process, the radio frequency power of the plasma treatment device is set to a range of 100W~500W.

[0029] Furthermore, prior to step S1, the following processing steps are also included: S01: Provides a front layer with metal interconnects formed thereon.

[0030] For example, refer to Figure 5 A front layer 1 is provided with metal interconnects 11 formed thereon, the metal interconnects 11 being made of copper.

[0031] S02: Sequentially deposit a metal barrier layer, a dielectric layer, a buffer layer, a hard mask layer, and a top cover layer on the front layer.

[0032] For example, refer to Figure 5 A metal barrier layer 2, a dielectric layer 3, a buffer layer 4, a hard mask layer 5, and a top capping layer 6 are sequentially deposited on the front layer 1. Specifically, the metal barrier layer 2 can be a silicon carbonitride layer, obtained through plasma-enhanced chemical vapor deposition (PECVD); the dielectric layer 3 can be a low-k dielectric layer, obtained through spin coating and curing; the buffer layer 4 can be a silicon oxynitride layer, formed through plasma-enhanced chemical vapor deposition; the hard mask layer 5 can be made of titanium nitride, obtained through physical vapor deposition (CVD); and the top capping layer 6 can be made of silicon dioxide, generated through plasma-enhanced chemical vapor deposition.

[0033] S03: A patterned photoresist layer is formed on the top cover layer, and the openings in the photoresist layer define trench regions and via regions.

[0034] For example, refer to Figure 6 A patterned photoresist layer (not shown in the figure) can be formed on the top capping layer 6 through processes such as coating, exposure, and development. The openings in the photoresist layer precisely define the trench region 301 and via region 302 required for subsequent etching.

[0035] S04: Using the photoresist layer as a mask, etch the top cover layer and hard mask layer in the trench region and via region to expose the underlying buffer layer.

[0036] For example, refer to Figure 6 The photoresist layer can be used as a mask, and the buffer layer 4 can be used as an etching stop layer. The top cover layer 6 and hard mask layer 5 in the trench region 301 and the via region 302 can be etched using a dry etching process, so that the buffer layer 4 below is exposed.

[0037] S05: Through a fully integrated etching process, trenches and vias for forming metal interconnect structures are formed in the dielectric layer.

[0038] Furthermore, step S05 may include the following processing: Using the hard mask layer as a mask, the buffer layer and part of the dielectric layer in the via region are initially etched to form the preliminary outline of the via.

[0039] For example, refer to Figure 7 Photolithography and etching processes can be used to initially etch the buffer layer 4 and part of the dielectric layer 3 in the via region 302 through reactive ion etching (RIE) to form the preliminary outline of the via 32.

[0040] Simultaneous partial etching is performed on the trench area and the via area so that the bottom of the via connects to the metal barrier layer, and a preliminary outline of the trench is formed.

[0041] For example, refer to Figure 8 The trench region 301 and the via region 302 can be partially etched simultaneously using reactive ion etching (RIE) technology, so that the bottom of the via 32 is connected to the metal barrier layer 2 and the preliminary outline of the trench 31 is formed.

[0042] Simultaneous main etching is performed on the trench area and the via area to shape the morphology of both the via and the trench.

[0043] For example, refer to Figure 9 The trench region 301 and the via region 302 can be simultaneously etched using reactive ion etching (RIE) technology, so that the morphology of both the via 32 and the trench 31 is formed.

[0044] Remove the metal barrier layer at the bottom of the through hole to connect the through hole to the metal wiring below.

[0045] For example, refer to Figure 2 The metal barrier layer 2 at the bottom of the via 32 can be removed by a high selectivity dry plasma etching process, so that the via 32 is connected to the metal connection 11 below.

[0046] The post-etching process provided in this application improves the reducing properties of the processing atmosphere by changing the post-etching process gas from a mixture of carbon monoxide and nitrogen to a mixture of hydrogen and nitrogen. This effectively inhibits oxidation of the copper interconnect surface, reduces the generation and residue of etching byproducts on the inner walls of vias and trenches, improves problems such as poor contact, abnormal resistance, and via failure caused by oxidation and foreign matter residue, enhances the conductivity reliability of the interconnect structure, and ultimately enables the device to stably pass the PPM-level via chain reliability test, thereby improving product yield and process stability.

[0047] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this application.

Claims

1. A post-etching treatment process, characterized in that, include: S1: Provides a semiconductor device processed by a fully integrated etching process, the semiconductor device comprising a front layer, a metal barrier layer, a dielectric layer and a buffer layer distributed from bottom to top, wherein metal interconnects are formed in the front layer, and trenches and vias for forming metal interconnect structures are formed in the dielectric layer, the bottom of the vias being connected to the metal interconnects; S2: A post-etching process for the surface of the semiconductor device using a plasma formed by a mixture of nitrogen and hydrogen gases.

2. The post-etching treatment process according to claim 1, characterized in that, In the nitrogen and hydrogen mixture, the gas flow rate of hydrogen ranges from 100 sccm to 300 sccm, and the gas flow rate of nitrogen ranges from 200 sccm to 600 sccm.

3. The post-etching treatment process according to claim 1, characterized in that, The processing time range of the post-etching treatment is 10s to 50s.

4. The post-etching treatment process according to claim 1, characterized in that, The processing temperature of the post-etching treatment process is less than 50°C.

5. The post-etching treatment process according to claim 1, characterized in that, In the post-etching process, the radio frequency power of the plasma treatment device is set to a range of 100W to 500W.

6. The post-etching treatment process according to claim 1, characterized in that, Before step S1, the following processing is also included: Provide a front layer with metal interconnects formed thereon; A metal barrier layer, a dielectric layer, a buffer layer, a hard mask layer, and a top capping layer are deposited sequentially on the front layer; A patterned photoresist layer is formed on the top cover layer, and the openings in the photoresist layer define trench regions and via regions. Using the photoresist layer as a mask, the top cover layer and hard mask layer in the trench region and via region are etched to expose the underlying buffer layer. Through a fully integrated etching process, trenches and vias for forming metal interconnect structures are formed in the dielectric layer.

7. The post-etching treatment process according to claim 6, characterized in that, The process of forming trenches and vias for forming metal interconnect structures in the dielectric layer through a fully integrated etching process includes: Using the hard mask layer as a mask, the buffer layer and part of the dielectric layer in the via region are initially etched to form the preliminary outline of the via; Simultaneous partial etching is performed on the trench area and the via area so that the bottom of the via connects to the metal barrier layer, and a preliminary outline of the trench is formed. Simultaneous main etching is performed on the trench region and the via region to shape the morphology of both the via and the trench. Remove the metal barrier layer at the bottom of the through hole to connect the through hole to the metal wiring below.

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