Pmi memory card and request management

Abstract

This invention relates to a computer device having at least one memory card, and more specifically, a memory card comprising multiple memory circuits, each of which has an embedded processor. The invention proposes a memory card architecture compatible with existing protocols, particularly DDR5, while utilizing an embedded memory controller, referred to as an embedded controller, and allowing complete read or write commands to be associated with a single memory circuit.

Description

Technical Field

[0001] This invention relates to the field of computer devices with memory, and more particularly to memory with an embedded processor (hereinafter referred to as "PIM memory circuit"). These embedded processors endow the memory with the ability to process and / or compute the data stored therein.

[0002] More specifically, the present invention relates to an architecture and a protocol adapted to better account for the presence of an embedded processor. Background Technology

[0003] Figure 1 A computer device 1 known in the prior art is shown. In particular, this computer device includes a main processor 2, a storage controller 3, and a memory card 4.

[0004] The main processor 2 is, for example, the computing and control unit of an electronic device (such as a computer, calculator, or other device capable of performing logical functions). In particular, the main processor 2 can be a central processing unit (CPU). In this case, the main processor 2 is used to generate read and / or write requests to the memory card 4.

[0005] Storage controller 3 is located between main processor 2 and memory card 4, and is configured to respond to requests from main processor 2 (in accordance with a specific storage protocol) according to a specific storage protocol. Figure 1 The request response from the memory card 4 (indicated by arrow "A") is interpreted before being transmitted to the memory card 4. The memory controller 3 is also configured to transmit the request response from the memory card 4 to the main processor 2 (in...). Figure 1 (Indicated by the arrow "B"). Among known storage protocols, the DDR5 (Double Data Rate) protocol is particularly noteworthy because it achieves double the bandwidth while consuming less power compared to the DDR4 protocol.

[0006] The memory card 4 includes multiple memory circuits, such as four memory circuits 5a, 5b, 5c, and 5d. Each of the memory circuits 5a, 5b, 5c, and 5d includes one or more memory blocks 6a, 6b, 6c, and 6d. Each memory block 6a, 6b, 6c, and 6d includes multiple rows of k memory cells.

[0007] Each of these storage circuits 5a, 5b, 5c, and 5d is connected to the storage controller 3 via a first bus and a second bus. In particular, the first bus, called the channel control and address bus 8, fully and equally connects all control and address ports of each storage circuit 5a, 5b, 5c, and 5d, while the second bus, called the data bus 9, only partially connects each data port of the storage circuits 5a, 5b, 5c, and 5d.

[0008] Therefore, as an example, a memory card, especially a DDR5 memory card with a 32-bit channel, may include four memory circuits 5a, 5b, 5c, and 5d, each including an 8-bit wide data port. According to this configuration, memory circuit 5d can be connected to bits [31:24] of the data bus 9, memory circuit 5c can be connected to bits [23:16] of the data bus 9, memory circuit 5b can be connected to bits [15:8] of the data bus 9, and memory circuit 5a can be connected to bits [7:0] of the data bus 9.

[0009] According to this architecture, the main processor 2 senses consecutive blocks of memory cells, even though they are distributed across multiple different memory circuits 4. For example, the write of 64 bytes of data can be distributed across each of the four memory circuits 5.

[0010] like Figure 2 As shown, the key is the ability to implement PIM storage circuits 5a, 5b, 5c, and 5d. These circuits are similar to those in the reference circuit. Figure 1 The described storage circuits 5a, 5b, 5c, and 5d include one or more storage blocks 6a, 6b, 6c, and 6d, and each circuit also has an embedded processor 7a, 7b, 7c, and 7d.

[0011] therefore, Figure 2 The architecture shown is Figure 1 The difference in the architecture shown is that each of the PIM storage circuits 5a, 5b, 5c, and 5d includes an embedded processor 7a, 7b, 7c, and 7d. Such PIM storage circuits are described in patent application WO 2017 / 055732 A1.

[0012] However, based on compliance Figure 2 The architecture shown still has problems implementing standard storage protocols, such as DDR5.

[0013] In practice, each embedded processor 7a, 7b, 7c, and 7d is only sensitive to the data written to the PIM storage circuits 5a, 5b, 5c, and 5d embedded within it (i.e., it can only process or read this data). In other words, information distributed across multiple storage circuits, as used in standard storage protocols, cannot be processed, calculated, or read by a single embedded processor 7a, 7b, 7c, and 7d.

[0014] In addition, still refer to Figure 2 The architecture shown uses the DDR5 standard storage protocol and cannot perform hardware arbitration between requests from the main processor 2 and requests from the embedded processors 7a, 7b, 7c, and 7d.

[0015] To address the above problems, software solutions were proposed in patent applications WO 2017 / 055732 A1 and EP 3 259 674 B1.

[0016] However, while these solutions are effective, they are cumbersome to use.

[0017] Alternatively, a significant modification to the standard storage protocol could be considered. However, this alternative remains time-consuming and expensive, and therefore cannot be considered the preferred solution.

[0018] Therefore, one object of the present invention is to provide an architecture, in particular a computer device with PIM storage circuitry, that allows the above-mentioned problems to be solved without requiring major modifications to the storage controller and the embedded processor. Summary of the Invention

[0019] This invention relates to a computer device, comprising:

[0020] - A memory card with a set of n memory circuits, each circuit being called circuit i, where i is from 1 to n. Each circuit i includes one or more memory blocks and at least one embedded processor, where each block includes multiple rows and each row includes multiple memory cells.

[0021] - The main processor is configured to send requests, called main requests ik, where each main request ik targets the address of one or more rows of one or more memory blocks of circuit i, called address ik;

[0022] - The storage controller executes an access protocol called the native protocol, which is configured to allow the storage controller to access n circuits i in parallel;

[0023] - At least one bus is configured to transmit commands, addresses, and data;

[0024] The computer device also includes a pre-controller located between the main processor and the memory controller, and each circuit i has an embedded memory controller, referred to as an embedded controller i. The pre-controller is configured to: upon receiving a main request ik from the main processor, split the main request ik into a set of secondary request ik, and send the secondary request set to the memory circuit i via the memory controller. Each embedded controller i is configured to reconstruct the set of secondary request ik into a main request ik, execute the main request ik, generate an execution confirmation as feedback, referred to as a main execution confirmation, split the main execution confirmation into a set of secondary execution confirmations, and transmit the secondary execution confirmation set to the pre-controller via the memory controller. The controller is also configured to reconstruct the secondary execution confirmation set into a primary execution confirmation. The pre-controller is also configured to output a primary result ik to the main processor in response to a primary request ik to read data (referred to as data ik) stored in circuit i. The primary result ik constitutes the primary execution confirmation and includes data ik. Each embedded controller i is also configured to execute memory access requests from the embedded processor, referred to as internal requests. The embedded controller i is also configured to generate all operations required to access the memory of storage circuit i in order to execute the primary request and the internal request, and, if necessary, to preload blocks, activate memory rows, and perform memory row refresh operations on behalf of the storage controller.

[0025] The native protocol is configured to allow the storage controller to access n circuits i in parallel. This means that the native protocol allows the storage controller to execute requests by generating commands, particularly send requests as described below. Specifically, and in detail below, a send request can consist of multiple sub-requests, each targeting a different circuit i, and can be executed in parallel on each effectively targeted circuit i. Furthermore, it should be noted that read or write commands in the native protocol are for all circuits i.

[0026] In one embodiment, the main execution confirmation of the read main request ik includes the data read by the corresponding read operation.

[0027] In one embodiment, the pre-controller is configured to encode each of the sub-requests ik set in the send request, wherein the send request may include up to n sub-requests, each sub-request targeting a different circuit i, and the pre-controller is also configured to send each send request to the storage controller, which is configured to generate a sequence of commands for its native protocol that allows the send request to be executed, the sequence of commands including at least one storage write command of the native protocol called a send command.

[0028] It should be noted that the above command sequence allows each secondary request that forms a send request in the circuit i targeted by the secondary request to be transmitted.

[0029] It is important to note that a request can only include one secondary request from the given set of secondary requests ik.

[0030] In one embodiment, the embedded controller of circuit i is configured to extract secondary requests from the sending commands received by it from the targeting-related circuit i.

[0031] In one embodiment, the pre-controller is configured to, as feedback to a previously sent transmit command, generate a read request called a response request when it anticipates an execution acknowledgment pending on one or more circuits i, and transmit it to the storage controller, which then executes these requests by generating a sequence of commands of the native protocol on one or more buses connecting the storage controller and the circuit i, the sequence of commands including at least one command called a response command, each of which is a storage read command of the native protocol.

[0032] In one embodiment, the embedded controller i is configured to perform secondary acknowledgment encoding in its response to a read command sent to the native protocol, and since the response to the read command is composed of responses generated by multiple circuits i, such a response may contain several secondary acknowledgments sent by different circuits i.

[0033] In one embodiment, the format and encoding of the sent request are the same as those of the written main request.

[0034] In one embodiment, the format and encoding of the response request are the same as those of the read main request.

[0035] In one embodiment, the secondary request of the targeting circuit i is encoded, in whole or in part, into the data to be written to the circuit i in the transmission request, which is then transmitted via at least one transmission command.

[0036] In one embodiment, the embedded controller of circuit i is configured to ignore native protocol commands when preloading one or more memory blocks and when activating one or more memory rows in a sequence of commands sent by the memory controller.

[0037] In one embodiment, the embedded controller of circuit i is configured to ignore native protocol commands sent by the storage controller when loading one or more storage rows.

[0038] In one embodiment, the pre-controller includes a buffer memory, referred to as the pre-controller memory, wherein each master request ik is stored in a register called the pre-register tik before being processed, and wherein each embedded controller i includes a buffer memory referred to as the intermediate buffer memory i.

[0039] In one embodiment, the computer device is configured to assign an identifier called a primary identifier to each primary request ik, and to assign one or more identifiers called secondary identifiers to each secondary request in the secondary request ik set, wherein all primary and secondary identifiers allow each primary request ik to be associated with the secondary request ik set obtained by splitting the primary request ik, and, as feedback, associate a primary execution confirmation ik with the secondary execution confirmation ik set obtained by splitting the primary execution confirmation.

[0040] In one embodiment, the embedded controller is configured to reconstruct the main request ik by storing it (or at least enough elements thereof) into an intermediate buffer during the reception of the secondary request ik, wherein the embedded controller is also configured to execute the main request after the main request has been fully reconstructed.

[0041] In one embodiment, the embedded controller is configured to store the main execution acknowledgment into an intermediate buffer containing the corresponding main request, and then release the intermediate buffer so that it can be used to reconstruct other main requests after the main execution acknowledgments have been fully sent in the form of a set of secondary execution acknowledgments.

[0042] In one embodiment, the embedded controller i uses a primary identifier and a secondary identifier to reassemble the secondary requests into primary requests in the correct order when the storage controller executes the send requests in an order different from the order in which the requests were received from the pre-controller.

[0043] In one embodiment, the pre-controller is configured to reconstruct the main execution acknowledgments ik by storing (or at least sufficient elements thereof) into the pre-register tik during the reception of the secondary execution acknowledgments ik; the pre-controller is also configured to, after these main execution acknowledgments are reconstructed, transfer the main execution acknowledgments corresponding to the main result to the main processor and release the corresponding pre-register tik so that it can be used to store new main requests generated by the main processor.

[0044] In one embodiment, the pre-controller is configured to release the pre-register tik containing the write master request upon delivery of the master execution acknowledgment corresponding to the write master request, so that the released register becomes available to store new master requests generated by the master processor.

[0045] In one embodiment, the pre-controller uses a primary identifier and a secondary identifier to reassemble secondary execution acknowledgments into primary execution acknowledgments in the correct order when the storage controller executes response requests in an order different from the order in which requests are received from the pre-controller.

[0046] In one embodiment, the at least one bus includes a command and address bus and a data bus.

[0047] In one embodiment, the at least one bus comprises a single bus.

[0048] The present invention also relates to another computer device, comprising:

[0049] - A memory card with a set of n memory circuits, each circuit being called circuit i, where i is from 1 to n. Each circuit i includes one or more memory blocks and at least one embedded processor, where each block includes multiple rows and each row includes multiple memory cells.

[0050] - The main processor is configured to send requests, called main requests ik, where each main request ik targets the address of one or more rows of one or more memory blocks of circuit i, called address ik;

[0051] - The storage controller executes an access protocol called the native protocol, which is configured to allow the storage controller to access n circuits i in parallel;

[0052] - At least one bus is configured to transmit commands, addresses, and data;

[0053] The computer device also includes a pre-controller located between the main processor and the storage controller, and each circuit i has an embedded storage controller, referred to as embedded controller i. The pre-controller is configured to: upon receiving a main request ik from the main processor, split the main request ik into a set of secondary requests ik, and send the set of secondary requests to circuit i via the storage controller. Each embedded controller i is configured to reconstruct the set of secondary requests ik into a main request ik, execute the main request ik, and generate an execution acknowledgment as feedback, referred to as the main execution acknowledgment. Each embedded controller i is also configured to, when necessary, replace the storage controller to perform block preloading and refresh the storage rows of circuit i to execute the main request ik.

[0054] In one embodiment, the pre-controller includes a plurality of command generation units specifically configured to split a primary request ik into a set of secondary requests ik, and the pre-controller also includes a command sending unit configured to send the secondary requests.

[0055] In one embodiment, the pre-controller includes a buffer memory, referred to as the pre-controller memory, wherein each master request ik is stored in a register called the pre-register tik before being processed, and wherein each embedded controller i includes a buffer memory referred to as the intermediate buffer memory i.

[0056] In one embodiment, the computer device is configured to assign an identifier called a primary identifier to each primary request ik, and to assign one or more identifiers called secondary identifiers to each secondary request in the set of secondary requests ik, wherein all primary and secondary identifiers allow each primary request ik to be associated with the set of secondary requests ik obtained by splitting the primary request ik.

[0057] In one embodiment, the pre-controller is configured to process the splitting of multiple main requests ik in parallel, wherein each main request ik targets a different storage circuit, and the pre-controller is also configured to send several secondary requests simultaneously, wherein each secondary request belongs to a set of secondary requests ik targeting each different storage circuit.

[0058] It is important to note that sending a request can be achieved by simultaneously sending several secondary requests, each belonging to a set of secondary requests ik targeting different memory circuits. In this case, the send request comprises several secondary requests ik, each targeting a different memory circuit. This send request can be transmitted to the memory circuit via the memory controller.

[0059] In one embodiment, the pre-controller is configured such that, after splitting the primary request ik into a set of secondary requests ik, the set of secondary requests ik includes secondary requests ikl, where l is from 0 to m, and the address ik in the circuit i targeted by the primary request ik is carried by at least one secondary request ikl.

[0060] In one embodiment, whenever the primary request ik is a write request, the embedded controller i is configured to store the secondary requests ikl (where l is 0 to m) of the secondary request set into the register ik of the intermediate buffer memory during the reception process. The embedded controller i is also configured to construct the primary request ik and execute the primary request ik once all the secondary requests ikl have been stored in the register ik.

[0061] In one embodiment, when the pre-controller receives at least two write master requests ik and jh, respectively targeting circuit i and circuit j, where j is different from i, the pre-controller splits the master requests ik and jh into a set of secondary requests ik and a set of secondary requests jh, respectively. The pre-controller is configured to simultaneously send a secondary request ikl to circuit i, where l is from 0 to m, send a secondary request jht to circuit j, where t is from 0 to m, and send a NOP command to circuit h, which is not targeted by the master requests. The NOP command is an invalid command. It should be noted that this simultaneous sending is accomplished through the sending requests described above.

[0062] In one embodiment, the embedded controller i is configured to send an execution acknowledgment of the main request ik to the pre-controller and reset the register ik of the intermediate buffer memory i, wherein the pre-controller is configured to reset the pre-register ik upon receiving the execution acknowledgment.

[0063] In one embodiment, when the main request ik is a read request for L bytes of data at address ik, the embedded controller i is configured to, upon receiving all the secondary requests of the secondary request ik set, reassemble the main request ik and then execute the main request ik so that after the embedded controller i executes the main request ik, it writes the read L bytes into register tik of its intermediate buffer memory.

[0064] In one embodiment, the embedded controller is further configured to split the L bytes that have been read and stored in register tik into a set of secondary results ik and transmit them to a pre-controller, wherein the pre-controller is configured to reassemble the secondary results of the set of secondary results ik into a primary result ik, and simultaneously form a response to the primary read request ik and a read execution confirmation.

[0065] In one embodiment, when the pre-controller receives at least two primary read requests ik and jh and targets circuit i and circuit j respectively, where j is different from i, the primary requests ik and jh are converted into a set of secondary requests ik and a set of secondary requests jh respectively, wherein the pre-controller is configured to simultaneously send at least one secondary request from the set of secondary requests ik to circuit i and at least one secondary request from the set of secondary requests jh to circuit j.

[0066] In one embodiment, the at least one bus includes a control and address bus and a data bus.

[0067] In one embodiment, the at least one bus comprises a single bus.

[0068] In one embodiment, the secondary requests of the secondary request set ik transmitted by the pre-controller to circuit i are transmitted through the storage controller. Attached Figure Description

[0069] Other features and advantages of the present invention will be explained in detail with reference to the following drawings, wherein:

[0070] [ Figure 1 ] Figure 1 It is a schematic illustration of a computer device with a memory card known in the prior art and adapted to implement standard storage protocols, in particular the memory card of such computer device includes storage circuitry without an embedded processor;

[0071] [ Figure 2 ] Figure 2It is a schematic diagram of a computer device with a memory card and each of its memory circuits includes an embedded processor;

[0072] [ Figure 3 ] Figure 3 These are schematic illustrations of a computer device conforming to the principles of this invention, especially Figure 3 The computer device shown includes, but is not limited to, four storage circuits. Detailed Implementation

[0073] This invention relates to a computer device having at least one memory card, and more specifically, a memory card comprising a plurality of memory circuits, each of which has an embedded processor. In particular, in the terminology of this invention, an embedded processor is a microelectronic device configured to execute instructions and perform, for example, calculations on data stored in its respective memory circuit. Those skilled in the art can refer to patent application WO 2017 / 055732 A1, which describes an example of a memory circuit with an embedded processor. However, it should be noted that the functions and architecture provided in patent application WO 2017 / 055732A1 are merely examples and should not be construed as limiting the scope of the invention in any way.

[0074] This invention proposes a memory card architecture that is compatible with existing protocols, especially with the DDR5 protocol, and uses an embedded memory controller, hereinafter referred to as the embedded controller.

[0075] Therefore, the present invention relates to a computer device, comprising:

[0076] - A memory card with a set of n memory circuits, each circuit being called circuit i, where i is from 1 to n. Each circuit i includes one or more memory blocks and at least one embedded processor, where each block includes multiple rows and each row includes multiple memory cells.

[0077] - The main processor is configured to send requests, called main requests ik, where each main request ik targets the address of one or more rows of one or more memory blocks of circuit i, called address ik;

[0078] - The storage controller executes an access protocol called the native protocol, which is configured to allow the storage controller to access n circuits i in parallel;

[0079] - At least one bus is configured to transmit commands, addresses, and data;

[0080] The computer device also includes a pre-controller located between the main processor and the memory controller, and each circuit i has an embedded memory controller, referred to as an embedded controller i. The pre-controller is configured to: upon receiving a main request ik from the main processor, split the main request ik into a set of secondary request ik, and send the secondary request set to the memory circuit i via the memory controller. Each embedded controller i is configured to reconstruct the set of secondary request ik into a main request ik, execute the main request ik, generate an execution confirmation as feedback, referred to as a main execution confirmation, split the main execution confirmation into a set of secondary execution confirmations, and transmit the secondary execution confirmation set to the pre-controller via the memory controller. The controller is also configured to reconstruct the secondary execution confirmation set into a primary execution confirmation. The pre-controller is also configured to output a primary result ik to the main processor in response to a primary request ik to read data (referred to as data ik) stored in circuit i. The primary result ik constitutes the primary execution confirmation and includes data ik. Each embedded controller i is also configured to execute memory access requests from the embedded processor, referred to as internal requests. The embedded controller i is also configured to generate all operations required to access the memory of storage circuit i in order to execute the primary request and the internal request, and, if necessary, to preload blocks, activate memory rows, and perform memory row refresh operations on behalf of the storage controller.

[0081] The native protocol, configured to allow the storage controller to access n circuits i in parallel, means that the native protocol allows the storage controller to execute requests by generating commands, particularly send requests as described below. Specifically, and as detailed below, a send request can consist of one or more sub-requests, each targeting a different circuit i, and can be executed in parallel on each validly targeted circuit i. Furthermore, it should be noted that read or write commands in the native protocol are applied to all circuits i.

[0082] Therefore, in this invention, each storage circuit includes an embedded controller that functions identically to the storage controller. However, the embedded controller performs these functions only within the storage circuit in which it resides.

[0083] Furthermore, in this invention, each master request issued by the main processor is assigned to a single memory circuit via a pre-controller.

[0084] Therefore, the master request assigned to a specific memory circuit can be handled entirely by the embedded controller of the relevant memory circuit. This configuration allows the utilization of the computing and data processing capabilities of each memory circuit through its embedded processor.

[0085] The present invention disclosed below is limited to describing the various functions of a computer device and its components. However, it should be noted that the present invention is not limited to the computer device itself, but also relates to one or more methods implemented by the relevant computer device.

[0086] Furthermore, the following uses at least one bus, which includes a command and address bus and a data bus. However, it should be noted that the at least one bus may include a single bus.

[0087] Those skilled in the art will understand from this document that the present invention relates to a method for a main request path, namely, from the main processor issuing a main request to the embedded controller of the relevant storage circuit executing the main request on the storage circuit. It should also be noted that this method can simultaneously handle both writing and reading main requests. Finally, it should be noted that the present invention can also relate to a computer program, which, when implemented, performs all the steps of the relevant method. Such a computer program may in particular include subroutines, such as subroutines stored and executed by a pre-controller, and subroutines stored and executed by an embedded controller.

[0088] The specification below uses memory circuits with embedded processors. However, those skilled in the art will recognize, upon reading this document, that the invention is also applicable to memory circuits without such embedded processors.

[0089] Therefore, in Figure 3 In the figure, a schematic diagram of a computer device 10 that conforms to the principles disclosed in this invention can be seen.

[0090] In particular, the computer device 10 includes a main processor 100. The main processor 100 may include, for example, a processing and control unit of an electronic device, such as a computer, calculator, or other device capable of performing logical functions. Specifically, the main processor 100 may be a central processing unit (CPU). In this case, the main processor 100 is used to generate master requests sent to the storage circuitry described below.

[0091] In particular, a master request may include a write master request and / or a read master request.

[0092] In this regard, a write request corresponds to storing data in the storage circuit, while a read request corresponds to reading the data stored in the storage circuit and transmitting it to the main processor 100.

[0093] The computer device 10 also includes a memory card 300. A "memory card" refers to a carrier element, such as a printed circuit board, on which one or more storage circuits are disposed. The memory card 300 may include a connection device, specifically allowing the memory card 300 to interface with a computer or computing unit.

[0094] The memory card 300 in this invention includes n memory circuits, each referred to as circuit i, where i is from 1 to n. It should be noted that unless otherwise specified, n is an integer.

[0095] Each circuit i includes one or more storage blocks, each storage block includes multiple rows, and each row includes storage cells.

[0096] The storage unit may include dynamic random access memory (DRAM). However, the invention is not limited thereto, and those skilled in the art may use any type of storage unit, especially static random access memory (SRAM).

[0097] Each circuit i includes at least one embedded processor.

[0098] exist Figure 3 In this example, as a non-limiting illustration, the memory card includes four storage circuits, labeled circuit 1, circuit 2, circuit 3, and circuit 4. Specifically, in... Figure 3 In the diagram, circuit 1 is labeled 301, circuit 2 is labeled 302, circuit 3 is labeled 303, and circuit 4 is labeled 304.

[0099] like Figure 3 As shown, each circuit 301, 302, 303, and 304 includes an embedded processor, labeled 311, 312, 313, and 314, and one or more memory blocks, labeled 321, 322, 323, and 324.

[0100] Each circuit i, where i is 1 to n, includes an embedded memory controller, each referred to as embedded controller i. The embedded controller is specifically configured to execute a main request, which is a reassembled version of secondary requests received via one or more buses, and also to execute requests generated by the embedded processor i to access memory contained in one or more blocks. Figure 3 As shown, each circuit 301, 302, 303, and 304 includes an embedded controller, labeled as 331, 332, 322, and 334, respectively.

[0101] The computer device 10 of this invention also includes a storage controller 200. In particular, the storage controller 200 of this invention possesses technical features of storage controllers known in the prior art. Specifically, the storage controller 200 of this invention is configured to send block preload commands, storage row activation commands, and / or storage row refresh commands. However, the computer device 10 of this invention is configured such that certain commands that the storage controller 200 may issue are ignored by the storage circuitry, particularly block preload commands, row activation commands, and / or row refresh commands. This, in particular, allows for limiting protocol adaptations related to the operation of the computer device 10.

[0102] The computer device 10 of this invention includes a data bus 500 connecting a storage controller 200 and a memory card 300, and a command and address bus 400 connecting the storage controller 200 and the memory card 300. Furthermore, it is known that each storage circuit is only partially connected to the data bus 500. More specifically, the width of the data bus (e.g., measured in "bits" or "bytes") is greater than the width of the data port of each storage circuit (e.g., measured in "bits" or "bytes"). Therefore, in this invention, all storage circuits can have the same data port width. Advantageously, the sum of the widths of the data ports of all storage circuits can be equal to the width of the data bus.

[0103] For example, the data port of each storage circuit can be equal to p (where p is an integer), and the width of the data bus can be equal to the product of p and n (where n is the number of storage circuits on the memory card).

[0104] It is important to note that write requests with a length equal to the product of n and p (or a multiple thereof) cannot pass through the data port of the storage circuit without modification.

[0105] Computer device 10 also includes a pre-controller 600 located between main processor 100 and memory controller 200. During operation, main processor 100 is configured to send requests, specifically main request ik, where i is 1 to n, wherein main request i targets one or more blocks of circuit i, with one or more rows of addresses, referred to as address i; a first exponent “i” assigned to main request ik indicates the circuit i targeted by the request. A second exponent “k” (note that other letters may also be used below) represents the request itself and, in particular, allows for the distinction between main request ik and main request ih, both of which target circuit i.

[0106] In this invention, the pre-controller 600 is adapted to receive and preprocess the main request ik issued by the main processor 100. In particular, the pre-controller 600 is configured to split the main request ik (where i is 1 to n) of the address ik of the targeting circuit i (issued by the main processor 100) into a set of secondary requests ik.

[0107] The sending of secondary requests is accomplished by encoding them into a write request called a send request. In particular, several secondary requests destined for different memory circuits i can be encoded into the same send request. The send request is transmitted to the memory controller 200, whereby the memory controller executes each send request by generating a command sequence on the control and address bus 400 and sending data on the data bus 500.

[0108] The command sequence for this includes:

[0109] - Optionally, the block preload command and the line activation command (each embedded controller is still configured to ignore these two commands);

[0110] - One or more write commands that carry data typically written to the DDR5 protocol on the data bus 500, but the data to be written is, within the scope of this invention, data that encodes a secondary request.

[0111] Furthermore, each embedded controller i is configured to extract secondary requests from write command data, which are generated by the storage controller when executing a send request. The embedded controller i uses the extracted set of secondary requests to reconstruct the main request, and executes the main request after reconstruction, performing block preloading and row activation as necessary, and flushing operations where required.

[0112] For each main request executed, the embedded controller i generates an execution confirmation. For a read main request, the execution confirmation corresponds to the data read by the read main request, while for a write main request, it corresponds to the secondary request identifier.

[0113] Whenever embedded controller i receives a response command, embedded controller i will output: – It can be a secondary result, that is, part of the execution confirmation of the read main request, which includes a secondary identifier and a portion of the data read according to the read main request; – This can be one or more execution confirmations written to the main request; – This can be a numerical value that encodes the case of unacknowledged execution, in which case the controller has either fully acknowledged the execution of all main requests it has executed, or has not acknowledged the execution of the main requests in either of the following situations: • Full execution confirmation not yet received • The main request has not yet been fully executed.

[0114] In a particularly advantageous embodiment, the pre-controller 600 may include n command generation units, each called a generation unit i, where i is 1 to n. Each generation unit i is specifically dedicated to splitting the main request ik of the targeting circuit i into a set of secondary requests ik. Still according to this embodiment, the pre-controller 600 may include a send request generation unit configured to encode several secondary requests into each send request, wherein these secondary requests are generated by different generation units i and thus target different memory circuits. The send requests thus generated are output to the memory controller 200, which executes them via control buses 400 and 500; thus, the pre-controller 600 sends the secondary requests of each set of secondary requests ik to the memory circuit i, and therefore to the embedded controller i, via the memory controller 200.

[0115] Advantageously, the pre-controller 600 may include a buffer memory, called the pre-controller memory, in which each master request ik is stored in a register called the pre-register tik before being processed. Advantageously, each embedded controller i may also include a buffer memory called the intermediate buffer memory i, where i is 1 to n.

[0116] In particular, as an example, the pre-register tik, which contains the main request ik, may include multiple fields, including an identifier, the cached allocated status, the address ik, and a data array.

[0117] The cache allocation status can include an idle status, a status where a read main request has been stored, and a status where a write main request has been stored. The status where a read main request ik has been stored can serve as a measure of the progress of sending a set of secondary requests ik to circuit i (splitting the read main request). Similarly, the status where a write main request ik has been stored can serve as a measure of the progress of sending a set of secondary requests ik to circuit i (splitting the write main request).

[0118] The computer device 10 can be configured to assign an identifier called a primary identifier to each primary request ik, and to assign one or more identifiers called secondary identifiers to each secondary request in a set of secondary requests ik. All primary and secondary identifiers specifically allow each primary request ik to be associated with a set of secondary requests ik derived from the primary request ik. In other words, the secondary identifier assigned to a secondary request in a particular set of secondary requests allows the association of a primary request with a set of secondary requests formed by related primary requests.

[0119] This also allows the main execution confirmation ik to be associated with the set of secondary execution confirmation ik generated by the splitting of the main execution confirmation as feedback.

[0120] In an advantageous embodiment, the pre-controller 600 can be configured to split multiple primary requests ik in parallel, wherein each primary request targets a different storage circuit i. Still in this embodiment, the pre-controller 600 can be configured to encode several secondary requests into the same transmission request, wherein each of these secondary requests belongs to a set of secondary requests ik targeting a different storage circuit i.

[0121] The pre-controller 600 can be configured such that, after splitting the primary request ik into a set of secondary requests ik, the set of secondary requests ik includes secondary requests ikl, where l is from 0 to m, and secondary requests ik0 carry the address ik in the circuit i targeted by the primary request ik.

[0122] The computer device 10 also includes a data bus 500 connecting the storage controller and the memory card, and a command and address bus 400 connecting the storage controller and the memory card.

[0123] The control and address bus 400 is a unidirectional bus that transmits command and address information through appropriate encoding. It is important to note that the command information specifies the action to be performed, such as executing a request, while the address information specifies the address of the circuit i in which the relevant request needs to be executed.

[0124] The data bus 500 is a bidirectional bus that includes several data communication fields i, more specifically, communication fields for n data i (i being 1 to n), wherein the communication field for each data i is dedicated to circuit i.

[0125] It should be noted that the data transmitted between circuit i and pre-controller 600 will pass through the communication field of data i.

[0126] Write or read secondary requests ikl, which respectively carry write and read requests, may also pass through the communication field of data i.

[0127] A write or read secondary request ik0, which carries the write and read addresses respectively, may also pass through the communication field of data i or the communication field of address ik, or be distributed across these two fields.

[0128] The embedded controller i is configured to store secondary requests ikl into register tik of intermediate buffer memory i during the reception of secondary requests ikl. The internal controller i is also configured to reconstruct the main request ik and execute it after all secondary requests ikl are stored in register tik. Executing the main request ik means, if necessary, preloading the block containing the relevant rows and activating the rows, and then reading or writing the cells of the rows specified by the request address for all rows targeted by the request.

[0129] Advantageously, the pre-register tik allocated in the memory of the pre-controller to the primary request ik records the progress of sending secondary requests ikl to the embedded controller i. The embedded controller i also allocates register tik to the set of secondary requests ik in its intermediate buffer memory i. In particular, this register tik records the reception progress of secondary requests ikl of the secondary request set.

[0130] The embedded controller is also configured to store the primary request execution acknowledgment into an intermediate buffer containing the corresponding primary request, and then release the intermediate buffer. This allows the intermediate buffer (in other words, the relevant registers) to be used to reconstruct other primary requests via a secondary set of acknowledgments after the primary request acknowledgments have been fully sent.

[0131] In this invention, the embedded controller i can also use a primary identifier and a secondary identifier to reassemble the secondary requests into a primary request in the correct order when the storage controller executes the sending request in an order different from the order in which the request was received from the pre-controller.

[0132] Still in this invention, the pre-controller uses a primary identifier and a secondary identifier to reassemble the secondary execution confirmations into primary execution confirmations in the correct order when the storage controller executes response requests in an order different from the order in which the requests are received from the pre-controller.

[0133] The pre-controller is configured to reconstruct the main execution acknowledgments ik by storing (or at least sufficient elements thereof) into the pre-register tik during the reception of secondary execution acknowledgments ik. The pre-controller is also configured to, after these main execution acknowledgments are reconstructed, transfer the main execution acknowledgment corresponding to the main result to the main processor and release the corresponding pre-register tik so that it can be used to store new main requests generated by the main processor.

[0134] The pre-controller is configured to release the pre-register tik containing the write master request when the master execution acknowledgment corresponding to the write master request is delivered, wherein the pre-register released as a result becomes available to store new master requests generated by the master processor.

[0135] Those skilled in the art, based solely on their general knowledge, can design the architecture of the pre-register TIK and the register TIK.

[0136] Each embedded controller i can be configured to, upon receiving all secondary requests from the secondary request set ik, reorganize the secondary requests in order to reconstruct the primary request and execute it.

[0137] The embedded controller i is also configured to, in response to a response request sent by the pre-controller, split the data that has been read and stored in register tik into a set of secondary results ik and transmit it to the pre-controller, wherein the pre-controller is configured to extract the secondary results of the set of secondary results ik from the data returned by the response requests (which are read requests related to the DDR5 protocol), and reassemble these secondary results into a main result ik, thereby forming a response to the main read request ik and an execution confirmation of the request.

[0138] Advantageously, when the pre-controller 600 receives at least two primary read requests ik and jh, respectively targeting circuit i and circuit j, where j is different from i, the pre-controller converts the primary requests ik and jh into a set of secondary requests ik and a set of secondary requests jh, respectively. The pre-controller is configured to simultaneously send a secondary request ikl to circuit i and a secondary request jht to circuit j. The pre-controller is configured to store all data (particularly the read data) in a pre-register before sending the data to the main processor.

[0139] Therefore, the computer device 10 is configured to process multiple master requests, each master request targeting a different storage circuit.

[0140] Therefore, in this invention, the use of secondary requests (smaller than the primary request) or secondary results allows the primary request to be executed completely in a single memory circuit, thereby fully utilizing the potential of the embedded processor in the relevant memory circuit.

[0141] The following describes the path of the write request in the computer device, where the memory card comprises four memory circuits. In this example, the data bus 500 is 32-bit and is evenly distributed across each circuit 301, 302, 303, and 304.

[0142] The path for writing the main request includes the main request being generated by the main processor. This main request may include, in particular, a request identifier, a target address i aligned to 64 bytes of circuit i, and 64 bytes of data to be written, i.e., the data to be written to address i.

[0143] Upon receiving a master request, the pre-controller 600 allocates a pre-register tik for the master request i in its buffer storage area.

[0144] The pre-controller 600 then transforms the primary request ik into five secondary requests ik, where k is 0 to 4. The pre-controller 600 may have four command generation units, each dedicated to transforming the primary request targeting its own dedicated memory circuit. In other words, the primary request ik targeting circuit i will be transformed into five secondary requests ikl (l is 0 to 4) by the command generation unit dedicated to circuit i. The address ik targeted in circuit i is contained in secondary request i0, along with a small portion of the data to be written, while the secondary requests ik (k is 1 to 4) contain the remaining data to be written.

[0145] These different secondary requests ik (k is 0 to 4) are sent by the command sending unit in the form of 5 write secondary commands.

[0146] Secondary requests sent to different memory circuits can be sent simultaneously. In particular, once adopted, the command sending unit can send four secondary requests from four different sets of secondary requests. In other words, write commands on four memory circuits can be executed simultaneously.

[0147] Therefore, completing the main processor's write request requires five write accesses instead of one, but up to four write requests can be executed simultaneously, each targeting a different memory circuit, achieving an efficiency of up to 80% in terms of bandwidth.

[0148] When the embedded controller i receives secondary request i0 and secondary request ik (k is 1 to 4), it updates the register tik. Once the state of register tik reaches a certain value, which indicates that all secondary requests ikl (l is 0 to 4) have been received by the embedded controller i, 64 bytes of data i will be written to the address targeted by the primary request ik on circuit i.

[0149] The pre-controller will send a response command, determining that the execution acknowledgment must wait in storage circuit i for reasons such as, but not limited to, sufficient time having elapsed since the last secondary request set (corresponding to the associated write primary request). Then, the embedded controller i will send an execution acknowledgment of the data i written, as a response to this response command, and reset register tik. If the embedded controller is not ready to output the execution acknowledgment upon receiving the response command, it will output a non-response value and this execution acknowledgment as a response to subsequent response commands. When the pre-controller receives a non-response, it will generate a response request again, which, after being executed by the storage controller, will generate another response command.

[0150] Ultimately, the execution confirmation is received by the pre-controller (via the storage controller), which then resets the pre-register tik, which can be allocated to the execution of another master request.

[0151] The following describes the path of the read master request in the computer device, where the memory card comprises four storage circuits. In this example, the data bus 500 is 32-bit and is evenly distributed across each circuit 301, 302, 303, and 304.

[0152] The path for reading the main request includes the main request being generated by the main processor. This main request may in particular include a request identifier and a target address i aligned to 64 bytes of circuit i.

[0153] Upon receiving a master request, the pre-controller 600 allocates a pre-register tik for the master request ik in its buffer storage area.

[0154] The target address i is used to determine the memory circuit i associated with the primary read request. In this case, the target address ik might, for example, involve circuit 302. The pre-controller then generates a set of secondary requests ik, for example, through a command generation unit dedicated to circuit i.

[0155] In this scenario, regarding read requests, the secondary request set ik includes a single secondary request i0, which is sent to circuit 302 via the data bus, specifically the data communication field associated with circuit 302. Secondary request i0 primarily carries the read address ik in circuit 302.

[0156] When the embedded controller i of circuit 302 receives a secondary request i0, it updates the register tik and executes the corresponding read command to store the read data into the register tik.

[0157] The pre-controller will send a series of response commands to collect a set of secondary execution acknowledgments containing the read data. The pre-controller determines that the read execution acknowledgments must wait in the storage circuit i for reasons such as, but not limited to, that sufficient time has elapsed since the secondary request i0 (corresponding to the relevant primary read request) was sent.

[0158] The embedded controller i then sends the current execution confirmation set, which is actually the secondary result set, in response to this series of response commands, thereby transmitting the read data and resetting the register tik.

[0159] Similar to the write command, the embedded controller can output a non-response value to the response command if it is not ready when it receives the response command, which will then be resent in a manner similar to that described in the write request path.

[0160] Data transmitted via bus 500 is transmitted in data blocks (English term "DATA BURST"), one of which typically contains 64 bytes.

[0161] The secondary result ik sent by circuit i is received by pre-controller 600. These secondary results can be, for example, 8-byte compressed (equal to half the number of bytes in a data block transmitted via the data communication field) or, for example, 16-byte regular (equal to the number of bytes in a data block transmitted via the data communication field). Typically, data can be transmitted to pre-controller 600 in the form of one compressed secondary result and four regular secondary results, where each secondary result, in addition to the data it carries, includes an identifier, such as an identifier associated with the pre-register tik containing the main request i.

[0162] For example, but not limited to, the embedded controller i encodes the response type it outputs to the response command in a 4-bit field at the beginning of the response. This 4-bit field primarily encodes the following types: no response, write acknowledgement, compressed result, and regular result.

[0163] Unresponsive, write-acknowledged, and compressed result types occupy 8 bytes, while regular result types occupy 16 bytes.

[0164] Therefore, the 16 bytes provided by the embedded controller i in response to a command can contain one of the following combinations: – Two unanswered questions; – One response was not received, while the other received a write confirmation; – One no response, one compressed result; – Two write confirmations; – One write confirmation, one compression result; – Two compression results; – A normal result.

[0165] Still in the non-restrictive example, the compressed result also includes an 8-bit identifier and 6 bytes of data, while the regular result also includes an 8-bit identifier and 14.5 bytes of data: one compressed result (6 bytes) and four regular results (4 x 14.5 bytes) transmit a total of 64 bytes of data.

[0166] Once the pre-controller 600 receives all results i (all the data to be read), it will aggregate them and transmit them to the main processor 100. The aggregated data may include the identifier of the main request i.

[0167] It is important to note that compressed data (unit: bytes) corresponds to half the amount of data transmitted through the data port by the storage circuit during a read or write command, while regular data (unit: bytes) corresponds to the entire amount of data.

[0168] Using compression allows two compressed results to be combined and sent simultaneously in response to a single response command, where the two compressed results correspond to different read requests. This results in improvements.

[0169] Similarly, a secondary read request i0 containing only the address to be transmitted can also be compressed, so that two such results corresponding to different primary read requests can be sent to the storage circuit i simultaneously with a single send command.

[0170] Therefore, in the illustrated scenario, executing the main read request will involve: • Send a compressed secondary request (8 bytes) • Send a compressed secondary result (8 bytes) • Send 4 secondary results of normal size (16 bytes each)

[0171] Therefore, all these transmissions correspond to 5 commands on the bus (one and a half commands + one and a half commands + 4 commands). Thus, the computer device can process up to 4 commands in parallel, as long as these commands involve different memory circuits, and thus achieves an efficiency of 80% in terms of bandwidth (4 accesses out of 5 commands).

[0172] The path examples of write or read requests given above can be extrapolated to any number of memory circuits. Furthermore, throughout this document, the number of secondary requests (ik) depends on the type of the primary request (read or write) and the number of memory circuits contained in the computer device. However, those skilled in the art will understand that this should not be construed as limiting. In fact, the principles of the invention presented above take into account the width of the address and control buses, as well as the width of the data bus. However, these widths are not fixed, and therefore different numbers of secondary requests can be considered.

[0173] The computer device 10 can also be configured to manage read errors when executing a read master request.

[0174] In the example described above, the data bus is only 32 bits wide and there are no protection measures to prevent errors that may temporarily affect it.

[0175] Therefore, it is advantageous to implement an optional cyclic redundancy check (CRC) mechanism, such as the one specified in the DDR5 protocol. Each circuit i outputs an additional 2 bytes in addition to its 16-byte response, containing two 8-bit CRCs. Each CRC is generated from half of the 16-byte response, allowing the two CRCs to protect the entire 16-byte response of each circuit i.

[0176] If a transmission error occurs, such as a temporary reversal of the signal on the data bus connecting the storage controller and circuit i: – The storage controller will detect this error because one of the two CRCs associated with the 16 bytes sent by circuit i is incorrect; – Although only 8 bytes of data are affected, for simplicity, the storage controller will reject all 64 bytes of data returned in response to the read request; The storage controller will resend the read command.

[0177] However, the internal workings of the storage controller may prevent this read request from being resent immediately, and other read or write requests may be sent in the meantime.

[0178] The problem is that read requests, which are also response requests, change the state of the embedded controller: when the latter selects a response to send, it also changes its internal state, especially the state of the relevant buffer register tik, so that it will not select this response when it receives other response commands.

[0179] Each secondary result for a read secondary request identifies the target location of the data bytes it contains. Read errors between the storage circuitry and the storage controller that affect secondary results include: – This will not cause bytes originally intended for reading main requests ik / jl / kv / lw to be incorrectly allocated to other main requests ia / jb / kc / ld. However, this will cause the bytes originally dedicated to the main request ik / jl / kv / lw to be lost and unable to be delivered.

[0180] Therefore, when the pre-controller discovers after a sufficiently long period of time that not all the bytes required by the main request ik / jl / kv / lw have been delivered, it will assume that these bytes have been lost and process them in the following order: – The pre-controller sends a command to cancel the master request ik / jl / kv / lw. – The pre-controller awaits confirmation of the execution of the command to cancel the main request ik / jl / kv / lw. – If the execution confirmation takes too long, the pre-controller will resend the cancellation command of the main request ik / jl / kv / lw. Finally, the pre-controller restarts the entire execution flow of the main request ik / jl / kv / lw.

[0181] Computer device 10 can also be configured to manage write errors when executing a write master request.

[0182] When the storage controller sends a write master request, it generates CRC bytes in the same way that storage circuits 301, 302, 303, and 304 generate when responding to a read master request.

[0183] If a transmission error occurs, such as a temporary reversal of the signal on the data bus connecting the storage controller and circuit i: The storage controller will detect this error because one of the two CRCs associated with the 16 bytes sent by circuit i is incorrect. Circuit i will ignore the command transmitted by the write secondary request, which could have been a command carrying a read address, a data write command, a cancel command, or a command without instructions. - Some bytes sent to main request i were lost and could not be delivered: • Neither read access, write access, nor cancellation operation was ever executed. • When the pre-controller detects that the main request i has not been completed after a sufficiently long period of time, it will determine that some bytes constituting the request have been lost and will process them in the following order: • The pre-controller sends a command to cancel the main request i. • The pre-controller awaits confirmation of the execution of the main request i cancel command. • If the execution confirmation takes too long, the pre-controller will resend the command to cancel the main request i. • The pre-controller restarts the entire execution flow of the main request i.

[0184] Alternatively, the storage circuitry can explicitly indicate that an error occurred during transmission through a specific type of response.

[0185] Of course, the present invention is not limited to the described embodiments, and other variations may be proposed without departing from the scope of the invention as defined in the claims.

Claims

1. A computer device (10), comprising: - A memory card (300) with a set of n memory circuits (301, 302, 303, 304), each of the circuits being called circuit i, where i is from 1 to n, each of the circuits i including one or more memory blocks and at least one embedded processor (311, 312, 313, 314), each of the one or more memory blocks including multiple rows, each row including multiple memory cells; - The main processor (100) is configured to send requests, called main requests ik, wherein each of the main requests ik targets an address of one or more rows of the one or more memory blocks of the circuit i, called an address ik; - The storage controller (200) executes an access protocol called the native protocol, wherein the native protocol is configured to allow the storage controller (200) to access the n circuits i in parallel; - At least one bus (400, 500) is configured to transmit commands, addresses and data; The computer device (10) further includes a pre-controller (600) located between the main processor (100) and the storage controller (200), and each circuit i has an embedded storage controller (331, 332, 333, 334), referred to as embedded controller i. The pre-controller (600) is configured to: upon receiving a main request ik from the main processor (100), split the main request ik into a set of secondary request iks, and send the secondary request sets to the storage circuit i via the storage controller (200). Each embedded controller i is configured to reconstruct the set of secondary request iks into the main request ik, execute the main request ik, generate an execution confirmation as feedback, referred to as a main execution confirmation, split the main execution confirmation into a set of secondary execution confirmations, and send the secondary execution confirmations to the storage circuit i via the storage controller (200). The confirmation set is transmitted to the pre-controller, which is also configured to reconstruct the secondary execution confirmation set into the main execution confirmation. The pre-controller is also configured to output a main result ik to the main processor (100) in response to a main request ik to read data (referred to as data ik) stored in circuit i. The main result ik constitutes the main execution confirmation and includes data ik. Each of the embedded controllers i is also configured to execute memory access requests from the embedded processors (311, 312, 313, 314), referred to as internal requests. The embedded controller i is also configured to generate all operations required to access the memory of the storage circuit i in order to execute the main request and the internal requests, and, if necessary, to preload the block, activate the storage line, and perform a storage line refresh operation on behalf of the storage controller (200).

2. The computer device (10) according to claim 1, wherein the main execution confirmation of the read main request ik includes the data read in the corresponding read operation.

3. The computer device (10) according to claim 1 or 2, wherein the pre-controller is configured to encode each of the sub-requests in the sub-request set ik in the sending request, wherein the sending request may include up to n sub-requests, each of the sub-requests targeting a different circuit i, the pre-controller is further configured to send each of the sending requests to the storage controller (200), and the storage controller (200) is configured to generate a sequence of commands of its native protocol that allows the execution of the sending request, the sequence of commands including at least one storage write command of the native protocol called a sending command.

4. The computer device (10) of claim 3, wherein the embedded controller of circuit i is configured to extract the secondary request from a transmission command received therefrom targeting related circuit i.

5. The computer device (10) according to claim 3 or 4, wherein the pre-controller is configured to, as feedback to a previously sent transmit command, generate a read request when it anticipates an execution confirmation pending on one or more circuits i, and transmit it to the storage controller (200), thereby causing the latter to execute these requests by generating a sequence of commands of the native protocol on one or more buses connecting the storage controller (200) and the circuit i, the sequence of commands including at least one command called a response command, each of the response commands being a storage read command of the native protocol.

6. The computer device (10) of claim 5, wherein the embedded controller i is configured to perform secondary acknowledgment encoding in its response to a native protocol read command, and since the response to the read command is composed of responses generated by multiple circuits i, such a response may include several secondary acknowledgments sent by different circuits i.

7. The computer device (10) according to claim 6, wherein the format and encoding of the sending request are the same as those of the write master request.

8. The computer device (10) according to claim 7, wherein the format and encoding of the response request are the same as those of the read master request.

9. The computer device (10) of claim 8, wherein a secondary request targeting the circuit i is encoded into data to be written to the circuit i in a transmission request, the data to be written being subsequently transmitted via at least one transmission command.

10. The computer device (10) of claim 9, wherein the pre-controller includes a buffer memory, referred to as the pre-controller memory, wherein each of the main requests ik is stored in a register referred to as the pre-register tik before being processed, and wherein each of the embedded controllers i includes a buffer memory referred to as the intermediate buffer memory i.

11. The computer device (10) of claim 10, wherein the computer device (10) is configured to assign an identifier called a primary identifier to each of the primary requests ik, and to assign one or more identifiers called secondary identifiers to each of the secondary requests ik set, wherein all primary identifiers and secondary identifiers allow each of the primary requests ik to be associated with the secondary requests ik set obtained by splitting the primary requests ik, and to associate a primary execution confirmation ik with the secondary execution confirmation ik set obtained by splitting the primary execution confirmation as feedback.

12. The computer device (10) of claim 11, wherein the embedded controller is configured to reconstruct the main request ik by storing it in an intermediate buffer during the reception of the secondary request ik, wherein the embedded controller is further configured to execute the main request after the main request has been fully reconstructed.

13. The computer device (10) of claim 12, wherein the embedded controller is further configured to store a main request execution confirmation into the intermediate buffer memory containing the corresponding main request, and then release the intermediate buffer memory.

14. The computer device (10) of claim 13, wherein the embedded controller i uses a primary identifier and a secondary identifier to reassemble the secondary requests into a primary request in the correct order when the storage controller (200) executes the transmission request in an order different from the order in which it receives the request from the pre-controller.

15. The computer device (10) of claim 14, wherein the pre-controller is configured to reconstruct the main execution confirmation ik by storing it in a pre-register tik during the receipt of the secondary execution confirmation ik; the pre-controller is further configured to, after the main execution confirmations are reconstructed, transmit the main execution confirmation corresponding to the main result to the main processor (100) and release the corresponding pre-register tik so that it can be used to store a new main request generated by the main processor (100).

16. The computer device (10) of claim 15, wherein the pre-controller is configured to release the pre-register tik containing the write master request upon delivery of a master execution acknowledgment corresponding to the write master request.

17. The computer device (10) of claim 16, wherein the pre-controller uses the primary identifier and the secondary identifier to reassemble the secondary execution acknowledgments into the primary execution acknowledgments in the correct order when the storage controller executes the response request in an order different from the order in which it receives the request from the pre-controller.

18. The computer device (10) according to any one of claims 3 to 17, wherein the embedded controller of the circuit i is configured to ignore commands of the native protocol when preloading one or more storage blocks and when activating one or more storage rows in a sequence of commands sent by the storage controller (200).

19. The computer device (10) according to any one of claims 3 to 18, wherein the embedded controller of the circuit i is configured to ignore the commands of the native protocol sent by the storage controller (200) when loading one or more storage lines.

20. The computer device (10) according to any one of claims 1 to 19, wherein the at least one bus includes a command and address bus and a data bus.

21. The computer device (10) according to any one of claims 1 to 19, wherein the at least one bus comprises a single bus.

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