Design support system, design support device, and design support method

Abstract

A design assistance system for a semiconductor integrated circuit capable of shortening a product development period in a multi-variety small-lot production is provided. The design assistance system assists a circuit design of a semiconductor device manufactured in cooperation with a plurality of functional circuit formation wafer fabs and a post-wiring process wafer fab. The plurality of functional circuit formation wafer fabs are responsible for a pre-wiring process of independently forming functional circuit blocks corresponding to independent functions in a pre-process, and storing them in a wafer library. A functional circuit design tool provides a server 1000 with a selection of functional circuit blocks corresponding to independent functions for realizing a desired overall function, and assists a design of configuring them on a semiconductor substrate. A post-wiring design tool provides a server 2000 with assistance in a logic design and a pattern design of a post-wiring process of selectively connecting a plurality of functional circuit blocks with different design rules from the pre-wiring process.

Description

Technical Field

[0001] This invention relates to a design assistance system, design assistance device, and design assistance method for assisting in the design process of forming semiconductor integrated circuits on a semiconductor substrate. Background Technology

[0002] (Development trends of semiconductor integrated circuits) In semiconductor integrated circuits formed on semiconductor substrates represented by silicon (Si) semiconductors, performance is improved by increasing the number of active devices such as transistors formed on a chip; in other words, by increasing the integration density.

[0003] Since the development and practical application of large-scale semiconductor integrated circuits (LSI), Moore's Law has been one of the empirical standards for predicting the future, discussed based on long-term trends in their manufacturing and production. Initially, Moore's Law stated that "the number of transistors on an integrated circuit doubles every two years." Due to improvements in the transistor structure of semiconductor integrated circuits and advancements in precision manufacturing technology, Moore's Law has generally maintained this trend over a long period. However, in recent years, its limitations have also been pointed out.

[0004] For example, as a transistor structure, taking typical CMOS (Complementary Metal-Oxide-Semiconductor) transistors as an example, suppressing short-channel effects when P-channel and N-channel FET transistors are planarly constructed on a Si substrate is a key challenge for refinement. Therefore, FinFETs (Fin Field-Effect Transistors) have been developed to improve performance by changing the shape of the silicon substrate from planar to fin-shaped. Furthermore, Gate-All-Around nanosheet structures with the gate surrounding the entire channel have also been developed.

[0005] As a result, in the current semiconductor integrated circuit industry, the most advanced technology for the development and practical application of logic ICs is the ultra-fine technology known as the "2nm process".

[0006] However, in reality, the applications of semiconductor integrated circuits are not only widely distributed in chips for artificial intelligence computing that require such cutting-edge technology, but also in semiconductor integrated circuits that require the use of more sophisticated technologies.

[0007] Furthermore, the wiring width / interval formed using the cutting-edge EUV (Extreme ultraviolet lithography) technology was originally around 20-30nm. The "2nm process," associated with the three-dimensionalization of transistor structures, is not a planar wiring processing dimension, but rather a symbolic name used through the term "area scaling." In reality, integrated circuits with more relaxed processing precision, such as those called "22-28nm processes," are widely used for automotive control applications and as "Logic Processing LSIs" mounted on the back of image sensors.

[0008] On the other hand, in the past, semiconductor integrated circuit manufacturing was carried out through vertical integration, where a single company handled everything from design to circuit formation on a semiconductor substrate (semiconductor wafer), chip dicing, bonding, and packaging. However, nowadays, semiconductor integrated circuits are generally manufactured through a horizontal division of labor: fabless companies responsible for design, foundries responsible for wafer fabrication (hereinafter referred to as "fabs"), and assembly companies responsible for assembly.

[0009] Figure 31 This is a conceptual diagram illustrating the manufacturing process of existing semiconductor devices.

[0010] Reference Figure 31 The front-end process, also known as wafer fabrication, involves manufacturing LSI chips on a silicon wafer. In contrast, the back-end process is the assembly process (or packaging) that cuts the completed LSI chips (also called "dies") from the wafer and packages them. In the front-end process, the workpiece is a silicon wafer; in the back-end process, it could be a silicon wafer, a chip, or a packaged chip.

[0011] like Figure 31 As shown, most wafer fabs now separate the front-end and back-end processes. Furthermore, in the front-end process, the front-end process mainly refers to the processes up to transistor formation, while the back-end process refers to the wiring processes that follow.

[0012] (ASIC and cell-based design) In particular, as mentioned above, for application-specific integrated circuits (ASICs) rather than general-purpose semiconductor ASICs, it is often not necessary to use the most advanced manufacturing processes. Here, application-specific integrated circuits are generally referred to as ASICs (application-specific integrated circuits), which are integrated circuits that integrate multiple functions into a single circuit for a specific purpose.

[0013] Here, ASICs are broadly categorized into "full-custom ICs," which involve building logic circuits from scratch, and "semi-custom ICs," which combine basic circuits and functional modules in their design. Of course, full-custom ICs have longer development cycles and higher development costs.

[0014] On the other hand, in semi-custom ICs designed to suppress these shortcomings, there are "gate array" methods, which prepare semi-finished products filled with basic logic circuits and implement functions by wiring between specified circuits, and "standard cell" methods, which combine component circuits (units) that have implemented a certain degree of coherent functions.

[0015] Regarding cell-based integrated circuits designed in a "standard cell" manner, such as integrated circuits configured based on standard cells and incorporating large-scale circuit blocks (mega cells and macro cells).

[0016] Cell-based semi-custom design methods have long been widely used in ASIC design. This approach improves IC design efficiency by combining intellectual properties (IPs) registered in a library and using automated placement and routing tools.

[0017] Patent Document 1 discloses a semiconductor integrated circuit designed to include: multiple basic units that are interconnected by internal wiring and have specific functions; a wiring region formed on a semiconductor substrate and having external wiring connecting the basic units; power supply wiring and ground wiring for supplying power to the semiconductor units; a first decoupling capacitor composed only of pMOS transistors on the semiconductor substrate; and a second decoupling capacitor composed of two metal layers formed on the semiconductor substrate. The decoupling capacitor unit, composed of the first and second decoupling capacitors, is disposed in an unused area not occupied by the basic units and configured to be connected to the power supply wiring and ground wiring. This allows for the design of a cell-based IC that can suppress power consumption while simultaneously reducing power and ground noise.

[0018] On the other hand, to address the high functionality and multi-functionality achieved by semiconductor integrated circuits, techniques are also used to assemble chips (dies) manufactured by one semiconductor manufacturing plant with another chip (die) manufactured by a different semiconductor manufacturing plant into a single package in subsequent processes. For example, "2.5D mounting technology," which uses an interposer to arrange, connect, and mount multiple semiconductor chips side-by-side, and "3D mounting technology," which stacks and mounts multiple semiconductor chips, such as memory and microcontrollers, in a three-dimensional manner within a package, are known.

[0019] In this way, when combining semiconductor chips manufactured by different semiconductor manufacturing plants, designers can use two or more PDKs (Process Design Kits) provided by the foundries that manufacture each chip to design the semiconductor device.

[0020] PDK compiles the necessary information for the design of custom ICs and analog ICs based on a specific semiconductor process. It is mostly provided by foundries responsible for the front-end processes of semiconductors (including transistor manufacturing processes such as diffusion processes) to fabless semiconductor manufacturers and IDM (Integrated Device Manufacturer) designers who are users, according to different processes (see Non-Patent Literature 1).

[0021] In custom ICs and analog ICs, it is sometimes necessary to design transistor units, and the PDK contains the information required for this. That is, it consists of the symbol on the circuit diagram of the transistor for that process, the SPICE (Simulation Program with Integrated Circuit Emphasis) model of the transistor, the mask level data of the transistor (parametric cells such as PCELL, QCELL data), the constraints of mask layout design (so-called DRC (design rule checking) rules), parasitic parameter extraction rules, etc.

[0022] This information is used in IC design software known as EDA (electronic design automation) tools. Furthermore, most PDKs also include design guidelines, design examples (reference designs), etc.

[0023] For PDKs (Product Design Kits) aimed at custom IC and analog IC design, the information provided by foundries to digital LSI designers is mostly referred to as a "design kit." This kit is also prepared according to different process technologies. The design kit is based on various design data (models for EDA tools) of the basic design elements (standard cells, macro cells) of that process. It also usually includes the same design guidelines and design examples (reference designs) as the PDK.

[0024] Patent Document 2 discloses a method and procedure for fabricating a Design Data Kit (PDK) capable of simultaneously designing all layers of a stacked IC. Specifically, the PDK fabrication method in Patent Document 2 includes: acquiring multiple design information libraries corresponding to multiple chips used in a semiconductor device; assigning unique identifiers to the strings contained in the design information libraries, depending on the design information library; and merging the multiple design information libraries. By assigning unique identifiers to the strings contained in the design information libraries, the names of simulation models, etc., can be set differently depending on the design information library. Therefore, duplication of simulation model names, etc., is avoided while merging multiple design information libraries. Furthermore, it is disclosed that by using the design information library thus created, all layers of a stacked IC can be designed simultaneously.

[0025] Existing technical documents Patent documents Patent Document 1: Japanese Patent Application Publication No. 2013-201158 Patent Document 2: Japanese Patent Application Publication No. 2017-156877 Non-patent literature Non-patent literature 1: https: / / xtech.nikkei.com / dm / article / WORD / 20130115 / 260353 / Summary of the Invention The technical problem that the invention aims to solve As explained above, compared with standard logic ICs, standard memory ICs, programmable logic devices that rewrite circuit designs, FPGAs, etc., ASICs have advantages such as smaller installation area, lower power consumption, higher operating speed, and lower unit price.

[0026] However, even when using standard cell designs as semi-custom ICs, once the wafer fabrication process is complete, device testing and design improvements are still required. Therefore, from the perspective of fabless manufacturers and other users, there are still issues of high development costs and long development times.

[0027] Furthermore, as foundries focus on high-volume, low-variety production of semiconductor chips using cutting-edge or near-cutting-edge processes with high profit margins, there is a tendency to lower the priority of manufacturing design standards compared to the more relaxed semiconductor integrated circuits. Moreover, with the increasing size of semiconductor substrates (wafers), the iterative process of prototyping and refining—requiring orders for a considerable number of chips for each prototype—increases the time required to complete the product (TAT, or turnaround time) and development costs.

[0028] On the other hand, for example, in semiconductor integrated circuits that rely on processing analog signals from sensors, such as IoT (Internet of Things), there is often a need for multi-variety, low-volume production.

[0029] As a result, there is a need for design and manufacturing methods for semiconductor integrated circuits that can adapt to the production of multiple varieties in small quantities, rather than developing a single semiconductor product that follows the established manufacturing model.

[0030] The present invention was made to solve the above-mentioned problems, and its purpose is to provide a design assistance system, design assistance device and design assistance method for semiconductor integrated circuits that can shorten the product development cycle in multi-variety, low-volume production.

[0031] Solutions for solving technical problems (Project 1) According to one aspect of the present invention, a design assistance system is provided that provides tools to assist in the circuit design of a semiconductor device manufactured in collaboration with multiple semiconductor manufacturing sites, the multiple semiconductor manufacturing sites comprising: multiple first semiconductor manufacturing sites responsible for front-end wiring processes according to a first manufacturing process of a first design rule; and at least one second semiconductor manufacturing site responsible for back-end wiring processes according to a second manufacturing process of a second design rule different from the first design rule. The design assistance system includes a first design assistance device that assists in the design of circuit patterns formed by the front-end wiring process on each of multiple dies on a semiconductor substrate. Each die includes multiple circuit blocks, and the multiple circuit blocks include multiple functional circuit blocks for implementing multiple independent functions constituting the overall function of the semiconductor device on the semiconductor substrate, respectively. The multiple functional circuit blocks include multiple stock circuits. The system comprises a plurality of stock circuit blocks, each pre-prepared with circuit pattern design information corresponding to a manufacturing process at a first semiconductor manufacturing site based on a first design rule. A first design assistance device includes a first design assistance unit that selects a predetermined number of stock circuit blocks from the plurality of stock circuit blocks to implement the overall function, assisting in the design for their placement on a semiconductor substrate. The system also includes a second design assistance device that assists in the design of post-wiring patterns in a post-wiring process for selectively connecting the plurality of circuit blocks formed in the pre-wiring process. The second design assistance device includes a second design assistance unit that selects a second semiconductor manufacturing site based on the manufacturing process of the selected plurality of stock circuit blocks, and performs logic and pattern design assistance for the post-wiring process according to a second design rule corresponding to the first design rule of the selected stock circuit blocks.

[0032] (Item 2) Preferably, in the structure of Item 1, the multiple circuit blocks further include multiple adjustment circuit blocks, which are separately disposed on the semiconductor substrate from the multiple functional circuit blocks, for fine-tuning the performance achieved by the functional circuit blocks respectively.

[0033] (Item 3) Preferably, in the structure of Item 2, the multiple functional circuit blocks include at least one custom circuit block. The custom circuit block is based on the first design rule of the selected first semiconductor manufacturing site, and the user designs the circuit pattern design information. The first design auxiliary device includes a storage device. The storage device stores the multiple semiconductor manufacturing sites and the multiple circuit design core groups containing the multiple functional circuit blocks respectively establish corresponding relationships according to the manufacturing process of the multiple semiconductor manufacturing sites. The first design auxiliary unit performs the logic design and pattern design assistance of the custom circuit block by using the first design rule corresponding to the first semiconductor manufacturing site selected according to the circuit design core group.

[0034] (Project 4) Preferably, in the structure of Project 3, when the first design auxiliary unit determines that multiple stock circuit blocks are insufficient to achieve the overall performance, it prompts the user to implement the design of custom circuit blocks.

[0035] (Item 5) Preferably, in the structure of any one of Items 1 to 4, the correspondence includes: a first correspondence between functional circuit blocks corresponding to multiple independent functions constituting the overall function; and a second correspondence between the performance specifications of the independent functions of the functional circuit blocks and multiple circuit design core groups used to implement the performance specifications, each circuit design core group containing design information of stock circuit blocks, which is used to specify a pre-defined independent circuit pattern that can implement the performance specifications for at least one independent function.

[0036] (Item 6) Preferably, in the structure of Item 5, the first design auxiliary module includes: a core group selection unit for selecting a circuit design core group that includes a combination of functional circuit blocks capable of realizing the overall function; and a design unit for determining a first semiconductor manufacturing site among multiple semiconductor manufacturing sites that corresponds to the selected circuit design core group, and performing logic design and pattern design based on the first design rules of the determined first semiconductor manufacturing site.

[0037] (Item 7) Preferably, in any one of Items 2 to 5, the first design aid includes a mask pattern generation unit for generating pattern data of an optical mask, wherein the pattern data of the optical mask is used, in at least a part of the pattern transfer process in the first semiconductor manufacturing site, to perform an exposure process of a die on which semiconductor devices are formed respectively in a segmented projection exposure manner; the second design aid includes a drawing data generation unit for generating drawing data for forming wiring patterns of interconnecting circuit blocks on the semiconductor substrate in the pattern transfer process in the second semiconductor manufacturing site.

[0038] (Item 8) Preferably, in the configuration of Item 7, the first design rule of the selected stock circuit block includes the overlap margin at the connection portion of the connection portion at the viahole of the wiring formed in the pre-wiring process and the wiring formed in the post-wiring process based on the second design rule.

[0039] (Item 9) Preferably, in the structure of Item 7 or Item 8, the drawing data generated by the drawing data generation unit includes: data on different wiring patterns in the subsequent wiring process for a die with common patterns of functional circuit blocks and adjustment circuit blocks in multiple dies.

[0040] (Item 10) Preferably, in the structure of Item 9, different wiring patterns are wiring patterns that connect common functional circuit blocks and different adjustment circuit blocks in the first and second bare chips contained in the patterned bare chips.

[0041] (Item 11) Preferably, in any one of Items 1 to 10, the plurality of functional circuit blocks include variable functional blocks that can change the characteristics of independent functions through a post-wiring pattern. The variable functional blocks have a basic circuit pattern for implementing independent functions and a characteristic adjustment circuit pattern for adjusting the characteristics based on the basic circuit pattern. The second design auxiliary unit assists in the design of connecting the basic circuit pattern and the characteristic adjustment circuit pattern through a predetermined number of die-usable post-wiring patterns on the semiconductor substrate.

[0042] (Item 12) Preferably, in the structure of Item 11, the characteristic adjustment circuit pattern includes a plurality of first passive circuit patterns, each of the first passive circuit patterns being designed to have a first impedance value, and the die common back wiring pattern includes a first back wiring pattern that interconnects a plurality of first passive circuit patterns of a specified number during the design.

[0043] (Item 13) Preferably, in the structure of Item 12, the multiple circuit blocks further include multiple adjustment circuit blocks, which are separately disposed on the semiconductor substrate from the multiple functional circuit blocks, for fine-tuning the performance implemented by the functional circuit blocks respectively.

[0044] (Item 14) Preferably, in the structure of Item 13, the plurality of adjustment circuit blocks include a plurality of second passive circuit patterns, each of the second passive circuit patterns being designed to have a second impedance value smaller than the first impedance value, and the back wiring pattern having: a first back wiring pattern common to a predetermined number of dies; and a second back wiring pattern that is different among the predetermined number of dies and connects the second passive circuit pattern to the first passive circuit pattern.

[0045] (Item 15) Preferably, in any one of Items 11 to 14, the basic circuit pattern is an analog circuit.

[0046] (Item 16) According to another aspect of the present invention, a computer-based design-aided method is provided, which operates a tool to assist in the circuit design of a semiconductor device manufactured in collaboration with multiple semiconductor manufacturing sites. The multiple semiconductor manufacturing sites include: multiple first semiconductor manufacturing sites responsible for front-end wiring processes according to a first manufacturing process of a first design rule; and at least one second semiconductor manufacturing site responsible for back-end wiring processes according to a second manufacturing process of a second design rule different from the first design rule. The computer includes a computing unit and a storage unit, the storage unit storing design information for multiple circuit blocks, the multiple circuit blocks including multiple functional circuit blocks, the multiple functional circuit blocks being used to implement multiple independent functions constituting the overall function of the semiconductor device on a semiconductor substrate, and the multiple functional circuit blocks including multiple stock circuit blocks. The plurality of stock circuit blocks are pre-prepared with design information for circuit patterns corresponding to manufacturing processes of each first semiconductor manufacturing site based on a first design rule. The method includes: a computing device selecting a predetermined number of stock circuit blocks from the plurality of stock circuit blocks to implement an overall function; a step to assist in the design of circuit patterns for a pre-wiring process that forms the plurality of circuit blocks on a semiconductor substrate; and a step to assist in the design of post-wiring patterns for a post-wiring process that selectively connects the plurality of circuit blocks formed in the pre-wiring process. The step of assisting in the design of the post-wiring patterns includes: selecting a second semiconductor manufacturing site according to the manufacturing process of the selected plurality of stock circuit blocks, and performing a step to assist in logic design and pattern design for the post-wiring process according to a second design rule corresponding to the first design rule of the selected stock circuit blocks.

[0047] (Item 17) According to another aspect of the present invention, a design aid device for a functional circuit is provided in a design aid system that provides tools to assist in the design of circuits for semiconductor devices manufactured in collaboration with multiple semiconductor manufacturing sites. The multiple semiconductor manufacturing sites include: multiple first semiconductor manufacturing sites responsible for the front-end wiring process according to a first manufacturing process based on a first design rule; and at least one second semiconductor manufacturing site responsible for the back-end wiring process according to a second manufacturing process based on a second design rule different from the first design rule. The device includes a storage device for storing design information of multiple circuit blocks required for assisting the design. The multiple circuit blocks include multiple functional circuit blocks, which are used to respectively implement the semiconductor device on a semiconductor substrate. The design aid device includes multiple independent functions of the overall function, and multiple functional circuit blocks include multiple stock circuit blocks. These stock circuit blocks are pre-prepared with design information of circuit patterns corresponding to the manufacturing process of each first semiconductor manufacturing site based on a first design rule. The design aid device also includes a computing device for performing design aid processing based on information stored in a storage device. The computing device selects a predetermined number of stock circuit blocks from the multiple stock circuit blocks to implement the overall function, and assists in the design of arranging the circuit patterns in the front wiring process on the semiconductor substrate. In the design process of the back wiring process for selectively connecting the multiple circuit blocks formed in the front wiring process, the design information of the circuit pattern arrangement in the front wiring process is stored in a predetermined shared storage area in order to share the design information.

[0048] (Item 18) Preferably, in the structure of Item 17, the design aid for the functional circuit includes a mask pattern generation unit for generating pattern data of an optical mask. The pattern data of the optical mask is used, in at least a part of the pattern transfer process in the first semiconductor manufacturing site, to perform exposure of dies on which semiconductor devices are formed respectively on a semiconductor substrate in a segmented projection exposure manner. The pattern transfer process in the second semiconductor manufacturing site is a process of directly drawing the wiring pattern of the interconnecting circuit blocks of the semiconductor substrate.

[0049] (Item 19) Preferably, in the structure of Item 18, the first design rule of the selected stock circuit block includes the overlap margin of the contact portion at the via of the wiring formed in the pre-wiring process and the wiring formed in the post-wiring process based on the second design rule.

[0050] (Item 20) According to another aspect of the invention, an auxiliary device, in a design aid system that provides tools to assist in the design of circuits for semiconductor devices manufactured in collaboration with multiple semiconductor manufacturing sites, assists in the design of a post-wiring process corresponding to the design of a front-end wiring process, wherein the multiple semiconductor manufacturing sites include: multiple first semiconductor manufacturing sites responsible for the front-end wiring process according to a first manufacturing process of a first design rule; and at least one second semiconductor manufacturing site responsible for the post-wiring process according to a second manufacturing process of a second design rule different from the first design rule. The device includes a storage device that stores inventory information of multiple semiconductor substrates completed and stored during the front-end wiring process up to the point where multiple circuit blocks are formed for each of multiple dies. The multiple circuit blocks include multiple functional circuit blocks for sorting... The design aid device implements multiple independent functions constituting the overall function of a semiconductor device on a semiconductor substrate. The multiple functional circuit blocks include multiple stock circuit blocks. These stock circuit blocks are pre-prepared with design information of circuit patterns corresponding to the manufacturing process of each first semiconductor manufacturing site based on a first design rule. The multiple semiconductor substrates in the stock are selected from the multiple stock circuit blocks to implement a predetermined number of stock circuit blocks for implementing the overall function. The circuit patterns in the pre-wiring process are formed on the semiconductor substrates. The design aid device also includes a computing device that performs design aid processing based on information stored in a storage device. The computing device selects semiconductor substrates for performing post-wiring processes based on the stock information. The computing device assists in the design process of the post-wiring pattern of the post-wiring process for selectively connecting the multiple circuit blocks formed in the pre-wiring process.

[0051] (Item 21) Preferably, in the structure of Item 20, the design aid device includes a direct drawing pattern generation unit, which generates direct drawing data in the pattern transfer process of the second semiconductor manufacturing site for performing wiring pattern transfer of dies on which semiconductor devices are formed respectively in a direct drawing manner.

[0052] (Item 22) Preferably, in the structure of Item 20 or Item 21, multiple functional circuit blocks include variable functional blocks that can change the characteristics of independent functions through a post-wiring pattern. The variable functional blocks have a basic circuit pattern for implementing independent functions and a characteristic adjustment circuit pattern for adjusting characteristics based on the basic circuit pattern. A design auxiliary unit assists in the design of connecting the basic circuit pattern and the characteristic adjustment circuit pattern through a predetermined number of die-common post-wiring patterns on the semiconductor substrate.

[0053] (Item 23) Preferably, in the structure of Item 22, the characteristic adjustment circuit pattern includes a plurality of first passive circuit patterns, each of which is designed to have a first impedance value, and the die common back wiring pattern includes a first back wiring pattern that interconnects a plurality of first passive circuit patterns of a specified number during design.

[0054] (Item 24) Preferably, in the structure of Item 23, the multiple circuit blocks further include multiple adjustment circuit blocks, which are separately disposed on the semiconductor substrate from the multiple functional circuit blocks, for fine-tuning the performance achieved by the functional circuit blocks respectively.

[0055] (Item 25) Preferably, in the structure of Item 24, the plurality of adjustment circuit blocks include a plurality of second passive circuit patterns, each second passive circuit pattern being designed to have a second impedance value smaller than the first impedance value, and the back wiring pattern having: a first back wiring pattern common to a specified number of dies; and a second back wiring pattern that is different among the specified number of dies and connects the second passive circuit pattern to the first passive circuit pattern.

[0056] Invention Effects According to the present invention, a design aid system, design aid device, and design aid method for semiconductor integrated circuits are made feasible, which can shorten product development time in multi-variety, low-volume production. Attached Figure Description

[0057] Figure 1 This is a conceptual diagram illustrating an outline of the manufacturing process of a semiconductor device according to Embodiment 1.

[0058] Figure 2 This is a diagram illustrating an example of a cross-sectional structure of a semiconductor device based on the manufacturing process of this embodiment.

[0059] Figure 3 It is used for explanation Figure 2 A conceptual diagram of the manufacturing process of a semiconductor device.

[0060] Figure 4 This is a conceptual diagram illustrating the design platform structure of the design aid system used in this embodiment.

[0061] Figure 5 This is a concept diagram of a server device that provides a design platform, extracted from the specifications.

[0062] Figure 6 This is a conceptual diagram showing the functionality and structural outline of DB1500.2, including its relationship with the wafer fab.

[0063] Figure 7 This is a diagram illustrating the detailed structure of DB1500.2, which explains the functions and wafer fab relationships.

[0064] Figure 8 This is a diagram illustrating the detailed structure of DB1500.2, which explains the functions and wafer fab relationships.

[0065] Figure 9This is a diagram illustrating the detailed structure of DB1500.2, which explains the functions and wafer fab relationships.

[0066] Figure 10 This is a diagram illustrating the detailed structure of DB1500.2, which explains the functions and wafer fab relationships.

[0067] Figure 11 This is a diagram showing the structure of the functional circuit design tool providing server 1000, the back-wiring design tool providing server 2000, and the designer terminal 5000.1 to 5000.P.

[0068] Figure 12 This is a functional block diagram showing the structure of server 1000 provided by the functional circuit design tool.

[0069] Figure 13 This is a functional block diagram showing the structure of the server 2000 provided by the back-wiring design tool.

[0070] Figure 14 This is a block diagram used to illustrate the hardware structure of the server 1000 provided by the functional circuit design tool.

[0071] Figure 15 This is a flowchart used to illustrate the operation of the server 1000 provided by the functional circuit design tool.

[0072] Figure 16 This is a flowchart used to illustrate the operation of the server 1000 provided by the functional circuit design tool.

[0073] Figure 17 This is a flowchart used to illustrate the actions of the post-wiring design tool for Server 2000.

[0074] Figure 18 This is a diagram used to illustrate a bare die formed on a semiconductor substrate after multiple pre-wiring processes.

[0075] Figure 19 This is a diagram used to illustrate a bare die formed on a semiconductor substrate after multiple post-wiring processes.

[0076] Figure 20 It is a diagram showing the design rules of the highest layer of cabling in the cabling group of the preceding cabling process, and the contact rules of the contact portion between the highest layer cabling M1 and the cabling M2 formed in the subsequent cabling process.

[0077] Figure 21 It is a conceptual diagram showing various variations of the pattern of the contact portion of the wiring formed in the top layer wiring and subsequent wiring processes.

[0078] Figure 22 This is a conceptual diagram illustrating the flexibility of design approaches for digital and analog circuits.

[0079] Figure 23 This diagram illustrates the relationship between the "function", "characteristics" and "characteristic values" implemented by a functional circuit, using an operational amplifier as an example.

[0080] Figure 24 This is a diagram showing three design conditions for an "amplifier".

[0081] Figure 25 It demonstrates a fully customized design. Figure 24 The circuit diagrams show the circuit structures under the three conditions shown.

[0082] Figure 26 This illustrates the design method of implementation method two. Figure 24 The circuit diagrams show the circuit structures under the three conditions shown.

[0083] Figure 27 This is a conceptual diagram showing the function block and the adjustment circuit block used to adjust the performance of the function block.

[0084] Figure 28 This is a conceptual diagram showing a comparison between the prototyping process using the design method of Implementation Method 2 and the conventional prototyping process.

[0085] Figure 29 This is a conceptual diagram illustrating how design data can be flowed / reused within or between wafer fabs.

[0086] Figure 30 This is a conceptual diagram illustrating the effect of a design approach based on an implementation method.

[0087] Figure 31 This is a conceptual diagram illustrating the manufacturing process of existing semiconductor devices. Detailed Implementation

[0088] The following describes the configuration of a semiconductor integrated circuit design assistance system, design assistance device, and design assistance method according to embodiments of the present invention. It should be noted that in the following embodiments, structural elements and processing steps given the same reference numerals are the same or similar, and their descriptions will not be repeated unless necessary.

[0089] It should be noted that the software for semiconductor integrated circuit design assistance implemented on the computer of the design assistance device of the present invention is described below as a computer program for circuit design assistance that is installed on a standalone computer device and executes circuit design assistance.

[0090] However, the processing of a design-aided system can also be distributed among multiple computer devices, and the computing devices executing the computer processing can be one or multiple. Furthermore, the processing of a design-aided system is not limited to programs installed on such general-purpose computer devices; generally speaking, it can also be implemented as a structure combining computing and storage devices in a dedicated computing processing unit.

[0091] (Terminology Definition) The terms used in this specification are defined as follows.

[0092] 1) "Semiconductor wafer": Typically, a wafer is cut from a single-crystal silicon (Si) ingot and shaped to a specified thickness and diameter. However, the type of semiconductor is not limited to silicon; other semiconductors can also be used. Furthermore, as the substrate of the wafer, an insulator wafer can be used, and a semiconductor layer can be grown on the surface of the insulator wafer using a specified crystal growth method.

[0093] 2) "Through hole": In semiconductor devices, this is a general term for the part that allows conduction between wiring layers such as gate wiring and metal wiring. Examples include contact holes connecting the silicon substrate to the upper wiring layer, cell contacts connecting capacitor electrodes to the substrate and wiring layers, and via holes connecting metal wiring layers.

[0094] 3) "Pre-processing": This refers to the process of forming an integrated circuit chip (bare die) on a semiconductor wafer, which consists of multiple active components (e.g., transistors) and achieves the overall function of the manufactured object.

[0095] 4) "First Semiconductor Manufacturing Site" and "Second Semiconductor Manufacturing Site": "First Semiconductor Manufacturing Site" refers to the site where the "front-end processes" and "front-end wiring processes" (described later) are performed in the wafer fabrication process for the semiconductor device to be manufactured. "Second Semiconductor Manufacturing Site" refers to the site where the "back-end wiring processes" (described later) are performed in the wafer fabrication process for the semiconductor device to be manufactured. The "First Semiconductor Manufacturing Site" and "Second Semiconductor Manufacturing Site" can be different sites, respectively called "First Semiconductor Factory" and "Second Semiconductor Factory." Alternatively, at least one of multiple "First Semiconductor Manufacturing Sites" and a "Second Semiconductor Manufacturing Site" can exist in different areas (e.g., different buildings) within the same factory site. However, as described below, after the "semi-finished wafers" manufactured in the "First Semiconductor Manufacturing Site" are temporarily stored as inventory in a "wafer warehouse," the selected wafers are sent to the manufacturing processes in the "Second Semiconductor Manufacturing Site" based on the selection made by the circuit designer in the back-end wiring process. Furthermore, different design rules and different wiring formation process technologies can be used in the "First Semiconductor Manufacturing Site" and the "Second Semiconductor Manufacturing Site."

[0096] 5) "Front-end wiring process": Within the first semiconductor manufacturing facility, the front-end process includes: a process of forming active components (e.g., transistors) on a semiconductor wafer (front-end process); and a process of electrically connecting multiple transistors through wiring layers via contact holes formed in the insulating layer on the transistors (first half of the back-end process). It includes at least the wiring process up to the cell contact, and may also include the metal wiring process up to the vias. In the front-end wiring process, multiple semiconductor circuits of various types formed on the semiconductor substrate correspond to independent functions of electrical circuits, including functional circuits and adjustment circuits.

[0097] 6) "Front-end process": This refers to the process in the preceding process of forming active components (e.g., transistors) on a semiconductor wafer. In the case of metal filling of the contact holes of transistors (e.g., the formation of W plugs), it includes the process up to the metal filling.

[0098] 7) "Back-end process": This refers to the process that forms multi-layer wiring after the front-end process. In silicon semiconductor technology, the metal wiring used for multi-layer wiring mostly uses aluminum wiring (including alloys with Al as the main material) for the lower layers and copper wiring for the upper layers. Furthermore, copper wiring often employs the so-called "dual damascene process." It should be noted that all wiring layers in the back-end process can also use aluminum wiring. Alternatively, all wiring layers in the back-end process can also use copper wiring based on the dual damascene process. However, the formation process for multi-layer wiring is not limited to these examples.

[0099] 8) "Functional circuit": This refers to multiple circuits on a semiconductor substrate that respectively implement multiple independent functions constituting the overall function of the semiconductor device being manufactured. It should be noted that functional circuits can also include "variable function circuits" whose independent functions and characteristics can be changed through subsequent wiring patterns. Variable function circuits include basic circuits and characteristic adjustment circuits. By selectively connecting the basic circuit and characteristic adjustment circuit using subsequent wiring patterns, different circuit functions and characteristics can be achieved. While there are no particular limitations on the basic circuit, it may include, for example, active circuits such as operational amplifiers and diodes. Characteristic adjustment circuits are passive circuits and include resistors, capacitors, inductors, etc. An "active circuit" is a circuit that includes active elements that perform active functions such as amplifying, rectifying, or converting the supplied electrical energy. A "passive circuit" is a circuit that includes only at least one passive element that performs passive actions such as consuming, storing, or releasing the supplied electrical energy.

[0100] 9) "Tuning circuit": This refers to multiple circuits that are separately mounted on a semiconductor substrate from multiple functional circuit blocks, and are used to fine-tune the performance of each functional circuit block. As long as the purpose is to fine-tune the performance of the functional circuits, the tuning circuit can include active components such as transistors (e.g., a single MOSFET) in addition to passive circuits. Furthermore, the tuning circuit can also be implemented as a combination of passive components and transistors.

[0101] 10) "Post-wiring process": This refers to the latter part of the front-end process, which is the second half of the back-end process. After the transistor fabrication process (front-end process) and the pre-wiring process are completed in the first semiconductor manufacturing facility, a second semiconductor manufacturing facility, different from the first semiconductor manufacturing facility, forms the wiring to connect the functional circuits and adjustment circuits formed on the semiconductor chip. Although not specifically limited, the post-wiring process can be configured to include: a process using a direct drawing technique with a photosensitive organic insulating film as an interlayer insulating film; and a process using a double damask technique to form copper wiring, performed the necessary number of times.

[0102] 11) "Back-end processes": These refer to the processes in the back-end wafer fab where semiconductor chips (bare dies) are diced from wafers that have formed semiconductor circuits in the front-end processes (front-end processes + front-end wiring processes + back-end wiring processes), and then bonded, packaged, and inspected before shipment. Further, this can also include the process of forming substrate-plated wiring on the bonding pads formed in the front-end processes, where bumps for flip-chip construction and stacking structures are formed on the substrate. That is, in the back-end processes, chips connecting wafers in a stacked structure can also be formed through flip-chip connections on the wafer substrate. It should be noted that the process of forming this plating wiring can also be included in the front-end processes.

[0103] 12) “Design Rules”: In this specification, “Design Rules” refers to the minimum design width of wiring in wafer fabrication.

[0104] 13) "Semi-finished wafer": refers to a semiconductor substrate (wafer) that is temporarily removed from the first semiconductor manufacturing site and stored in a designated storage area after the front-end wiring process is completed. Therefore, within the chip formed on the semiconductor substrate, multiple functional circuits and at least one adjustment circuit are formed through the front-end and front-end wiring processes. It is desirable that the protective film, described later, is formed over a generally complete area, in which multiple through-holes are formed for connections based on wiring in the subsequent wiring processes.

[0105] 14) "Stock": This refers to the situation where semi-finished wafers, after the front-end wiring process is completed, are temporarily stored in a designated storage area after leaving the first semiconductor manufacturing site. In cases where the "first semiconductor manufacturing site" and the "second semiconductor manufacturing site" are "first semiconductor factory" and "second semiconductor factory" operated by different operators, the semi-finished wafers are stored in a storage area (warehouse, etc.) as stock after leaving the first semiconductor factory. This storage area is called a "wafer warehouse".

[0106] Furthermore, although the definitions of the above terms are based on the definitions of representative technologies at the time of this application, with the development of technology, the technical content and process flow of semiconductor manufacturing processes are improved and modified, which does not prevent the interpretation from being changed within the scope of the spirit of this invention as described in the following specification.

[0107] In the first embodiment described below, silicon semiconductor is used as an example as the semiconductor substrate, and planar FET transistor is used as an example as the active element formed on the semiconductor substrate.

[0108] Furthermore, in the front-end wiring process, aluminum wiring is used as the lower-layer wiring, and the process of forming copper wiring using direct drawing technology with photosensitive organic insulating film as the interlayer insulating film and using double damask technology is described as the back-end wiring process. However, the process flow described above is not limited to the multilayer wiring process. In addition, as an example, the case where "first semiconductor manufacturing site" and "second semiconductor manufacturing site" are different factories, namely "first semiconductor factory" and "second semiconductor factory", will be described.

[0109] [Implementation Method 1] (An overview of the manufacturing process in Implementation Method 1) Figure 1 This is a conceptual diagram illustrating an outline of the manufacturing process of a semiconductor device according to Embodiment 1.

[0110] Reference Figure 1 The receiving wafers, the first half of the front-end process (front-end process and front wiring formation process) is handled by multiple semiconductor manufacturing plants, each corresponding to multiple functional circuit forming wafer fabs 01 to N (N≧2, natural number).

[0111] As will be described later, since functional circuit forming wafer fabs 01 to N each use different semiconductor process technologies to form semiconductor chips on silicon wafers, even based on the same design, the functional circuits may not necessarily have the same characteristics or perform the same function. Furthermore, the functional circuits that can be manufactured in functional circuit forming wafer fabs 01 to N have different performance characteristics, and the types of functional circuits that can be manufactured also differ. Correspondingly, the types and characteristics of the adjustment circuits formed in functional circuit forming wafer fabs 01 to N are also different.

[0112] By completing the pre-wiring formation process in the functional circuit forming wafer fab 01 to N, "functional circuits" and "adjustment circuits" corresponding to the respective functional circuit forming wafer fab 01 to N manufacturing processes are formed on the semiconductor wafer.

[0113] Here, on semiconductor wafers shipped from functional circuit forming wafer fabs 01 to N, although functional circuits that implement independent functions and adjustment circuits for fine-tuning them have been formed, the wiring for connecting the functional circuits to each other, connecting the functional circuits to the adjustment circuits, and connecting the adjustment circuits to each other has not been formed. Therefore, the "semiconductor device" that will become the final manufacturing object has not yet been formed on the semiconductor wafer; only the individual components have been formed. Therefore, semiconductor wafers shipped from functional circuit forming wafer fabs 01 to N are called "semi-finished wafers."

[0114] Semi-finished wafers, such as those produced from wafer fabs 01 to N, which are formed from multiple functional circuits, are temporarily stored as inventory in a place called a wafer warehouse. Semi-finished wafers stored in the wafer warehouse are called "inventory semiconductor wafers".

[0115] For designers of "semiconductor devices" that become the final manufacturing targets, they can sometimes manufacture the semiconductor devices they design and want to outsource manufacturing by connecting the functional circuits and adjustment circuits already formed on the wafers stored in the wafer library using wiring. In this case, the time required for the pre-wiring process can be omitted to manufacture prototypes.

[0116] In addition, in any of the multiple post-wiring process foundries 01 to M (M≧1, natural number), the prototype of a "semiconductor device" can be completed by connecting post-wiring on the stock semiconductor wafers stored in the wafer warehouse.

[0117] Moreover, as described below, the post-wiring formation process can employ direct drawing technology using a photosensitive organic insulating film as an interlayer insulating film and a double damask technology for forming copper wiring.

[0118] At this point, the front wiring formation process can be a pattern transfer process using a stepper or scanner with a reduced projection, employing a reticle-based stepping machine. As a result, the combination of functional and adjustment circuits fabricated up to the front wiring stage can contain multiple patterns (e.g., two combined patterns) within the same photomask. However, from the perspective of the semiconductor wafer as a whole, the same pattern of functional and adjustment circuit combinations will be repeated with the number of photomask exposure steps. Here, "step" refers to the process of photomask exposure in reticle-based exposure. In a stepper, a square area of ​​the photomask is exposed with a single shot in one step, while in a scanner, the photomask is synchronized with the wafer, irradiating light while laterally moving a narrow, elongated slit-shaped irradiation area.

[0119] While not specifically limited, for example, multiple functional circuits and multiple adjustment circuits may be pre-formed on the same die, allowing multiple chips (dies) to be contained within a single photomask. In such cases, the combination of functional circuits is common across these multiple chips (dies). However, the connection methods of the adjustment circuits between dies can be varied according to the characteristics and performance of the functional circuits. As a result, to achieve a semiconductor device with desired performance, the selection and connection methods of the adjustment circuits in combination with the functional circuits can be varied and manufactured within a single wafer. However, the range of variation for the selection and connection of these adjustment circuits is at least limited by the number of chips (dies) within the photomask. In other words, the range of variation in this case is generally limited to the number of chips within a single photomask as described above.

[0120] On the other hand, in this embodiment, although not specifically limited, the post-wiring photolithography process (pattern transfer process) is a process using direct drawing technology. Furthermore, with direct drawing technology, it is ultimately possible to form different post-wiring patterns for each semiconductor chip manufactured on a semiconductor wafer, based on the designer's design. In this case, the chip (die) located within the photomask is no longer subject to the limitation of shared wiring patterns between exposure steps, as was the case with the pre-wiring process.

[0121] In other words, for a chip (die) located at a specific position in the exposure step, if a stepper or scanning exposure machine using a photomask is used for exposure until the post-wiring process, the post-wiring will have the same pattern between different steps. In this case, the chip (die) at the aforementioned defined position within the photomask has a common functional circuit pattern and adjustment circuit pattern between different steps.

[0122] In contrast, if the post-wiring process is performed by direct drawing, then different post-wiring connection patterns can be formed between the chips (bare dies) on the semiconductor substrate.

[0123] As a result, within a single wafer, compared to dicing projection exposure, direct patterning allows for the prototyping of "combinations of functional circuits" and the corresponding "selection and connection methods of adjustment circuits in combination with functional circuits among multiple adjustment circuits" in a variety of variations.

[0124] As a result, when implementing the post-wiring process using direct drawing, the optimization of the post-wiring connection method (post-wiring pattern) is more ideal for a single production lot compared to the case using segmented projection exposure.

[0125] Furthermore, in the case of multi-layer routing in the front-end routing process, the topmost routing layer in the front-end routing process is the routing layer that forms a connection with the routing layer in the subsequent routing process. For example, it is also possible to use direct drawing technology in the photolithography of the etch mask used to form this topmost routing layer (e.g., Al routing). In this case, the minimum size requirement for the photolithography of the topmost routing layer in the front-end routing process is not as stringent as the requirement for the lower routing layers. On the other hand, by also using direct drawing technology in the front-end routing process, there is an advantage in terms of greater freedom in the variation of the pattern during the initial prototype and greater freedom in the pattern revision after the initial prototype. It should be noted that the routing layer using direct drawing technology in the front-end routing process is not limited to only the topmost routing layer. Multiple routing layers on the upper side of the front-end routing process can also be formed using direct drawing technology.

[0126] Therefore, if we follow the example shown below Figure 1 The manufacturing process shown can be used to manufacture semiconductor devices, and can provide a circuit design method that can be handled in a short time and at low cost for the casing identified in the first manufacturing of semiconductor integrated circuits.

[0127] That is, based on the problems identified in the first manufacturing process, sometimes the problem can be addressed by changing the wiring pattern in the subsequent wiring process. In this case, in the second and subsequent manufacturing processes, by using the results of the initial large-scale change in the wiring pattern, it is possible to manufacture a semiconductor chip with a small change range and a good yield that carries the desired semiconductor integrated circuit.

[0128] Here, for example, as a problem that may be identified in the first manufacturing process, the following is envisioned.

[0129] i) Performance degradation due to items not fully described in the datasheet (parasitic components, parasitic capacitance, noise, etc.) ii) Items that cannot be fully verified by simulation alone (circuit oscillation, input offset voltage, etc.) iii) Items identified due to insufficient simulation caused by inadequate setting of parasitic components or insufficient thermal design (such as thermal runaway). iv) Items determined after the manufacture of semiconductor integrated circuits (ESD (Electro-Static-Discharge) withstand capability, EMI (Electro-Magnetic Interference) withstand capability, etc.) v) Performance degradation due to mismatch in production line process performance (component performance). exist Figure 1In the manufacturing process shown, in order to solve the above problems through design improvements after they are identified, the functional circuit and the adjustment circuit are configured independently, and the connection between the functional circuit and the adjustment circuit is a structure that can be fully modified through subsequent wiring processes.

[0130] Moreover, since such changes are only made in the post-routing process, the likelihood of design changes used to address the problem being resolved before a comprehensive design improvement is increased.

[0131] As a result, it is possible to reduce development time and development costs.

[0132] (Example of cross-sectional structure of the manufacturing process based on this embodiment and details of the manufacturing process) Figure 2 This is a diagram illustrating an example of the cross-sectional structure of a semiconductor device demonstrating the manufacturing process of this embodiment.

[0133] Figure 3 It is used for explanation Figure 2 A conceptual diagram of the manufacturing process of a semiconductor device.

[0134] Reference Figure 2 and Figure 3 In the design process, functional circuits corresponding to independent functions that achieve the overall function of the semiconductor device to be manufactured, and adjustment circuits corresponding to these functional circuits, are designed according to the procedure described below. This process produces a photolithography mask for the processes (front-end processes + front wiring processes) implemented in the wafer fab where the functional circuits are formed. As described above, such a photolithography mask can be used as a photomask for optical stepper machines and scanning photomasks.

[0135] It should be noted that, as Figure 2 As shown, the adjustment circuit ACKT and the functional circuit FCKT are separately disposed on the semiconductor substrate SUB, and are used to fine-tune the performance of the functional circuit ACKT.

[0136] After the mask is fabricated and the semiconductor substrate (SUB) (bare wafer) is received by the functional circuit forming wafer fab, it undergoes a prescribed cleaning and drying process. The silicon wafer surface is then thermally oxidized, and a silicon nitride film is formed on top of the oxide film using methods such as reduced-pressure CVD (Chemical Vapor Deposition). Shallow trenches are then etched using a slicing projection lithography process to form a buried oxide film. The buried oxide film is formed using methods such as CVD. Then, the buried oxide film is planarized using CMP (Chemical Mechanical Polishing), and the oxide and nitride films are removed, thus forming the device separation region (ISO). This is called Shallow Trench Isolation (STI) technology. Depending on the processing size, other methods for forming device separation regions, such as Local Oxidation of Silicon (LOCOS) technology, can also be used.

[0137] Next, after forming the sacrificial oxide film, the well region for forming the MOSFET is formed through ion implantation and activation annealing. For CMOS, a p-type P-well and an n-type N-well are formed as a double-well configuration, but... Figure 2 It is assumed to be a single well.

[0138] Next, a polycrystalline silicon film and a silicide film are stacked to form the gate oxide (GOF) and gate electrode material (TG). A photolithography process using segmentation projection exposure is used to form a photoresist pattern for the gate electrode, and the gate electrode is formed by etching. Then, after removing the photoresist, the drain region (DL) and source region (SL) are formed by ion implantation and annealing, for example, using a self-aligned technique.

[0139] Next, using techniques such as plasma CVD, an etch stop layer and an interlayer insulating film, known as a PMD (Pre Metal Dielectric) film, are formed. Planarization is also performed here using CMP (Cellular Metallurgy) technology.

[0140] Then, a photoresist pattern is formed using a segmented projection photolithography process, and the contact holes of the source region (SL) and drain region (DL) are etched. After the photoresist is removed, a glue layer (TiN / Ti, etc.) based on sputtering and a blanket tungsten film based on reduced pressure CVD are formed within the contact holes. Excess blanket tungsten film and glue layer on the PMD film are removed using a CMP process to form the blanket tungsten plug (CH) within the contact holes. It should be noted that although not shown in the figure, the blanket tungsten plug within the contact hole of the gate electrode is also formed simultaneously.

[0141] Then, as the first metal wiring layer, an aluminum wiring layer is formed, for example, by sputtering. A photoresist pattern is formed by a photolithography process using a segmented projection exposure method. The pattern of the first metal wiring layer M1 is formed by dry etching. After the photoresist is removed, an insulating film layer of silicon oxide is further formed, and then planarization is performed again using CMP technology. Finally, a silicon nitride film PLV1 is formed as a passivation film in the previous wiring process.

[0142] Although not specifically limited, the silicon nitride film PLV1 functions as a protective or passivating film for circuits on a semiconductor substrate that is a semi-finished product after the pre-wiring process.

[0143] By forming a protective film, impurities such as moisture and sodium from the outside air are prevented from penetrating into the circuitry on the semi-finished semiconductor substrate.

[0144] Then, in the topmost layer of the preceding wiring process (the first metal wiring M1 in this example), a via V1 is formed for connecting the metal wiring M2 in the subsequent wiring process. The via V1 can be formed by dry etching of a photoresist pattern obtained by a photolithography process based on a segmented projection exposure method.

[0145] After via V1 is formed, the photoresist is removed.

[0146] At this point, the front-end process and the front-wiring process are completed. Then, after implementing the formed functional circuit, adjusting the electrical characteristics of the circuit, etc., the test results are stored in a designated shared storage area (e.g., storage device 2300 described later) and shipped to the wafer warehouse as stock semiconductor wafers. Because the silicon nitride film PLV1 is formed on the surface, even in this way, the impact on reliability can be suppressed.

[0147] Therefore, the semiconductor substrates of semi-finished products shipped to the wafer warehouse do not achieve overall functionality at the time of shipment, and are thus referred to as "semi-finished wafers" as described above.

[0148] It should be noted that, although not specifically limited, the formation of via V1 can also be performed at the very beginning of the post-routing process. For example, in the pre-routing process, the via V1 is opened only in the TEG (Test Element Group) portion for circuit testing, and the via V1 in the connection portion with the wiring in the post-routing process can also be opened by etching in the post-routing process. Such etching is performed by forming an etched photoresist mask using photomask-based exposure or direct drawing techniques, such as dry etching.

[0149] Based on the test results, the design process for post-wiring is implemented (not shown). The inventory of semiconductor wafers suitable for forming the semiconductor integrated circuits envisioned by the designer is searched and selected in the wafer library and shipped to the post-wiring process wafer fab.

[0150] It should be noted that, as described below, designers can choose from multiple wafer fabs that can form the desired semiconductor integrated circuits.

[0151] When the back-end wiring process wafer fab receives inventory semiconductor wafers that have had vias V1 formed up to the point of the front-end wiring process, it forms the interlayer insulating film for the back-end wiring process with a photosensitive organic insulating film. Although there are no particular limitations, photosensitive polyimide or the like can be used as the photosensitive organic insulating film.

[0152] In the post-wiring process, direct drawing is performed on photosensitive polyimide, for example, using a laser direct drawing device. Laser direct drawing allows for simple drawing under atmospheric pressure, making it suitable as a wiring formation process in the post-wiring process. After direct drawing, unwanted portions of the photosensitive polyimide are removed through a developing process to form a pattern for wiring M2 corresponding to via V1, and then cured.

[0153] However, as a technique for direct drawing, techniques other than lasers can also be used, and photosensitive resins other than photosensitive polyimide can also be utilized.

[0154] Next, wiring M2 is formed using a double damask process.

[0155] Furthermore, a photosensitive organic insulating film is coated onto the wafer again, and the via V2 pattern and the corresponding wiring M3 pattern are formed by direct drawing, followed by curing. Wiring M3 is formed using a double damask process.

[0156] Next, the final passivation film PLV2 is formed. The passivation film PLV2 can be, for example, a silicon nitride film based on plasma CVD.

[0157] In the photolithography and etching processes, an opening is formed in the passivation film PLV2 of the specified area of ​​the wiring M3, and in the wiring film formation process, a bonding pad BP is formed.

[0158] It should be noted that photolithography using photoresist and masks can be used for etching these vias, or direct patterning techniques can be used. When using such photolithography, the prerequisite is that the chip mounting frame in the subsequent assembly process has been standardized. That is, the prerequisite is that the pad positions on the chip side where wire bonding is performed have been standardized. However, there is a possibility that pads may not be wire-bonded due to bonding options, etc. With direct patterning, even such situations can be flexibly addressed, and a via structure requiring only the necessary openings can be adopted.

[0159] It should be noted that the semiconductor manufacturing processes described above can be achieved through combinations of currently commonly used process technologies; therefore, detailed descriptions of the process conditions for each step are omitted. Those skilled in the art can set the process conditions and execute each step.

[0160] (Design platform structure) Figure 4 This is a conceptual diagram illustrating the structure of the design platform of the design aid system used to explain this embodiment.

[0161] Figure 5 This is an explanation of the extraction process. Figure 4 A conceptual diagram of a portion of the server device that provides the design platform in the structure shown.

[0162] It should be noted that, Figure 4 and Figure 5 The server device shown can be either an on-premise server or a cloud server. However, from the perspective of multiple designers sharing and utilizing data, a cloud server is preferable. Here, designers can belong to the same enterprise or different enterprises.

[0163] Furthermore, the designers who set up the functional circuits and the designers who design the semiconductor devices (post-wiring processes) that become the final product can be designers within the same company or designers from different companies. Figure 4 In general, the records document the circumstances of designers from different companies.

[0164] When the company designing the functional circuit and the company designing the semiconductor device as the final product are different entities, the company designing the functional circuit may provide functional circuit design information to companies that manufacture and sell the semiconductor device as the final product. Alternatively, the company to which the designer of the semiconductor device as the final product belongs may sell semi-finished wafers stored in the wafer warehouse (WBANK) to companies that manufacture and sell the semiconductor device as the final product.

[0165] By setting the design platform as Figure 4 The structure shown can realize various business models.

[0166] Reference Figure 4 and Figure 5 The design platform is a design aid system that provides circuit design tools to assist in the manufacturing of semiconductor devices in collaboration with wafer fabs WFFAB.1 to WFFAB.N for functional circuit formation and wafer fabs WLFAB.1 to WLFAB.M for post-wiring processes.

[0167] The functional circuit forming wafer fabs WFFAB.1 to WFFAB.N are the first manufacturing processes of the first design rule, responsible for the front-end routing process. The back-end routing wafer fabs WLFAB.1 to WLFAB.M are the second manufacturing processes of the second design rule, which is different from the first design rule, responsible for the back-end routing process.

[0168] The functional circuit forming wafer fabs WFFAB01 to WFFABN provide design reference data (PDK) to the design platform, and the storage device 1500 saves it as design reference data 1500.1 for the pre-routing process.

[0169] The functional circuit design tool, provided by server 1000, assists in designing circuit patterns for the pre-wiring process of forming multiple circuit blocks on a semiconductor substrate. Here, the multiple circuit blocks include multiple functional circuit blocks, each used to implement multiple independent functions constituting the overall function of the semiconductor device being manufactured on the semiconductor substrate. Furthermore, the multiple functional circuit blocks include multiple stock circuit blocks, which, based on the aforementioned first design rule, have pre-prepared circuit pattern design information corresponding to the manufacturing processes of each functional circuit forming wafer foundry WFFAB.1 to WFFAB.N. The design information of these stock circuit blocks is stored in storage device 1600 as a functional circuit design library 1600.1, and the performance information (specification information) of the stock circuit blocks is stored as standard circuit performance information 1600.2.

[0170] The functional circuit design tool provides servers 1000 to designer terminals 5000.1 to 5000.P (P: a natural number) to assist in the design of selecting a specified number of stock circuit blocks from multiple stock circuit blocks to implement the overall function of the semiconductor device and configuring them on a semiconductor substrate. Here, "design assistance" refers to assistance with logic design and pattern design, which may be configured to be implemented by collaborating with existing EDA tools.

[0171] In addition, multiple circuit blocks include multiple adjustment circuit blocks, which are separately disposed on the semiconductor substrate from the multiple functional circuit blocks, and the performance implemented by the functional circuit blocks is fine-tuned separately. The design information of the adjustment circuit is stored in the adjustment circuit design library 1600.3, and the performance information of the adjustment circuit is stored as standard circuit performance information 1600.2.

[0172] It should be noted that after the pre-wiring process is completed, the functional circuit design information and specifications of the functional circuits, as well as the design information and specifications of the adjustment circuits for the semi-finished wafers stored in the wafer library (WBANK), are saved in the storage device 2300 as a wafer library inventory information database (hereinafter referred to as "wafer library inventory information DB") 2300.1. Although not specifically limited, it can be configured such that the functional circuit design tool providing server 1000 performs the storage of information to such wafer library inventory information DB 2300.1 and the updating of information as described below.

[0173] When the functional circuit design tool server 1000 determines that wafers containing functional and adjustment circuits capable of achieving the overall function are stored in the wafer library WBANK, it provides the designer terminals 5000.1 to 5000.P with the functional and adjustment circuits to be connected to these wafers via post-routing, thereby confirming through simulation that the desired overall function can be achieved. If the functional circuit design tool server 1000 determines that the simulation results achieve the overall function, it selects these stored semi-finished wafers as wafers to be sent to the post-routing process. Information showing that such a selection has been made is stored in the wafer library inventory information DB2300.1.

[0174] It should be noted that when a specific company sends a wafer that has been selected to be stored in the wafer library WBANK to the post-routing process, access to the wafer's inventory information DB2300.1 in the wafer library is managed to be restricted to that specific company.

[0175] On the other hand, the functional circuit design tool provides server 1000 with the assistance of designing new functional circuits and adjustment circuits to manufacture the insufficient functions when it is determined that the inventory of semi-finished wafers is insufficient to achieve the overall function. In addition to the selected number of inventory circuit blocks and corresponding adjustment circuit blocks, the tool also assists in the design of new functional circuits and adjustment circuits to manufacture the insufficient functions.

[0176] It should be noted that, as an example, as described above, the designer terminal 5000.1 to 5000.P can be located in a different company (functional circuit design company) from the company that implements the post-routing design process (fabless manufacturer). However, the designer terminal 5000.1 to 5000.P can also be located in the same company as the company that implements the post-routing design process.

[0177] Additionally, as described later, the storage device 1500 stores a function-facility relationship database (hereinafter referred to as "function-facility relationship DB") 1500.2, which is used to select and determine the functional circuit forming fabs WFFAB.1 to WFFAB.N responsible for manufacturing the semiconductor substrate that achieves the overall function of the semiconductor device. Based on PDK information, the function-facility relationship DB 1500.2 stores the correspondence between "independent functions" used to achieve the overall function and "design information in the functional circuit design library 1600.1 and adjustment circuit design library 1600.3". The "functional circuit design library 1600.1 and adjustment circuit design library 1600.3" are provided in advance for the processes corresponding to the functional circuit forming fabs WFFAB.1 to WFFAB.N.

[0178] The functional circuit design library 1600.1 and the adjustment circuit design library 1600.3 are collectively referred to as "IP core design information". Within the corresponding wafer foundries WFFAB.1 to WFFAB.N for each functional circuit, the IP core design information includes the types of functional circuits that can be manufactured, their design information, and specifications; as well as the types of adjustment circuits that can be manufactured, their design information, and specifications. This information can be configured and provided as a PDK (Product Development Kit).

[0179] In addition, the multiple functional circuit blocks include at least one custom circuit block, which is based on the first design rules of the selected wafer fabs WFFAB.1 to WFFAB.N formed by the functional circuits, and the design information of the circuit pattern designed by any one of the designer terminals 5000.1 to 5000.P.

[0180] When the functional circuit design tool providing server 1000 determines that multiple stock circuit blocks are insufficient to achieve the overall performance, it displays a prompt to implement the design of custom circuit blocks for the designer terminals 5000.1 to 5000.P, which are performing designs corresponding to the previous wiring process. Then, based on the IP core design information, the functional circuit design tool providing server 1000 performs logic and pattern design assistance for the custom circuit blocks and corresponding adjustment circuit blocks according to the first design rule corresponding to the wafer fab selected to manufacture the semi-finished wafer that achieves the overall function. Here, when the wafer fab responsible for manufacturing the semi-finished wafer that achieves the overall function is selected based on the IP core design information, it can be configured to select a wafer fab capable of producing the most functional circuits corresponding to the individual functions required to achieve the overall function. In the case of implementing custom circuit block design, the functional circuit design tool providing server 1000 provides mask data for photomask fabrication to the selected wafer fab among the functional circuit forming wafer fabs WFFAB.1 to WFFAB.N.

[0181] It should be noted that by selecting the company responsible for the front-end wiring design, the design information of newly designed custom circuit blocks and corresponding adjustment circuit blocks can also be added to the "IP Core Design Information". In this case, the newly designed custom circuit block is added as one of the inventory circuit blocks.

[0182] The post-routing design tool provides server 2000 to designer terminals 5100.1 to 5000.Q (Q: a natural number) to assist in designing circuit patterns in the post-routing process for selectively connecting multiple circuit blocks formed in the pre-routing process. It should be noted that among the multiple circuit blocks formed in the pre-routing process, there may also be circuit blocks that are not prominently connected to any other circuit blocks through post-routing and are therefore not used.

[0183] The post-routing design tool server 2000 selects any one of the wafer fabs WLFAB.1 to WLFAB.M from the manufacturing process of a plurality of stock circuit blocks selected for manufacturing. There are no particular restrictions on this selection, but, for example, as described below, it can also be configured to select based on the pattern and size information of the contact portion between the topmost routing layer of the preceding routing process and the routing formed by the subsequent routing process, and based on the overlay margin during exposure in the subsequent routing process. Then, the post-routing design tool server 2000 performs logic design and pattern design assistance for the post-routing process using a second design rule corresponding to the first design rule of the selected stock circuit block. Here, "design assistance" also refers to assistance with logic design and pattern design, and can be implemented, for example, by collaborating with existing EDA tools.

[0184] Corresponding to the post-routing process, the storage device 2500 stores routing structure design reference data 2500.1 provided as a PDK from the post-routing wafer fabs WLFAB.1 to WLFAB.M, and adjustment circuit parameter data 2500.2 showing the performance parameters of the adjustment circuit formed in the previous process. The performance parameters of the adjustment circuit can be configured to include not only design parameters but also information on the results of circuit tests performed in the previous routing process.

[0185] The post-routing design tool provides server 2000 with reference wafer library inventory information DB2300, and performs post-routing logic design and pattern design on wafers sent to the post-routing process based on routing structure design baseline data 2500.1 and adjustment circuit parameter data 2500.2 (including test data of functional circuits in the pre-routing process).

[0186] The back-routing design tool provides server 2000 with drawing data for direct drawing to selected wafer fabs in the back-routing process, WLFAB.1 to WLFAB.M.

[0187] Once the post-wiring process is completed, the subsequent processes are carried out in any of the assembly process wafer fabs ASFAB.1 to ASFAB.L, which are responsible for the assembly process, and finally the semiconductor device is shipped out as a product.

[0188] Design terminals 5000.1 to 5000.Q can, according to the designer's or the company to which the designer belongs, continuously accumulate relevant information about the problems identified during prototyping and the methods for solving these problems through redesign and reprototyping. This information is stored in the Problem Information + Solution Information Database (hereinafter referred to as "Problem Information + Solution Information DB") 2200.1 of storage device 2200. Once the information is stored in the Problem Information + Solution Information DB 2200.1, it can be referenced from designer terminals 5000.1 to 5000.P, and thus used as a reference in the selection of functional circuits provided by the functional circuit design tool server 1000 and in the circuit pattern design in the pre-wiring process. In this way, by referring to information on past defects, the lead time for prototyping can be further shortened.

[0189] It should be noted that the information stored in the Project Information + Solution Information DB2200.1 can also be configured to be referenced only by the designer terminal 5000.i of the company that is authorized to reference the information, through separate contracts signed with the company responsible for the design of the subsequent wiring process.

[0190] Alternatively, the information stored in the problem information + solution information DB2200.1 can also be widely used outside the enterprise. In any case, the scope of information that an enterprise can access depends on the consensus reached by the platform's operators and users.

[0191] Furthermore, in the functional circuit design tool providing server 1000, artificial intelligence can learn by using information stored in the problem information + solution information DB2200.1 as learning data and taking the problem information as input to output a solution. In this case, the functional circuit design tool providing server 1000 can also be configured to automatically provide a solution to the problem to the designer terminals 5000.1 to 5000.P. Alternatively, the content of artificial intelligence learning is not limited to this structure. For example, if the problem information is generated by accumulating combinations of specific functional circuits or combinations of specific functional circuits with specific adjustment circuits, it can be configured to provide warnings about the possibility of defects to the designer terminals 5000.1 to 5000.P while the designer is performing design processing.

[0192] (Conceptual diagram of functional and wafer fab relationship data) Figure 6 This is a conceptual diagram showing the outline of the structure of DB1500.2, including its functions and wafer fab relationships.

[0193] Figures 7-10 This is a diagram illustrating the details of the DB1500.2 structure, which is used to explain the functions and wafer fab relationships.

[0194] Reference Figure 6 The DB1500.2 database stores the following correspondence between functions and wafer fabs.

[0195] That is, the function and foundry relationship DB1500.2 includes: a first correspondence relationship TBL1, which indicates the correspondence between functional circuit blocks corresponding to multiple independent functions that constitute the overall function of the application and the product, and the relationship between adjustment circuits corresponding to the functional circuit blocks and capable of fine-tuning their performance; and a second correspondence relationship TBL2, which is the relationship between the performance specifications of the independent functions of the functional circuit blocks and the performance specifications of the adjustment circuit blocks, and the relationship between multiple IP core design information groups used to implement the performance specifications respectively.

[0196] Figure 7 The details of the first correspondence TBL1 are shown.

[0197] For example, as a semiconductor layer device that becomes the final product, in the case of a semiconductor integrated circuit for motor control, (function AA, function BB, ...) are required as independent functions.

[0198] Corresponding to these independent functions (function AA, function BB, ...), there are corresponding functional circuits (analog-to-digital converter circuit ADC, digital-to-analog converter circuit DAC, ...), and performance specifications are set for each functional circuit.

[0199] Similarly, corresponding to the independent functions (function AA, function BB, ...), there are adjustment functions (transistor capacitor adjustment, constant current source current value adjustment, phase margin adjustment, ...) and corresponding functional circuits, and the specifications of these performances are also set.

[0200] exist Figure 7 In the diagram, 0 indicates the existence of corresponding functional circuits and adjustment circuits for the required independent functions and each adjustment function.

[0201] It should be noted that the functional circuits corresponding to independent functions are not limited to the above-mentioned contents, and also include the following circuits.

[0202] • OSC (oscillator circuit) • RTC (Real-time Clock) circuit • PLL (Phase-locked loop) circuit • VCO (Voltage Controlled Oscillator) • OP-AMP (Operational Amplifier Circuit) COMP (comparator) • REF (reference voltage generation circuit, reference current generation circuit) • POR (Power-on reset circuit) • REG (voltage regulator circuit) •CP (charge pump circuit) • I / O (Input / Output) circuits •MEM (small-scale memory circuits) It should be noted that, as a functional circuit, it is not limited to these.

[0203] In addition, the corresponding adjustment circuit also includes the following circuit.

[0204] • Passive circuits such as parasitic element adjustment Input offset voltage adjustment circuit Noise adjustment circuit Thermal runaway control circuit • ESD tolerance adjustment circuit EMI tolerance adjustment circuit • Resistor and capacitor adjustment array circuit It should be noted that the adjustment circuit is not limited to these.

[0205] Figure 8 This shows the functional circuits and their specifications used to implement independent functions, as well as the adjustment circuits and their specifications, and their relationship to the pre-prepared IP core design information (IP core group 1, IP core group 2, ..., custom core) that can be implemented respectively. Correspondences are also indicated here with 0.

[0206] IP core group i (i: natural number) contains design information for stock circuit blocks, while custom cores contain design information for custom circuit blocks.

[0207] Each IP core design information group contains "design information for stock circuit blocks" that specify a pre-defined independent circuit pattern capable of achieving at least one performance specification for an independent function.

[0208] Back Figure 6 The DB1500.2 document contains the IP core design information (IP core group 1, IP core group 2, ..., custom core) as circuit design information, and the correspondence between the IP cores that can be manufactured in the functional circuit forming wafer fabs WFFAB.1 to WFFAB.N, respectively, in document TBL3. Figure 9 The following correspondence is shown in TBL3.

[0209] Furthermore, the DB1500.2 document contains the correspondence between the IP core design information that can be manufactured and the corresponding foundry and manufacturing process (based on the first design rule) in the TBL4 document. Figure 10 The following correspondence is shown in TBL4.

[0210] The functional circuit design tool server 1000 selects an IP core design information group containing combinations of functional circuit blocks capable of implementing the overall function, based on the function and wafer fab relationship DB1500.2. Then, the functional circuit design tool server 1000 determines the wafer fab corresponding to the selected IP core design information group from the functional circuit forming wafer fabs WFFAB.1 to WFFAB.N, and performs logic design and pattern design based on the first design rule corresponding to the determined wafer fab.

[0211] (The structure and operation of the design platform server) The following diagram illustrates the structure and operation of the server that constitutes the design platform.

[0212] Figure 11 This is a diagram showing the structure of the functional circuit design tool providing server 1000, the back-wiring design tool providing server 2000, and the designer terminal 5000.1 to 5000.P.

[0213] Here, it is assumed that designer terminals 5000.1 to 5000.P correspond to designer terminals 5000.1 to 5000.Q respectively, and the illustrations of designer terminals 5000.1 to 5000.Q are omitted. Hereinafter, when referring to designer terminals 5000.1 to 5000.P in general, they will be referred to as designer terminal 5000.

[0214] As an example, the functional circuit design tool providing server 1000 and the back-wiring design tool providing server 2000 of the design platform are servers in the cloud, which can be communicatively connected to the designer terminal 5000.1 to 5000.P via network 2.

[0215] (The functional circuit design tool provides the structure and operation of the server 1000) Figure 12 This is a function block diagram showing the structure of server 1000 provided by the functional circuit design tool.

[0216] Figure 15 and Figure 16 This is a flowchart used to illustrate the operation of the server 1000 provided by the functional circuit design tool.

[0217] Reference Figure 12 The functional circuit design tool provides a server 1000 including a communication interface 1002 for implementing communication with the outside world, an arithmetic processing unit 1100, and a memory 1200 that runs as a job storage area of ​​the arithmetic processing unit 1100.

[0218] Figure 15 , Figure 16 The semiconductor acquisition module 1110, independent function setting module 1120, adjustment circuit setting module 1130, IP core selection module 1140, foundry selection module 1150, logic circuit design module 1160, circuit pattern design module 1170, and mask pattern generation module 1180 described herein, when the server 1000 is provided with a computer as a functional circuit design tool, are equivalent to the CPU (Central Processing Unit) equivalent to the arithmetic processing unit 1100 executing the functions of the corresponding modules in the program stored in the memory.

[0219] Reference Figure 12 and Figure 15 , Figure 16 When the designer sets the overall function of the semiconductor circuit to be designed and the specifications of the independent functions used to implement the function through the designer terminal 5000 (S100), the functional circuit design tool provides the semiconductor manufacturing acquisition module 1110 and the independent function setting module 1120 of the server 1000 to obtain the information of the overall function and the independent function. Based on the specifications of the functional circuit that implements the independent function, the IP core selection module 1140 explores the IP core design information that can achieve the overall function (S104).

[0220] When the IP core selection module 1140 determines that the overall function can be achieved using the functional circuit IP core library in the inventory (S106 is Y), it selects the IP core group that can achieve the required functional circuit and adjustment circuit (step 108). On the other hand, when the IP core selection module 1140 determines that the overall function cannot be achieved (S106 is N), the processing is transferred to... Figure 16 Step 150.

[0221] Returning to step 108, the foundry selection module 1150 then selects a foundry that has the capability to implement the selected IP core group process (step S110).

[0222] Depending on the choice of the contract manufacturer, the designer sets the specifications of the adjustment circuit (S112) for changing the characteristics of the functional circuit through the designer terminal 5000.

[0223] The foundry selection module 1150 reads the inventory design information of the adjustment circuit corresponding to the functional circuit of the set specification from the database in the storage device 1600 (step S114), and determines whether there is a wafer with a circuit formed in the wafer library by referring to the inventory information DB2300.1 in the wafer library (S116).

[0224] When the foundry selection module 1150 determines that a wafer has already been formed (S116 is Y), the logic circuit design module 1160 and the circuit pattern design module 1170 obtain the circuit configuration information of the wafer in the wafer library (S118) and transfer it to the foundry selection module 1150. Figure 16 In step S164, the wafer library inventory information DB2300.1 is updated in a manner that specifies the wafers sent to the subsequent routing process in the wafer library inventory information DB2300.1.

[0225] On the other hand, in the absence of a formed wafer (S116 is N), the foundry selection module 1150, logic circuit design module 1160 and circuit pattern design module 1170 design and determine the configuration of the IP core (functional circuit and adjustment circuit) in the photomask within the IP core group (S120).

[0226] Reference Figure 16 In step S106, if the IP core selection module 1140 determines that the overall function cannot be realized (S106 is N), it notifies the designer terminal 5000 of the situation, and the designer sets the specifications of the insufficient independent functional circuits through the designer terminal 5000 (S150).

[0227] The logic circuit design module 1160 provides logic design for the independent functional circuit with insufficient auxiliary functions and the corresponding adjustment circuit (S152).

[0228] Next, the circuit pattern design module 1170 designs the functional circuit that has been logically designed and adjusts the circuit pattern, which is stored in the storage device 1600 as customized design information. In addition, the function and foundry relationship DB are updated (S154).

[0229] Furthermore, the logic circuit design module 1160 and the circuit pattern design module 1170, based on the inventory design information of the functional circuits and adjustment circuits in the inventory and the generated customized design information, assist in the logic design for achieving the overall function and the pattern design when necessary, and simulate the possibility of achieving the overall function (S156).

[0230] When the designer instructs the circuit layout design based on the process structure design benchmark of the corresponding foundry through the designer terminal 5000 (S158), the circuit pattern design module 1170 determines the pattern and configuration of the front-end process and front wiring process of the functional circuit and the adjustment circuit that can achieve the target function (S160), and the mask pattern generation module 1180 generates and outputs mask data based on the configuration information in the photomask of the functional circuit and the adjustment circuit (S162).

[0231] The logic circuit design module 1160 and the circuit pattern design module 1170 update the wafer warehouse inventory information DB based on the completion of the previous wiring process and the wafer warehouse inventory information (S164).

[0232] (The back-wiring design tool provides the structure and operation of Server 2000) Figure 13 This is a function block diagram showing the structure of the server 2000 provided by the back-wiring design tool.

[0233] Figure 17 This is a flowchart used to illustrate the actions of the post-wiring design tool for Server 2000.

[0234] Reference Figure 13 The back-wiring design tool provides a server 2000 including a communication interface 2002 for implementing communication with the outside world, a computing unit 2100, and a memory 2200 that runs as a job storage area of ​​the computing unit 2100.

[0235] Figure 17 The semiconductor acquisition module 2110, independent function setting module 2120, adjustment circuit setting module 2130, IP core selection module 2140, foundry selection module 2150, logic circuit design module 2160, circuit pattern design module 2170, and drawing data generation module 2180 described herein, when the server 2000 is provided with a computer as a back-wiring design tool, are equivalent to the CPU, which is equivalent to the arithmetic processing unit 2100, executing the functions of the corresponding modules in the program stored in the memory.

[0236] Reference Figure 13 and Figure 17 When setting the overall function of the manufactured semiconductor device in the designer terminal 5000, and... Figure 12Similarly, through the semiconductor acquisition module 2110, independent function setting module 2120, adjustment circuit setting module 2130, IP core selection module 2140, and foundry selection module 2150, the foundry to be selected from the independent functions and adjustment functions is determined, the test result data of the wafers that have completed the pre-routing process is obtained (S200), and the wafers to be sent to the post-routing process are searched and selected from the wafer library (S202). It should be noted that if a company that has implemented the pre-routing process design also implements the post-routing process design, the wafers to be sent to the post-routing process can be determined from the wafer library based on the information obtained from the pre-routing process design.

[0237] When the designer terminal 5000, referencing the wafer library inventory information DB, indicates the presence of wafers with pre-formed circuits in the wafer library (S204 is Y), the post-routing design tool providing server 2000 selects an adjustment circuit from the performance margin of the functional circuit and prompts it to the designer terminal 5000 (S206). Then, when specifying the connection between the functional circuit and the adjustment circuit in the designer terminal 5000 (S208), the logic circuit design module 2160 performs logic circuit design (including simulation) in the post-routing process. Based on the results of the logic circuit design, the logic circuit design module 2160 prompts the designer terminal 5000 with candidate functional circuits and adjustment circuits that can achieve the target function (S210). The designer terminal 5000 selects candidate functional circuits and adjustment circuits that can achieve the target function (S212) and instructs the design of the routing layout based on the structural design reference of the corresponding post-routing process technology (S214). The circuit pattern design module 2170 generates the routing layout according to the instruction, and the drawing data generation module 2180 generates and outputs the drawing data (S216).

[0238] Figure 14 It is used for explanation Figure 12 The functional circuit design tool shown provides a block diagram of the hardware structure of the server 1000.

[0239] It should be noted that the following assumes that the functional circuit design tool providing server 1000 runs on a server in the cloud. However, the functional circuit design tool providing server 1000 can also run, for example, on an internally deployed server.

[0240] It should be noted that although the following explanation uses the structure of the server 1000 provided by the functional circuit design tool as an example, the hardware structures of the server 2000 and the designer terminal 5000 provided by the post-wiring design tool are basically the same.

[0241] Reference Figure 14Server 1000 can be configured to perform computational processing using its own internal computing unit (CPU). Part of the program processing can also be executed on other servers. The following describes the scenario where the computing unit within its own chassis performs computational processing.

[0242] Reference Figure 14 The server 1000 includes a computer device 1010, a network communication unit 1012 for communicating with a network, and a recording medium (e.g., a memory card) 1210 for recording data from the outside and providing it to the computer device 1010.

[0243] It should be noted that, for example, the recording medium 1210 can be a USB memory, memory card, external storage device, etc. Furthermore, the network communication unit 1012 can utilize wired LAN or wireless LAN communication functions, for example. The network communication unit 1012 and the input / output interface 1090 constitute the communication interface 1002.

[0244] like Figure 14 As shown, the main computer unit constituting the computer device 1010, in addition to the disk drive 1030 and the memory drive 1020, also includes a CPU 1100 connected to the bus 1050, a memory 1200 including ROM (Read Only Memory) 1200.1 and RAM (Random Access Memory) 1200.2, a non-volatile, rewritable, non-volatile storage device 1300, and an input / output interface 1090 for communication via a network and for sending and receiving data with external devices. The non-volatile storage device 1300 may be, for example, an HDD (Hard Disc Drive) or an SSD (Solid State Drive). The following description uses an SSD as an example. An optical disc can be installed in the disk drive 1030. A memory card 1210 can be installed in the memory drive 1020.

[0245] During the program execution of computer device 1010, the data and program information that form the basis of the computer's operation are stored in SSD 1300.

[0246] It should be noted that, in Figure 14In this context, the medium that records information such as programs installed on the computer body can be, for example, a DVD-ROM (Digital Versatile Disc), a memory card, a USB storage device, etc. Correspondingly, the computer body is equipped with a drive device (memory drive 1020, disk drive 1030) capable of reading these media.

[0247] The main components of the computer device 1010 consist of computer hardware and software executed by the CPU 1100. Generally, this software is stored in a storage medium or circulated via a network, and is acquired via the disk drive 1030 and network communication unit 1012 and temporarily stored in the SSD 1300. It is then further read from the SSD 1300 into the RAM 1200.2 in memory, where it is executed by the CPU 1100. It should be noted that, in the case of a network connection, the software may not be stored in the SSD 1300, but may be directly loaded into RAM for execution.

[0248] The program that enables the computer device 1010 to function does not necessarily need to include an operating system (OS) that enables the computer 1010 to perform functions such as information processing. The program only needs to contain instructions that call appropriate functions (modules) in a controlled manner to obtain the desired results. How the computer system 1010 operates is well-known, and detailed explanations are omitted.

[0249] Furthermore, the CPU1100 can be a single-core processor or a multi-core processor. That is, it can be either a single-core or multi-core processor. Additionally, the server 1000 can be composed of multiple servers configured to perform distributed processing.

[0250] (The structure of the die after the pre-wiring process and the die after the post-wiring process) Figure 18 This is a diagram used to illustrate a bare die formed on a semiconductor substrate after multiple pre-wiring processes.

[0251] exist Figure 18 In this process, multiple functional circuits and multiple adjustment circuits are formed on a single die.

[0252] It should be noted that, in Figure 18 In this context, functional circuits and adjustment circuits are presented in multiple layers, such as... Figure 2 As illustrated, it is shown that multiple wiring and insulating film layers are formed sequentially during the manufacture of these circuits.

[0253] Figure 19 This diagram illustrates a bare die formed on a semiconductor substrate after multiple post-wiring processes.

[0254] exist Figure 19 In the example, two nude films are shown as components of different nude films.

[0255] As described above, the functional circuit design tool provides server 1000 to generate an optical mask pattern, which is used in the pattern transfer process of a first semiconductor manufacturing facility (e.g., a functional circuit forming wafer fab) to perform exposure processing on a semiconductor substrate on which semiconductor devices are respectively formed using a segmented projection exposure method. Here, as previously mentioned, at least one wiring layer on the upper side of the front wiring process can also be formed using direct drawing technology. Therefore, in other words, the optical mask pattern is generated relative to at least a portion of the pattern transfer process in the first semiconductor manufacturing facility. Drawing data for implementing the direct drawing method can also be generated relative to the remaining processes of the pattern transfer process in the first semiconductor manufacturing facility. On the other hand, the back wiring design tool provides server 2000 to generate drawing data, which is used in the pattern transfer process of a second semiconductor manufacturing facility (e.g., a back wiring wafer fab) to form wiring pattern drawing data for connecting circuit blocks on a semiconductor substrate.

[0256] like Figure 19 As shown, by using direct drawing, different wiring patterns are formed for bare dies with common patterns of functional circuit blocks and adjustment circuit blocks in multiple bare dies, which are then used in the subsequent wiring process.

[0257] More specifically, the different wiring patterns are wiring patterns that connect common functional circuit blocks and different adjustment circuit blocks in the first and second bare dies included in the bare die containing common patterns of functional circuit blocks and adjustment circuit blocks.

[0258] Figure 20 This diagram illustrates the design rules for the topmost layer of wiring within a wiring group during the preceding wiring process, as well as the design rules for the contact portion between the topmost layer wiring M1 and the wiring M2 formed in the subsequent wiring process.

[0259] like Figure 20 As shown in (a), the design rules for the top layer routing set the routing interval to S (nm) and the routing width to L (nm).

[0260] On the other hand, such as Figure 20 As shown in (b), in the design rules for the contact portion of the topmost routing in the pre-routing process and the routing formed in the post-routing process, the first design rule of the stock circuit block includes the superposition margin at the contact portion of the via for connecting the routing formed in the pre-routing process and the routing formed in the post-routing process based on the second design rule.

[0261] More specifically, although there are no particular limitations, for example in Figure 20In the structure shown, the expected relationship is either i) or ii).

[0262]

[0263] Here, DR BE DR FE These are the minimum design dimensions for the routing width of the front routing process and the back routing process, respectively. As a design benchmark, the minimum design dimension of the front routing process is smaller than that of the back routing process, and the positional alignment accuracy between masks (between processes) is also higher.

[0264] Therefore, although not specifically limited, for example, if the planar structure of the top layer routing formed in the pre-routing process has a rectangular portion for forming via hole contacts, it is desirable that one side of this rectangular portion be set to be at least 2.5 times the minimum width of the top layer routing design reference. Here, "2.5 times" refers to the typical value in the formula exemplified in ii), where DR... BE =2.0μm, DR FE =0.8μm, but not limited to this.

[0265] Figure 21 It is a conceptual diagram showing various variations of the pattern of the contact portion between the topmost layer of wiring in the preceding wiring process and the wiring formed in the subsequent wiring process.

[0266] like Figure 21 As shown, in order to connect with the first layer of wiring in the subsequent wiring process, the shape of the contact area formed by the top layer of wiring in the preceding wiring process can have various possibilities.

[0267] Therefore, the design assistance system and design assistance method according to Implementation Method 1 can shorten the product development cycle in multi-variety, small-batch production.

[0268] In addition, by having designers from multiple companies use design-aided systems as a design platform to share the information needed for design, it is easier to shorten the time required for design and prototyping.

[0269] Furthermore, this design platform enables transactions where companies supplying semi-finished wafers sell them to fabless companies responsible for the back-end wiring processes. As a result, the design platform itself will need to reduce its own inventory of semi-finished wafers. By adding a variety of semi-finished wafer suppliers, the timeline from prototype to mass production of semiconductor devices can be further shortened, and costs can be reduced.

[0270] [Implementation Method Two] In the first embodiment described above, a structure was described in which the "performance" of the functional circuit block is finely adjusted by an "adjustment circuit" for the "functional circuit" formed in the previous wiring process through the subsequent wiring pattern in the subsequent wiring process.

[0271] In the second implementation method, the structure of the functional circuit that can not only adjust the "performance" but also change the "function" and "characteristics" of the functional circuit through the subsequent wiring pattern will be explained.

[0272] Although this is just one example, regarding the so-called "operational amplifier" circuit, there exist analog circuits whose functions and characteristics can be altered by changing the characteristic values ​​(e.g., resistance value, capacitance value) of passive circuits connected externally (e.g., resistors, capacitors) and their connection to the input / output nodes. Examples include "gain amplifiers," "attenuation amplifiers," "buffer amplifiers," "comparators," "differentiating circuits," "integrating circuits," and "detector / absolute value circuits." More specifically, given the existence of a basic circuit like the "operational amplifier," functions and characteristics such as "amplification," "filtering," "signal conversion (e.g., converting current changes into voltage changes)," "signal processing (e.g., signal synthesis, differentiation, integration)," and "oscillation" can be achieved by changing the characteristic values ​​of the passive circuits connected to the input / output nodes and their connection methods.

[0273] In contrast, in Implementation Method 1, the "performance" that is the object of adjustment refers to the degree of functionality achieved under the same characteristics and functions. The "adjustment circuit" is used to fine-tune such performance to make it closer to the design value. For example, if it is "amplification", it means fine-tuning the "amplification rate", etc.

[0274] In contrast, in Embodiment 2, a structure is described that allows for changes to the "function implemented by the functional circuit" and the "characteristics of the functional circuit" through the post-wiring pattern in the post-wiring process. By adopting such a structure, the design freedom is increased when implementing specification changes based on the post-wiring pattern in the post-wiring process, by utilizing "semi-finished wafers" formed in the pre-wiring process and temporarily stored as inventory in the "wafer library".

[0275] Figure 22 This is a conceptual diagram that compares and illustrates the flexibility of design approaches for digital and analog circuits.

[0276] Figure 22 The horizontal axis represents flexibility. Here, "flexibility" refers to the degree to which the circuit function can be switched by changing the wiring pattern after the first design and trial production, based on the trial production results.

[0277] Whether it's digital or analog circuits, in fully custom ICs designed on a cell-based basis, if design changes occur after the initial design based on prototype results, it's essentially necessary to redesign from scratch.

[0278] On the other hand, as design principles that enable circuit functionality through rewiring using photomasks, there are "Gate Array", "Embedded Array", and "Analog Master Slice".

[0279] Gate array (GSA) technology in digital circuits refers to semi-custom LSIs manufactured by applying wiring corresponding to the design to a substrate with pre-fabricated logic cells (e.g., 2-input NAND gates). Circuit functions can be switched or modified by rewiring through photomasks without altering the logic cell portion.

[0280] On the other hand, the analog master wafer method refers to a method where a wafer with pre-formed transistors, resistors, capacitors, and other components is prepared in advance. In order to achieve the functions that meet the user's needs, the photomask used to form the wiring layer is changed to realize the user's own analog semi-custom IC / LSI.

[0281] Furthermore, in digital circuits and mixed digital and analog circuits, an "embedded array approach" is sometimes employed. The "embedded array approach" refers to a design and manufacturing method that combines the features of gate arrays and cell-based ICs. When the cell-based IP used by the user is determined, the silicon wafer is pre-loaded into the production line. Meanwhile, the user logic circuitry is fabricated using gate arrays. Once the user logic design is complete, the configuration and routing of the user logic section are implemented using a routing-only process.

[0282] Furthermore, the most flexible approach is the "FPGA (Field Programmable Gate Array) approach" or "design method of implementation one or two," which does not require rewiring using photomasks.

[0283] As the name suggests, "FPGA" is a design method for digital circuits that integrates a structure of logic circuits that can be programmed in the field. Through programming, the internal circuitry, or the processing capabilities of the device, can be rewritten.

[0284] In contrast, the "design method of implementation method one or two" is applicable not only to digital circuits, but also to analog circuits, and even to mixed circuits of digital and analog circuits.

[0285] As a result, based on the "Design Method of Embodiment One" described above or the "Design Method of Embodiment Two" described later, for example, it is possible to develop semiconductor integrated circuit chips with high flexibility and reduced development costs in analog / digital-analog hybrid ICs.

[0286] Figure 23 Taking an operational amplifier as an example, this diagram illustrates the relationship between the "function", "characteristics", and "characteristic values" implemented by the functional circuit.

[0287] As mentioned above, the functions (major categories) implemented by the operational amplifiers in basic circuits include, for example, "gain amplifiers", "attenuation amplifiers", "buffer amplifiers", and "comparators".

[0288] In addition, as a subcategory of "gain amplifier" and "attenuation amplifier" functions, there is also a category for whether the standby mode (Power down mode) is on or off.

[0289] Generally speaking, operational amplifiers are designed to operate within a certain range of supply voltage, especially in operational amplifiers with added standby functionality, which can be set to keep the supply current below a specified value. This standby function achieves low power consumption, for example, when powered by battery.

[0290] As a characteristic of gain amplifiers, voltage gain is designed with a substrate pattern (circuit pattern manufactured up to the previous wiring process) in a way that allows the value to be changed to, for example, 10dB, 20dB, etc. In attenuation amplifiers, voltage gain is also a characteristic, and the value is designed to be changed to, for example, -20dB.

[0291] Using the same operational amplifier circuit structure as the basic circuit, these functions can be variably set by connecting passive circuits (resistance values) with specified values ​​to the input and output nodes in a specified connection manner.

[0292] However, if it is like this Figure 22 The analog circuit described above, which involves rewiring using existing photomasks, requires separate circuit patterns, including wiring patterns, to be designed for each function.

[0293] In contrast, in the design method of Implementation Method Two, the structure of the operational amplifier circuit is formed as the basic circuit pattern in the front wiring process, and the connection with the passive circuit is changed in the rear wiring process. In this way, for all functions, the circuit pattern (substrate pattern) formed on the semiconductor substrate in the front wiring process can be a common pattern.

[0294] Figure 24This is a diagram showing three design conditions for a "gain amplifier".

[0295] like Figure 24 As shown, although the common function is gain amplifier, the presence or absence of standby is used as a function (sub-category), and the voltage gain changes of 10dB and 20dB are used as characteristic values. The design is based on the conditions set as in variants A, B, and C.

[0296] Figure 25 It demonstrates a fully customized design. Figure 24 The circuit diagrams show the circuit structures under the three conditions shown.

[0297] Variant A is a gain amplifier used in analog circuits, with no standby function and a voltage gain of 10dB.

[0298] In contrast, such as Figure 25 As shown, in the "non-inverting amplifier circuit" corresponding to variant A, when the resistance value R1 between the inverting input and ground is set to 10kΩ, the resistance value R2 of the feedback from the output to the inverting input is 20kΩ.

[0299] This is the gain G (dB) of a non-inverting amplifier circuit, which can be calculated inversely from the following formula when the input voltage is Vi and the output voltage is Vo.

[0300]

[0301] Similarly, in the "non-inverting amplifier circuit" corresponding to variant B, when the resistance value R1 between the inverting input and ground is set to 10kΩ, the resistance value R2 for feedback from the output to the inverting input is 90kΩ.

[0302] Furthermore, in the "non-inverting amplifier circuit" corresponding to variant C, a structure is formed that adds a standby function to the "non-inverting amplifier circuit" corresponding to variant B.

[0303] Figure 26 This illustrates the design method of implementation method two. Figure 24 The circuit diagrams show the circuit structures under the three conditional circuit scenarios.

[0304] First, in the pre-wiring process, the basic circuit 6000 and the characteristic adjustment circuit 6100 are formed.

[0305] In this example, the basic circuit 6000 is an analog circuit and an operational amplifier circuit with standby function.

[0306] That is, in Figure 26For example, as multiple functional circuit blocks formed in the pre-wiring process, as a basic circuit pattern of a variable function block whose independent functions and characteristics can be changed by the post-wiring pattern, an "operational amplifier circuit with standby function" is formed.

[0307] The characteristic adjustment circuit 6100 is a circuit pattern used to adjust the function and characteristics based on a basic circuit pattern.

[0308] The characteristic adjustment circuit 6000 includes a plurality of first passive circuit patterns 6110.i (e.g., resistor patterns, i: natural number). Each of these first passive circuit patterns is designed to have a first impedance value (e.g., 10kΩ). However, the impedance values ​​of the first passive circuit patterns within the characteristic adjustment circuit 6100 do not need to be all identical; they can be designed to have different values.

[0309] Regarding variant A, it is an amplifier with no standby function and a voltage gain of 10dB.

[0310] In contrast, such as Figure 26 As shown, in the "non-inverting amplifier circuit" corresponding to variant A, the post-wiring pattern in the characteristic adjustment circuit 6100 is designed such that the inverting input node is connected to the ground node via a first passive circuit pattern, so that the resistance value R1 between the inverting input node and the ground node is 10kΩ. Furthermore, the post-wiring pattern is designed such that the output node is connected to the inverting input node via two first passive circuit patterns, so that the feedback resistance value R2 from the output node to the inverting input node is 20kΩ. Additionally, to disable the standby function, the standby function node PD is connected to a "Low" level.

[0311] exist Figure 26 In the middle, the pattern of the back wiring is shown with dashed lines.

[0312] In the "non-inverting amplifier circuit" corresponding to variant B, the back wiring pattern in the characteristic adjustment circuit 6100 is designed such that the inverting input node is connected to the ground node via a first passive circuit pattern, so that the resistance value R1 between the inverting input node and the ground node is 10kΩ. Furthermore, the back wiring pattern is designed such that the output node is connected to the inverting input node via nine first passive circuit patterns, so that the feedback resistance value R2 from the output node to the inverting input node is 90kΩ. Additionally, to disable the standby function, the standby function node PD is connected to a "Low" level.

[0313] Furthermore, in the "non-inverting amplifier circuit" corresponding to variant C, and in the "non-inverting amplifier circuit" corresponding to variant B, in order to enable the standby function, the standby function node PD is connected to the "High" level.

[0314] That is, in the pre-wiring process, for example, N (N: a natural number) dies are formed on a semiconductor substrate. In the design of Embodiment 2, as described below, the basic circuit pattern 6000 and the characteristic adjustment circuit pattern 6100 are connected on the semiconductor substrate by a post-wiring pattern common to at least m (m≤N, m: a natural number) dies. In other words, for at least m dies on the semiconductor substrate, the design is carried out in a way that makes the functions and characteristics implemented by the basic circuit of the variable function block common. For the other dies among the N dies, the design can also be carried out in a way that makes the functions and characteristics implemented by the basic circuit different from those of the m dies. Alternatively, for all N dies, the post-wiring pattern can also be designed in a way that makes the functions and characteristics implemented by the basic circuit common.

[0315] For example, consider the prototype fabrication of a variant B circuit for m dies on a semiconductor substrate. In this case, to ensure that the functions and characteristics achieved through the basic circuit of the variable function block are common, a common post-wiring pattern for the m dies is included in the design to specify a number ( Figure 26 The first post-wiring pattern is a series of nine first passive circuit patterns interconnected.

[0316] Figure 27 This is a conceptual diagram showing the functional blocks and the adjustment circuit blocks used to adjust the performance of the functional blocks.

[0317] like Figure 27 As shown, the plurality of circuit blocks formed on the semiconductor substrate die include a plurality of adjustment circuit blocks 6200 and 6300 for fine-tuning the performance implemented by the functional circuit blocks, respectively. The plurality of adjustment circuit blocks 6200 and 6300 are separate from the plurality of functional circuit blocks and formed in the die on the semiconductor substrate on which these functional circuit blocks are formed. It should be noted that the number of adjustment circuit blocks is not limited to this example and may be greater. Furthermore, the number of passive circuit patterns formed within the adjustment circuit blocks and the impedance value of each passive circuit pattern are not limited to the examples described below.

[0318] exist Figure 27 In the middle, as a functional circuit block, with Figure 26The variable function block described herein is used as an example. The variable function block serves as the basic circuit pattern, forming an "operational amplifier circuit with standby function." Corresponding to variant C, in the characteristic adjustment circuit 6100, the post-wiring pattern is designed such that the inverting input node is connected to the ground node via a first passive circuit pattern, so that the resistance value R1 between the inverting input node and the ground node is 10kΩ. Furthermore, corresponding to the feedback resistance value R2 from the output node to the inverting input node, nine first passive circuit patterns are selected and designed to be connected via the adjustment circuit block using the post-wiring pattern. Additionally, to enable the standby function, the standby function node PD is connected to a "High" level.

[0319] The adjustment circuit block 6200 includes a plurality of second passive circuit patterns (e.g., resistor patterns). Each of the second passive circuit patterns is designed to have a second impedance value (e.g., 1kΩ) smaller than the first impedance value (e.g., 10kΩ).

[0320] The adjustment circuit block 6300 includes a plurality of third passive circuit patterns (e.g., resistor patterns). Each of the third passive circuit patterns is designed to have a third impedance value (e.g., 100Ω) smaller than the first impedance value (e.g., 10kΩ).

[0321] The back wiring pattern has a first back wiring pattern designed for nine first passive circuit patterns that are common to m bare dies as described above, and second back wiring patterns 6400.1 and 6400.2 that connect the second passive circuit pattern and the third passive circuit pattern to the first passive circuit pattern.

[0322] exist Figure 27 In the initial prototype, the back wiring pattern was designed to connect four first passive circuit patterns, three second passive circuit patterns, two third passive circuit patterns, and five first passive circuit patterns in series. Therefore, the feedback resistance value R2 from the output node to the inverting input node is shown below.

[0323] R2= 4×10(kΩ)+3×1(kΩ)+2×0.1(kΩ)+5×10(kΩ) =93.2(kΩ) It should be noted that in the first trial production, for m bare dies, the first passive circuit pattern selected in the characteristic adjustment circuit 6100 is common, and the second passive circuit pattern selected in the adjustment circuit block 6200 and the third passive circuit pattern selected in the adjustment circuit block 6300 can also be common. Alternatively, the second passive circuit pattern selected in the adjustment circuit block 6200 and the third passive circuit pattern selected in the adjustment circuit block 6300 can be different among the bare dies, depending on the purpose of the trial production.

[0324] After the first prototype, an electrical evaluation of the circuit characteristics is performed. Based on this, it is determined whether it is necessary to change the performance achieved by the functional blocks (e.g., the voltage amplification rate of the gain amplifier).

[0325] In this case, in order to change the performance achieved by the functional block (e.g., the voltage amplification of the amplifier), the first back wiring pattern set for the first passive circuit pattern selected in the characteristic adjustment circuit 6100 is the same as in the first prototype, while the back wiring pattern that connects the second passive circuit pattern selected in the adjustment circuit block 6200 and the third passive circuit pattern selected in the adjustment circuit block 6300 is changed in the design to become the second back wiring patterns 6400.3 and 6400.4.

[0326] like Figure 27 As shown, in the second prototype, the back wiring pattern was designed to connect four first passive circuit patterns, one second passive circuit pattern, eight third passive circuit patterns, and five first passive circuit patterns in series. Therefore, the feedback resistance value R2 from the output node to the inverting input node is shown below.

[0327] R2=4×10(kΩ)+1×1(kΩ)+8×0.1(kΩ)+5×10(kΩ) =91.8 (kΩ) In this way, by changing the design of the post-wiring pattern formed by the semiconductor substrate that has been stored after the pre-wiring process, the performance of the function achieved by the functional block can be adjusted each time a prototype is manufactured. At this time, for example, based on the adjusted value, at least one of the second passive circuit pattern of the adjustment circuit block 6200 and the third passive circuit pattern of the adjustment circuit block 6300 can also become a structure in which there is no connection pattern in the post-wiring pattern.

[0328] In addition, the design of the post-wiring pattern formed by changing the semiconductor substrate that was originally completed and stored by changing the pre-wiring process can also change the "function and characteristics" achieved by the functional block itself.

[0329] Figure 28 This is a conceptual diagram showing a comparison between the prototyping process using the design method of Implementation Method 2 and the conventional prototyping process.

[0330] Here, in the existing approach, a fully custom IC with wiring patterns formed by photomasks is illustrated.

[0331] In conventional prototyping, the circuit patterns formed on the bare dies on the semiconductor substrate are common. As a result, if the desired characteristic values ​​are not obtained in prototyping (1), in prototyping (2), it is necessary to form different circuit patterns for all the bare dies on the semiconductor substrate again to confirm the characteristic values. If the desired characteristic values ​​are not obtained in prototyping (2), prototyping (3) must be carried out.

[0332] Especially in the simulation of analog circuits, there are limitations. The simulation results often differ from the actual chip characteristics, so it is necessary to make prototypes multiple times.

[0333] That is, it is necessary to verify through trial and error until the optimal characteristic value is obtained.

[0334] In contrast, in the design of Implementation Method Two, the circuit pattern ("substrate pattern") manufactured and stored in the pre-wiring process is not modified. Based on this, for example, if n×m dies are formed in a semiconductor substrate, the post-wiring pattern in the wiring process can be modified, designed, and prototyped according to m dies in each row.

[0335] In this case, although there are no particular limitations, semiconductor substrates with substrate patterns formed on them and stored in a wafer library can be selected. For example, for each row of n×m bare wafers, the second passive circuit pattern selected in adjustment circuit block 6200 and the third passive circuit pattern selected in adjustment circuit block 6300 can be changed n times, and the manufacturing process can be performed. In this case, the same verification performed on the n prototypes can be performed as on the single prototype. Such verification is called "multi-variant simultaneous verification".

[0336] It should be noted that the first passive circuit pattern selected in the characteristic adjustment circuit 6100 can be common to all dies, or different structures can be used in the die rows.

[0337] In other words, in this implementation method, by performing a post-routing process using direct rerouting, multiple variants can be prototyped simultaneously, and device characteristics can be verified at the same time. Therefore, compared with the conventional method, the lead time for the redesign process used for adjustments can be significantly shortened.

[0338] Unlike digital processing that handles "0" or "1" signals, the analog circuits described above present a significant design challenge due to the need to process minute signal variations. The ability to perform such simultaneous verification of multiple variations significantly shortens the development time for analog circuits or hybrid analog / digital circuits.

[0339] Figure 29It is a conceptual diagram illustrating how design data can be used and reused within or between contract manufacturers.

[0340] For a long time, regarding the "functional circuits" used in the manufacture of product X in a foundry (wafer fab A), even within the same foundry, when manufacturing product Y with different required characteristics, the "functional circuits" need to be redesigned from scratch.

[0341] However, if the design method of Implementation Method 2 is used, most of the design data of the "functional circuit" used for manufacturing product X in wafer fab A can be directly reused in the design for manufacturing product Y in wafer fab A. Furthermore, most of the design data of the "functional circuit" used for manufacturing product X in wafer fab A can be directly reused in the design for manufacturing product Z in wafer fab B.

[0342] This also means that the construction period required for the design can be shortened.

[0343] Figure 30 This is a conceptual diagram illustrating the effect of a design approach based on an implementation method.

[0344] As in Figure 28 As explained in the description, in the design of the implementation method, by means of... Figure 29 The reuse of design IP shown can not only shorten the lead time (LT) of design by enabling "simultaneous verification of multiple variants", but also reduce development costs and significantly reduce the lead time required for development.

[0345] The embodiments described herein are examples of structures for specific implementation of the present invention and do not limit the technical scope of the present invention. The technical scope of the present invention is indicated by the scope of the claims rather than by the description of the embodiments, and is intended to include the scope of the words of the claims and modifications within the scope of their equivalents.

[0346] Explanation of reference numerals in the attached figures 1000 Functional Circuit Design Tool Server, 1002 Communication Interface, 1100 Processing Unit, 1200 Memory, 1110 Semiconductor Acquisition Module, 1120 Independent Function Setting Module, 1130 Adjustment Circuit Setting Module, 1140 IP Core Selection Module, 1150 Foundry Selection Module, 1160 Logic Circuit Design Module, 1170 Circuit Pattern Design Module, 1180 Mask Pattern Generation Module, 1500, 1600 Storage Device, 2000 Back-Wiring Design Tool Server, 2002 Communication Interface, 2100 Processing Unit, 2200 Memory, 2110 Semiconductor Acquisition Module, 2120 Independent Function Setting Module, 2130 Adjustment Circuit Setting Module, 2140 IP Core Selection Module, 2150 Foundry Selection Module, 2160 Logic Circuit Design Module, 2170 Circuit Pattern Design Module, 2180 Drawing data generation module, 2200, 2300, 2500 storage devices, 5000.1~5000.P, 5000.1~5000.Q designer terminals, 6000 basic circuits, 6100 characteristic adjustment circuits, WFFAB.1~WFFAB.N functional circuit forming foundry, WLFAB.1~WLFAB.M post-routing process foundry, WBANK wafer library, ASFAB.1~ASFAB.L assembly process foundry.

Claims

1. A design assistance system providing a tool to assist a circuit design of a semiconductor device manufactured in cooperation with a plurality of semiconductor manufacturing sites, wherein, The plurality of semiconductor manufacturing sites include: a plurality of first semiconductor manufacturing sites responsible for the front-end wiring process according to a first manufacturing process of a first design rule; and at least one second semiconductor manufacturing site responsible for the back-end wiring process according to a second manufacturing process of a second design rule different from the first design rule. The design assistance system includes a first design assistance device that assists in the design of circuit patterns formed on each of a plurality of dies on a semiconductor substrate through a pre-wiring process. The plurality of bare dies contain a plurality of circuit blocks. The plurality of circuit blocks include a plurality of functional circuit blocks, which are used to implement a plurality of independent functions constituting the overall function of the semiconductor device on the semiconductor substrate. The plurality of functional circuit blocks include a plurality of stock circuit blocks, which are pre-prepared with design information of circuit patterns corresponding to manufacturing processes of each of the first semiconductor manufacturing sites based on the first design rules. The first design assistance device includes a first design assistance unit, which selects a predetermined number of stock circuit blocks from the plurality of stock circuit blocks to implement the overall function, and assists in the design for configuring them on the semiconductor substrate. The design assistance system further includes a second design assistance device, which assists in the design of a post-wiring pattern in a post-wiring process for selectively connecting multiple circuit blocks formed in the pre-wiring process. The second design aid device includes a second design aid unit, which selects a second semiconductor manufacturing location based on the manufacturing process of the selected plurality of stock circuit blocks, and performs logic design and pattern design assistance for the subsequent wiring process according to the second design rule corresponding to the first design rule of the selected stock circuit blocks.

2. The design assistance system of claim 1, wherein, The plurality of circuit blocks further include a plurality of adjustment circuit blocks, which are separately disposed on the semiconductor substrate from the plurality of functional circuit blocks, and are used to fine-tune the performance achieved by the functional circuit blocks respectively.

3. The design assistance system of claim 1, wherein, The plurality of functional circuit blocks includes at least one custom circuit block, which is based on the first design rules of the selected first semiconductor manufacturing site and the design information of the circuit pattern designed by the user. The first design aid includes a storage device. The storage device stores, according to the manufacturing processes of the plurality of semiconductor manufacturing sites, a corresponding relationship established between the plurality of semiconductor manufacturing sites and the plurality of circuit design core groups containing the plurality of functional circuit blocks. The first design assistance unit performs the logic design and pattern design assistance of the custom circuit block by means of the first design rules corresponding to the first semiconductor manufacturing site selected according to the circuit design core group.

4. The design assistance system of claim 3, wherein, When the first design assistance unit determines that the multiple stock circuit blocks are insufficient to achieve the overall performance, it prompts the user to implement the design of the custom circuit block.

5. The design assistance system according to claim 3, wherein, The correspondence includes: A first correspondence between the functional circuit blocks that correspond to the plurality of independent functions constituting the overall function; as well as The second correspondence between the performance specifications of the independent functions of the functional circuit blocks and the multiple circuit design core groups used to implement the performance specifications. Each of the circuit design core groups contains design information for the stock circuit blocks, which specifies a pre-defined independent circuit pattern capable of achieving performance specifications for at least one of the independent functions.

6. The design assistance system according to claim 5, wherein, The first design assistance module includes: The core group selection unit selects the circuit design core group, which includes a combination of functional circuit blocks capable of implementing the overall function; and The design unit is used to determine the first semiconductor manufacturing site among the plurality of semiconductor manufacturing sites that corresponds to the selected circuit design core group, and to perform logic design and pattern design based on the first design rules of the determined first semiconductor manufacturing site.

7. The design assistance system according to claim 2, wherein, The first design aid includes a mask pattern generation unit for generating pattern data for an optical mask. This pattern data is used, in at least a portion of a pattern transfer process in the first semiconductor manufacturing facility, to perform an exposure process in a segmented projection exposure manner on which dies for which the semiconductor devices are formed are respectively formed on a semiconductor substrate. The second design aid includes a drawing data generation unit that generates drawing data for forming wiring patterns connecting the circuit blocks on the semiconductor substrate during a pattern transfer process in the second semiconductor manufacturing facility.

8. The design assistance system according to claim 7, wherein, The first design rule of the selected inventory circuit block includes the overlap margin at the contact portion of the vias used to connect the wiring formed in the pre-wiring process and the wiring formed in the post-wiring process based on the second design rule.

9. The design assistance system according to claim 7, wherein, The drawing data generated by the drawing data generation unit includes data on different wiring patterns for the functional circuit blocks and adjustment circuit blocks in the plurality of dies in the subsequent wiring process.

10. The design assistance system according to claim 9, wherein, The different wiring patterns are wiring patterns that connect the common functional circuit blocks and the different adjustment circuit blocks in the first and second bare dies included in the common pattern bare die.

11. The design assistance system according to claim 1, wherein, The plurality of functional circuit blocks include variable functional blocks that can change the characteristics of the individual functions through the post-wiring pattern. The variable function block has a basic circuit pattern for implementing the independent function, and a characteristic adjustment circuit pattern for adjusting the characteristics based on the basic circuit pattern. The second design aid unit assists in the design of connecting the basic circuit pattern and the characteristic adjustment circuit pattern through the common back wiring pattern of a predetermined number of the dies on the semiconductor substrate.

12. The design assistance system according to claim 11, wherein, The characteristic adjustment circuit pattern includes multiple first passive circuit patterns, each of which is designed to have a first impedance value. The common back wiring pattern of the die includes a first back wiring pattern that interconnects a specified number of the plurality of first passive circuit patterns during design.

13. The design assistance system according to claim 12, wherein, The plurality of circuit blocks further include a plurality of adjustment circuit blocks, which are separately disposed on the semiconductor substrate from the plurality of functional circuit blocks, and are used to fine-tune the performance achieved by the functional circuit blocks respectively.

14. The design assistance system according to claim 13, wherein, The plurality of adjustment circuit blocks include a plurality of second passive circuit patterns, each of which is designed to have a second impedance value that is smaller than the first impedance value. The post-wiring pattern has: the first post-wiring pattern common to the specified number of the bare dies; And a second post-wiring pattern, which is different among the specified number of dies, connecting the second passive circuit pattern to the first passive circuit pattern.

15. The design assistance system according to any one of claims 11 to 14, wherein, The basic circuit pattern is an analog circuit.

16. A design-aided method, which is a computer-based design-aided method, comprising a tool for assisting in the circuit design of a semiconductor device manufactured in collaboration with multiple semiconductor manufacturing sites, the multiple semiconductor manufacturing sites including: multiple first semiconductor manufacturing sites responsible for front-end wiring processes according to a first manufacturing process of a first design rule; and at least one second semiconductor manufacturing site responsible for back-end wiring processes according to a second manufacturing process of a second design rule different from the first design rule, wherein the computer includes a computing device and a storage device. The storage device stores design information for multiple circuit blocks, each including multiple functional circuit blocks. These functional circuit blocks are used to implement multiple independent functions constituting the overall function of the semiconductor device on the semiconductor substrate. The multiple functional circuit blocks also include multiple inventory circuit blocks, which are pre-prepared with design information for circuit patterns corresponding to manufacturing processes at each of the first semiconductor manufacturing sites, based on the first design rules. Design aids include: The computing device selects a predetermined number of stock circuit blocks from the plurality of stock circuit blocks to implement the overall function, assisting in the design of circuit patterns in the pre-wiring process for forming the plurality of circuit blocks on the semiconductor substrate. as well as A step that assists in designing the post-wiring pattern in the post-wiring process for selectively connecting multiple circuit blocks formed in the pre-wiring process. The steps for assisting in the design of the post-wiring pattern include selecting a second semiconductor manufacturing location based on the manufacturing process of the selected plurality of stock circuit blocks, and performing steps to assist in the logic design and pattern design for the post-wiring process using a second design rule corresponding to a first design rule of the selected stock circuit blocks.

17. A design aid device, in a design aid system that provides tools to assist in the design of circuits for semiconductor devices manufactured in collaboration with multiple semiconductor manufacturing sites, assists in the design of pre-wiring processes, wherein, The plurality of semiconductor manufacturing sites include: a plurality of first semiconductor manufacturing sites responsible for the front-end wiring process according to a first manufacturing process of a first design rule; and at least one second semiconductor manufacturing site responsible for the back-end wiring process according to a second manufacturing process of a second design rule different from the first design rule. The design assistance device includes a storage device for storing design information of multiple circuit blocks required for the design assistance. The plurality of circuit blocks include a plurality of functional circuit blocks, which are used to implement a plurality of independent functions constituting the overall function of the semiconductor device on the semiconductor substrate. The plurality of functional circuit blocks include a plurality of stock circuit blocks, which are pre-prepared with design information of circuit patterns corresponding to manufacturing processes of each of the first semiconductor manufacturing sites based on the first design rules. The design assistance device also includes a computing unit for performing design assistance processing based on information stored in the storage device. The computing device selects a predetermined number of stock circuit blocks from the plurality of stock circuit blocks to implement the overall function, assisting in the design of configuring the circuit pattern in the pre-wiring process onto the semiconductor substrate. In the design process of a subsequent routing process used to selectively connect multiple circuit blocks formed in the preceding routing process, the design information of the array of circuit patterns in the preceding routing process is stored in a designated shared storage area in order to share the design information.

18. The design assistance system according to claim 17, wherein, The design aid includes a mask pattern generation unit, which generates pattern data for an optical mask. This pattern data is used, in at least a portion of a pattern transfer process in the first semiconductor manufacturing facility, to perform an exposure process in a segmented projection exposure manner on which dies for which the semiconductor devices are formed are respectively formed on a semiconductor substrate. The pattern transfer process in the second semiconductor manufacturing facility is a process of directly drawing the wiring pattern of the circuit blocks connected to the semiconductor substrate.

19. The design assistance system according to claim 18, wherein, The first design rule of the selected inventory circuit block includes the overlap margin at the contact portion of the vias used to connect the wiring formed in the pre-wiring process and the wiring formed in the post-wiring process based on the second design rule.

20. A design aid device, in a design aid system that provides tools to assist in the design of circuits for semiconductor devices manufactured in collaboration with multiple semiconductor manufacturing sites, assists in the design of subsequent wiring processes corresponding to the design of preceding wiring processes, wherein, The plurality of semiconductor manufacturing sites include: a plurality of first semiconductor manufacturing sites responsible for the front-end wiring process according to a first manufacturing process of a first design rule; and at least one second semiconductor manufacturing site responsible for the back-end wiring process according to a second manufacturing process of a second design rule different from the first design rule. The design assistance device includes a storage device that stores inventory information of multiple semiconductor substrates completed and stored up to the point where multiple circuit blocks are formed for each of the multiple bare dies during the pre-wiring process. The plurality of circuit blocks include a plurality of functional circuit blocks, which are used to implement a plurality of independent functions constituting the overall function of the semiconductor device on the semiconductor substrate. The plurality of functional circuit blocks include a plurality of stock circuit blocks, which are pre-prepared with design information of circuit patterns corresponding to manufacturing processes of each of the first semiconductor manufacturing sites based on the first design rules. The plurality of semiconductor substrates in stock are selected from the plurality of stock circuit blocks to implement the overall function, and the circuit pattern from the previous wiring process is formed on the substrate of the semiconductor substrate. The design assistance device also includes a computing unit that performs design assistance processing based on information stored in the storage device. Based on the inventory information, the computing device selects the semiconductor substrate to perform the subsequent wiring process. The computing device assists in the design of the design process for the subsequent wiring pattern of the subsequent wiring process, which is used to selectively connect multiple circuit blocks formed in the preceding wiring process.

21. The design aid device according to claim 20, wherein, The design aid device includes a direct drawing pattern generation unit that generates direct drawing data in the pattern transfer process at the second semiconductor manufacturing site for performing direct drawing of wiring pattern transfer of dies on which the semiconductor devices are formed on a semiconductor substrate.

22. The design assistance device according to claim 20, wherein, The plurality of functional circuit blocks include variable functional blocks that can change the characteristics of the individual functions through the post-wiring pattern. The variable function block has a basic circuit pattern for implementing the independent function, and a characteristic adjustment circuit pattern for adjusting the characteristics based on the basic circuit pattern. The design assistance unit assists in the design of connecting the basic circuit pattern and the characteristic adjustment circuit pattern through a predetermined number of common back wiring patterns of the dies on the semiconductor substrate.

23. The design assistance device according to claim 22, wherein, The characteristic adjustment circuit pattern includes multiple first passive circuit patterns, each of which is designed to have a first impedance value. The common back wiring pattern of the die includes a first back wiring pattern that interconnects a specified number of the plurality of first passive circuit patterns during design.

24. The design aid device according to claim 23, wherein, The plurality of circuit blocks further include a plurality of adjustment circuit blocks, which are separately disposed on the semiconductor substrate from the plurality of functional circuit blocks, and are used to fine-tune the performance achieved by the functional circuit blocks respectively.

25. The design aid device according to claim 24, wherein, The plurality of adjustment circuit blocks include a plurality of second passive circuit patterns, each of which is designed to have a second impedance value that is smaller than the first impedance value. The post-wiring pattern has: the first post-wiring pattern common to the specified number of the bare dies; And a second post-wiring pattern, which is different among the specified number of dies, connecting the second passive circuit pattern to the first passive circuit pattern.

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