Single display using heterogeneous physical interface

Abstract

Video frames can be split into a first data stream and a second data stream by the host processor and provided through video ports or interfaces having a first display protocol and a second display protocol, respectively. The ratio of pixels represented by the first data stream to pixels represented by the second data stream corresponds to the ratio of the bandwidth of a first data link having the first display protocol to the bandwidth of a second data link having the second display protocol. The first and second data streams can be provided to a first display controller and a second display controller, respectively, via the first and second data links, which also have the first and second display protocols. Through the first and second display controllers, the first and second data streams can be combined across a single display screen to reproduce the original video.

Description

Background Technology

[0001] Computing devices commonly include a screen or display on which the results of processing operations (such as text, graphics, images, etc.) are displayed as an aspect of the user interface. The processing system may have a display port configured to output a data stream according to a display protocol. Examples of display protocols include High Definition Multimedia Interface (HDMI), DisplayPort (DP), Display Serial Interface (DSI), etc. A display module may include a display panel and one or more display controllers, also known as display driver integrated circuits (DDICs). The DDIC drives the individual transistors or other display elements corresponding to the individual pixels of the display panel. Data cables connect the processing system's display port to the DDIC. The DDIC associated with the display module is typically configured according to the same display protocol configured for the processing system's display port.

[0002] The processing system can have multiple display ports, such as two display ports (i.e., dual display ports). The display ports of the processing system can be configured according to the same display protocol. Either of the two display ports can be connected to the display module via a DDIC of the display module. Alternatively, the two display ports of the processing system can be connected to the display module by connecting each of the display ports to a corresponding DDIC of the display module with dual DDICs. In a dual DDIC display module, either DDIC can drive the entire display panel, i.e., activate any pixel. In split-screen technology, the processing system can transmit the first portion of a frame to one DDIC and the second portion of the frame to the other DDIC. In this way, a single high-resolution (i.e., more pixels) display panel can be used instead of two lower-resolution display panels. Summary of the Invention

[0003] Systems, methods, and other examples of displaying video using a combination of two or more different (i.e. heterogeneous) display protocols are disclosed.

[0004] An exemplary method for displaying video may include splitting each frame of a video data frame stream into a first data stream and a second data stream along a horizontal display axis by a host processor. The ratio of pixels represented by the first data stream to pixels represented by the second data stream may correspond to the ratio of the bandwidth of a first data link configured using a first display protocol to the bandwidth of a second data link configured using a second display protocol. The method may further include providing the first data stream to a first display controller via the first data link, the first display controller being configured using the first display protocol and associated with a display panel. The method may further include providing the second data stream to a second display controller via the second data link, the second display controller being configured using the second display protocol and associated with a display panel.

[0005] An exemplary system for displaying video may include a host processor, a first display controller associated with a display panel, and a second display controller associated with the display panel. The first display controller can be configured using a first display protocol. The second display controller can be configured using a second display protocol. The host processor may be configured to split each frame in a video data frame stream into a first data stream and a second data stream along a horizontal display axis. The ratio of pixels represented by the first data stream to pixels represented by the second data stream may correspond to the ratio of the bandwidth of a first data link configured using the first display protocol to the bandwidth of a second data link configured using the second display protocol. The first display controller may be configured to receive the first data stream via the first data link. The second display controller may be configured to receive the second data stream via the second data link.

[0006] Another exemplary system for displaying video may include components for splitting each frame in a video data frame stream into a first data stream and a second data stream along a horizontal display axis. The ratio of pixels represented by the first data stream to pixels represented by the second data stream may correspond to the ratio of the bandwidth of a first data link configured using a first display protocol to the bandwidth of a second data link configured using a second display protocol. The system may further include components for providing the first data stream via the first data link to a first display controller associated with a display panel. The system may also further include components for providing the second data stream via the second data link to a second display controller associated with the display panel. Attached Figure Description

[0007] In the accompanying drawings, unless otherwise indicated, similar reference numerals are used throughout the various views to refer to similar parts. For reference numerals with letter character names (such as "101A" or "101B"), the letter character names distinguish two similar parts or elements in the same drawing. When the aim is to have reference numerals cover all parts with the same reference numerals in all drawings, the letter character names of the reference numerals may be omitted.

[0008] Figure 1 This is a block diagram of a system for displaying video according to an exemplary embodiment.

[0009] Figure 2 and Figure 1 Similarly, data link features according to an exemplary implementation are shown.

[0010] Figure 3 This is a flowchart illustrating a method for displaying video according to an exemplary embodiment.

[0011] Figure 4AThis is a timing diagram showing a synchronization signal and a feedback signal representing the deviation between the synchronization signals according to an exemplary embodiment.

[0012] Figure 4B This illustrates a method according to an exemplary embodiment. Figure 4A The timing diagram adjusts the synchronization signal to reduce deviation.

[0013] Figure 5 and Figure 3 Similarly, deviation adjustment features according to an exemplary implementation are additionally shown.

[0014] Figure 6 This is a block diagram of a computing device having a system for displaying video according to an exemplary embodiment. Detailed Implementation

[0015] The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” The word “illustrative” may be used synonymously with “exemplary” herein. Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or superior to other aspects.

[0016] like Figure 1 As shown, in an exemplary or illustrative embodiment, computing system 102 may include a system-on-a-chip (SoC) 104 and a display module 106. The term "computing system" may include, for example, a desktop or laptop computer, a data center system, a tablet computer, an automotive system, an Internet of Things (IoT) device, etc. Display module 106 may include a screen or display panel 108. Display panel 108 may be based on any display technology, such as, for example, a liquid crystal display (LCD), an organic light-emitting diode (OLED), variations or derivatives thereof, such as active-matrix organic light-emitting diode (AMOLED), in-plane switching (IPS) LCD technology, or other display technologies. It can be noted that various display technologies provide a matrix or array of elements that can be activated in response to electrical signals to illuminate or otherwise present the individual pixels constituting an image. Video images may include a frame stream, with each frame including an array of pixels. The demand for larger displays (i.e., more pixels) is increasing. For example, an automotive system may include a wide screen extending across the width of a car's dashboard to display status information about the vehicle (e.g., speed), video images captured by cameras, or other information.

[0017] SoC 104 may include processor 110, such as a central processing unit (CPU) or a graphics processing unit (GPU), which may be one of any number of processors (other processors are not shown for clarity). Although not shown for clarity, computing system 102 or SoC 104 may include other computing device components, such as a memory subsystem, a communication subsystem, interfaces, buses, etc. Processor 110 may also be referred to as a host processor and display module 106 may be referred to as a peripheral device used by the host processor to display video. For example, the host CPU may output video as part of executing an application.

[0018] SoC 104 may include a first display interface 112 configured according to a first display protocol and a second display interface 114 configured according to a second display protocol. The first display interface 112 and the second display interface 114 may be coupled to processor 110. For example, the first display interface 112 and the second display interface 114 may be coupled to processor 110 via one or more data buses or other data interconnects.

[0019] The first display interface 112 and the second display interface 114 may include circuitry configured to send signals according to a corresponding display protocol. The first display interface 112 and the second display interface 114 may include circuitry and physical ports (not shown separately). Although the illustrated computing system 102 has two display interfaces 112 and 114 configured according to two different display protocols, other examples (not shown) may have more than two display interfaces and these display interfaces may be configured according to more than two different display protocols.

[0020] Display module 106 may include a first display controller 116 configured according to the first display protocol mentioned above, and a second display controller 118 configured according to the second display protocol mentioned above. The first display controller 116 and the second display controller 118 may be coupled to display panel 108.

[0021] The first data link 120 may include a first display interface 112 and a first display controller 116. The second data link 122 may similarly include a second display interface 114 and a second display controller 118. The first data link 120 and the second data link 122 may also include cables or other physical signal transmission media through which data is transmitted from one end of the data link to the other. Based on the corresponding display protocols of the first and second data links, the first data link 120 and the second data link 122 may have corresponding first and second bandwidths that are different from each other. That is, one of the first data link 120 and the second data link 122 may be able to transmit video data faster than the other (e.g., more bits per second).

[0022] The components described above can be configured to display video on display panel 108 in the following manner. Processor 110 can be configured to process data in the form of a video frame stream. Processor 110 can be configured to split each frame in the stream into two parts along the horizontal display axis 124. That is, the video frame can be split into two parts line by line (the rows of the frame are parallel to axis 124) and processor 110 can be configured to provide a first data stream representing the left portion of the video image and a second data stream representing the right portion of the video image. An example is described below following this description of computing system 102. Note that... Figure 1 The horizontal display axis 124 shown is for reference only and is not a feature of the display panel 108 or the computing system 102. A vertical display axis perpendicular to the horizontal display axis is not shown.

[0023] Processor 110 can split each horizontal line of the video (and thus each frame) based on the ratio of the bandwidth of the first data link 120 to the bandwidth of the second data link 122. That is, each horizontal line can be split into several (N) pixels such that the ratio of the number of pixels represented by the first data stream to the number of pixels represented by the second data stream corresponds to the ratio of the bandwidth of the first data link 120 to the bandwidth of the second data link 122. Processor 110 can be configured to provide a first data stream to a first display controller 116 via the first data link 120 and a second data stream to a second display controller 118 via the second data link 122.

[0024] It should be understood that each of the first display interface 112 and the second display interface 114 may have a maximum resolution determined by the first display protocol and the second display protocol, respectively. The maximum resolution of each of the first display interface 112 and the second display interface 114 is less than the maximum resolution of the display panel 108. It should be understood that the maximum or full resolution of the display panel 108 cannot be utilized if the processor 110 attempts to provide a full (raw or unsplit) frame via either the first display interface 112 or the second display interface 114 itself without using the solution described herein. That is, the solution described herein can advantageously achieve maximum or full resolution utilization of the display panel 108 even if each of the first display protocol and the second display protocol only supports a lower maximum resolution.

[0025] like Figure 2 As shown, in an exemplary or illustrative embodiment, computing system 202 may include SoC 204 and display module 206. Computing system 202 may be computing system 102 described above. Figure 1Examples of SoC 204 and display module 206 are provided below. SoC 204 and display module 206 may be examples of SoC 104 and display module 106 described above. Display module 206 may include a screen or display panel 208. Display panel 208 may have a resolution of, for example, 3456 pixels (horizontal) multiplied by 2160 pixels (vertical). Computing system 202 may be, for example, an automotive system in which display panel 208 is included in a vehicle dashboard. Display panel 208 may be used to display, for example, video images to be viewed by a vehicle operator and may include vehicle status information, images captured by a camera (not shown), etc. It should be understood that the resolution or display size (such as 3456 x 2160) described herein are merely examples, and in other exemplary embodiments, such resolution, frame size, bandwidth, etc., may have other values.

[0026] SoC 204 may include processor 210, such as a CPU. Although not shown for clarity, computing system 202 or SoC 204 may include other computing device components, such as memory subsystems, communication subsystems, interfaces, buses, etc. In addition to processing video images, SoC 204 and processor 210 can provide processing for various vehicle functions.

[0027] SoC 104 may include a Display Serial Interface (DSI) protocol interface 212 and a Display Port (DP) protocol interface 214. DSI interface 212 and DP interface 214 may include circuitry configured to transmit signals according to the DSI display protocol and the DP display protocol, respectively. DSI interface 212 and DP interface 214 may also be referred to as ports or display ports. DSI interface 212 and DP interface 214 may be coupled to processor 110.

[0028] Display module 206 may include DSI display driver integrated circuit (DDIC) 216 and DP DDIC 218. DSI DDIC 216 and DSP DDIC 218 may include circuitry configured to receive signals according to the DSI display protocol and DP display protocol, respectively. DSI DDIC 216 and DP DDIC 218 may be coupled to display panel 208. For example, DSI DDIC 216 and DP DDIC 218 may be mounted to a portion of display panel 208 and electrically coupled to circuitry of display panel 208 that activates transistors or other components of display panel 208 that present video images.

[0029] DSI data link 220 may include a serializer 224 configured to convert data from a parallel format to a serial format, and a deserializer 226 configured to convert data from a serial format back to a parallel format. Cable 228 may couple the output of serializer 224 to the input of deserializer 226. The input of serializer 224 may be coupled to a physical port of DSI interface 212. The output of deserializer 226 may be coupled to the input of DSI DDIC 216. This configuration provides fast video data transfer in a space-saving manner, where SoC 204 and display module 206 are located at a distance (e.g., a few meters) from each other, a distance that may be traversed by cable 228. For example, in a vehicle, display module 206 may be located on the vehicle's dashboard, while SoC 204 may be located more centrally within the vehicle along with other electronic components.

[0030] Similarly, the DP data link 222 may include a serializer 230 and a deserializer 232, with the output of the serializer 230 coupled to the input of the deserializer 232 via a cable 234. The input of the serializer 230 may be coupled to a physical port of the DP interface 214. The output of the deserializer 232 may be coupled to the input of the DP DDIC 218.

[0031] Processor 210 can be configured to split each frame in the video stream into two parts along the horizontal display axis 236. That is, processor 210 can provide a first data stream representing the left portion 238 of the video image to DSI interface 212 and a second data stream representing the right portion 240 of the video image to DP interface 214. In an alternative example, processor 210 can provide a first data stream representing the left portion 238 of the video image to DP interface 214 and a second data stream representing the right portion 240 of the video image to DSI interface 212. DSI DDIC 216 and DP DDIC 218 can be configured to determine which of them presents the left portion 238 and which of them presents the right portion 240.

[0032] For example, each frame can have a size of 3456 pixels by 2160 pixels (or alternatively labeled "3456 x 2160" or "3456"). 2160”). That is, each frame can contain 3456 pixels horizontally (i.e., parallel to the horizontal display axis 236) and 2160 pixels vertically. Note that each frame contains 3456 pixels. 2160 = 7,464,960 pixels (where the asterisk symbol " ") (Instructions for multiplication). Processor 210 can divide 7,464,960 pixels into a first data stream and a second data stream based on the ratio of DSI data link bandwidth to DP data link bandwidth. For example, the DSI data link bandwidth can be measured as approximately 600,000,000 bytes per second and the DP data link bandwidth can be measured as approximately 900,000,000 bytes per second. The frame rate can be, for example, 60 frames per second. Each pixel can be represented by, for example, 3 bytes. Therefore, the video produced by processor 210 can have the following data rate: 7,464,960 pixels per second. 60 3 = 1,343,692,800 bytes. Accordingly, in this example, processor 210 can split each horizontal row based on a ratio of 600,000,000 bytes per second DSI link bandwidth to 900,000,000 bytes per second DP bandwidth: providing 1426 pixels to the first (i.e., DSI) data stream and 2030 pixels to the second (i.e., DP) data stream. That is, when processor 210 processes video data frame streams, processor 210 can provide 1426 bytes per second to DSI interface 212. 2160 60 3 bytes, and provides 2030 per second to DP interface 214. 2160 60 Three bytes. A higher bandwidth display protocol (DP in this example) can be used to provide the wider portion of the displayed image (the right portion 240 in this example). A lower bandwidth display protocol (DSI in this example) can be used to provide the narrower portion of the displayed image (the left portion 238 in this example). In other words, using the DSI interface 212 and the DP interface 214, the DSI protocol data stream and the DP protocol data stream can be combined across the display panel 208 (i.e., horizontally) to reproduce the original video.

[0033] exist Figure 3 The diagram illustrates a method 300 for displaying video. As indicated by box 302, a frame can be split into a first data stream and a second data stream based on the bandwidth ratio of a first data link to a second data link. The first and second data links can conform to a first display protocol and a second display protocol, respectively. As indicated by box 304, the first and second data streams can be provided to a first display controller and a second display controller associated with a display panel, respectively. It is understood that since the video is processed and provided in a streaming manner, the operations indicated by boxes 302 and 304 can be performed simultaneously, i.e., in a pipelined manner.

[0034] exist Figure 4AThe diagram illustrates an example of DSI horizontal synchronization (Hsync) signal 402 and DP Hsync signal 404. DSI Hsync signal 402 can be included in a DSI DDIC 216 ( Figure 2 The DP Hsync signal 404 can be included in the DSI data stream received by the DP DDIC 218 ( Figure 2 The received DP data stream. Although not shown for clarity, the DSI vertical synchronization (Vsync) signal and the DSP Vsync signal may also be included in the DSI data stream and the DP data stream, respectively.

[0035] Brief reference again Figure 2 The display module 206 can provide the feedback signal 242 to the SoC 204 and thus to the processor 210. (Back to...) Figure 4A Feedback signal 242 can indicate a timing difference or deviation between the DSI Hsync signal 402 and the DP Hsync signal 404. In other examples (not shown), such a feedback signal can indicate the timing difference or deviation between the DSI Vsync signal and the DP Vsync signal. In such other examples, as a supplement to or alternative to the feedback signal 242 described above for indicating deviation between Hsync signals, a feedback signal indicating deviation between Vsync signals can be provided. Such a feedback signal can be provided to indicate deviation between any type of video synchronization signals received by the display module.

[0036] Processor 210 ( Figure 2 The processor 210 can adjust one or more synchronization signals in response to feedback signal 242. For example, the processor 210 can control one or both of the DSI interface 212 and DP interface 214 based on feedback signal 242, causing the DSI interface 212 and DP interface 214 to adjust one or more synchronization signals. Figure 4B In the example shown, processor 210 has adjusted one or both of the DSIHsync signal 402 and the DP Hsync signal 404 to reduce the deviation between them to zero. That is, in Figure 4B The DSI Hsync signal 402 and the DP Hsync signal 404 are synchronized with each other.

[0037] exist Figure 5The diagram illustrates a method 500 for displaying video. As indicated in box 502, a frame may be split into a first data stream and a second data stream based on the bandwidth ratio of a first data link to a second data link. The first and second data links may conform to a first display protocol and a second display protocol, respectively. As indicated in box 504, the first and second data streams may be provided to a first display controller and a second display controller associated with a display panel, respectively. As indicated in box 506, one or more synchronization signals (e.g., Vsync, Hsync, etc.) in the data streams may be adjusted based on a feedback signal representing the deviation between such signals received at the display controller.

[0038] Figure 6 An example of a portable computing device (PCD) 600 is provided, which can provide exemplary implementations of systems, methods, and other examples for displaying video. The PCD 600 can be, for example, a laptop or tablet computer, or a smartphone, automotive computing system, IoT device, etc. For clarity, some data buses, interconnects, signals, etc., are not shown. Figure 6 As shown in the image.

[0039] PCD 600 may include SoC 602. SoC 602 may include various processors or processing subsystems, such as CPU 604, GPU 606, digital signal processor (DSP) 607, analog signal processor 608, and modem / modem subsystem 654. CPU 604 may include one or more CPU cores, such as first CPU core 604A, second CPU core 604B, and so on up to Nth CPU core 604N.

[0040] SoC 602 may include a first display interface 610 and a second display interface 616 coupled to CPU 604. For example, the first display interface 610 may be a DSI interface and the second display interface 616 may be a DP interface. A touchscreen display 614 external to SoC 602 may be coupled to a first DDIC 620 and a second DDIC 618 in a display module (not shown). SoC 602 may also include a touchscreen controller 612 coupled to CPU 604. The first (e.g., DSI) display interface 610 may be coupled to the first (e.g., DSI) DDIC 620 and the second (e.g., DP) display interface 616 may be coupled to the second (e.g., DP) DDIC 618. CPU 604 may be configured by software as described above to split video frames into a first data stream and a second data stream, and provide the first data stream and the second data stream to the first display interface 610 and the second display interface 616.

[0041] The Universal Serial Bus (USB) controller 622 can also be coupled to the CPU 604. The USB controller 622 can also be coupled to the USB port 624. The Subscriber Identity Module (SIM) card 626 can also be coupled to the CPU 604.

[0042] CPU 604 may be coupled to one or more memories, and CPU 604 may initiate memory transactions with one or more memories. The one or more memories may include volatile memory, non-volatile memory, or both NVM. Examples of volatile memory include static random access memory (RAM) 628 and dynamic random access memory (DRAM) 630 and 631. Such memories may be internal to SoC 602 (as in the case of DRAM 630) or external to SoC (as in the case of DRAM 631). DRAM controller 632, coupled to CPU 604, may control the writing of data to and from DRAM 630 and 631.

[0043] A stereo audio codec 634 can be coupled to an analog signal processor 608. Additionally, an audio amplifier 636 can be coupled to the stereo audio codec 634. A first stereo speaker 638 and a second stereo speaker 640 can be coupled to the audio amplifier 636, respectively. Furthermore, a microphone amplifier 642 can be coupled to the stereo audio codec 634, and a microphone 644 can be coupled to the microphone amplifier 642. An FM radio tuner 646 can be coupled to the stereo audio codec 634. An FM antenna 648 can be coupled to the FM radio tuner 646. Additionally, stereo headphones 650 can be coupled to the stereo audio codec 634. Other devices that can be coupled to the CPU 604 include one or more digital (e.g., CCD or CMOS) cameras 652.

[0044] An RF transceiver or modem subsystem 654 may be coupled to an analog signal processor 608 and a CPU 604. An RF switch 656 may be coupled to a modem subsystem 654 and an RF antenna 658. Additionally, a keypad 660, a mono headset 662 with a microphone, and a vibrator device 664 may be coupled to the analog signal processor 608. Furthermore, the SoC 602 may have one or more internal or on-chip thermal sensors 670A and may be coupled to one or more external or off-chip thermal sensors 670B. An analog-to-digital converter controller 672 may convert the voltage drop generated by the thermal sensors 670A and 670B into a digital signal. A power supply 674 and a power management integrated circuit (PMIC) 676 may supply power to the SoC 602.

[0045] Specific implementation examples are described in the following numbered clauses.

[0046] 1. A method for displaying video, the method comprising:

[0047] The host processor splits each frame in the video data frame stream along the horizontal display axis into a first data stream and a second data stream. The pixel ratio of the pixels represented by the first data stream to the pixels represented by the second data stream corresponds to the ratio of the first bandwidth of the first data link configured using a first display protocol to the second bandwidth of the second data link configured using a second display protocol; and

[0048] The host processor provides the first data stream to a first display controller associated with the display panel via the first data link and provides the second data stream to a second display controller associated with the display panel via the second data link.

[0049] 2. The method according to Clause 1, wherein providing the first data stream includes providing the first data stream through a first display port of the system-on-chip (SoC), and providing the second data stream includes providing the second data stream through a second display port of the SoC.

[0050] 3. The method according to Clause 1 or 2, wherein the first data link includes a first serializer and a first deserializer, and the second data link includes a second serializer and a second deserializer.

[0051] 4. The method according to any one of Clauses 1 to 3, wherein providing the first data stream to the first display controller includes providing the first data stream to a first display driver integrated circuit (DDIC), and providing the second data stream to the second display controller includes providing the second data stream to a second DDIC.

[0052] 5. The method according to any one of Clauses 1 to 4, wherein the first display protocol and the second display protocol are selected from the group consisting of: High Definition Multimedia Interface (HDMI), DisplayPort (DP), and Display Serial Interface (DSI).

[0053] 6. The method according to any one of Clauses 1 to 5, the method further comprising adjusting the deviation between a first synchronization signal of the first data stream and a second synchronization signal of the second data stream by the host processor.

[0054] 7. The method according to Clause 6, the method further comprising providing a feedback signal indicating the deviation to the host processor, and wherein adjusting the deviation includes adjusting the deviation based on the feedback signal.

[0055] 8. A system for displaying video, the system comprising:

[0056] A host processor configured to split each frame in a video data frame stream into a first data stream and a second data stream along a horizontal display axis, wherein the pixel ratio of the pixels represented by the first data stream to the pixels represented by the second data stream corresponds to the ratio of a first bandwidth of a first data link configured using a first display protocol to a second bandwidth of a second data link configured using a second display protocol.

[0057] A first display controller associated with the display panel, the first display controller being configured to receive the first data stream via the first data link; and

[0058] A second display controller associated with the display panel, the second display controller being configured to receive the second data stream via the second data link.

[0059] 9. The system according to Clause 8, wherein the host processor is configured to provide the first data stream via a first display port of the system-on-chip (SoC) and to provide the second data stream via a second display port of the SoC.

[0060] 10. The system according to Clause 8 or 9, further comprising a first serializer and a first deserializer in the first data link, and a second serializer and a second deserializer in the second data link.

[0061] 11. The system according to any one of Clauses 8 to 10, wherein the host processor is configured to provide the first data stream to a first display driver integrated circuit (DDIC) and to provide the second data stream to a second DDIC.

[0062] 12. The system of any one of Clauses 8 to 11, wherein the first display protocol and the second display protocol are selected from the group consisting of: High Definition Multimedia Interface (HDMI), DisplayPort (DP), and Display Serial Interface (DSI).

[0063] 13. The system according to any one of Clauses 8 to 12, wherein the host processor is configured to adjust the deviation between a first synchronization signal of the first data stream and a second synchronization signal of the second data stream.

[0064] 14. The system according to Clause 13, wherein the host processor is configured to adjust the deviation based on a feedback signal.

[0065] 15. A system for displaying video, the system comprising:

[0066] A component for splitting each frame in a video data frame stream into a first data stream and a second data stream along a horizontal display axis, wherein the pixel ratio of the pixels represented by the first data stream to the pixels represented by the second data stream corresponds to the ratio of the first bandwidth of a first data link configured using a first display protocol to the second bandwidth of a second data link configured using a second display protocol.

[0067] Components for providing the first data stream to a first display controller associated with the display panel via the first data link; and

[0068] A component for providing the second data stream to a second display controller associated with the display panel via the second data link.

[0069] 16. The system according to Clause 15, wherein:

[0070] The components for providing the first data stream include components for providing the first data stream through a first display port of the system-on-chip (SoC); and

[0071] The component for providing the second data stream includes a component for providing the second data stream through a second display port of the SoC.

[0072] 17. The system according to Clause 15 or 16, wherein the first data link includes a first serializer and a first deserializer, and the second data link includes a second serializer and a second deserializer.

[0073] 18. The system according to any one of clauses 15 to 17, wherein:

[0074] The components for providing the first data stream to the first display controller include components for providing the first data stream to the first display driver integrated circuit (DDIC); and

[0075] The component for providing the second data stream to the second display controller includes a component for providing the second data stream to the second DDIC.

[0076] 19. The system of any one of Clauses 15 to 18, wherein the first display protocol and the second display protocol are selected from the group consisting of High Definition Multimedia Interface (HDMI), DisplayPort (DP), and Display Serial Interface (DSI).

[0077] 20. The system according to any one of Clauses 15 to 19, the system further comprising a component for adjusting the deviation between a first synchronization signal of the first data stream and a second synchronization signal of the second data stream.

[0078] Alternative embodiments will become apparent to those skilled in the art to which this invention pertains. Therefore, although alternative aspects have been illustrated and described in detail, it should be understood that various substitutions and changes may be made therein.

Claims

1. A method for displaying video, the method comprising: The host processor splits each frame in the video data frame stream into a first data stream and a second data stream along the horizontal display axis. The pixel ratio of the pixels represented by the first data stream to the pixels represented by the second data stream corresponds to the ratio of the first bandwidth of the first data link configured using a first display protocol to the second bandwidth of the second data link configured using a second display protocol. as well as The host processor provides the first data stream to a first display controller associated with the display panel via the first data link and provides the second data stream to a second display controller associated with the display panel via the second data link.

2. The method of claim 1, wherein providing the first data stream comprises providing the first data stream through a first display port of the system-on-chip (SoC), and providing the second data stream comprises providing the second data stream through a second display port of the SoC.

3. The method according to claim 1, wherein the first data link includes a first serializer and a first deserializer, and the second data link includes a second serializer and a second deserializer.

4. The method of claim 1, wherein providing the first data stream to the first display controller includes providing the first data stream to a first display driver integrated circuit (DDIC), and providing the second data stream to the second display controller includes providing the second data stream to a second DDIC.

5. The method of claim 1, wherein the first display protocol and the second display protocol are selected from the group consisting of: High Definition Multimedia Interface (HDMI), DisplayPort (DP), and Display Serial Interface (DSI).

6. The method of claim 1, further comprising adjusting the deviation between a first synchronization signal of the first data stream and a second synchronization signal of the second data stream by the host processor.

7. The method of claim 6, further comprising providing a feedback signal indicating the deviation to the host processor, and wherein adjusting the deviation includes adjusting the deviation based on the feedback signal.

8. A system for displaying video, the system comprising: A host processor configured to split each frame in a video data frame stream into a first data stream and a second data stream along a horizontal display axis, wherein the pixel ratio of the pixels represented by the first data stream to the pixels represented by the second data stream corresponds to the ratio of a first bandwidth of a first data link configured using a first display protocol to a second bandwidth of a second data link configured using a second display protocol. A first display controller associated with the display panel, the first display controller being configured to receive the first data stream via the first data link; and A second display controller associated with the display panel, the second display controller being configured to receive the second data stream via the second data link.

9. The system of claim 8, wherein the host processor is configured to provide the first data stream via a first display port of the system-on-chip (SoC) and to provide the second data stream via a second display port of the SoC.

10. The system according to claim 8, further comprising a first serializer and a first deserializer in the first data link, and a second serializer and a second deserializer in the second data link.

11. The system of claim 8, wherein the host processor is configured to provide the first data stream to a first display driver integrated circuit (DDIC) and to provide the second data stream to a second DDIC.

12. The system of claim 8, wherein the first display protocol and the second display protocol are selected from the group consisting of: High Definition Multimedia Interface (HDMI), DisplayPort (DP), and Display Serial Interface (DSI).

13. The system of claim 8, wherein the host processor is configured to adjust the deviation between a first synchronization signal of the first data stream and a second synchronization signal of the second data stream.

14. The system of claim 13, wherein the host processor is configured to adjust the deviation based on a feedback signal.

15. A system for displaying video, the system comprising: A component for splitting each frame in a video data frame stream into a first data stream and a second data stream along a horizontal display axis, wherein the pixel ratio of the pixels represented by the first data stream to the pixels represented by the second data stream corresponds to the ratio of the first bandwidth of a first data link configured using a first display protocol to the second bandwidth of a second data link configured using a second display protocol. A component for providing the first data stream to a first display controller associated with the display panel via the first data link; and A component for providing the second data stream to a second display controller associated with the display panel via the second data link.

16. The system according to claim 15, wherein: The components for providing the first data stream include components for providing the first data stream through a first display port of the system-on-chip (SoC); and The component for providing the second data stream includes a component for providing the second data stream through a second display port of the SoC.

17. The system of claim 15, wherein the first data link includes a first serializer and a first deserializer, and the second data link includes a second serializer and a second deserializer.

18. The system according to claim 15, wherein: The components for providing the first data stream to the first display controller include components for providing the first data stream to the first display driver integrated circuit (DDIC); and The component for providing the second data stream to the second display controller includes a component for providing the second data stream to the second DDIC.

19. The system of claim 15, wherein the first display protocol and the second display protocol are selected from the group consisting of: High Definition Multimedia Interface (HDMI), DisplayPort (DP), and Display Serial Interface (DSI).

20. The system of claim 15, further comprising a component for adjusting the deviation between a first synchronization signal of the first data stream and a second synchronization signal of the second data stream.

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