Multi-plane word line

Abstract

In some implementations, a controller of a storage device can configure the storage device to have a multi-plane word line that includes a first word line of a first plane having a first index and a second word line of a second plane having a second index that is offset from the first index. The controller can perform a write operation or a read operation on the multi-plane word line. In this way, the multi-plane word line can include word lines at different indices of different planes and thereby reduce high error rates of a particular multi-plane word line that might otherwise be caused by a physical defect that is common to word lines at the same index of different planes.

Description

[0001] Cross-reference to related applications

[0002] This patent application claims priority to U.S. Patent Application Serial No. 18 / 807,975, filed August 17, 2024, entitled “MULTI-PLANE WORD LINES,” and Provisional Patent Application No. 63 / 555,398, filed February 19, 2024, also entitled “MULTI-PLANE WORD LINES.” The disclosure of the earlier applications is considered part of this patent application and is incorporated herein by reference. Technical Field

[0003] This disclosure relates generally to multi-plane word lines in storage devices. Specifically, the multi-plane word line can be configured such that it includes word lines of a first plane located at a first word line index and word lines of a second plane located at a second word line index, the second word line index being offset from the first word line index. Background Technology

[0004] Non-volatile memory devices may include memory devices capable of storing and retaining data without an external power source. An example of a non-volatile memory device is a NAND flash memory device. A non-volatile memory device (also referred to as a “memory device”) may be configured with word lines located on respective planes of the memory device. A word line may include bits from multiple bit lines (e.g., where bit lines are organized in a dimension perpendicular to the word line). Word lines from multiple planes (e.g., where multiple planes are organized in a dimension perpendicular to the word line) may be combined to form a multi-plane word line. Summary of the Invention

[0005] In some specific implementations, a method performed by a controller of a storage device includes: configuring the storage device to have a multi-plane word line, the multi-plane word line including a first word line of a first plane having a first index and a second word line of a second plane having a second index, the second index being offset from the first index; and performing a write operation or a read operation on the multi-plane word line.

[0006] In some specific implementations, a system includes: a controller for a non-volatile memory device, the controller being configured to: configure the memory device to have multi-plane word lines, the multi-plane word lines including a first word line with a first index on a first plane and a second word line with a second index on a second plane, the second index being offset from the first index; and perform a write operation on the multi-plane word lines.

[0007] In some embodiments, a computer program product includes: one or more computer-readable storage media, and program instructions commonly stored on the one or more computer-readable storage media, the program instructions including: program instructions for configuring a storage device to have a multi-plane word line, the multi-plane word line including a first word line of a first plane having a first index, and a second word line of a second plane having a second index, the second index being offset from the first index; and program instructions for performing a write operation or a read operation on the multi-plane word line. Attached Figure Description

[0008] Figures 1A to 1D This is an illustration of an example of a multi-plane character line as described in this article.

[0009] Figure 2 This is an illustration of an example of using multi-plane letter lines as described in this article.

[0010] Figure 3 yes Figures 1A to 2 A diagram illustrating example components of one or more devices.

[0011] Figure 4 This is a flowchart of an example process associated with the use of multiplane word lines, as described in this article. Detailed Implementation

[0012] The following detailed description of the specific implementation of the example is with reference to the accompanying drawings. The same reference numerals in different drawings may identify the same or similar elements.

[0013] Storage devices may include solid-state drives (SSDs). In some examples, storage devices such as SSDs may include multiple non-volatile memory devices, such as NAND flash memory devices, but are not limited thereto. Non-volatile memory devices may store data that can be accessed via a controller. The controller may include one or more application-specific integrated circuits (ASICs) or firmware.

[0014] Data storage on storage devices (e.g., non-volatile memory devices) can be corrupted. For example, data stored on a storage device may be stored in physical components such as transistors or other binary memory cells. To store data bits within the storage device (using a write operation), a controller may apply a voltage to a transistor, changing the transistor's state so that it reads a 1 or 0 when a read voltage is applied during a read operation. Applying voltage during a read or write operation may fail, which can lead to data corruption.

[0015] Furthermore, over time and after numerous programming / erase and write operations, the storage performance on a storage device may degrade, at least in part, due to the degradation of the physical components of the transistors or connected devices. For example, insulating materials, channel materials, gates, or conductive layers can interact, causing the barriers used to form current paths and voltage storage within the storage device to degrade.

[0016] Data stored on a storage device can be organized into word lines that span multiple bit lines (e.g., one bit per bit line). Based at least in part on the manufacturing process of the storage device, if a bit on a word line has an error caused by a physical defect in the storage device (e.g., a physical defect along the bit line), the likelihood that other bits on that word line may have errors caused by physical defects in the storage device increases.

[0017] Word lines can be indexed within a plane of a channel in a storage device. A bit similar to a word line, having an increased probability of error at least in part based on the first bit having an error caused by a physical defect in the storage device, may also have an increased probability of error at least in part based on the first bit having an error caused by a physical defect in the storage device.

[0018] In some storage devices, data can be further organized into multi-plane word lines (e.g., super word lines), which include word lines with the same index on multiple planes of the storage device (e.g., multiple planes associated with the same channel or die of the storage device). However, based at least in part on word lines with the same index on other planes, and at least in part on the increased probability of errors due to physical defects in the storage device, the multi-plane word line may have too many errors to be corrected by error correction operations (e.g., XOR operations or examples such as low-density parity check (LDPC)). In this way, physical defects can lead to the invalidation of data stored on the multi-plane word line.

[0019] In some respects, storage devices (such as SSDs) will eventually fail over time. Failures on storage devices can be induced by the storage medium (such as NAND dies). For example, defects such as word line-to-word line or word line-to-memory hole short circuits can cause storage device failure.

[0020] RAID5 or RAID6 parity (e.g., using an XOR scheme) can be used for data loss recovery from loss caused by various reasons, such as the aforementioned defects associated with word lines. However, these parity techniques may recover from errors to a certain extent (e.g., no more than 2 or 3 failures). Beyond this extent, parity will fail and XOR will be unable to reconstruct the original data (e.g., recover the data).

[0021] As the number of storage media (e.g., NAND dies) in a storage device increases (e.g., this number may exceed 1000), unrecoverable errors become increasingly likely. Furthermore, word line errors may increase with NAND scaling, during which more layers of word lines are built (e.g., from 64 layers to 96, 128, 160, 232, or over 300 layers, etc.). The likelihood of failure also increases at the level of each storage medium (e.g., each NAND die).

[0022] In some aspects described herein, a controller can configure a storage device with multi-plane word lines having a first set of indices on a first plane and a second set of indices on a second plane. For example, a particular word line may have a first index on the first plane and a second index offset from the first index on the second plane. In this way, for multi-plane word lines, physical defects that could cause errors between the word line at the first index and adjacent word lines (e.g., the first word line of the multi-plane word line) may be at least partially offset from the first index based on the second index and not extend to the second word line at the second index.

[0023] In some respects, logical block address (LBA) to physical block address (PBA) translation can be performed at the controller level of the storage device. The controller can determine the PBA used for write or read operations. For address bits of word lines controlling a particular storage medium or plane (e.g., NAND address bits), the controller can insert an offset equal to a given number, such as "d100". For edge word lines, the controller can use a different offset in the opposite direction, such that when programming or reading from the storage medium or plane, instead of WL(n) (e.g., associated with an LBA), the controller can actually read the word line at WL(n+z), where z can be positive or negative. The value of z can be controlled by the storage device or the controller. Multi-plane word lines can include word lines at WL(n) and WL(n+z) from different storage media or planes. Offsets reduce the likelihood of WL(n) defects occurring simultaneously across multiple storage media or planes. For example, if a physically induced failure exists at WL(n), the same failure is unlikely to occur at WL(n+z) because it is offset from WL(n), and XOR parity is more likely to recover the lost data.

[0024] This technique can be referred to as an "out-of-order" programming scheme on storage media. In some respects, by properly choosing the value of "z", this technique can mitigate the effects of "out-of-order" by following the "layering" principle of programming scheduling (e.g., NAND programming scheduling).

[0025] At least in part, based on the fact that the first index of the first word line of a multi-plane word line is offset from the second index of the second word line of the multi-plane word line, errors in the multi-plane word line are likely to be fewer than in a multi-plane word line where all word lines have the same index. At least in part, based on the fewer errors, error correction operations may have an increased probability of success in correcting data stored via the multi-plane word line, and may have improved reliability. In this way, the storage device can have an improved success rate in storing and retrieving data. For example, the storage device can reduce defects per million units (DPPM), reduce the uncorrectable block error rate (UBER), or reduce the annual failure rate (AFR), etc.

[0026] In some examples, defects caused by storage media failures can be halved by offsetting with values ​​as low as z=1, without changing the techniques used for XOR parity recovery.

[0027] In some respects, having this offset can reduce the probability of defects in large-scale storage devices (e.g., SSDs), where errors are more likely to occur. In some respects, the offset can be managed by the storage medium itself (e.g., NAND) or by the storage device controller (e.g., an ASIC controller). In some respects, the offset can be configured or used on-the-fly as the storage device or storage medium ages. In this way, using an offset is a solution that can be applied at the storage device or storage medium level without incurring additional implementation costs at the factory or manufacturing site. Additionally, using an offset can improve the user experience.

[0028] In some respects, the XOR scheme or other decoding techniques can vary at least in part based on implementation choices. However, using offsets within the word line can add value to improved decoding, regardless of which XOR scheme or decoding technique is implemented. For example, this technique can be used with Peripheral Component High-Speed ​​Interconnect (PCIe), Non-Volatile Memory Standard (NVMe), and Compute Fast Link (CXL) protocols.

[0029] Figures 1A to 1D This is an illustration of an example of a multi-plane character line as described in this article. Figures 1A to 1D Multi-plane word lines can be configured within a storage medium that may include multiple channels (e.g., each channel is associated with a different storage medium, or a set of channels is associated with different storage media, and other examples). Although shown as including word lines from multiple channels, multi-plane word lines may include word lines from only one channel or from only one storage medium. Furthermore, the offsets and number of word lines shown are provided as examples and are not limiting.

[0030] like Figure 1AAs shown, the storage medium 102 of the first channel (referred to as storage medium 102) may include planes 104, 106, and 108, and the storage medium 110 of the second channel (referred to as storage medium 110) may include planes 112, 114, and 116. Planes 104, 106, 108, 112, 114, and 116 include word lines located at index number 118. For example, each plane may include a set of word line index numbers (e.g., the same set of word line index numbers).

[0031] In some storage devices not shown, multi-plane word lines may include word lines located on multiple planes at the same word line index. However, based at least in part on the manufacturing process of bit lines that form planes spanning multiple word lines (e.g., all word lines at each index number), where multiple word lines are formed simultaneously in different layers, the likelihood of errors occurring at adjacent word line indices on multiple planes increases.

[0032] like Figure 1A As shown, multi-plane word lines may include word lines 120, 122, 124, 126, 128, and 130. Consecutive word lines (e.g., 120 and 122) may be located at a word line index with an offset of 132. Figure 1A As shown, the offset 132 between consecutive word lines 120 and 122 can be the same in magnitude as the offset 132 between consecutive word lines 122 and 124. In this way, word lines 120 and 124 can be located at the same index. Storage medium 102 may include word lines located on additional planes, wherein word lines of multi-plane word lines alternate between two or more index values ​​having the same offset 132.

[0033] Similarly, the offset 132 between consecutive word lines 126 and 128 may be the same in magnitude as the offset 132 between consecutive word lines 122 and 124. Alternatively, the offset 132 associated with storage medium 102 may be different from the offset 132 associated with storage medium 110. Additionally or alternatively, the last word line of storage medium 102 may be offset from the first word line of storage medium 110.

[0034] like Figure 1BAs shown, word lines 120, 122, 124, 126, 128, and 130 can alternate between levels of the word line index. For example, planes 104, 106, 108, 112, 114, and 116 can include a first level and a second level divided by level division 134. In this way, offset 132 can be large enough to separate word lines 120 and 122 to be in different levels. For example, the offset can be equal to the number of word line indices within the level. In this way, offset 132 can force consecutive word lines into different levels. For example, a first word line (e.g., word line 120) can be associated with a first word line level, and a second word line (e.g., word line 122) can be associated with a second word line level. If the offset is equal to the number of word line indices within a certain level, then word line 120 may have the same word line index in the first level as word line 122 has in the second level (e.g., a second word line from the bottom edge of each level).

[0035] like Figure 1C As shown, with Figure 1B Similarly, offset 132 separates word line 120 and word line 122 into different levels. Figure 1B compared to, Figure 1C Word line 122 is shown, having an index value equal to the difference between the highest value and a first value in the index range. For example, if the word line index number ranges from 0 to 99, word line 120 may have an index value of 1, and word line 122 may have an index value of 98 (99 is the highest value, 1 is the index value of word line 120, therefore 99-1=98). Alternatively, the index of word line 122 within the second level may be counted in the opposite direction to the index of word line 120 within the first level. For example, word line 120 may have an index counted from bottom to top (e.g., towards the second level including word line 122), and word line 122 may have an index counted from top to bottom (e.g., towards the first level including word line 120). For example, word line 120 may have an index value of 1 counted from bottom to top (e.g., towards level division 134) in a lower level (e.g., below level division 134), and word line 122 may also have an index value of 1 counted from top to bottom (e.g., towards level division 134) in a higher level (e.g., above level division 134). As an example, in the case of two levels, the selected word lines are the second word line from the top in plane 106 and the second word line from the bottom in plane 104. According to NAND technology, these two word lines can operate simultaneously. Similarly, word line 122 and word line 124 may have the same word line index counted in opposite directions, or the index of word line 124 may be equal to the difference between the highest value of the index range and the first value.

[0036] like Figure 1DAs shown, additional word lines (e.g., second word lines) are also stored on storage media 102 and storage media 110. Figure 1D As shown, additional multiplane word lines may include word lines 136, 138, 140, 142, 144, and 146. Consecutive word lines in the additional multiplane word lines may be separated by an index equal to offset 148. In some respects, offset 148 may be equal to offset 132. Alternatively, offset 148 may be different from offset 132.

[0037] In some respects, offsets 132 or 148 may be the same between each word line in a continuous word line. In some respects, offsets 132 or 148 may be different between some or each continuous word line. In some respects, there may be no offset within the first group of continuous word lines, and the first group of continuous word lines may be offset from the second group of continuous word lines. For example, the first pair of word lines may be located at the same index number, and the second pair of word lines may be located at a second index number offset from the first pair of word lines.

[0038] Figure 2 This is a diagram illustrating an example process 200 associated with the use of multi-plane word lines. In some specific implementations, Figure 2 One or more process frames can be executed by a controller (e.g., a NAND controller). In some specific implementations, Figure 2 One or more process frames may be executed by another device or a group of devices, separate from or including the controller. Additionally or alternatively, Figure 2 One or more process frames can be defined as follows: Figure 3 The device 300 shown may be executed by one or more components (such as processor 320, memory 330, storage component 340, input component 350, output component 360 and / or communication component 370).

[0039] like Figure 2 As shown, the storage device can be programmed with host data. For example, the storage device can receive commands from the host device to write data to the storage device via a set of planes having a set of word lines. The word lines can be organized into a multi-plane word line that includes word lines from different planes.

[0040] like Figure 2 As shown, at box 210, the storage device controller can perform a translation from host logical block address (LBA) to flash LBA and then to virtual physical block address (PBA). In this way, the controller can translate an index indicated by the host (e.g., indicating the location of data) into an index of the physical location of the data stored on the storage device.

[0041] like Figure 2As shown, at box 220, the controller can enable reliable address decoding for that box. For example, the controller can enable reliable address decoding based at least in part on one or more metrics associated with the expected error rate of the data stored on the block. In some aspects, the expected error rate can be based at least in part on programming / erase cycle counts, and other examples.

[0042] like Figure 2 As shown, at box 230, the controller can identify whether a condition is met. For example, the controller can determine whether one or more metrics meet a threshold. If the condition is met, at box 240, the controller can offset the word line address decoding by selecting different physical word line locations on different planes (e.g., the NAND plane). In some aspects, the controller can offset word lines on the same die or different dies (e.g., NAND dies) of the storage device. At box 250, the storage device can use virtual PBAs with offset word lines. The storage device can write data to these virtual word lines and then read data from these virtual word lines. In this way, the use of word lines with offsets (e.g., virtual word lines) can be transparent to the host device because the host device references the host LBA, and the storage device translates that host LBA into multi-plane word lines with offsets.

[0043] If the conditions are not met, at box 260, the controller may continue with existing decoding. For example, the controller may decode data stored on a multiplane word line that includes only word lines with the same word line index. At box 270, the controller may continue with existing programming formats. For example, the controller may program data onto one or more storage media on a multiplane word line that includes only word lines with the same word line index or another configuration of multiplane word lines used at the storage device. At box 280, the controller may update the LBA to the physical block address table accordingly. Additionally or alternatively, subsequent read operations may follow the same read scheme, provided the table is complete.

[0044] Figure 3 This is a diagram illustrating example components of device 300, which may correspond to... Figures 1A to 2 One or more devices, such as a storage device or the storage device. In some implementations, the controller or host device may include one or more devices 300 and one or more components of device 300. Figure 3 As shown, device 300 may include bus 310, processor 320, memory 330, storage component 340, input component 350, output component 360 and communication component 370.

[0045] Bus 310 includes components enabling wired or wireless communication between components of device 300. Processor 320 includes a central processing unit, graphics processing unit, microprocessor, controller, microcontroller, digital signal processor, field-programmable gate array, application-specific integrated circuit, or other type of processing component. Processor 320 is implemented in hardware, firmware, or a combination of hardware and software. In some embodiments, processor 320 includes one or more processors that can be programmed to perform functions. Memory 330 includes random access memory, read-only memory, or another type of memory (e.g., flash memory, magnetic memory, or optical memory). In some embodiments, memory 330 may include the ECC engine or LDPC engine described above. In this case, memory 330 may be its own ecosystem, with its own processor, controller, LDPC engine, and storage media such as NAND.

[0046] Storage component 340 (e.g., storage device 105) stores information or software related to the operation of device 300. For example, storage component 340 may include a hard disk drive, disk drive, optical disk drive, solid-state drive, optical disk, digital versatile optical disk, or another type of non-transitory computer-readable medium. In some implementations, storage component 340 may include the ECC engine or LDPC engine described above. In this case, storage component 340 may be its own ecosystem, with its own processor, controller, LDPC engine, and storage media such as NAND.

[0047] Input component 350 enables device 300 to receive input, such as user input or sensed input. For example, input component 350 may include a touchscreen, keyboard, keypad, mouse, button, microphone, switch, sensor, GPS component, accelerometer, gyroscope, or actuator. Output component 360 enables device 300 to provide output, such as via a display, speaker, or one or more light-emitting diodes. Communication component 370 enables device 300 to communicate with other devices, such as via a wired or wireless connection. For example, communication component 370 may include a receiver, transmitter, transceiver, modem, network interface card, or antenna.

[0048] Device 300 may perform one or more processes described herein. For example, a non-transitory computer-readable medium (e.g., memory 330 or storage component 340) may store a set of instructions (e.g., one or more instructions, code, software code, or program code) for execution by processor 320. Processor 320 may execute the set of instructions to perform one or more processes described herein. In some embodiments, execution of the set of instructions by one or more processors 320 causes one or more processors 320 or device 300 to perform one or more processes described herein. In some embodiments, hardwired circuitry may be used in place of or in combination with instructions to perform one or more processes described herein. Therefore, the embodiments described herein are not limited to any particular combination of hardware circuitry and software.

[0049] Figure 3 The number and arrangement of components shown are provided as an example. Device 300 may include components with... Figure 3 The components shown are compared to additional components, fewer components, different components, or components arranged in a different manner. Additionally or alternatively, a set of components of device 300 (e.g., one or more components) may perform one or more functions described as being performed by another set of components of device 300.

[0050] Figure 4 This is a flowchart of an example process 400 associated with the use of multi-plane word lines. In some specific implementations, Figure 4 One or more process frames can be executed by a controller (e.g., a NAND controller). In some specific implementations, Figure 4 One or more process frames may be executed by another device or a group of devices, separate from or including the controller. Additionally or alternatively, Figure 4 One or more process frames may be executed by one or more components of the device 300, such as processor 320, memory 330, storage component 340, input component 350, output component 360 and / or communication component 370.

[0051] like Figure 4 As further shown, process 400 may include selecting the offset of the multiplane word line (box 410). For example, as described above, the controller of the storage device or the storage medium selects the offset of the multiplane word line.

[0052] like Figure 4As shown, process 400 may include configuring a storage device to have a multi-plane word line, the multi-plane word line including a first word line with a first index in a first plane and a second word line with a second index in a second plane, the second index being offset from the first index (box 420). For example, a controller may configure a storage device to have a multi-plane word line including: a first word line with a first index in a first plane and a second word line with a second index in a second plane, the second index being offset from the first index, as described above.

[0053] like Figure 4 As further shown, process 400 may include performing a write operation or a read operation on a multiplane word line (block 430). For example, the controller may perform a write operation or a read operation on a multiplane word line as described above.

[0054] Process 400 may include additional implementations, such as any single implementation or any combination of implementations described below and / or in conjunction with one or more other processes described elsewhere herein.

[0055] In some specific implementations, the multiplane word line includes a third word line with a third index in the third plane, and wherein the amount by which the third index is offset from the second index is equal to the amount by which it is offset from the second index to the first index.

[0056] In some specific implementations, the first index and the second index are associated with an index range, which is associated with a word line level, wherein the first index has a first value and is associated with a first word line level, wherein the second index has a second value and is associated with a second word line level, and wherein the second value is equal to the first value.

[0057] In some specific implementations, the first index and the second index are associated with an index range, which is associated with a word line level, wherein the first index has a first value and is associated with a first word line level, wherein the second index has a second value and is associated with a second word line level, and wherein the second value is equal to the difference between the highest value of the index range and the first value.

[0058] In some specific implementations, the first index and the second index are associated with an index range, which is associated with a word line level, wherein the first index has a first value and is associated with a first word line level counted in a first direction, and the second index has a second value and is associated with a second word line level counted in a second direction opposite to the first direction.

[0059] In some implementations, the first and second indexes are associated with an index range, which is associated with a word line level, and the offset between the first and second word line indices is equal to the length of the word line level.

[0060] In some specific implementations, the additional multiplane word lines in a plurality of multiplane word lines include a third word line with a third index in the first plane and a fourth word line with a fourth index in the second plane, wherein the amount of offset of the fourth index from the third index is different from the amount of offset from the first index to the second index.

[0061] In some implementations, performing a read operation includes applying error correction operations to correct one or more word lines in a multiplane word line.

[0062] In some implementations, the offset between the first index and the second index is associated with the first die of the storage device, and an additional offset between the first index and the second index is associated with the second die of the storage device.

[0063] In some implementations, either alone or in combination with one or more of the first to eighth implementations, the storage device is configured to have a multiplane word line in which the second index is offset from the first index, at least in part based on: satisfying the error rate of read operations associated with a multiplane word line in which the second index is not offset from the first index.

[0064] In some implementations, process 400 includes selecting the size of the offset between the second word line and the first word line, based at least in part on the error rate of the read operation associated with the multi-plane word line.

[0065] In some implementations, process 400 includes: enabling reliable address decoding based at least in part on one or more metrics associated with the expected error rate of data stored on the block; and identifying whether a condition is met. In some implementations, identifying whether a condition is met includes: determining whether one or more metrics meet a threshold; and selecting different physical word line locations associated with the offset on different planes. In some aspects, reliable address decoding includes decoding associated with production screening statistics to check whether the probability of simultaneous failure of the same word line index across different planes meets a threshold.

[0066] In some implementations, a write operation can be performed on the multiplane word line to write data before a read operation is performed to read the data. The address decoding of the newly formed multiplane word line is memorized by the system for performing write and read operations on the multiplane word line.

[0067] although Figure 4 An example block diagram of process 400 is shown, but in some specific implementations, process 400 may include... Figure 4 The boxes depicted in the process 400 may be fewer, different, or arranged differently than additional boxes, fewer, different, or different from other boxes. Alternatively, two or more boxes in the process 400 may be executed in parallel.

[0068] In some implementations, a method performed by a controller of a storage device includes configuring the storage device to have multi-plane word lines, the multi-plane word lines including a first word line with a first index in a first plane and a second word line with a second index in a second plane, the second index being offset from the first index. The method also includes performing a write operation or a read operation on the multi-plane word lines.

[0069] In some implementations, a system includes a controller for a non-volatile memory device, the controller being arranged to configure the memory device to have multi-plane word lines, the multi-plane word lines including a first word line with a first index on a first plane, and a second word line with a second index on a second plane, the second index being offset from the first index. The controller may also be configured to perform write or read operations on the multi-plane word lines.

[0070] In some implementations, the computer program product includes one or more computer-readable storage media, and program instructions co-stored on the one or more computer-readable storage media. The program instructions include instructions for configuring the storage device to have a multi-plane word line, the multi-plane word line including a first word line with a first index on a first plane, and a second word line with a second index on a second plane, the second index being offset from the first index. The program instructions also include instructions for performing write or read operations on the multi-plane word line.

[0071] Various embodiments of this disclosure have been described for illustrative purposes, but these descriptions are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best illustrate the principles of the embodiments, the practical application of or improvement of technology superior to that found on the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

[0072] As used herein, the term "component" is intended to be interpreted broadly as hardware, firmware, or a combination of hardware and software. It will be apparent that the systems or methods described herein can be implemented in various forms of hardware, firmware, or combinations of hardware and software. The actual dedicated control hardware or software code used to implement these systems or methods does not limit the specific implementation. Therefore, this document describes the operation and behavior of systems or methods without reference to any specific software code, and it should be understood that software and hardware can be used to implement systems or methods, at least in part, based on the description herein.

[0073] As used in this article, depending on the context, a threshold can refer to a value greater than the threshold, greater than or equal to the threshold, less than the threshold, less than or equal to the threshold, equal to the threshold, or not equal to the threshold.

[0074] Although specific combinations of features are stated in the claims or disclosed in the specification, these combinations are not intended to limit the disclosure of various embodiments. In fact, many of these features can be combined in ways not specifically stated in the claims or disclosed in the specification. While each dependent claim listed below may directly depend on only one claim, the disclosure of various embodiments includes each dependent claim in combination with each other claim in the claim group. As used herein, the phrase “at least one of” in the list of entries refers to any combination of these entries, including a single member. As an example, “at least one of a, b, or c” is intended to cover a, b, c, ab, ac, bc, and abc, as well as any combination with multiple identical items.

[0075] Unless explicitly stated otherwise, no element, action, or instruction used herein should be construed as critical or necessary. Additionally, as used herein, the articles “a” and “one” are intended to include one or more items and are interchangeable with “one or more.” Furthermore, as used herein, the article “the” is intended to include one or more items mentioned in connection with the article “the” and is interchangeable with “one or more.” Furthermore, as used herein, the term “set” is intended to include one or more items (e.g., related items, unrelated items, or a combination of related and unrelated items) and is interchangeable with “one or more.” Where only one item is intended, the phrase “only one” or similar language is used. Additionally, as used herein, the terms “having,” “possessing,” etc., are intended to be open-ended terms. Furthermore, unless explicitly stated otherwise, the phrase “based on at least partially” is intended to mean “based on at least partially.” Additionally, as used herein, the term “or” is intended to be open-ended when used in a series and is interchangeable with “or” unless explicitly stated otherwise (e.g., if used in conjunction with “any” or “only one”).

Claims

1. A method executed by a controller of a storage device, the method comprising: The storage device is configured to have multi-plane word lines, the multi-plane word lines including: The first word line of the first plane with the first index, and A second word line with a second index in the second plane, the second index being offset from the first index; and Perform write or read operations on the multi-plane word lines.

2. The method of claim 1, wherein the multi-plane word line includes a third word line with a third index on a third plane, and The amount by which the third index is offset from the second index is equal to the amount by which the third index is offset from the second index to the first index.

3. The method of claim 1, wherein the first index and the second index are associated with an index range, and the index range is associated with a word line level. The first index has a first value and is associated with a first word line level. The second index has a second value and is associated with the second word line level, and The second value is equal to the first value.

4. The method of claim 1, wherein the first index and the second index are associated with an index range, and the index range is associated with a word line level. The first index has a first value and is associated with a first word line level. The second index has a second value and is associated with the second word line level, and The second value is equal to the difference between the highest value of the index range and the first value.

5. The method of claim 1, wherein the first index and the second index are associated with an index range, the index range being associated with a word line level, and The offset between the first word line index and the second word line index is equal to the length of the word line level.

6. The method of claim 1, wherein the additional multiplane word lines in the plurality of multiplane word lines comprise: The third word line with the third index in the first plane, and The second plane has a fourth word line with a fourth index, the fourth index being offset from the third index by an amount different from the amount of offset from the first index to the second index.

7. The method of claim 1, wherein performing the read operation comprises: An error correction operation is applied to correct one or more word lines in the multi-plane word lines.

8. The method of claim 1, wherein the offset between the first index and the second index is associated with a first die of the storage device, and The additional offset between the first index and the second index is associated with the second die of the storage device.

9. The method of claim 1, wherein configuring the storage device to have the multiplane word line, wherein the second index is offset from the first index, is at least partially based on: The error rate of read operations associated with the multiplane word line where the second index is not offset from the first index.

10. The method of claim 1, wherein the method comprises selecting the magnitude of the offset between the second character line and the first character line based at least in part on: The error rate of the read operation associated with the multi-plane word line is satisfied.

11. A system comprising: A controller for a non-volatile memory device, the controller being configured to: The storage device is configured to have multi-plane word lines, the multi-plane word lines including: The first word line of the first plane with the first index, and A second word line with a second index in the second plane, the second index being offset from the first index; and Perform a write operation on the multi-plane word line.

12. The system of claim 11, wherein the multi-plane word line includes a third word line located at one of the first index or the second index.

13. The system of claim 11, wherein the first index and the second index are associated with an index range, and the index range is associated with a word line level. The first index has a first value within the first word line level. The second index has the first value within the second word line level.

14. The system of claim 13, wherein the first index is counted along a first direction within the first word line level, and The first index is counted within the second word line level along a second direction opposite to the first direction.

15. The system of claim 11, wherein the multi-plane word line comprises word lines located within a plurality of storage media.

16. A computer program product, the computer program product comprising: One or more computer-readable storage media, and program instructions commonly stored on the one or more computer-readable storage media, the program instructions comprising: Program instructions for configuring a storage device to have multi-plane word lines, the multi-plane word lines including: The first word line of the first plane with the first index, and A second word line in the second plane having a second index, the second index being offset from the first index; and Program instructions for performing write or read operations on the multiplane word lines.

17. The computer program product of claim 16, wherein the multi-plane word line includes a third word line having a third index on a third plane, and The amount by which the third index is offset from the second index is different from the amount by which the third index is offset from the second index to the first index.

18. The computer program product of claim 16, wherein the program instructions include program instructions for selecting the magnitude of the offset between the second word line and the first word line based at least in part on: The error rate of read operations is satisfied with one or more planes associated with the multiplane word line.

19. The computer program product of claim 16, wherein the program instructions include program instructions for: Reliable address decoding is enabled, at least in part, based on one or more metrics associated with the expected error rate of the data stored on the block; and Does the identifier meet the conditions? 20. The computer program product of claim 19, wherein, in order to identify whether the condition is satisfied, the program instructions include program instructions for the following operations: Determine whether the one or more metrics meet the threshold; and Select different physical word line positions associated with the offset on different planes.

21. The computer program product of claim 19, wherein the reliability address decoding comprises: The decoding, associated with production screening statistics, is used to check whether the probability of simultaneous failure of the same word line index across different planes meets a threshold.

22. The computer program product of claim 16, wherein the program instructions comprise: Program instructions for performing the write operation before performing the read operation.

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