Multi-level programmable resistance memory cell

Abstract

This application describes a multi-level programmable resistive memory cell (200, 300, 400, 600, 800) using charge-trapping transistors (CTTs). A programmable resistor network is connected between two resistor nodes (A, B) and includes multiple charge-trapping transistors (T1…TN). The cell can operate in a programming mode to selectively program each of the CTTs to a selected on-resistance state by programming the amount of charge trapped in the CTTs; and in an output mode, where each of the CTTs is driven by a corresponding gate-source voltage. The cell is configured such that by programming the CTTs in the programming mode, the cell resistance between the two resistor terminals in the output mode can be selectively changed among at least three different resistance values.

Description

[0001] The embodiments disclosed herein relate to programmable resistor memory cells.

[0002] Analog computing performs computational operations using changes in the voltage and / or current levels of data signals. Therefore, analog computing offers an alternative to traditional digital computing systems, where such operations are performed using binary data. An advantage of analog computing systems is that they can be tailored for low-power operation. This makes analog computing systems particularly suitable for low-power, always-on applications, such as edge computing. The concept of "edge computing" shifts at least some of the computational load associated with processing for applications that would typically be performed by some central computing facility to "edge devices" (such as smartphones, tablets, etc.) that collect the relevant data to be processed. This can significantly reduce the computational burden on central facilities.

[0003] For some applications, such as time-critical systems (e.g., speech processing), traditional von Neumann computing architectures can face bottlenecks in performing any computational operation. This requires the processor module to access a separate memory module to retrieve data and then write the output of any processing operation back to memory for future use. The constant data reads and writes between the processor and memory consume processing cycles and / or power, thus limiting the overall efficiency of analog computing systems designed for low-power, fast-response operations.

[0004] To address this bottleneck, memristors have been proposed as an option for implementing in-processor memory. A memristor can be described as a resistor with memory, where its resistance can be programmed to store data. Once programmed, applying a controlled voltage or current to the memristor provides an output current or voltage that depends on the memristor's resistance and therefore on the stored data. The controlled voltage or current can be a defined read voltage or current to allow data to be read, or it can be a voltage or current controlled by some input data, in which case the output from the memristor is the product of the input data and the stored data. This allows the memristor to be implemented as part of an analog computing circuit, where the action of accessing data is performed as part of the computation step, thus avoiding the need for separate memory access and processing steps.

[0005] Therefore, this memristor-based memory can offer some advantages for applications such as analog computing. However, the process for manufacturing memristors may require some non-standard circuit processing steps, which could increase the cost of such circuits, and some existing memristor technologies may lead to problems such as resistance variations between components and / or programming repetitiveness.

[0006] Embodiments of this disclosure relate to a programmable resistor memory that alleviates at least some of the aforementioned problems.

[0007] In a first aspect, a multi-level programmable resistive memory cell is provided, comprising: a first resistive node and a second resistive node; and a programmable resistive network connected between the first and second resistive nodes, wherein the programmable resistive network includes a first plurality of charge-trapping transistors. The multi-level programmable resistive memory cell is operable in the following modes: a programming mode for selectively programming each of the first plurality of charge-trapping transistors to a selected on-resistance state by programming the amount of charge trapped in the charge-trapping transistors; and an output mode, wherein each of the first plurality of charge-trapping transistors is driven by a corresponding gate-source voltage. The multi-level programmable resistive memory cell is configured such that, by programming the first plurality of charge-trapping transistors in the programming mode, a cell resistance between a first resistive terminal and a second resistive terminal can be selectively changed among at least three different resistance values ​​in the output mode.

[0008] In some implementations, the resistor network can be configured such that each of the first plurality of charge-trapping transistors is configured as part of a corresponding weighted bit portion of the multilevel programmable resistive memory cell, such that programming the charge-trapping transistor programs the corresponding weighted bit of the multilevel programmable resistive memory cell.

[0009] In some implementations, for a first group of two or more charge-trapping transistors in the plurality of charge-trapping transistors, each of the charge-trapping transistors in the first group has a source electrode connected to a common source node. In some implementations, the first group includes all of the first plurality of charge-trapping transistors. The multilevel programmable resistive memory cell can be configured such that, in the output mode, the gate electrode of each of the first plurality of charge-trapping transistors in the first group is connected to a common bias voltage.

[0010] In some implementations, each of the first plurality of charge-trapping transistors may be arranged in a corresponding branch of a plurality of parallel branches of the resistor network.

[0011] One or more of the parallel branches of the resistor network may include a fixed resistor connected in series with the charge-trapping transistor, wherein the resistance value of the fixed resistor is different in the different parallel branches. For each parallel branch of the resistor network in which the fixed resistor is connected in series with the charge-trapping transistor, the fixed resistor may be connected to the drain electrode of the charge-trapping transistor.

[0012] One or more of the parallel branches of the resistor network may include an active resistive element configured to provide an on-resistance value to the charge-trapping transistor string, wherein the active resistive element includes a transistor. The active resistive element may include a charge-trapping transistor in a second plurality of charge-trapping transistors. The first plurality of charge-trapping transistors may include an n-channel transistor, while the second plurality of charge-trapping transistors may include a p-channel transistor, and vice versa. In such parallel branches, the drain of the charge-trapping transistor in the first plurality of charge-trapping transistors may be connected to the drain of the charge-trapping transistor in the second plurality of charge-trapping transistors. The gate of the charge-trapping transistor in the first plurality of charge-trapping transistors may be connected to the source voltage of the charge-trapping transistor in the second plurality of charge-trapping transistors, and vice versa.

[0013] In some implementations, the resistor network may include a plurality of fixed resistors connected in series, wherein each of the plurality of charge trapping transistors is connected in parallel with a different number of the series-connected fixed resistors.

[0014] The multilevel programmable resistive memory cell can be configured such that at least some of the first plurality of charge-trapping transistors in the output node are driven by different gate-source voltages from each other.

[0015] The multilevel programmable resistive memory cell can be configured such that at least some of the first plurality of charge trapping transistors are configured to have different channel length to channel width ratios.

[0016] The multilevel programmable resistive memory cell can be configured such that at least some of the charge trapping transistors are configured to have different body electrode bias voltages from each other.

[0017] The multilevel programmable resistor memory cell can be configured to program the first plurality of charge-trapping transistors in a sequential process. In this programming mode, the on-resistance value of the multilevel programmable resistor memory cell can be determined after each charge-trapping transistor is programmed in the sequential process, and the programming of subsequent charge-trapping transistors in the sequential process can be controlled to compensate for any inaccuracies in the determined on-resistance value of the multilevel programmable resistor memory cell. The multilevel programmable resistor memory cell can be configured to determine a resistance change in the on-resistance after each charge-trapping transistor is programmed, and to control the programming of subsequent charge-trapping transistors in the sequential process to: increase the threshold voltage offset of the subsequent charge-trapping transistor if the determined resistance change is less than expected; and decrease the threshold voltage offset of the subsequent charge-trapping transistor if the determined resistance change is greater than expected.

[0018] This multilevel programmable resistive memory cell can be implemented as part of an analog computing circuit, such as as part of a multiply-accumulate circuit and / or an artificial neural network, or it can be implemented as part of a digital memory.

[0019] Those skilled in the art will understand that the various features described herein with reference to different examples and implementations can be combined in the same implementation unless they are obviously incompatible.

[0020] The embodiments of this disclosure will now be described by way of example and with reference to the accompanying drawings, wherein: Figure 1 An example of a charge trapping transistor is shown; Figure 2 An example of a multi-level programmable resistive memory cell formed by multiple charge-trapping transistors is shown; Figure 3 Another example of a multi-level programmable resistive memory cell formed by multiple charge-trapping transistors is shown; Figure 4 An example of a multi-level programmable resistive memory cell formed by multiple charge-trapping transistors having a common source node is shown; Figure 5 It shows how one can deal with, for example Figure 4 The charge trapping transistors of the memory cells shown are used for programming; Figure 6 Another example is shown of a multi-level programmable resistive memory cell formed by multiple charge-trapping transistors having a common source node; Figure 7 It shows how one can deal with, for example Figure 6 The charge trapping transistors of the memory cells shown are used for programming; Figure 8a and Figure 8b Another example is a multi-level programmable resistive memory cell formed by multiple charge-trapping transistors and active resistive devices; Figure 9a and Figure 9b This demonstrates how the resistance of memory cells that do not change monotonically with programming code can be mapped to a reordered sequence of code. Figure 10 An example of a multi-level programmable resistive memory cell formed by charge trapping transistors with different W / L ratios is shown; Figure 11 A multiply-accumulate circuit implemented using multi-level programmable resistive memory cells is shown; and Figure 12 Options for reading data from a multi-level programmable resistive memory cell are shown.

[0021] Embodiments of this disclosure relate to programmable resistive memory, wherein charge-trapping transistors are used as programmable resistive memory components, and more specifically to multi-level programmable resistive memory cells using charge-trapping transistors, wherein the resistance of the memory cell can be programmed to any of at least three different resistance values, i.e., to multi-bit programmable resistive memory cells.

[0022] Charge-trapping transistors (CTTs) are known semiconductor devices that can be used to store electrical charge. However, unlike conventional floating-gate transistors (where charge is stored in a conductive floating gate), in a CTT, charge is stored in an insulating charge-trapping layer.

[0023] Figure 1 The left side shows the basic structure of a simplified example of the CTT 100, while the right side shows the circuit symbol of the CTT that will be used in this disclosure.

[0024] The CTT 100 includes a substrate 101, typically silicon, with a drain region 102 and a source region 103. An insulating layer 105 is formed over the channel region of the substrate 2801, wherein the charge trapping layer 105 and the control gate 106 are on top of the substrate. For some examples of CTTs, silicon dioxide is used as the insulating layer, and silicon nitride is used as the charge trapping layer, but other material systems may also be used.

[0025] For some semiconductor manufacturing processes, such as for smaller process nodes (e.g., 22 nm or smaller), the fabrication of floating-gate transistor devices can utilize a layer of high-k dielectric material, for example, as part of the gate stack, and in such devices, the high-k dielectric material can act as a charge-trapping layer. For some other applications, the charge-trapping effect of high-k dielectric materials may be undesirable, but such devices can be advantageously used as CTTs.

[0026] CTTs can be implemented as N-channel or P-channel devices, for example, as NMOS or PMOS transistors, and either type of CTT can be used in embodiments of this disclosure. However, in some applications, NMOS devices may be preferred because NMOS devices can generally be implemented with a smaller circuit footprint than PMOS devices.

[0027] The basic operating principle of a CTT (Cellular Threshold Transistor) is the trapping and release of electrons or holes in the charge trapping layer 105. Applying a suitable voltage to the control gate 106, and sometimes together with a voltage applied between the drain 102 and the source 103, generates an electric field. This electric field allows charge carriers to tunnel through the insulating layer 104 to the charge trapping layer 105, where they are trapped. This trapped charge alters the transistor's threshold voltage V. T Specifically, different voltages can be applied to the control gate to cause charge release or detrapping. However, without applying such a specific release voltage, the time constant for the spontaneous release of trapped charge can be very high, for example, several years in some implementations, thus allowing data to be stored through the trapped charge and to have a corresponding effect on the threshold voltage of CTT.

[0028] Assuming the CTT is biased into the linear region, for example, the gate-source voltage is higher than the threshold voltage V. T And the drain-source voltage V DS If the drain-source resistance R is relatively small, then DS It can be given by the following formula: Where k is the Boltzmann constant, and W and L are the width and length of the transistor channel, respectively.

[0029] Therefore, the drain-source resistance R DS (It can be considered as the 'on-resistance' of a transistor) can be effectively programmed by controlling the amount of charge trapped by the CTT, and therefore the CTT can be used as a programmable resistive memory element.

[0030] CTTs, including those specifically provided with layers for charge trapping, have been implemented as CTT devices for storing charge, and such CTTs have been proposed for applications such as flash memories. However, in such flash memory applications, CTTs are typically implemented as binary memory cells, where multiple individual binary memory cells are addressed using appropriate bit-line and word-line addressing to store multi-bit values. However, in applications such as analog computing, such bit-line and word-line addressing is undesirable, but binary memory cells alone cannot provide sufficient resolution.

[0031] In some applications, the on-resistance R of the CTT can be simulated or continuously. DS (For a given gate-source voltage V) GS It can be programmed to any value within its operating range to enable the storage of data in an analog manner. However, achieving sufficient accuracy can be challenging.

[0032] A more robust approach employed in embodiments of this disclosure is to provide a memory cell comprising a resistor network including multiple CTTs, wherein different CTTs can be independently programmed to apply a threshold voltage V. T An offset that is essentially fixed and repeatable, for example, setting the threshold voltage to a defined first value V. T1 Or the second distinct value V as defined T2 Either of them, and therefore the resistance R DS Set as two corresponding specific values ​​R DS1 Or R DS2 Either of them (for a fixed gate-source voltage V) GS That is, each CTT acts as a binary programmable resistor element. The resistor network is configured such that programming multiple CTTs in this way provides multi-level (i.e., multi-bit) programmable resistor memory cells, that is, the on-resistance of the memory cells can be selectively varied between at least three different resistance values. Therefore, a CTT itself can act as a binary programmable resistor memory element, and a multi-bit programmable resistor memory cell can be synthesized from multiple such CTT binary programmable resistor memory elements. However, in some applications, a CTT can be selectively programmed to have more than two discrete resistance states, for example, by setting the threshold voltage V... T Set as N different possible values ​​V T1 V T2 ...V TN The selected value in.

[0033] Compared to memristors, using CTT offers several advantages. CTTs can be formed using standard semiconductor manufacturing techniques. Some processes used to produce memristors involve specialized fabrication to form the memristor, which may require additional and / or non-standard circuit layers, increasing manufacturing costs. In contrast, CTTs can be formed using standard fabrication steps used to form the rest of the circuitry.

[0034] Additionally, from the R above DS The equation will show that the change in on-resistance is related to V. GS –V T Inversely proportional, and therefore the threshold voltage V TControlled changes in resistance result in linear changes in conductance, which can be beneficial for analog computing applications and for using CTT to store weight values. In analog computing, changes in the conductance of multi-level programmable elements can be advantageous, which typically requires hyperbolic changes in resistance.

[0035] Multilevel memory elements or cells can be formed in a variety of different ways. For example, Figure 2 A multi-level programmable resistive memory cell 200 is shown to be implemented using multiple CTTs arranged as multiple bit portions connected in series between a first terminal A and a second terminal B of the memory cell. Figure 2 In the example, the three bit portions P1, P2 and P3 are marked by dashed lines, where each bit portion includes a different number of parallel CTTs. Figure 2 The diagram illustrates the first part P1 using a single CTT, the second part using two parallel CTTs, and the third part using four parallel CTTs. The number of CTTs in each part is selected to provide the desired weight for that part. Figure 2 In the example, the weight is a binary weight. When used, all CTTs of each part can be programmed to the same resistance state, such as the same state in a high on-resistance state or a low on-resistance state, to program the relevant bit part. Figure 2 The diagram shows only three bit segments, but this can be extended to more bit segments to provide higher bit resolution for memory cells. However, this would require a large number of CTTs.

[0036] Figure 3 An alternative multi-level programmable resistor memory cell 300 is shown, which also has multiple bit portions connected in series between the first terminal A and the second terminal B. However, in this example, the second and third bit portions each include a single CTT connected in parallel with a corresponding fixed (i.e., invariable) resistor RP2 or RP3, wherein the values ​​of the fixed resistors RP2 or RP3 are different from each other and are selected to provide the desired weight to the relevant bit portions.

[0037] However, from the resistance R of CTT DS The equations will show that the on-resistance of the CTT depends on the gate-source voltage V applied to the CTT in use. GS Therefore, when outputting data from a memory cell, the gate-source voltage V... GS It should be controlled to a known value. In at least some examples, for simplicity and / or consistency, the same gate-source voltage V is used for at least some (and possibly all) of a set of CTTs during data output. GS The value may be advantageous. For example, Figure 2 and Figure 3The arrangement of the series-connected CTTs shown, where providing a specific, defined gate-source voltage for each CTT, would involve monitoring the relevant source voltage along the series connection and providing some feedback control to adjust the gate voltage accordingly. While feasible, this arrangement can involve some relatively significant complexities.

[0038] In at least some implementations, a group of at least some (or possibly all) CTTs of the memory cell can therefore be preferably connected in such a way that the source of the relevant CTT is connected to a defined reference voltage. In this way, the gate voltage of the relevant CTT can be set with respect to the defined reference voltage. Advantageously, to reduce the number of required reference voltages, a multi-stage programmable resistor unit can be configured such that multiple CTTs have a common source terminal; that is, a group of at least some (or possibly all) CTTs is arranged such that their source terminals are connected to a common source node that can be at the defined reference voltage.

[0039] Figure 4 An example of a multi-level programmable resistor unit 400 formed by CTT according to an implementation scheme is shown. Figure 4 A multi-level programmable resistor unit 400 is shown extending between two terminals A and B and including multiple parallel branches. In this example, the first branch includes a first CTT T0, the second branch includes a fixed resistor RF, and each subsequent branch includes resistors R1…RN connected in series with the corresponding CTT T1…TN.

[0040] The common resistor R0 is connected in series with the parallel branches, but in some examples this common resistor can be omitted. Similarly, in some examples, the parallel branches with only a fixed resistor (i.e., resistor RF as shown in the figure) can be omitted, and / or each branch can include a resistor in series with CTT, i.e., the branch with only CTT T0 can be omitted.

[0041] In use, by appropriately adjusting the threshold voltage V T Each CTT can be programmed to a desired on-resistance state, for example, at least a high on-resistance state HI or a low on-resistance state LO. As those skilled in the art will understand, this changes the series on-resistance of the associated branch, and thus the total on-resistance of the multi-stage programmable resistor unit 400. The values ​​of resistors R0 and RF (if present) and R1 through RN are selected to provide appropriate weights for each parallel branch in order to provide a multi-stage programmable resistance range for the multi-stage programmable resistor unit 400. Thus, CTTs are associated with different weighted bit portions, which can be programmed individually.

[0042] exist Figure 4In the example, the source terminal of each CTT is connected to a common source node, terminal B in this example is terminal B, and any resistors connected in series with the CTTs in the branch are connected to the drain side of the CTT device. This means that the source terminals of all CTTs are connected to a common source node. Therefore, when outputting data from a memory cell, the voltage at the common source node (e.g., terminal B) can be controlled to be at a defined reference voltage, meaning that the same gate voltage can be applied to all CTTs to make each of the CTTs achieve the same gate-source voltage V. GS .

[0043] Figure 5 This demonstrates how it is possible to use in programming mode. Figure 4 The example program uses CTT in a parallel branch. For clarity, Figure 5 Only two parallel branches are shown, but it will be understood that other branches can be programmed in the same way.

[0044] In programming mode, the CTTs in the parallel branches can be programmed sequentially. To program CTT T1, a defined drain-source voltage is applied across CTT by connecting the drain to the defined programming drain voltage VDP via switch SDP1 and the common source node to the defined programming source voltage VSP via switch SSP. The gate of CTT T1 is then connected to the gate programming voltage VGP via switch SGP1. During programming of CTT T1, the amplitude of the gate programming voltage VGP is greater than the gate voltage applied when reading a value from a memory cell, and this amplitude is selected to trap or detrap the charge in CTT as needed. In some cases, the gate programming voltage VGP may comprise a series of voltage pulses or some other different voltage waveforms.

[0045] During programming of CTT T1, the programming source voltage VSP is applied to the common source node, and therefore also to the source of CTT T2. To control the voltage across the unprogrammed CTT T2, the drains of CTT T2 (and any other unprogrammed CTTs) can be biased to a known safe voltage. This safe voltage can be applied directly to the drain of each unprogrammed CTT, but, for example, when there are two or more parallel branches with CTTs, to reduce the total number of switches, the safe voltage VDSafe can be applied via switch SDSC to the node shared by all parallel branches, thus providing a safe voltage to the drain of each of the unprogrammed CTTs. However, this arrangement does mean that when the programming drain voltage is applied to the drain of CTT T1 and the safe voltage VDSafe is applied to the node shared by all parallel branches, a voltage difference can be formed across the fixed resistor R1, which can cause some current flow, and the voltage can be controlled to avoid excessive current flow. When programming CTT T1, the gate of CTT T2 (and any other unprogrammed CTT) can also be controlled to a known safe voltage below the programming threshold to avoid unwanted charge trapping or detrapping in that CTT.

[0046] It should be noted that Figure 5 The diagram shows that the body electrode of each CTT can be connected to the source electrode, such that the body electrode of the CTT is biased to the same voltage as the source electrode, which is a relatively simple and straightforward implementation. However, in some examples, the CTT can be configured so that the body electrode of the CTT can be selectively biased to a different voltage during programming mode. This is because changing the bias of the body electrode of the CTT during programming can facilitate auxiliary charge trapping or release, but at the cost of requiring some additional switches at the body electrode terminals of the CTT.

[0047] Once CTT T1 is properly programmed, switch SDP1 can be opened to disconnect the drain of CTT T1 from the drain programming voltage, causing the drain of CTT T1 to be driven to the safe voltage VDSafe, while the gate of CTT T1 is driven to a voltage below the programming threshold. Switch SDP2 is then closed to connect the drain of CTT T2 to the drain programming voltage VDP, and the gate of CTT T2 is then driven to the appropriate programming voltage VGP to induce charge trapping or detrapping as needed. This operation is then repeated for each parallel branch until all CTTs have been properly programmed.

[0048] Subsequently, for data output, the programmed memory cell 400 can operate in output mode, where the common source node can be connected to the defined source reference voltage VS via switch SSR. The gates of CTT T1 and T2 can each be connected to the bias voltage VB via corresponding switches SGR1 and SGR2, such that the same gate-source voltage VB is achieved. GS Each of the switches SDP1, SDP2, and SDCP is disconnected, thus disconnecting the drain of the CTT from both the drain programming voltage VDP and the safe drain voltage VDsafe, and allowing switch SDR to close to provide the appropriate voltage VD to allow data output from the multi-stage programmable resistor unit. Depending on the application, the applied voltage VD can be a defined read voltage, but in some applications, the applied voltage VD may depend on the data input.

[0049] Figure 6 An alternative example of a multi-level programmable resistor cell 600 formed from CTTs according to an embodiment is shown. In this example, the series connection of resistors R1 to RN is arranged between two terminals A and B of the multi-level memory cell 600, wherein CTTs T1 to TN are nested in parallel with different numbers of series-connected resistors. Again, this means that the voltage at terminal B can be controlled at a defined reference voltage, and the same gate voltage can be applied to all CTTs to achieve the same gate-source voltage V for each of the CTTs. GS .

[0050] As those skilled in the art will understand, in use, CTT can be programmed to change the total on-resistance of memory cell 3100 by different on-resistance states.

[0051] Figure 7 It shows how it can be done Figure 6 The example program CTT in nested loops, and Figure 7 In the middle, provide and such reference Figure 5 Switches and voltages with similar functionalities discussed are identified by the same labels. For clarity, Figure 7 Only two loops are shown, but it will be understood that other CTTs in additional loops can also be programmed in the same way.

[0052] As a reference Figure 5 As in the discussed examples, during programming mode, CTTs can be programmed sequentially, one by one. During CTT programming, a programming source voltage VSP is applied to the common source node, and a programming drain voltage VDP is applied to the CTT programmed by the associated switch, for example, CTT T1 via switch SDP1, or CTT T2 via switch SDP2. Figure 5As with the example, the drain of an unprogrammed CTT can be driven to a safe voltage VDsafe, for example, via switches SDS1 for CTT T1 and SDS2 for CTT T2 (but this can also cause a voltage difference to form across some fixed resistors, which can lead to current flow). The gate of a programmed CTT is connected to be driven by a suitable gate programming voltage VGP to cause charge trapping or detrapping as needed, while the gates of other CTTs can be controlled to a suitable low voltage to avoid accidental programming.

[0053] For data output, the drain of the CTT is disconnected from the drain programming voltage, the common source node is connected to the defined reference voltage VS, and the gate of the CTT is connected to the bias voltage VB to achieve the same gate-source voltage V. GS Apply to all CTTs.

[0054] exist Figure 5 and Figure 7 In each of the examples, the CTT is programmed sequentially. In some implementations, programming the CTT in a programmable mode may involve a tuning process that allows fine-tuning of the CTT's resistance settings, and thus fine-tuning of the resistance of the programmable resistor memory cell.

[0055] When setting the on-resistance state of each CTT in sequence, the programming voltage used can be adjusted to increase or decrease the charge trapping (or detrapping) of the CTT. Therefore, for example, consider the following: Figure 5 The programming of the two parallel branches shown is illustrated. The on-resistance of cell 400 can be determined, for example, by operating in output mode and applying a defined voltage VD in the initial state. CTT T1 can then be programmed to the desired resistance state of CTT, and the resistance of the cell can then be determined again. If the resistance change due to programming CTT T1 is different from the expected change, the programming voltage used to program CTT T2 can be adjusted as needed for compensation.

[0056] For example, if the measured resistance change is lower than expected due to programming of CTT T1, the programming of CTTT2 can be adjusted to increase the threshold voltage V. T The offset, and if the resistance change is greater than expected, the programming of CTT T2 can be adjusted to reduce the threshold voltage V. T The offset. This can be extended to program additional CTTs.

[0057] It should be noted that the on-resistance of each individual CTT can be monitored, rather than the on-resistance of the entire memory cell, before and after programming to determine any necessary compensation. However, since the total on-resistance of the cell is used to store the relevant data, monitoring the on-resistance of the individual cells may be the most efficient and / or most accurate method.

[0058] Generally, the CTT corresponding to each bit of a multi-level programmable resistor cell can be programmed and tuned sequentially, where the programming of each CTT in the sequence is based on adjustments to the programming of the previous CTT in order to improve the accuracy of programming the entire memory cell. Thus, the first CTT can be programmed, and the cell's resistance is measured, and the programming of the next CTT is adjusted as needed to account for any variations between the cell's actual resistance and the desired value, thereby improving the overall programming accuracy.

[0059] It will be understood that the on-resistance value of the CTT can be changed by altering the amount of captured charge and thus the resulting threshold voltage V of the CTT. T Tuning can be achieved by adjusting the gate-source voltage V applied to the CTT during output mode, but it can also be achieved by controllably changing the gate-source voltage V applied to the CTT during output mode. GS Tuning is required. However, as mentioned above, providing a tuned gate voltage for each of the CTTs increases circuit complexity, and therefore, tuning the threshold voltage during programming may be preferred. However, in some implementations, multiple different bias voltages can be selectively used as the gate voltages of the CTTs, thereby allowing at least some tuning of the resistance value of the programmed CTTs.

[0060] Another way to tune the on-resistance of each individual CTT is to change the body electrode bias of the transistor in output mode, and in some examples, the body electrode voltage applied to the body electrode of the transistor can be controlled to vary. However, controlling the body electrode voltage in this way can also increase some complexity and may introduce some nonlinear problems.

[0061] In some cases, the ability to tune the resistance of a CTT element, for example by fine-tuning the threshold voltage, can allow for a relaxation of some design constraints on the accuracy of fixed resistors, which can be beneficial in terms of circuit area and / or cost.

[0062] Typically, resistors formed as part of an integrated circuit can be made relatively large to reduce the impact of any process variations, i.e., to minimize the degree of variation between components. A given resistance value can usually be achieved using resistors of different sizes, but for larger resistors, the effect of any process variation on the resistance value is generally smaller than the effect on smaller resistors. Therefore, resistors in integrated circuits can be designed to a specific size to meet a defined tolerance in terms of resistance value.

[0063] In embodiments of this disclosure, when the CTT is arranged together with one or more fixed resistors to provide controlled resistance variation for memory cells, the ability to tune the resistance variation of the CTT can also be used to at least partially compensate for any process variations in the fixed resistors, i.e., any variation between the actual resistance value and the nominal design value. This can allow for a loosening of the performance tolerances of the fixed resistors, thereby allowing them to be smaller in size.

[0064] Therefore, the multi-level programmable resistor CTT memory cell according to the embodiments of this disclosure can be programmed to be one of at least three different resistance values ​​by programming the CTT to one of a plurality of different resistance states and tuning the programming of the CTT to achieve a desired total resistance value.

[0065] While the preceding examples were discussed in the context of CTT being connected to a resistor network and the fixed resistor being implemented by a resistor, in some examples, the functionality of the fixed resistor can alternatively be provided by using an active device instead of a resistor. For example, Figure 8a An example of a multi-level programmable resistor unit 800 is shown, which is configured to work with a reference. Figure 4 Similar approaches to the discussion include resistor networks with multiple parallel branches, but in Figure 8a In the example, each parallel branch includes CTT T1…TN connected in series with the corresponding active device M1…MN, which is controlled to provide the desired resistance value. Each of the active devices may include a suitable transistor that can be controlled to provide a suitable on-resistance.

[0066] The active devices M1 to MN can be implemented as conventional (non-charge-trapping) transistors, in which case the gate of each transistor M1 to MN can be biased via corresponding bias voltages VR1 to VRN. However, in some examples, the active devices M1 to MN themselves can be implemented using CTTs programmed to provide the desired on-resistance. Therefore, the parallel branches can include two CTTs connected in series. Advantageously, these two CTTs can include a p-channel CTT and an n-channel CTT, for example, a PMOS CTT and an NMOS CTT, connected together via their drains. In this way, the source elements of the NMOS CTTs in different branches can be connected to a common NMOS source node on one side of the parallel branch, while the source elements of the PMOS CTTs in different branches can be connected to a common PMOS source node on the other side of the parallel branch, thereby allowing a first gate voltage to be applied to all PMOS CTTs to provide a constant gate-source voltage, and a second gate voltage to be applied to all NMOS CTTs to provide a constant gate-source voltage. In some cases, the first gate voltage of a PMOS CTT can be the same as the source voltage of an NMOS CTT, while the second gate voltage of an NMOS CTT can be the same as the source voltage of a PMOS CTT, such as... Figure 8b As shown in the diagram, this illustration depicts only one of a parallel branch implemented using a PMOS CTT and an NMOS CTT (connected in series via their drains). This arrangement provides a compact, self-biased structure where the gates of the CTTs do not require external bias. In use, one of the CTTs can be programmed to provide a fixed on-resistance value that appropriately weights the parallel branch and does not change during use, i.e., it does not change in the memory cell's programming mode, while the other CTT can be (re)programmed in programming mode to store data. However, in some cases, both CTTs can be programmed in programming mode to provide the desired resistance for the branch.

[0067] In some cases, depending on the resistance coefficient, the resistance of a multi-stage programmable resistor unit may not change monotonically with the programming code. For example, consider a reference... Figure 4 The multi-stage programmable resistor cell described herein has four parallel branches, each including a current-limiting time (CTT). If each of the four different CTTs can be programmed to either a high on-resistance state (HI) or a low on-resistance state (LO), then sixteen different code words are available for programming the multi-stage resistor cell. However, for some implementations, the sequence of code words may not monotonically change with the on-resistance of the memory cell. Figure 9aA graph is shown illustrating how the on-resistance of an example cell can vary non-monotonicly with a programming codeword. In this case, the sequence of programming codewords can be effectively reordered to provide a monotonic variation in on-resistance. Figure 9b The reordered code sequence is shown, corresponding to the programming code sequence {1,2,3,5,9,4,6,10,7,11,13,8,12,14,15,16}. Therefore, in use, the input code for requesting a specific on-resistance value can be translated into the relevant programming code that provides the correct value.

[0068] The above example is based on the following: each of the CTTs is programmed to be programmable between two or more different on-resistance states (for a defined gate-source voltage V). GS Each of the CTTs is designed and controlled to exhibit the same resistance state and have the same nominal resistance change between corresponding on-resistance states. R (affected by any variations implemented as part of the tuning of the programmed resistance unit). That is, each of the CTTs is implemented such that the resistance change between any two equivalent on-resistance states... R is essentially the same for each of the CTTs. For example, for a CTT controlled to vary between only two different on-resistance states, HI and LO, the resistance variation between the HI resistance state and the LO resistance state is... R is the same for each of the CTTs.

[0069] However, in some applications, at least some CTTs can be implemented to provide different nominal on-resistance changes to each other when switching between different on-resistance states, i.e., providing different on-resistance values ​​to each other. R value.

[0070] From the drain-source resistance R DS The equation will again show that the resistance of CTT depends on the gate-source voltage V. GS Threshold voltage V T Compared to the W / L ratio of the CTT. Additionally, it will be understood that biasing the body electrode of the CTT can also alter the baseline threshold voltage (in the absence of any trapped charge) via the body electrode effect. In some cases, one or more of these parameters can be varied to provide different values ​​for different CTTs. R value.

[0071] The gate-source voltage V can be varied by applying different bias voltages to the gate and / or source connections of one or more CTTs. GSFor example, a first group of one or more CTTs can be operated with a first gate-source voltage for readout, and a second group of one or more CTTs can be operated with a second different gate-source voltage. At least one of the gate voltage and source voltage of the first group will be different from the second group. Alternatively, different CTTs can be programmed to have a threshold voltage V. T The significant difference lies in the change of V between the continuous resistance states of CTT, i.e., by altering the amount of trapped charge. T Step size. Alternatively, at least some CTTs can be subjected to different body electrode bias voltages to change the baseline threshold voltage via the body electrode effect. For example, some CTTs can connect their body electrodes to the source electrodes, while other CTTs can bias their body electrodes with different bias voltages.

[0072] However, in some examples, at least some CTTs can be implemented with different W / L ratios from one another. Figure 10 An example of a programmable resistor unit 1000 is shown, comprising a first CTT T1 and a second CTT T2 connected in parallel, wherein the channel width W of the first CTT T1 is equal to its length L by a first ratio, and the channel width W of the second CTT T1 is equal to its length L by a second different ratio. The resistance variation between these ratios is related to (W / L). V T Inversely proportional, among which V T It is the threshold voltage change between any two on-resistance states. Therefore, if the W / L ratio of the first CTT T1 is twice the W / L ratio of the first CTT T2, then under the same threshold voltage change, the resistance change of the first CTT T1 is... R will be the resistance change of the second CTT T2. Half of R.

[0073] Therefore, in general, a multi-level programmable resistor cell using CTTs can comprise a resistor network between two terminals, which may be referred to as a first resistor node and a second resistor node. The resistor network comprises multiple CTTs, and in at least some examples, the CTTs can be arranged as part of a resistor network having one or more fixed resistors to implement a weighted bit portion of the memory cell, and / or having controlled active devices to provide the desired resistance. By changing the charge trapped by the CTTs, the CTTs can be programmed to any of a plurality of discrete resistance states, and the programmed cell can be used for data output by driving all CTTs with a defined gate-source voltage, in some cases which may be substantially the same as at least a first set of gate-source voltages used for two or more of the CTTs.

[0074] The use of CTT's multi-level programmable resistor cells according to embodiments of this disclosure can be used in any application that may require the ability to program circuit elements to hold any of a plurality of different resistance values ​​without the application of power. For example, CTT's multi-level programmable resistor cells can be used as part of an analog computing circuit, such as as part of a multiply-accumulate circuit.

[0075] Figure 11 An example of an analog multiply-accumulate circuit using a memory cell is shown according to an embodiment of the present disclosure. Figure 11 A first memory cell 1101a and a second memory cell 1101b are shown. Each memory cell can be implemented by any of the memory cells discussed herein, but it will be understood that additional memory cells may also be provided.

[0076] Terminal A of the first memory cell 1101a is connected to a first data input to receive a first data voltage VD1, and terminal B is connected to a data output. Terminal A of the second memory cell 1101b is connected to a second data input to receive a second data voltage VD1, and terminal B of the second memory cell 1101b is connected to the same data output. In use, the first memory cell 1101a and the second memory cell 1101b are each programmed to a desired resistance state to represent the corresponding stored value, such as a weight value. In this example, the stored value corresponds to the conductance of the memory cell. In use, the first data voltage VD1 and the second data voltage VD2 are controlled based on some input data, and the voltage at the output is maintained at a defined reference value VS. This results in a data-dependent voltage being generated across each memory cell, which generates corresponding currents I1 and I2, which are the product of the stored weight value and the input data (plus some offset current due to the minimum on-resistance of the memory cell). These currents are combined to form a combined current Icom, which is equal to the sum of I1 and I2. The combined current or its mirror version can then be further processed as needed.

[0077] Those skilled in the art will understand that Figure 11 A relatively simplified multiply-accumulate arrangement is shown, and more complex implementations can be provided, such as to eliminate offset current, provide linearization, and / or provide differential operation. It will also be understood that alternative arrangements can supply data in the form of current, and the output can be in the form of a synthesized voltage.

[0078] In some applications, CTT's multi-level programmable resistor units can be implemented as multi-bit digital memory units. Figure 12Two examples of how such a memory cell 1201 can be arranged for reading are shown. The memory cell 1201 may include a multi-level programmable resistor unit, such as the multi-level programmable resistor unit discussed with reference to any of the embodiments discussed above. As discussed above, the memory cell 1201 can be programmed to store multi-bit data values. To read the stored data from the memory cell 1201, the memory cell 1201 will operate in a data output mode, and a defined current from the current source 1202 will be driven into terminal A of the memory cell, such as... Figure 12 As shown on the left, memory cell 1201 can be arranged as part of a voltage divider with fixed resistor 1203, such as Figure 12 As shown on the right. In either case, the other side of the memory cell (i.e., terminal B) can be connected to a defined reference voltage (such as ground), which can provide a defined reference voltage for the common source node. The resulting voltage at terminal A of the memory cell (which depends on the resistance value stored in the memory cell) can be determined by the ADC 1204. In implementations with multiple memory cells (not shown), the ADC 1204 can be multiplexed among the different memory cells to provide sequential reads from the memory cells, and in some cases, as those skilled in the art will understand, individual memory cells can be addressed via bit lines and word lines.

[0079] Therefore, generally speaking, some embodiments relate to a programmable resistor element comprising a plurality of programmable resistor memory assemblies arranged in combination between a first terminal and a second terminal of the multi-level element to define a plurality of programmable portions, wherein each programmable portion includes one or more of the programmable resistor memories, the programmable resistor memories being configured such that each programmable portion can be individually programmed to a selected resistance state among at least two different resistance states, and wherein the plurality of programmable portions can be combined and programmed to provide a selected total resistance value among two or more total resistance values ​​between the first terminal and the second terminal.

[0080] This invention is not limited to the embodiments described herein, and modifications or adjustments can be made without departing from the scope of this invention.

Claims

1. A multi-level programmable resistive memory cell, comprising: First resistor node and second resistor node; as well as A programmable resistor network connected between a first resistor node and a second resistor node, wherein the programmable resistor network includes a first plurality of charge trapping transistors; The multi-level programmable resistor memory cell can operate in the following modes: A programming mode for selectively programming each of the first plurality of charge trapping transistors to a selected on-resistance state by programming the amount of charge trapped in the charge trapping transistors. as well as Output mode, wherein each of the first plurality of charge trapping transistors is driven by a corresponding gate-source voltage; The multi-level programmable resistor memory cell is configured such that, by programming the first plurality of charge trapping transistors in the programming mode, the cell resistance between the first resistor terminal and the second resistor terminal in the output mode can be selectively changed among at least three different resistance values.

2. The multilevel programmable resistive memory cell of claim 1, wherein the resistive network is configured such that each of the first plurality of charge-trapping transistors is configured as part of a corresponding weighted bit portion of the multilevel programmable resistive memory cell, such that programming the charge-trapping transistors programs the corresponding weighted bit of the multilevel programmable resistive memory cell.

3. The multi-level programmable resistive memory cell of claim 1 or 2, wherein for a first group of two or more charge-trapping transistors in the first plurality of charge-trapping transistors, each of the charge-trapping transistors in the first group has a source electrode connected to a common source node.

4. The multi-level programmable resistive memory cell of claim 3, wherein the first group comprises all of the first plurality of charge trapping transistors.

5. The multilevel programmable resistive memory cell of claim 3 or 4, wherein the multilevel programmable resistive memory cell is configured such that, in the output mode, the gate electrode of each of the first plurality of charge trapping transistors in the first group is connected to a common bias voltage.

6. The multi-level programmable resistive memory cell of any one of claims 1 to 5, wherein each of the first plurality of charge-trapping transistors is arranged in a corresponding parallel branch of a plurality of parallel branches of the resistive network.

7. The multi-level programmable resistor memory cell of claim 6, wherein one or more of the parallel branches of the resistor network include a fixed resistor connected in series with the charge trapping transistor, wherein the resistance value of the fixed resistor is different in the different parallel branches.

8. The multi-level programmable resistive memory cell of claim 7, wherein for each of the one or more parallel branches in the parallel branches of the resistive network, a fixed resistor is included in series with the charge trapping transistor, the fixed resistor being connected to the drain electrode of the charge trapping transistor.

9. The multi-level programmable resistive memory cell of any one of claims 6 to 8, wherein one or more of the parallel branches of the resistive network include active resistive elements configured to provide an on-resistance value with respect to the charge trapping transistor string, wherein the active resistive element includes a transistor.

10. The multi-level programmable resistive memory cell of claim 9, wherein the active resistive element comprises a charge trapping transistor in a second plurality of charge trapping transistors.

11. The multi-level programmable resistive memory cell of claim 10, wherein: The first plurality of charge-trapping transistors include n-channel transistors, while the second plurality of charge-trapping transistors include p-channel transistors, and vice versa; and In one or more parallel branches, the drain of the charge trapping transistor in the first plurality of charge trapping transistors is connected to the drain of the charge trapping transistor in the second plurality of charge trapping transistors.

12. The multi-level programmable resistive memory cell of claim 11, wherein: The gate of the charge-trapping transistor in the first plurality of charge-trapping transistors is connected to the source voltage of the charge-trapping transistor in the second plurality of charge-trapping transistors; and The gate of the charge trapping transistor in the second plurality of charge trapping transistors is connected to the source voltage of the charge trapping transistor in the first plurality of charge trapping transistors.

13. The multi-level programmable resistive memory cell of any one of claims 1 to 8, wherein the resistive network comprises a plurality of series-connected fixed resistors, and wherein each of the plurality of charge-trapping transistors is connected in parallel with a different number of the series-connected fixed resistors.

14. The multilevel programmable resistive memory cell of any one of claims 1 to 13, wherein the multilevel programmable resistive memory cell is configured such that at least some of the first plurality of charge trapping transistors in the output node are driven by gate-source voltages that are different from each other.

15. The multilevel programmable resistive memory cell of any one of claims 1 to 14, wherein the multilevel programmable resistive memory cell is configured such that at least some of the first plurality of charge trapping transistors are configured to have channel length to channel width ratios that are different from each other.

16. The multilevel programmable resistive memory cell of any one of claims 1 to 15, wherein the multilevel programmable resistive memory cell is configured such that at least some of the charge trapping transistors are configured to have different body electrode bias voltages from each other.

17. The multilevel programmable resistive memory cell of any one of claims 1 to 16, wherein the multilevel programmable resistive memory cell is configured to program the first plurality of charge trapping transistors in a sequential process.

18. The multilevel programmable resistor memory cell of claim 17, wherein the multilevel programmable resistor memory cell is configured such that, in the programming mode, after programming each charge trapping transistor in the sequential flow, an on-resistance value of the multilevel programmable resistor memory cell is determined, and wherein programming subsequent charge trapping transistors in the sequential flow is controlled to compensate for any inaccuracies in the determined on-resistance value of the multilevel programmable resistor memory cell.

19. The multi-level programmable resistive memory cell of claim 18, wherein the multi-level programmable resistive memory cell is configured to determine a change in on-resistance after programming each charge-trapping transistor, and control the programming of subsequent charge-trapping transistors in the said sequential flow to: If the determined resistance change is lower than expected, then the threshold voltage offset of the subsequent charge trapping transistor is increased; and If the determined resistance change is greater than expected, then the threshold voltage offset of the subsequent charge trapping transistor is reduced.

20. An analog computing circuit comprising a multi-level programmable resistive memory cell as claimed in any one of claims 1 to 19.

21. A digital memory comprising a multi-level programmable resistive memory cell as claimed in any one of claims 1 to 19.

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