Accelerated programming of quadgate split gate flash memory cells

Abstract

A method for programming a memory device including control gate lines, erase gate lines, select gate lines, source lines, and bit lines connected to rows and columns of memory cells, the method comprising: performing an erase operation including applying a first voltage to one of the erase gate lines; performing a pre-programming operation including electrically connecting one of the erase gate lines to a pair of control gate lines to pre-charge the pair of control gate lines using positive charge on one of the erase gate lines from the erase operation; and performing a programming operation including applying a second voltage to one of the erase gate lines and the pair of control gate lines.

Description

Related applications

[0001] This application claims the benefit of U.S. Provisional Application No. 63 / 607,409, filed December 7, 2023, and U.S. Patent Application No. 18 / 594,492, filed March 4, 2024. Technical Field

[0002] This invention relates to non-volatile memory arrays. Background Technology

[0003] Split-gate nonvolatile memory devices are well known in the art. See, for example, U.S. Patent 7,868,375, which discloses a four-gate memory cell configuration and is incorporated herein by reference for all purposes. Specifically, this disclosure… Figure 1 An example is illustrated of a pair of 11-split-gate memory cells 10, each having a spaced-apart source region 14 and a drain region 16 formed in a silicon semiconductor substrate 12. The source region 14 may be referred to as a source line SL (because it is typically connected to other source regions of other memory cells in the same row or column), and the drain region 16 is typically connected to a bit line. A channel region 18 of the substrate 12 extends between the source / drain regions 14 / 16. A floating gate 20 is disposed above a first portion of the channel region 18 (i.e., vertically disposed above and laterally overlapping it) and is insulated from (and directly controls) the conductivity of the first portion (and is partially located above and insulated from) the source region 14). A control gate 22 is disposed above and insulated from the floating gate 20. A select gate 24 (also referred to as a word line gate) is disposed above and insulated from (and directly controls) the conductivity of a second portion of the channel region 18. An erase gate 26 is disposed above and insulated from the source region 14 and is laterally adjacent to the floating gate 20. The erase gate 26 may include a notch facing the edge of the floating gate 20.

[0004] Multiple such memory cells 10 can be arranged in rows and columns to form a memory cell array, such as Figure 2 exemplified. Although Figure 1 Only one pair of 11 memory cells 10 is shown (sharing a common source region 14 and an erase gate 26), but the memory cell pairs can be arranged end-to-end to form a row of memory cells (where adjacent memory cell pairs can share a common drain region). Although in Figure 2Only two such columns are shown, but many such columns can exist. Each column may include a bit line 16a electrically connecting all drain regions 16 in that column. Each row of memory cells may include a control gate line 22a electrically connecting all control gates 22 in that row of memory cells. For example, all control gates 22 in each row of memory cells may be formed as a continuous line of conductive material, wherein a portion of the continuous line passing through any given memory cell serves as its control gate 22. Each row of memory cells may include a select gate line 24a electrically connecting all select gates 24 in that row of memory cells. For example, all select gates 24 in each row of memory cells may be formed as a continuous line of conductive material, wherein a portion of the continuous line passing through any given memory cell serves as its select gate 24. Each row of memory cells may include an erase gate line 26a electrically connecting all erase gates 26 in that row of memory cells. For example, all erase gates 26 in each row of memory cells may be formed as a continuous line of conductive material, wherein a portion of the continuous line passing through any given memory cell pair serves as its erase gate 26. Finally, each row of memory cell pairs may include a source line 14a that electrically connects all source regions 14 together in that row of memory cell pairs. For example, all source regions 14 in each row of memory cell pairs may be formed as a continuous line of conductive diffusion in the substrate 12, wherein a portion of the continuous line passing through any given memory cell pair serves as its source region 14.

[0005] Various combinations of voltages are applied to the control gate 22, select gate 24, erase gate 26, and source region 14 / drain region 16 to program the split-gate memory cell 10 (i.e., inject electrons into the floating gate 20), erase the split-gate memory cell 10 (i.e., remove electrons from the floating gate 20), and read the split-gate memory cell 10 (i.e., measure or detect the conductivity of the channel region 18 by, for example, measuring or detecting the read current through the channel region 18 to determine the programming state of the floating gate 20).

[0006] The split-gate memory cell 10 can be operated digitally, wherein the split-gate memory cell 10 is configured to only one of two possible states: a programming state and an erase state. The split-gate memory cell 10 is erased by applying a high positive voltage to the erase gate 26 and optionally a negative voltage to the control gate 22, causing electrons to tunnel from the floating gate 20 to the erase gate 26 (putting the floating gate 20 in a more positively charged state – the erase state). The split-gate memory cell 10 can be programmed by applying positive voltages to the control gate 22, the erase gate 26, the select gate 24, and the source region 14, and by applying current to the drain region 16. Electrons then flow along the channel region 18 from the drain region 16 to the source region 14, where the electrons become accelerated and heated, thereby some of them being injected into the floating gate 20 via hot electron injection (putting the floating gate 20 in a more negatively charged state – the programming state).

[0007] The split-gate memory cell 10 can be read by applying a positive voltage to the select gate 24 (which conducts a portion of the channel region 18 below the select gate 24 by making it conductive) and the drain region 16 (and optionally to the erase gate 26 and / or the control gate 22) and sensing the current flowing through the channel region 18. If the floating gate 20 is positively charged (i.e., the split-gate memory cell 10 is erased), the split-gate memory cell 10 will be turned on because both portions of the channel region 18 are conductive due to the lack of electrons on the floating gate 20, and current will flow from the drain region 16 to the source region 14 (i.e., the split-gate memory cell 10 is sensed to be in its erase "1" state based on the sensed current flow). If the floating gate 20 is negatively charged (i.e., the split-gate memory cell 10 is programmed), a portion of the channel region 18 below the floating gate is turned off (low conductivity), thereby preventing significant current flow (i.e., the split-gate memory cell 10 is sensed to be in its programmed "0" state based on no or minimal current flow). Memory cells 10 are considered non-volatile because they retain their logical (programmed) state even when no power is applied to the semiconductor device.

[0008] The split-gate memory cell 10 may alternatively operate in an analog manner, wherein the memory state of the split-gate memory cell 10 (i.e., the amount of charge on the floating gate 20, such as the number of electrons) can be incrementally changed anywhere from a fully erased state (the minimum number of electrons on the floating gate 20) to a fully programmed state (the maximum number of electrons on the floating gate 20), or only a portion of that range. This means that the storage of the split-gate memory cell 10 is analog, which allows for very precise and individual tuning of each split-gate memory cell 10 in the array of split-gate memory cells 10. Alternatively, the split-gate memory cell 10 may operate as an MLC (multilevel cell), wherein it is configured to be programmed to one of many discrete values ​​(such as 16 or 64 different values).

[0009] Typically, memory cells are programmed immediately after being erased. This means that the memory cell transitions from a high voltage applied to its erase gate (for removing electrons from the floating gate) to a lower programming voltage applied to the control gate 22, select gate 24, erase gate 26, and source region 14 of the selected memory cell (for adding electrons to the floating gate). This transition can be relatively time-consuming and power-intensive.

[0010] There is a need for a technology that reduces the time and power required to transition from an erase operation to a programming operation. Summary of the Invention

[0011] The aforementioned problems and needs are addressed by a method for programming a memory device including control gate lines, erase gate lines, select gate lines, source lines, and bit lines connected to rows and columns of memory cells. The method includes: performing an erase operation comprising applying a first voltage to one of the erase gate lines; performing a pre-programming operation comprising electrically connecting one of the erase gate lines to a pair of control gate lines to pre-charge the control gate line pair using positive charge from the erase operation on one of the erase gate lines; and performing a programming operation comprising applying a second voltage to one of the erase gate lines and the pair of control gate lines.

[0012] A memory device includes: memory cells arranged in rows and columns, wherein each memory cell includes a source region, a drain region, a floating gate, a control gate, a select gate, and an erase gate; a first control gate line electrically connecting the control gates of a first row of memory cells together; a second control gate line electrically connecting the control gates of a second row of memory cells together, wherein the first control gate line is electrically connected to the second control gate line; an erase gate line electrically connecting the erase gates of the first row of memory cells and the second row of memory cells together; a source line electrically connecting the source regions of the first row of memory cells and the second row of memory cells together; a charge pump; a first switch configured to connect the charge pump to the erase gate line in an on state and to disconnect the charge pump from the erase gate line in an off state; a second switch configured to connect the erase gate line to the first control gate line and the second control gate line in an on state and to disconnect the erase gate line from the first control gate line and the second control gate line in an off state. The system includes: a second control gate line disconnection; a third switch, configured to electrically connect the first and second control gate lines to a reference potential in its on state and disconnect the first and second control gate lines from the reference potential in its off state; and a control circuit configured to: perform an erase operation comprising placing the first switch in its on state, placing the second switch in its off state, placing the third switch in its on state, and causing a charge pump to generate a first voltage to be applied from the charge pump to the erase gate line; perform a pre-programming operation comprising placing the second switch in its on state to pre-charge the first and second control gate lines with positive charge from the erase operation on the erase gate line; and perform a programming operation comprising placing the first switch in its on state, placing the second switch in its on state, and causing a charge pump to generate a second voltage to be applied from the charge pump to the erase gate line and to the first and second control gate lines.

[0013] Other objects and features of this disclosure will become apparent from a review of the specification, claims and drawings. Attached Figure Description

[0014] Figure 1 This is a cross-sectional view of a conventional memory cell.

[0015] Figure 2 This is a schematic diagram illustrating a conventional memory array architecture.

[0016] Figure 3 This is a schematic diagram illustrating an example of a memory array architecture.

[0017] Figure 4It is shown in Figure 3 The table provides a first example of the operation of the switches during the operation of different memory cells in the memory array architecture.

[0018] Figure 5 It is shown in Figure 3 The table provides a second example of the operation of the switches during different memory cell operations in the memory array architecture.

[0019] Figure 6 This is a schematic diagram illustrating the architecture of an example memory device. Detailed Implementation

[0020] Methods and apparatus for converting erase operations into programming operations are disclosed. Figure 1 The memory cell of the type shown is row- and column-oriented and is associated with, for example, a memory cell of the type shown. Figure 2 The various line connections shown. The method and apparatus relate to, for example... Figure 3 The line configuration shown is as follows. Figure 3 The diagram shows a line configuration for only one row of the memory cells in row 11 of memory cell 10 (i.e., a first select gate line 24a1 and a second select gate line 24a2 (a pair of select gate lines), wherein the first select gate line 24a1 electrically connects the select gates in the first row of memory cells of memory cell 10 together, and the second select gate line 24a2 electrically connects the select gates in the second row of memory cells of memory cell 10 together; a first control gate line 22a1 and a second control gate line 22a2 (a pair of control gate lines), wherein the first control gate line 22a1 electrically connects the control gates in the first row of memory cells of memory cell 10 together, and the second control gate line 22a2 electrically connects the control gates in the second row of memory cells of memory cell 10 together; a source line 14a and an erase gate line 26a, all extending in the row direction; and a bit line 16a, all extending in the column direction). Figure 3 The configuration of the lines in the middle is similar to Figure 2The configuration of the lines is different, but with the following differences. A pair of control gate lines (first control gate line 22a1 and second control gate line 22a2) are electrically connected together. A first switch KI alternately connects and disconnects the charge pump 30 and the erase gate line 26a. The charge pump 30 supplies different voltages during erase operations (e.g., Vers), pre-programming operations (e.g., Vpre-pgm), and programming operations (e.g., Vpgm), which will be described in more detail below. A second switch K2 alternately connects and disconnects the erase gate line 26a from the first control gate line 22a1 and the second control gate line 22a2. A third switch K3 alternately connects and disconnects the first control gate line 22a1 and the second control gate line 22a2 from a reference potential RP (e.g., ground Gnd). Each switch has an ON (on) state and an OFF (off) state. In the ON state, the switch is conductive (i.e., the switch is closed and electrically connects the corresponding wires / components together), and in the OFF state, the switch is non-conductive (i.e., the switch is open and does not electrically connect the corresponding wires / components together—the corresponding wires / components are disconnected from each other). As used herein, placing a switch in a specific state includes changing the state of the switch (from another state) to that specific state, and maintaining the switch in that specific state if it was previously in that specific state. Switches K1-K3 can be implemented in any convenient location.

[0021] Figure 4 The switch configurations for erase, pre-programming, programming, and programming end operations are summarized. During an erase operation (which erases all memory cells in a row of memory cell pair 11 sharing erase gate line 26a), charge pump 30 provides a high erase voltage Vers (first voltage) while first switch K1 and third switch K3 are turned on, and second switch K2 is turned off. This results in the erase voltage Vers being applied only to erase gate line 26a, while first control gate line 22a1 and second control gate line 22a2 are electrically connected to reference potential RP. To protect the application of erase voltage Vers during the erase operation, second switch K2 can be turned off and third switch K3 can be turned on before first switch K1 is turned on. Select gate lines 24a1 and 24a2 and source line 14a can also be connected to reference potential RP during the erase operation (switches connecting select gate lines 24a1 and 24a2 and source line 14a to reference potential RP are not shown). When the erasure operation is completed (erasure ends), the first switch K1 and the third switch K3 can be turned off.

[0022] Then, in the pre-programming operation following the erase operation, the second switch K2 is turned on, while the first switch K1 and the third switch K3 remain off, wherein the erase gate line 26a is electrically connected to the first control gate line 22a1 and the second control gate line 22a2. This is used to precharge the first control gate line 22a1 and the second control gate line 22a2 with the positive charge stored on the erase gate line 26a from the previous erase operation, and to also precharge the erase gate line 26a. It has been determined that the final voltage on the erase gate line 26a and the first control gate line 22a1 and the second control gate line 22a2 can be between one-third and one-half of the erase voltage Vers applied to the erase gate line 26a during the earlier erase operation.

[0023] Then, in the programming operation following the pre-programming operation (which programs the selected memory cell by injecting electrons into the floating gate of the selected memory cell (target memory cell) within the memory cell), charge pump 30 provides a programming voltage Vpgm (a second voltage), while the first switch K1 and the second switch K2 are in their on state, and the third switch K3 is in its off state. This results in the application of the programming voltage Vpgm to the erase gate line 26a and the first control gate line 22a1 and the second control gate line 22a2. While the programming voltage Vpgm is applied to the erase gate line 26a and the first control gate line 22a1 and the second control gate line 22a2, other positive programming voltages are applied from other voltage sources (i.e., one or more other charge pumps) to the select gate lines 24a1, 24a2 and the source line 14a of the target memory cell, and current is supplied to the bit line 16a of the target memory cell, thereby programming the target memory cell. Instead of raising these lines from a zero-voltage state to the programming voltage Vpgm, the transition time and power consumption are reduced by raising the voltage on the erase gate line 26a, the first control gate line 22a1, and the second control gate line 22a2 from the voltage achieved during the pre-programming operation to the programming voltage Vpgm during the programming operation. Power and energy consumption are also reduced because the charge pump 30 can remain off during the pre-programming operation.

[0024] After the programming operation is completed, a programming termination operation can be performed, in which the second switch K2 and the third switch K3 can be turned on, while the first switch K1 is turned off. This will erase the gate line 26a and the first control gate line 22a1 and the second control gate line 22a2, which are electrically connected to the reference potential RP, thereby discharging these lines.

[0025] Figure 5 Another example is shown, which is similar to Figure 4The example is illustrated, but the first switch K1 can be in its on state during the pre-programming operation. If the floating potential on the erase gate line 26a and the first control gate line 22a1 and the second control gate line 22a2 (generated by the positive charge stored on the erase gate line 26a from the previous erase operation) is too low or lasts too long (e.g., due to leakage), the charge pump 30 can be turned on to generate the pre-programming voltage Vpre-pgm (a third voltage), wherein the first switch K1 is additionally in its on state during the pre-programming operation so as to further charge the erase gate line 26a and the first control gate line 22a1 and the second control gate line 22a2 as needed during the pre-programming operation.

[0026] While the examples above illustrate a switching configuration for a single row in memory cell pair 11 (which comprises two rows of memory cells 10), it should be understood that these examples can be implemented in other or all rows of memory cell pair 11 in a memory array. The programming techniques described above offer several advantages. The resulting memory device exhibits higher performance, with reduced time required to program data. The device consumes less power than first discharging the erase gate line to a reference potential RP (such as ground) after an erase operation and then performing the programming operation, by utilizing the charge stored on the erase gate line after the erase operation to precharge the control gate line for programming.

[0027] Figure 6 An example memory device architecture is illustrated. The memory device includes an array 50 of non-volatile memory cells 10, which can be divided into two separate planes (plane A 52a and plane B 52b). The memory cells 10 can be... Figure 1 The type of memory cell shown is formed on a single chip and arranged in multiple rows and columns in a semiconductor substrate 12, such as... Figure 2 The depicted and included Figure 3The switches K1-K3 are shown. Adjacent to the non-volatile memory cell array are address decoders, such as a low-voltage LV row decoder 54 (e.g., XDEC), a source line driver 56 (e.g., SLDRV), a column decoder 58 (e.g., YMUX), a high-voltage row decoder 60 (e.g., HVDEC), and a bit line controller 62 (e.g., BLINHCTL), which decode addresses and supply various voltages to the gates and regions of the various memory cells during read, program, and erase operations of the selected memory cells. The column decoder 58 includes a sense amplifier containing circuitry for measuring the current on the bit lines during read operations. Control circuitry 66 controls various device elements to perform each operation (programming, erasing, read) on the target memory cell, including the aforementioned peripheral circuitry and switches K1-K3, to provide signals on various lines. As a non-limiting example, switches K1-K3 may be included as part of the high-voltage row decoder 60. The charge pump CHRGPMP 64 provides various voltages for reading, programming, and erasing memory cells under the control of the control circuit 66, and includes the charge pump 30. The control circuit 66 operates the memory device to program, erase, and read memory cells 10.

[0028] It should be understood that this disclosure is not limited to the examples above and illustrated herein, but covers any and all variations within the scope of any claim. For example, while the above examples relate to a four-gate memory cell and the control gate line is charged from the erase gate line after an erase operation, the above configuration and techniques can be used with memory cells having different gate and line configurations, wherein the line used to erase the memory cell can be used to charge different lines used for subsequent programming. References to this disclosure or the invention or examples herein are not intended to limit the scope of any claim or claim terminology, but only to refer to one or more features that may be covered by one or more claims. The materials, processes, and values ​​described above are merely examples and should not be construed as limiting the claims. Finally, as used herein, the terms “forming” and “formed” should include material deposition, material growth, or any other technique used to provide the disclosed or claimed material.

[0029] It should be noted that, as used herein, the terms “above” and “on” inclusively include “directly on” (without intermediate material, elements, or spaces between) and “indirectly on” (with intermediate material, elements, or spaces between). Similarly, the term “adjacent” includes “directly adjacent” (without intermediate material, elements, or spaces between) and “indirectly adjacent” (with intermediate material, elements, or spaces between), “mounted to” includes “directly mounted to” (without intermediate material, elements, or spaces between) and “indirectly mounted to” (with intermediate material, elements, or spaces between), and “electrically coupled to” includes “directly electrically coupled to” (without intermediate material or elements electrically connecting the elements together) and “indirectly electrically coupled to” (with intermediate material or elements electrically connecting the elements together). For example, forming an element “above a substrate” can include forming the element directly on the substrate without intermediate material / elements between them, and forming the element indirectly on the substrate with one or more intermediate materials / elements between them.

Claims

1. A method for programming a memory device, the memory device including control gate lines, erase gate lines, select gate lines, source lines, and bit lines connected to rows and columns of memory cells, the method comprising: Perform an erase operation, the erase operation including applying a first voltage to one of the erase gate lines; Perform a pre-programming operation, the pre-programming operation including electrically connecting one of the erase gate lines to a pair of control gate lines to pre-charge the pair of control gate lines using the positive charge on the one of the erase gate lines from the erase operation; as well as Perform a programming operation, the programming operation including applying a second voltage to one of the erase gate lines and the pair of control gate lines.

2. The method according to claim 1, wherein the method comprises: During the erase operation, the pair of control gate lines are electrically connected to a reference potential.

3. The method according to claim 2, wherein the method comprises: During the erase operation, a pair of select gate lines are electrically connected to the reference potential.

4. The method of claim 3, wherein the reference potential is ground.

5. The method according to claim 1, wherein the method comprises: During the preprogramming operation, a positive voltage is applied to one of the select gate lines, a positive voltage is applied to one of the source lines, and a current is applied to one of the bit lines.

6. The method according to claim 1, wherein the method comprises: During the programming operation, a positive voltage is applied to one of the select gate lines, a positive voltage is applied to one of the source lines, and a current is applied to one of the bit lines.

7. The method according to claim 1, wherein the method comprises: After the programming operation, one of the pair of control gate lines and the erase gate line is electrically connected to a reference potential.

8. The method of claim 7, wherein the reference potential is ground.

9. The method according to claim 1, wherein the method comprises: During the pre-programming operation, a third voltage is applied to one of the erase gate lines and the pair of control gate lines.

10. A memory device, the memory device comprising: The memory cells are arranged in rows and columns, wherein each memory cell includes a source region, a drain region, a floating gate, a control gate, a select gate, and an erase gate; A first control gate line electrically connects the control gates in the first row memory cells of the memory cell together. A second control gate line electrically connects the control gates in the second row of memory cells of the memory cell together, wherein the first control gate line is electrically connected to the second control gate line; Erasure gate line, the erase gate line electrically connects the erase gates in the first row memory cell and the second row memory cell of the memory cell together; Source line, the source line electrically connects the source regions in the first row memory cell and the second row memory cell of the memory cell together; Charge pump; A first switch connects the charge pump to the erase gate line in its on state and disconnects the charge pump from the erase gate line in its off state. A second switch, in its on state, electrically connects the erase gate line to the first control gate line and the second control gate line, and in its off state, disconnects the erase gate line from the first control gate line and the second control gate line. A third switch, wherein in its on state, the first control gate line and the second control gate line are electrically connected to the reference potential, and in its off state, the first control gate line and the second control gate line are disconnected from the reference potential; as well as Control circuit, the control circuit being used for: Perform an erase operation, the erase operation including setting the first switch to its on state, setting the second switch to its off state, setting the third switch to its on state, and causing the charge pump to generate a first voltage so as to apply the first voltage from the charge pump to the erase gate line; Perform a pre-programming operation, the pre-programming operation including placing the second switch in its on state so that the positive charge from the erase operation on the erase gate line pre-charges the first control gate line and the second control gate line. as well as Perform a programming operation, the programming operation including setting the first switch to its on state, setting the second switch to its on state, and causing the charge pump to generate a second voltage so as to apply the second voltage from the charge pump to the erase gate line and the first control gate line and the second control gate line.

11. The memory device of claim 10, wherein during the erase operation, the control circuitry is configured to place the second switch in its off state and the third switch in its on state, and then place the first switch in its on state.

12. The memory device of claim 10, wherein after the erase operation and before the pre-programming operation, the control circuitry is configured to place the first switch in its off state and the third switch in its off state.

13. The memory device of claim 10, wherein the memory device comprises: A first select gate line electrically connects the select gates in the first row memory cell of the memory cell together; as well as The second select gate line electrically connects the select gates in the second row of memory cells of the memory cell together; During the pre-programming operation, the control circuit applies a positive voltage to the first selected gate line and the second selected gate line, and applies a positive voltage to the source line.

14. The memory device of claim 10, wherein during the pre-programming operation, the control circuitry is configured to place the first switch in its off state.

15. The memory device of claim 14, wherein during the pre-programming operation, the control circuitry is configured to place the third switch in its off state.

16. The memory device of claim 10, wherein during the pre-programming operation, the control circuitry is configured to place the first switch in its on state and cause the charge pump to generate a third voltage so as to apply the third voltage from the charge pump to the erase gate line and the first control gate line and the second control gate line.

Images