Sampler input calibration using self-generated reference voltage in a serdes receiver

Abstract

A calibration circuit includes a replica summing circuit, a replica sampling circuit, and a control circuit. The replica summing circuit is a replica of a sampling circuit in a serializer / deserializer (SerDes) interface and is configured to provide a summer output signal representing a common mode voltage at an input of the SerDes interface. The replica sampling circuit is a replica of the sampling circuit in the SerDes interface. The replica sampling circuit includes a first input transistor having a gate coupled to the summer output signal and a second input transistor configured to provide an internal reference voltage at a drain thereof. The drain of the second input transistor is coupled to a gate of the second input transistor. The control circuit is configured to control current flow in the replica summing circuit in response to a calibration signal output by the replica sampling circuit.

Description

Cross-reference of related applications

[0001] This patent application claims priority to pending U.S. nonprovisional application No. 18 / 582,027, filed February 20, 2024, which has been assigned to the assignee of this application and is expressly incorporated herein by reference, as fully set forth below and for all applicable purposes. Technical Field

[0002] This disclosure relates in general to high-speed data communication interfaces using serializers and / or deserializers, and more specifically to the dynamic control of current sources in summing circuits. Background Technology

[0003] Electronic device technology has experienced explosive growth in recent years. For example, better communication, hardware, larger networks, and more reliable protocols have driven the development of cellular and wireless communication technologies. Wireless service providers are now able to offer their customers an ever-expanding range of features and services, providing users with unprecedented levels of access to information, resources, and communications. To keep pace with these service enhancements, mobile electronic devices (e.g., cellular phones, tablets, laptops, etc.) have become more powerful and complex than ever before. Wireless devices may include high-speed bus interfaces for signal communication between hardware components. For example, a high-speed bus interface may be implemented using a Peripheral Component Interconnect (PCIe) bus. High-frequency signals may be equalized at the receiver. The receiver may utilize a combination of summing and sampling circuitry when processing the received signal. The performance of these circuits may be adversely affected by changes or variations in the common-mode voltage associated with the received signal. There is a continuous need for improved circuitry to equalize and amplify, or otherwise process signals received via the bus interface. Summary of the Invention

[0004] Certain aspects of this disclosure relate to systems, apparatus, methods, and techniques for dynamically calibrating gain in high-frequency interfaces including serializers / deserializers (SerDes). Dynamic control of the reference voltage enables reliable operation even as process parameters, voltage, and / or temperature change.

[0005] In various aspects of this disclosure, a calibration circuit includes a replica summing circuit, a replica sampling circuit, and control circuitry. The replica summing circuit is a replica of the sampling circuitry in the SerDes interface and is configured to provide a summer output signal representing the common-mode voltage at the input of the SerDes interface. The replica sampling circuitry is a replica of the sampling circuitry in the SerDes interface. The replica sampling circuitry may include: a first input transistor having a gate coupled to the summer output signal; and a second input transistor configured to provide an internal reference voltage at its drain. The drain of the second input transistor may be coupled to its gate. The control circuitry may be configured to control current flow in the replica summing circuitry in response to a calibration signal output from the replica sampling circuitry.

[0006] In various aspects of this disclosure, an apparatus includes: components for generating a summer output signal representing a common-mode voltage at an input of a serializer / deserializer (SerDes) interface, the components including a copy of a summing circuit disposed in the SerDes interface; components for comparing the summer output signal with an internal reference voltage in a copy of a sampling circuit in the SerDes interface, the internal reference voltage being provided by a diode-connected transistor; and components for controlling current flow in the copy of the summing circuit based on a calibration signal output from the copy sampling circuit.

[0007] In various aspects of this disclosure, a method for calibrating a summing circuit includes: generating a summer output signal representing a common-mode voltage at an input of a SerDes interface using a copy of the summing circuit in a serializer / deserializer (SerDes) interface; comparing the summer output signal with an internal reference voltage in a copy of a sampling circuit in the SerDes interface; and controlling current flow in the copy of the summing circuit in response to a calibration signal output by the copy of the sampling circuit. The copy of the sampling circuit may include: a first input transistor having a gate coupled to the summer output signal; and a second input transistor configured to provide an internal reference voltage at its drain. The drain of the second input transistor may be coupled to the gate of the second input transistor.

[0008] In one aspect, the summer output signal has a voltage level defined by the integral of the current flow in a replica of the summing circuit over a time period. This time period can be defined by a clock signal.

[0009] In one aspect, the current flow in the replica of the summing circuit can be controlled by configuring the current source using a calibration code. The current flow in the replica of the summing circuit can also be controlled by configuring the current source based on tap coefficients defined for the decision feedback equalizer.

[0010] In some respects, the current flow in the summing circuit of the SerDes interface can be controlled in response to a calibration signal output from the replica sampling circuit. In some instances, the same level of current can flow in both the replica summing circuit and the summing circuit in the SerDes interface.

[0011] In various aspects of this disclosure, a calibration circuit includes a replica summer and a replica sampling circuit. The replica summer includes a pair of summing input transistors, each having: a gate configured to receive an input signal representing a common-mode voltage input to an analog front-end circuit; a drain coupled to a summer output signal; and a source coupled to at least one summer source transistor configured to control current flowing in the pair of summing input transistors. The replica sampling circuit includes a pair of sampling input transistors, including a first sampling input transistor having: a gate configured to receive the summer output signal; a source coupled to a sampling source transistor configured to control current flowing in each of the sampling input transistors; and a drain coupled to a first feedback signal. The second sampling input transistor is a diode-connected transistor having a gate and a drain coupled to a second feedback signal. Attached Figure Description

[0012] Figure 1 Examples of System-on-Chip (SOC) according to certain aspects of this disclosure are illustrated.

[0013] Figure 2 Examples of data communication systems that can be adapted according to certain aspects of this disclosure are illustrated.

[0014] Figure 3 This illustrates some aspects of the operation of a data communication interface that can be implemented in a SoC or another IC device.

[0015] Figure 4 An example of a multi-tap decision feedback equalizer that can be used in a data communication interface that can be adapted according to certain aspects of this disclosure is illustrated.

[0016] Figure 5 Examples of current summers and sampling circuits that can be used in conventional multi-tap decision feedback equalizers are shown.

[0017] Figure 6 An example of a calibration circuit that can be adapted or reconfigured according to certain aspects of this disclosure is shown.

[0018] Figure 7Examples of calibration circuits that can be used to adjust common-mode voltage according to certain aspects of this disclosure are illustrated.

[0019] Figure 8 Including examples of use Figure 7 The calibration circuit calibrates the summer to account for some effects of the common-mode voltage during calibration.

[0020] Figure 9 Examples of copy sampling circuits configured and operated according to certain aspects of this disclosure are illustrated.

[0021] Figure 10 An example of an apparatus employing processing circuitry adaptable to certain aspects disclosed herein is illustrated.

[0022] Figure 11 This is a flowchart illustrating an example of a method for calibrating a summing circuit in a high-speed SerDes interface, based on certain aspects disclosed herein. Detailed Implementation

[0023] The detailed description below, taken in conjunction with the accompanying drawings, is intended as a description of various configurations and not as representing only the configurations in which the concepts described herein can be practiced. To provide a thorough understanding of the various concepts, the detailed description includes specific details. However, it will be apparent to those skilled in the art that these concepts can be practiced without these specific details. In some instances, to avoid obscuring such concepts, well-known structures and components are shown in block diagram form.

[0024] Several exemplary aspects of this disclosure will now be described with reference to the accompanying drawings. The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects.

[0025] The terms “computing device” and “mobile device” are used interchangeably herein to refer to any or all of the following: servers, personal computers, smartphones, cellular phones, tablet computers, laptop computers, netbooks, ultrabooks, handheld computers, personal data assistants (PDAs), wireless email receivers, cellular phones with multimedia internet support, global positioning system (GPS) receivers, wireless game controllers, and similar personal electronic devices that include programmable processors. While these aspects are particularly useful in mobile devices (e.g., smartphones, laptops, etc.) with limited resources (e.g., processing power, battery, size, etc.), they are generally useful in any computing device that can benefit from improved processor performance and reduced power consumption.

[0026] The term "multi-core processor" is used herein to refer to a single integrated circuit (IC) chip or chip package containing two or more independent processing units or cores (e.g., CPU cores) configured to read and execute program instructions. The term "multiprocessor" is used herein to refer to a system or device comprising two or more processing units configured to read and execute program instructions.

[0027] The term "System-on-a-Chip" (SoC) is used herein to refer to a single integrated circuit (IC) chip containing multiple resources and / or processors integrated on a single substrate. A single SoC may contain circuitry for digital, analog, mixed-signal, and radio frequency functions. A single SoC may also include any number of general-purpose and / or special-purpose processors (digital signal processors (DSPs), modem processors, video processors, etc.), blocks of memory (e.g., read-only memory (ROM), random access memory (RAM), flash memory, etc.), and resources (e.g., timers, regulators, oscillators, etc.), any one or all of which may be included in one or more cores.

[0028] The memory technologies described herein are suitable for storing instructions, programs, control signals, and / or data for use in or by a computer or other digital electronic device. Any references to terms and / or technical details relating to individual memory types, interfaces, standards, or memory technologies are for illustrative purposes only and are not intended to limit the scope of the claims to a particular memory system or technology, unless specifically stated in the language of the claims. The complexity of mobile computing device architectures has increased and now typically includes multiple processor cores, SoCs, coprocessors, functional modules including dedicated processors (e.g., communication modem chips, GPS receivers, etc.), complex memory systems, intricate electrical interconnects (e.g., buses and / or structures), and many other resources for executing complex and power-intensive software applications (e.g., video streaming applications, etc.).

[0029] The process technologies used to manufacture semiconductor devices, including integrated circuit (IC) devices, are constantly being improved. Process technologies encompass the manufacturing methods used to fabricate IC devices and define transistor size, operating voltage, and switching speed. Features that are components of the circuitry within an IC device can be referred to as technology nodes and / or process nodes. The terms "technology node," "process node," and "process technology" are used to characterize a specific semiconductor manufacturing process and its corresponding design rules. By using smaller feature sizes to produce smaller transistors that enable the fabrication of higher-density ICs, faster and more efficient technology nodes are continuously being developed.

[0030] Certain aspects of this disclosure apply to circuitry for generating, transmitting, receiving, processing, and / or propagating differential signals. A conductor pair comprises two conductors, connectors, interconnects, or other conductors through which a differential signal is transmitted. The differential signal is carried in two phase versions on the conductor pair, whereby the conductors, connectors, interconnects, or other conductors in the conductor pair carry versions of the differential signal that are 180° out of phase with each other. The versions of the differential signal transmitted through the conductor pair may be referred to as complementary signals. The differential signal is transmitted through the conductors, connectors, interconnects, or other conductors using voltages of equal amplitude but opposite polarity. A received signal can be generated at a receiving device, representing the difference between the signaling states of the conductor pair. The same direct current (DC) offset from system ground carried by each conductor in the pair may be referred to as a common-mode voltage. The common-mode voltage may be measured at the input of the receiving device. The same signal carried in phase by each conductor in the pair may be referred to as a common-mode signal. Common-mode noise affecting the conductors, connectors, interconnects, or other conductors may be expected to cause nearly identical interference signals in the conductor pair. Interference signals are usually eliminated by subtraction at the receiver without affecting the received signal.

[0031] Certain aspects of this disclosure relate to calibration circuitry used in interfaces including high-speed serializer-deserializer (SerDes) circuitry. Certain calibration circuitry that can be deployed in the analog front-end (AFE) of a receiver is described. In one aspect, calibration techniques and circuitry are disclosed. These calibration techniques and circuitry may relate to components of the AFE gain stage, which may include equalizers such as decision feedback equalizers (DFE), variable gain amplifiers (VGA), buffers, summers, etc. In one example, certain aspects of this disclosure relate to circuitry including a summer and a sampler.

[0032] Figure 1 Example components and interconnects in a System-on-Chip (SoC) 100 suitable for implementing certain aspects of this disclosure are illustrated. The SoC 100 may include multiple heterogeneous processors, such as a central processing unit (CPU) 102, a modem processor 104, a graphics processor 106, and an application processor 108. Each processor 102, 104, 106, 108 may include one or more cores, and each processor / core may perform operations independently of the other processors / cores. The processors 102, 104, 106, 108 may be organized in close proximity to each other (e.g., on a single substrate, die, integrated chip, etc.), allowing the processors to operate at much higher frequencies / clock rates than would be possible with off-chip signal propagation. The proximity of the cores also allows for the sharing of on-chip memory and resources (e.g., voltage rails), and allows for more coordinated cooperation between the cores.

[0033] SoC 100 may include system components and resources 110 for managing sensor data, analog-to-digital conversion, and / or wireless data transmission, as well as for performing other specialized operations such as decoding high-definition video, video processing, etc. System components and resources 110 may also include components such as voltage regulators, oscillators, phase-locked loops (PLLs), peripheral bridges, data controllers, system controllers, access ports, timers, and / or other similar components for supporting processors and software clients running on computing devices. System components and resources 110 may also include circuitry for interfacing with peripheral devices such as cameras, electronic displays, wireless communication devices, external memory chips, etc.

[0034] SoC 100 may also include a Universal Serial Bus (USB) or other serial bus controller 112, one or more memory controllers 114, and a Centralized Resource Manager (CRM) 116. SoC 100 may also include input / output modules (not shown) for communicating with resources outside the SoC, each of which may be shared by two or more internal SoC components.

[0035] Processors 102, 104, 106, and 108 can be interconnected via interconnect / bus module 122 to USB controller 112, memory controller 114, system components and resources 110, CRM 116, and / or other system components. This interconnect / bus module may include reconfigurable gate arrays and / or implement a bus architecture. Communication may also be provided by advanced interconnects such as high-performance on-chip networks (NoC).

[0036] Interconnect / bus module 122 may include or provide a bus master system configured to grant exclusive control of the bus to SoC components (e.g., processors, peripherals, etc.) (e.g., data transfer in burst mode, block transfer mode, etc.) to set duration, number of operations, number of bytes, etc. In some cases, interconnect / bus module 122 may implement an arbitration scheme to prevent multiple master components from attempting to drive the bus simultaneously. Memory controller 114 may be a dedicated hardware module configured to manage the flow of data to and from memory 124 via memory interface / bus 126.

[0037] The memory controller 114 may include one or more processors configured to perform read and write operations on the memory 124. Examples of processors include microprocessors, microcontrollers, digital signal processors (DSPs), field-programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, gated logic units, discrete hardware circuitry, and other suitable hardware configured to perform various functionalities described throughout this disclosure. In some aspects, the memory 124 may be part of a SoC 100.

[0038] Figure 2 An example of a data communication system 200 adaptable to certain aspects of this disclosure is illustrated. The data communication system 200 includes a transmitter 202, a data communication channel 210, and a receiver 222. The transmitter 202 may be disposed in a first device configured to transmit data signals to a second device. The data communication channel 210 provides a transmission medium through which data signals propagate from the first device to the second device. The receiver 222 may be disposed in the second device and may be configured to receive and process data signals.

[0039] In one example, transmitter 202 includes a serializer 204 configured to convert parallel data into serial data. Transmitter 202 also includes a transmit driver 206 configured to generate a data signal based on the serial data for transmission to receiver 222 via data communication channel 210.

[0040] Data communication channel 210 can be implemented using any type of transmission medium through which data signals can be propagated from transmitter 202 to receiver 222. Examples of data communication channel 210 include striplines, microstrips, coaxial cables, twisted pairs, one or more metallized traces on a printed circuit board (PCB) (which may include one or more vias), etc.

[0041] In the illustrated example, receiver 222 includes a VGA with a continuous-time linear equalizer (CTLE), a clock data recovery circuit (CDR 226), and a deserializer 228. The combination of VGA and CTLE is referred to herein as VGA / CTLE 224. CTLE can refer to a technique used to boost higher frequency components of the signal at the receiver so that all frequency components of the signal achieve similar amplitude ratios before channel attenuation, thereby improving jitter and eye diagram performance. As disclosed herein, VGA / CTLE 224 is configured to perform equalization and amplification of the received data signal. CDR 226 is configured to recover the clock associated with the data signal and use this clock to recover the serial data from the data signal. Deserializer 228 is configured to convert the serial data back into parallel data.

[0042] Data communication channel 210 typically has a frequency response H1(ƒ) similar to a low-pass filter. For example, the frequency response H1(ƒ) ranges from direct current (DC) to a specific cutoff frequency ƒ. c1 It has relatively low loss; therefore, the loss is at the cutoff frequency ƒ. c1 The frequency response H1(ƒ) of the data communication channel 210 limits the data rate that can be transmitted through the channel. For example, the cutoff frequency ƒ c1It should at least reach the Nyquist rate of the data signal. If the Nyquist rate of the data signal is higher than the cutoff frequency ƒ c1 If the data signal is distorted at receiver 222, it can be characterized by the eye in the signal eye diagram closing or becoming smaller, making it difficult to recover the clock and data via CDR 226.

[0043] The VGA / CTLE 224 can perform equalization and amplification to increase the high-frequency components of the data signal, thereby increasing the data rate at which the data signal can be transmitted over the data communication cable and reliably recovered at the receiver 222. For example, the VGA / CTLE 224 can be configured to provide a frequency ƒ from DC to the zero point. z The frequency response H2(ƒ) is essentially flat. Then, at the zero frequency ƒ z Above this, the frequency response H2(ƒ) of the VGA / CTLE 224 increases to the frequency ƒ corresponding to the pole. p At the pole frequency ƒ p Above this, the frequency response H2(ƒ) of the VGA / CTLE 224 decreases monotonically. In some examples, the VGA / CTLE 224 may have more than one pole and one zero.

[0044] The VGA / CTLE 224 can be configured to have a frequency response H2(ƒ), where the pole frequency ƒ p The cutoff frequency ƒ of the frequency response H1(ƒ) of the data communication channel 210 c1 They are essentially the same. When the data communication channel 210 is cascaded with the VGA / CTLE 224, the frequency response H1(ƒ) of the data communication channel 210 and the frequency response H2(ƒ) of the VGA / CTLE 224 are combined at the output of the VGA / CTLE 224 to form a composite frequency response H3(ƒ). Therefore, the pole frequency ƒ of the VGA / CTLE frequency response H2(ƒ) is... p The high-frequency boost at that point compensates for the cutoff frequency ƒ of the channel frequency response H1(ƒ). c1 The loss roll-off at the point is used to generate a cutoff frequency ƒ with a higher channel frequency response H1(ƒ). c1 A much higher cutoff frequency ƒ c3 The composite frequency response H3(ƒ) is obtained. Therefore, by using VGA / CTLE 224, a much higher data rate can be achieved between transmitter 202 and receiver 222.

[0045] Figure 3This illustration demonstrates certain effects of PVT variations on the operation of transistors and other components in a data communication interface 300. The illustrated data communication interface 300 can be implemented in a SoC or another IC device. The receiver 302 in the data communication interface 300 includes differential signal processing circuitry, including an equalizer 304 and a variable gain amplifier (VGA 306). The differential signal processing circuitry can be configured to generate a differential output signal 316 by applying a frequency-dependent gain to a differential input signal 312, which, in the illustrated example, is received from a differential communication channel 310. The differential output signal 316 can be provided to a sampler circuitry 308 configured to extract data and other information transmitted through the communication channel 310. In one example, the differential input signal 312 is applied to the gate inputs or other control inputs of a pair of input transistors in the equalizer 304, and the output of the equalizer 304 is provided to the VGA 306. The gain of the VGA 306 can be configured via a gain control input 314. In one example, the gain control input 314 may include a 4-bit binary value that selects the gain setting from 16 possible settings.

[0046] In receiver 302, VGA 306 collaborates with equalizer 304 to equalize and amplify the small differential input signal 312 to a level that can be processed by the next stage. Ideally, the frequency response 320 of equalizer 304 and the frequency response 322 of VGA 306 produce an ideal combined frequency response 324 for each gain setting of VGA 306. Ideally, the responses are substantially parallel for the multiple gain settings in the combined frequency response 324. Parallel responses indicate consistent frequency responses regardless of gain settings. A consistent equalization frequency response is generally desired regardless of the gain configured for VGA 306. For example, the same equalization frequency response is generally expected for low-amplitude and high-amplitude signals, including when different gain settings are configured for the two signals.

[0047] Maintaining parallel responses for different VGA gain settings can be very challenging in conventional systems. In many conventional systems, variations in VGA gain can affect the location of equalizer poles / zeros at high data rates. The observed combined frequency response 326 illustrates the consistency loss between different VGA gain settings, indicated by the parallelism loss at higher frequencies. In some instances, variations in VGA 306 can affect the location of parasitic zeros in the frequency response 326 in a manner referred to herein as “zero pull-in” 328.

[0048] Certain aspects of this disclosure relate to using summer output calibration to optimize the performance of a sampler in a high-frequency interface including SerDes circuitry. An example of a DFE (Digital Equalizer) is used herein to facilitate the description of certain aspects of this disclosure. A DFE is a nonlinear equalizer commonly used in serial links, including in high-speed SerDes circuitry, to flatten the channel response and limit signal distortion. In some examples, the DFE samples the received data signal to capture a time series of bits that can be configured to eliminate inter-symbol interference (ISI) in the bits, which can be attributed to previous bits received in the received data signal. A summer and a sampler can be configured within the DFE.

[0049] Figure 4 Examples of conventional multi-tap DFE 400s that can be used in data communication interfaces adaptable to certain aspects of this disclosure are provided. For example, the calibration techniques and circuits currently disclosed can accommodate or compensate for the effects of process, voltage and / or temperature (PVT) variations on the sampler 404 and / or current summers 402, 412 provided within the DFE 400.

[0050] The current summer 402 can be configured to add the input data signal 420 received from the communication link to the feedback signal 422 provided by the finite input response (FIR) filter 410. The output 424 of the current summer 402 is provided to a sampler 404, which can be implemented using a flip-flop or latch clocked by a sampling clock signal (CLK_SA signal 426), derived from a clock signal corresponding to the input data signal 420. For example, the CLK_SA signal 426 can be configured to capture data from a serial bus. The sampler 404, which can be referred to as a limiter, generates a limited data signal 428 to the input of the FIR filter 410.

[0051] The illustrated FIR filter 410 includes a delay line 414 that maintains the signaling state of the input data signal 420 across multiple previous transmission intervals. In one example, the signaling state may be represented by binary bits. In other examples, the signaling state may be represented by multiple binary bits. In some examples, the signaling state of the multiple-bit input signal may be represented by symbols. The output of sampler 404 represents the current symbol value or signaling state of the channel in the current transmission interval. The current transmission interval may be referred to as a cursor. The output of delay line 414 maintains a representation of the symbol value or signaling state of the channel in one or more subsequent cursor transmission intervals and can be used to eliminate reflections and other subsequent cursor ISIs affecting the channel in the current transmission interval. A weighted version of the output of delay line 414 can be used to subtract subsequent cursor ISIs from the input data signal 420.

[0052] In the illustrated example, the limiting data signal 428 is used to drive the delay line 414. The delay line includes multiple ( ) spools controlled by the clock signal CLK_SA 426. N (Number) D flip-flops (D-FF 4061 to 406) N The weight values ​​can be applied to D-FF4061 to 406. N The output. In the illustrated example, the weighted tap coefficient can be configured from 4080 to 408. N D-FF 4061 to 406 applied in the feedback path N The output feedback path includes a current summer 412, which sums the weighted previous decisions to generate a feedback signal 422. In some implementations, the current summer 402 can be used to sum the input data signal 420 and the weighted previous decisions.

[0053] In the illustrated example, feedback signal 422 provides negative feedback. The weighted tap coefficients 4080 to 408 are configurable, calibrated, or adjustable. N The magnitude and polarity of the weighted taps are adjusted to compensate for channel characteristics. The multi-tap DFE 400 can be configured to eliminate ISI attributable to previous bits received in the input data signal 420, thereby allowing subsequently received bits to be sampled or detected by the sampler 404 with a reduced bit error rate (BER). In some instances, the weighted tap coefficients are 4080 to 408. N It can be pre-configured by the designer or application. The controller can determine the weight values ​​based on pre-configured information or information obtained from calibration or training. In some instances, the weighted tap coefficients are 4080 to 408. N Configuration, calibration, training, or tuning can be performed using adaptive algorithms. In some specific implementations, weighted tap coefficients of 4080 to 408 are applied. N The current level can be controlled using a current digital-to-analog converter (IDAC) and / or bias control circuitry. The multi-tap DFE 400 is presented merely as an example of using a summer and sampler. Other types of circuitry may include summers and samplers to perform functions beyond those specific to the DFE.

[0054] Figure 5 An example of a current summer 500 and sampling circuit 520 that can be used in a conventional DFE is illustrated. The current summer 500 is a resistive load summer where multiple currents are added to an offset current to produce a combined current (I) flowing through the load supplied by resistor 502. The resistor can be implemented using a suitably biased transistor. The product of the combined current and the resistance (IR) determines the differential voltage at the output (i.e., Out). sum+ 514a and Out sum-The voltage difference between 514b). The resistance (R) provided by resistor 502, combined with the wire capacitance 504 and the load capacitance 506 (collectively referred to as "C"), may affect the settling time of the data signal transition due to the resulting RC time constant. The resistance value of resistor 502 determines the oscillation time of the output of current summer 500. Current summer 500 includes current sources 5081 to 508. N These current sources have N taps, 5101 to 510. N Each of them provides DC bias current. N taps 5101 to 510 N The current supplied by each of them is configured by a corresponding differential weighting signal, which includes differential pairs H1 and H'1 in the weighting signal provided to the first tap 5101 and the current provided to the Nth tap 510. N The difference pair H in the weighted signal N and H' N .

[0055] When Clk_sa 532 transitions to a high signaling state, sampling circuit 520 is enabled. The gates of input transistors 522a and 522b receive the differential input signal from the summing circuit. Input transistors 522a and 522b drive the differential output (Dint 530). In the illustrated example, the differential input signal is provided by current summer 500. The gate of the first input transistor 522a is coupled to Out. sum+ 514a, and the gate of the second input transistor 522b is coupled to the complementary Out. sum- 514b.

[0056] In the illustrated example, a pair of reference transistors 524a and 524b, coupled in parallel with input transistors 522a and 522b, are supplied with a threshold voltage that enables the sampling circuit 520 to determine the signaling state of the differential input signal. The gates of the reference transistors 524a and 524b receive the differential threshold signal. The gate of the first reference transistor 524a is coupled to V... th+ Signal 534a, and the gate of the second reference transistor 524b is coupled to the complementary V. th- Signal 534b. In one example, the differential threshold signal may be provided by a digital-to-analog converter (DAC). The drain of the first reference transistor 524a is coupled in parallel with the drain of the first input transistor 522a, such that the first reference transistor 524a determines the gate voltage at which the first input transistor 522a switches between an on state and an off state. The drain of the second reference transistor 524b is coupled in parallel with the drain of the second input transistor 522b, such that the second reference transistor 524b determines the gate voltage at which the second input transistor 522b switches between an on state and an off state.

[0057] Figure 6 A calibration circuit 600 in a high-speed interface is illustrated, comprising a replica summing circuit 602 and a replica sampling circuit 610, which can be adapted or reconfigured according to certain aspects of this disclosure. The illustrated replica summing circuit 602 and replica sampling circuit 610 are replica circuits that can be used to determine operating parameters in the interface. Samplers are typically highly sensitive to changes in the common-mode (CM) voltage of their inputs. The CM voltage can affect the sensitivity of the sampler and can increase or decrease the delay between the sampler's input and output in a manner that hinders calibration. The CM voltage can depend on the data rate through the sampler. For example, in some specific implementations, the sampler is expected to operate at data rates between 2.5 gigabits per second (Gbps) and 32 Gbps. The CM voltage also depends on the PVT angle. The PVT angle can refer to the operating point, parameters, and / or conditions defined by manufacturing tolerances (process angles) and different voltage or temperature limits defined for the circuitry included in the SerDes interface.

[0058] Conventional samplers use an external reference voltage (V) Ref 622), the external reference voltage is based on Figure 4 The input CM voltage of the sampler 404 is used to define the voltage. V Ref 622 is typically the DC voltage output by the DAC. The DAC can be defined by bits in external registers such as the Configuration and Status Register (CSR). The CSR can be configured during system initialization and / or calibration, and changes in operating data rate, PVT, and other conditions may require recalibration to maintain optimized operation. Optimized operation may involve limitations on sensitivity and delay specified for the sampler. The illustrated calibration circuit 600 generates an output signal (Sum_cal). out Signal 624), this output signal can be used to configure the replica summing circuit 602 and / or the corresponding summing circuit in the interface to accommodate the CM voltage level (V_cm) at the input of the interface. afe 616).

[0059] In the illustrated example, the replica summing circuit 602 is actually... Figure 4 A copy of the summing circuit in the illustrated summer 412. The summer 412 includes at least... N A summing circuit is used to sum the values ​​in the FIR filter 410. NThe contributions of each tap are summed. The circuit structure and / or signaling path set in the replica summing circuit 602 are nominally the same as the corresponding structure and / or signaling path in the summing circuit of the summer 412. The replica summing circuit 602 is clocked by a summer enable signal (Clk_sum signal 614) used to control the sampling timing. In the illustrated example, the replica summing circuit 602 is enabled when the Clk_sum signal 614 is in a first signaling state (which may be referred to as a high signaling state), and is disabled when the Clk_sum signal 614 is in a second signaling state (which may be referred to as a low signaling state). When the Clk_sum signal 614 is in a high signaling state, the gates of the input transistors 606a and 606b are coupled to V_cm. afe 616. The sources of input transistors 606a and 606b are coupled to corresponding current sources 608a and 608b, which can be configured during calibration to provide the desired, determined, or specified current in the replica summing circuit 602. Changes in the current in the replica summing circuit 602 can be reflected in the gain of the summing circuits in the summerizer 412, which can be configured to define weighted tap coefficients 4080 to 408. N In some examples, the current in the replica summing circuit 602 controls the rate of change of the voltage at the output of the replica summing circuit 602. The voltage at the output of the replica summing circuit 602 can be defined or represented by the integral of the current flowing through the replica summing circuit 602 over a time period. In one example, this time period may correspond to a small portion of the time period of the Clk_sum signal 614.

[0060] The drain of each of the input transistors 606a and 606b is coupled to the output of the duplicate summing circuit 602. sum 620). Out sum 620 is provided to the first input of the replica sampling circuit 610, which is configured to compare the voltage at the first input with V. Ref 622 is compared. The output of the replica sampling circuit 610 drives Sum_cal. out Signal 624.

[0061] In one example, the replica sampling circuit 610 is enabled when the sampling clock signal (Clk_SA signal 612) is in the first signaling state. sum 620 is provided to the gate of the first input transistor 632 in the copy sampling circuit 610, and V Ref 622 is coupled to the gate of the second input transistor 634. The differential output (Dint 630) of the replica sampling circuit 610 represents Out. sum 620 and V Ref The difference between 622 and 622.

[0062] Figure 7 An example of a calibration circuit 700 is illustrated, which can be used to adjust the common-mode voltage in the signal provided to the sampler in the interface circuitry. In the illustrated example, the sampler in the interface circuitry receives a reference voltage signal (V0) from a programmable resistor divider 732. Ref 730). V Ref The voltage of 730 can be controlled using a multi-bit control code (V). Ref_prog 734) is used to adjust or configure. In other examples, V Ref 730 is supplied by DAC. V Ref_prog 734 can be configured during system initialization and / or calibration.

[0063] The calibration circuit 700 includes a replica sampling circuit 706 and a replica summing circuit 702. The illustrated replica summing circuit 702 and replica sampling circuit 710 are replica circuits that can be used to determine operating parameters in the interface and / or respond to operating parameters in the same manner as the corresponding sampler and summer in the interface circuitry. The calibration circuit 700 can be configured to compensate for changes in the CM voltage in the signal provided to the sampler in the interface circuitry. Changes in the CM voltage may affect the sensitivity and delay between the input and output of a previously calibrated sampler. The CM voltage may vary with the data rate passing through the sampler, which may range from 2.5 Gbps to 32 Gbps. The CM voltage may change in response to PVT variations.

[0064] The illustrated calibration circuit 700 generates an output signal (Sum_cal). out Signal 716), this output signal can be used to adjust the current supplied in the replica summing circuit 702 and / or the corresponding summing circuit in the interface to suit the CM voltage level (V_cm) at the input of the analog front-end (AFE) sub-circuit in the interface circuit. afe The change of 728).

[0065] In the illustrated example, the replica summing circuit 702 is actually... Figure 4 A copy of the summing circuit in the illustrated summer 412. The summer 412 includes at least... N A summing circuit is used to sum the values ​​in the FIR filter 410. NThe contributions of each tap are summed. The circuit structure and / or signaling path set in the replica summing circuit 702 are nominally the same as the corresponding structure and / or signaling path in the summing circuit of the summer 412. The replica summing circuit 702 is clocked by a summer enable signal (Clk_sum signal 710) used to control the sampling timing. In the illustrated example, the replica summing circuit 702 is enabled when the Clk_sum signal 710 is in a first signaling state (which may be referred to as a high signaling state), and is disabled when the Clk_sum signal 710 is in a second signaling state (which may be referred to as a low signaling state). The gates of the input transistors 722a and 722b are coupled to V_cm. afe 728. The sources of input transistors 722a and 722b are coupled to corresponding transistors 724a and 724b that control the current supplied in the replica summing circuit 702. The current supplied in the replica summing circuit 702 can be controlled by a bias voltage (ib). main 712) determines that the bias voltage is controlled or configured by the feedback loop of the calibration circuit 700.

[0066] The copy summation circuit 702 provides a representation of V_cm. afe The output of 728 (Out_sum 714). The voltage level of Out_sum 714 can be increased within the time period defined by the Clk_sum signal 710. The increase in the voltage level of Out_sum 714 can be represented as the integral of the current supplied in the replica summing circuit 702 over the time period defined by the Clk_sum signal 710. Out_sum 714 is provided to the output Sum_cal. out One input terminal of the replica sampling circuit 706 for signal 716. Sum_cal out Signal 716 represents Out_sum 714 and V Ref The difference between 730 and Sum_cal out Signal 716 is provided to loop control circuit 708, which determines the relationship between Out_sum 714 and V. Ref Does the difference between 730 need to be adjusted for ib? main 712 is adjusted. In some implementations, the loop control circuit 708 is implemented using processing circuitry including a processor, controller, sequencer, signal processor, or general-purpose processor. The processing circuitry can implement a state machine. In some implementations, the loop control circuit 708 uses a response to Sum_cal out The combinational logic provided in signal 716 is used for implementation. In some specific implementations, the loop control circuit 708 may be based on Out_sum 714 and V. RefThe sign (+ or -) of the difference between 730 is used to increment or decrement the current source control circuit 704 by providing a calibration code 718. In some specific implementations, the loop control circuit 708 may be based on Out_sum 714 and V Ref The value of calibration code 718 is determined by the difference between 730 and the previous value configured for calibration code 718.

[0067] Calibration code 718 can be used to configure the operating point of the variable transistor 744 or the transistor array. In one example, calibration code 718 selects multiple transistors to be coupled in parallel to provide the variable transistor 744. The number of transistors determines the current flowing through the variable transistor 744, thereby determining the voltage at the gate of the variable transistor 742. The voltage at the drain of the variable transistor 742 is defined as ib. main 712. The voltage at the drain of the variable transistor 742 is determined in part by its gate voltage and the current flowing through its drain, which in turn is determined by the number of transistors coupled in parallel to provide the variable transistor 742. In one example, the number of transistors coupled in parallel to provide the variable transistor 742 may be selected to provide the desired tap factor (see [link to relevant documentation]). Figure 4 The illustrated multi-tap DFE 400. The tap coefficients can be defined by the DFE step codes provided by the controller in the interface circuit. In some implementations, the tap coefficients are defined by the loop control circuit 708.

[0068] The calibration method illustrated in calibration circuit 700 has certain drawbacks. For example, the calibration method relies on the calibration of external components, such as the programmable resistor divider 732 or a DAC. These external components are fixed and do not automatically follow or respond to changes in the input CM voltage. Recalibration of the external components may be necessary to accommodate changes in the input CM voltage caused by variations in data rate and PVT.

[0069] Figure 8 Including timing diagrams 800 and 810, which illustrate the use of Figure 7 The calibration circuit 700's interface circuit has certain effects on the CM voltage level during the calibration of the summer. To describe timing diagrams 800 and 810, it is assumed that the replica sampling circuit 706 uses... Figure 6This is implemented by the illustrated replica sampling circuit 610. The output of the replica summing circuit 702 (i.e., Out_sum 714) begins to decrease at the transitions 804, 814 from Clk_SUM 710 to the high signaling state. The rate at which Out_sum 714 decreases depends on the current supplied by the current sources 608a, 608b. The voltage of Out_sum 714 can be expressed as the integral of the current supplied by the current sources 608a, 608b. The replica sampling circuit 706 is enabled when Clk_SA 802, 812 transitions to the high signaling state 806, 816.

[0070] In the first timing diagram 800, the CM voltage at the input of the interface circuit is high enough to cause the sampler output to drop rapidly 808. This rapid drop in the sampler output can cause one or more transistors 632, 634 in the replica sampling circuit 610 to leave saturation mode and enter triode mode, thereby limiting or reducing the sensitivity of the replica sampling circuit 610. The saturation mode of the transistor corresponds to the change in drain current and gate-source voltage (Vs). GS The operating region is defined by a substantially linear relationship between the poles (V and V). In the tripolar region (also known as the Ohmic region), for a fixed V... GS The drain current can vary with the drain-source voltage (V). DS The voltage CM at the input of the interface circuit is low enough to cause the sampler output to drop slowly 818 and reduce the timing of the sampler, and may limit the data rate that can be achieved by the interface.

[0071] Figure 8 This includes a third timing diagram 820 corresponding to a calibration circuit configured and operated according to certain aspects of this disclosure. Figure 9 Examples of a replica sampling circuit 900 configured and operated according to certain aspects of this disclosure are illustrated. In one example, the replica sampling circuit 900 can be used to implement... Figure 7 The illustrated calibration circuit 700 includes a replica sampling circuit 706 and a programmable resistor divider 732. The replica sampling circuit 900 can be used to determine operating parameters in the interface. In one example, the replica sampling circuit 900 is used for... Figure 7 The calibration period of the illustrated copy summing circuit 702.

[0072] The illustrated replica sampling circuit 900 can be configured to mitigate or eliminate the effects of common-mode (CM) voltage variations at its input, and to optimize the sensitivity of the replica sampling circuit 900 and the delay duration between the input and output of the sampler. The CM voltage can depend on the data rate through the sampler and the PVT variation.

[0073] In one aspect, the replica sampling circuit 900 can operate without an external voltage reference generated by a DAC or resistor network. However, certain implementations offer the option to use an external voltage reference. In the illustrated example, the replica sampling circuit 900 includes a switch 924 that, when closed, allows an external source to provide a voltage reference (V0) used by the replica sampling circuit 900. Ref 914). In the illustrated example, the external source of the reference voltage is implemented as a programmable resistor divider 920. In other examples, a DAC could be used to implement the external source. For example, a switch 924 could be included to support certain legacy operating modes.

[0074] When Clk_SA 912 transitions to a high signaling state, the replica sampling circuit 900 is enabled. The gate of the first input transistor 902 of the replica sampling circuit 900 is coupled to the output of the replica summing circuit. In the illustrated example, the gate of the first input transistor 902 is coupled to the output of the replica summing circuit. Figure 7 The illustrated replica summation circuit 702 provides Out_sum 714. The replica sampling circuit 900 can operate without an external voltage reference by making the second input transistor 904 diode-connected. The second input transistor 904 can be diode-connected when its gate and drain are coupled. In the illustrated example, the gate and drain of the second input transistor 904 are selectively coupled via a switch 906, which can be turned off during legacy mode calibration using an external reference voltage source. When switch 906 is closed or activated, for the second input transistor 904, V... GS = V DS When its associated power supply is provided within the specified operating voltage range, the diode-connected transistor operates in saturation mode. The second input transistor 904 is expected to operate in saturation mode regardless of the CM voltage level. Therefore, the summer output can be calibrated to the optimal voltage level for all PVT angles and all expected or specified data rates. It is expected that the optimal voltage level of the summer output will maintain the sampler circuitry and transistors in saturation during the sensing cycle 828, ensuring that the sampler performs optimally in terms of sensitivity and input-to-output delay.

[0075] Refer again Figure 8 In the third timing diagram 820, the elimination of the fixed reference voltage provides a sampling window 824 with a uniform duration. GS This serves as a variable reference voltage generated internally for the copy sampling circuit 900. The sampling window 824 corresponds to V. GS (and V) DSThe duration of transition 826. The output (Dint 910) of the copy sampling circuit 900 provided to the loop control circuit 708 relative to the conventional copy sampling circuit 610 (see Figure 6 and Figure 8 The output (Dint 630) is optimized for sensitivity and input-to-output delay.

[0076] The calibration circuit provided according to certain aspects of this disclosure includes a replica summer and a replica sampling circuit. In one example, the replica summer corresponds to... Figure 7 The illustrated replica summing circuit 702 and the replica sampling circuit correspond to Figure 9 The illustrated replica sampling circuit 900. The replica summer may include a pair of summing input transistors, which may correspond to... Figure 7 The illustrated input transistors are 722a and 722b. Each summing input transistor may have a gate configured to receive an input signal representing a common-mode voltage input to the analog front-end circuitry. Each summing input transistor may have a drain coupled to the summer output signal. Each summing input transistor may have a source coupled to at least one summer source transistor configured to control the current flowing in the pair of summing input transistors. In one example, a pair of summer source transistors may be provided, such as transistors 724a and 724b controlling the current supplied in the replica summing circuitry 702.

[0077] The replica sampling circuit may have a pair of sampling input transistors, which may correspond to Figure 9 The illustrated input transistors are 902 and 904. A sampling input transistor may include a first sampling input transistor having a gate configured to receive a summer output signal. The source of the first sampling input transistor may be coupled to a sampling source transistor that controls the current flowing in each of the sampling input transistors. The drain of the first sampling input transistor may be coupled to a first feedback signal. A second sampling input transistor may be a diode-connected transistor. The drain and gate of the second sampling input transistor may be coupled to a second feedback signal. The first and second feedback signals may be complementary signals to the differential feedback signals.

[0078] In some implementations, the differential feedback signal is provided as a differential input to the current source control circuit. The current source control circuit may have a control output coupled to the gate of at least one summer source transistor. The current source control circuit may include a current source configured using a calibration code. The current source control circuit may include a current source configured based on tap coefficients defined for the decision feedback equalizer.

[0079] In some implementations, the replica summing circuit is a partial copy of the current summer in the SerDes interface; however, it is conceivable that the replica summing circuit can completely replicate the structure of the current summer in the SerDes interface. Similarly, the replica sampling circuit can be a partial copy of the sampler in the SerDes interface; however, it is conceivable that the sampling circuit can completely replicate the structure of the sampler in the SerDes interface. In some implementations, the same level of current flows in the pair of summing input transistors and the corresponding pair of transistors in the current summer of the SerDes interface.

[0080] Examples of processing circuits and methods Figure 10 This is a diagram illustrating an example of a hardware implementation of device 1000. In some examples, device 1000 may perform one or more functions disclosed herein. According to various aspects of this disclosure, processing circuitry 1002 may be used to implement elements, any portion of elements, or any combination of elements as disclosed herein. Processing circuitry 1002 may include one or more processors 1004 controlled by some combination of hardware modules and software modules. Examples of processors 1004 include microprocessors, microcontrollers, digital signal processors (DSPs), SoCs, ASICs, field-programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, sequencers, gated logic components, discrete hardware circuitry, and other suitable hardware configured to perform the various functionalities described throughout this disclosure. One or more processors 1004 may include dedicated processors that perform specific functions and may be configured, enhanced, or controlled by one of the software modules 1016. One or more processors 1004 may be configured by a combination of software modules 1016 loaded during initialization and may be further configured by loading or unloading one or more software modules 1016 during operation.

[0081] In the illustrated example, processing circuitry 1002 may be implemented using a bus architecture, typically represented by bus 1010. Bus 1010 may include any number of interconnect buses and bridges, depending on the specific application of processing circuitry 1002 and overall design constraints. Bus 1010 links together various circuits including one or more processors 1004 and storage devices 1006. Storage devices 1006 may include memory devices and mass storage devices, and may be referred to herein as computer-readable media and / or processor-readable media. Bus 1010 may also link various other circuits, such as timing sources, timers, peripherals, voltage regulators, and power management circuitry. Bus interface 1008 provides an interface between bus 1010 and one or more transceivers 1012a, 1012b. Transceivers 1012a, 1012b may be provided for each networking technology supported by the processing circuitry. In some cases, multiple networking technologies may share some or all of the circuitry or processing modules found in transceivers 1012a, 1012b. Each transceiver 1012a, 1012b provides components for communicating with various other devices via a transmission medium. In one example, transceiver 1012a may be used to couple device 1000 to a multi-wire bus. In another example, transceiver 1012b may be used to connect device 1000 to a radio access network. Depending on the nature of device 1000, a user interface 1018 (e.g., keypad, display, speaker, microphone, joystick) may also be provided, and this user interface may be communicatively coupled to bus 1010, either directly or via bus interface 1008.

[0082] Processor 1004 may be responsible for managing bus 1010 and for general processing, which may include executing software stored in a computer-readable medium (which may include storage device 1006). In this regard, processing circuitry 1002 (including processor 1004) may be used to implement any of the methods, functions, and techniques disclosed herein. Storage device 1006 may be used to store data manipulated by processor 1004 during software execution, and the software may be configured to implement certain methods disclosed herein.

[0083] One or more processors 1004 in the processing circuitry 1002 can execute software. Software should be broadly interpreted as instructions, instruction sets, code, code segments, program code, programs, subroutines, software modules, applications, software applications, software packages, routines, subroutines, objects, executable files, threads of execution, procedures, functions, algorithms, etc., regardless of whether it is referred to as software, firmware, middleware, microcode, hardware description languages, or other names. The software may reside in a computer-readable form in storage device 1006 or on an external computer-readable medium. External computer-readable media and / or storage device 1006 may include non-transitory computer-readable media. For example, non-transitory computer-readable media include magnetic storage devices (e.g., hard disks, floppy disks, magnetic stripes), optical discs (e.g., compact discs (CDs) or digital multifunction discs (DVDs)), smart cards, flash memory devices (e.g., "flash drives," cards, sticks, or key drives), RAM, ROM, programmable read-only memory (PROM), erasable PROM (EPROM, including EEPROM), registers, removable disks, and any other suitable media for storing software and / or instructions that can be accessed and read by a computer. The computer-readable media and / or storage device 1006 may also include, for example, carrier waves, transmission lines, and any other suitable media for transmitting software and / or instructions that can be accessed and read by a computer. The computer-readable media and / or storage device 1006 may reside in processing circuitry 1002, in processor 1004, outside of processing circuitry 1002, or distributed across multiple entities including processing circuitry 1002. The computer-readable media and / or storage device 1006 may be embodied in a computer program product. For example, a computer program product may include a computer-readable medium in packaging material. Those skilled in the art will recognize how best to achieve the functionality described throughout this disclosure depends on the specific application and the overall design constraints imposed on the system as a whole.

[0084] Storage device 1006 can maintain and / or organize software in loadable code segments, modules, applications, programs, etc., which may be referred to herein as software module 1016. Each software module in software module 1016 may include instructions and data that, when installed or loaded on processing circuitry 1002 and executed by one or more processors 1004, contribute to a runtime image 1014 that controls the operation of one or more processors 1004. Some instructions, when executed, cause processing circuitry 1002 to perform functions according to certain methods, algorithms, and processes described herein.

[0085] Some software modules in software module 1016 may be loaded during the initialization of processing circuit 1002, and these software modules 1016 may configure processing circuit 1002 to perform the various functions disclosed herein. For example, some software modules 1016 may configure the internal devices and / or logic circuit 1022 of processor 1004, and may manage access to external devices such as transceivers 1012a, 1012b, bus interface 1008, user interface 1018, timers, math coprocessors, etc. Software module 1016 may include control programs and / or operating systems that interact with interrupt handlers and device drivers and control access to various resources provided by processing circuit 1002. Resources may include memory, processing time, access to transceivers 1012a, 1012b, user interface 1018, etc.

[0086] One or more processors 1004 of the processing circuitry 1002 can be multifunctional, whereby some software modules in software module 1016 are loaded and configured to perform different functions or different instances of the same function. One or more processors 1004 may also be adapted to manage background tasks initiated in response to inputs, such as from user interface 1018, transceivers 1012a, 1012b, and device drivers. To support the execution of multiple functions, one or more processors 1004 may be configured to provide a multitasking environment, whereby each of the multiple functions is implemented as a set of tasks in a corresponding context, which is serviced by one or more processors 1004 as needed or desired. In one example, the multitasking environment may be implemented using a time-sharing program 1020 that transfers control of the processors 1004 between different tasks, whereby each task returns control of the one or more processors 1004 to the time-sharing program 1020 upon completion of any incomplete operation and / or in response to inputs such as interrupts. When a task has control over one or more processors 1004, the processing circuitry operates in the corresponding context and is effectively dedicated to the purpose addressed by the function associated with the control task. The time-sharing program 1020 may include an operating system, a main loop that transmits control on a loop-based basis, a function that allocates control of one or more processors 1004 according to function priority, and / or an interrupt-driven main loop that provides control of one or more processors 1004 to processing functions in response to external events.

[0087] In one example, processing circuitry 1002 may be used to implement calibration circuitry or perform functions related to calibration circuitry. Calibration circuitry may include a replica summing circuit, a replica sampling circuit, and control circuitry. The replica summing circuit may be a replica of the summing circuitry in the SerDes interface and may be configured to provide a summer output signal representing the common-mode voltage at the input of the SerDes interface. The replica sampling circuit may be a replica of the sampling circuitry in the SerDes interface. The replica sampling circuit may include: a first input transistor having a gate coupled to the summer output signal; and a second input transistor configured to provide an internal reference voltage at its drain. The drain of the second input transistor may be coupled to its gate. Control circuitry may be configured to control current flow in the replica summing circuitry in response to a calibration signal output by the replica sampling circuitry.

[0088] In some cases, the summer output signal has a voltage level defined by the integral of the current flow in the replica summing circuit over a time period. This time period can be defined by a clock signal.

[0089] In some implementations, the current flow in the replica summing circuit is controlled by a current source configured with a calibration code provided by the control circuit. The current source can also be configured based on tap coefficients defined for the decision feedback equalizer.

[0090] In some implementations, the control circuitry is also configured to control the current flow in the summing circuit of the SerDes interface in response to a calibration signal output from the replica sampling circuitry. The control circuitry can also be configured to ensure that the same level of current flows in both the replica summing circuitry and the summing circuitry in the SerDes interface.

[0091] Figure 11 This is a flowchart illustrating an example of a method 1100 for calibrating a summing circuit in a high-speed SerDes interface. In one example, the replica sampling circuit uses an internal reference voltage and generates a calibration signal based on a comparison of the internal reference voltage with the common-mode voltage at the input of the SerDes interface. The calibration signal can be used to calibrate a current source that controls the current in the replica summing circuit. The replica sampling circuit and the replica summing circuit can be incorporated into the calibration circuitry. Certain aspects of the calibration circuitry may correspond to... Figure 7 The illustrated calibration circuit 700, and certain aspects of the replica sampling circuit, may correspond to... Figure 9 The illustrated copy sampling circuit 900. Certain parts of method 1100 can be used. Figure 10 The illustrated processing circuit 1002 performs this operation.

[0092] At block 1102, a copy of the summing circuitry in the SerDes interface can be used to generate a summer output signal. The summer output signal can represent the common-mode voltage at the input of the SerDes interface. At block 1104, the summer output signal can be compared with an internal reference voltage in a copy of the sampling circuitry in the SerDes interface. The copy of the sampling circuitry can include a first input transistor and a diode-connected second input transistor, the first input transistor having a gate coupled to the summer output signal, and the diode-connected second input transistor being configured to provide an internal reference voltage at its drain. The drain of the second input transistor can be coupled to the gate of the second input transistor. At block 1106, current flow in the copy of the summing circuitry can be controlled in response to a calibration signal output by the copy of the sampling circuitry.

[0093] In some cases, the summer output signal has a voltage level defined by the integral of the current flow in a replica of the summing circuit over a time period. This time period can be defined by a clock signal.

[0094] In some implementations, the current flow in a copy of the summing circuit can be controlled by configuring the current source using calibration codes. The current flow in a copy of the summing circuit can also be controlled by configuring the current source based on tap coefficients defined for the decision feedback equalizer.

[0095] In some implementations, the current flow in the summing circuit of the SerDes interface can be controlled in response to a calibration signal output from the replica sampling circuit. In some instances, the same level of current can flow in both the replica summing circuit and the summing circuit in the SerDes interface.

[0096] The operational steps described in any exemplary aspect of this document are described to provide a subset of examples of possible specific implementations. The described operations may be performed in numerous different orders other than the illustrated order. Furthermore, the operations described in a single operational step may actually be performed in multiple different steps. In addition, one or more operational steps discussed in the exemplary aspects may be combined. It will be understood that, as will be apparent to those skilled in the art, numerous different modifications may be made to the operational steps illustrated in the flowcharts. Those skilled in the art will also understand that any of a variety of different techniques and arts can be used to represent information and signals. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be mentioned throughout the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or optical particles, or any combination thereof.

[0097] The various operations of the methods described above can be performed by any suitable component capable of performing the corresponding function. This component can include various hardware and / or software components and / or modules, including but not limited to circuits, application-specific integrated circuits (ASICs), or processors. Generally, in the presence of operations illustrated in the accompanying drawings, those operations may have corresponding components with similar numbering, plus functional components.

[0098] In some aspects, an apparatus includes components for generating a summer output signal representing a common-mode voltage at an input of a SerDes interface. The components for generating the summer output signal may include a copy of the summing circuitry disposed within the SerDes interface. The apparatus may include components for comparing the summer output signal with an internal reference voltage in a copy of the sampling circuitry in the SerDes interface. The internal reference voltage may be provided by a diode-connected transistor. The apparatus may include components for controlling current flow in the copy of the summing circuitry based on a calibration signal output from the copy of the sampling circuitry.

[0099] In some cases, the summer output signal has a voltage level defined by the integral of the current flow in a replica of the summing circuit over a time period. This time period can be defined by a clock signal.

[0100] In some implementations, the components used to control the current flow in a copy of the summing circuit include current sources configured using calibration codes. The components used to control the current flow in a copy of the summing circuit may include current sources configured based on tap coefficients defined for the decision feedback equalizer.

[0101] In some implementations, the current flow in the summing circuit of the SerDes interface is configured or adjusted in response to a calibration signal output from the replica sampling circuit. This allows the same level of current to flow in both the replica summing circuit and the summing circuit in the SerDes interface.

[0102] Some specific implementation examples are described in the following numbered clauses: 1. A calibration circuit comprising: a replica summing circuit, the replica summing circuit being a replica of a summing circuit in a serializer / deserializer (SerDes) interface and configured to provide a summer output signal representing a common-mode voltage at an input of the SerDes interface; a replica sampling circuit, the replica sampling circuit being a replica of a sampling circuit in the SerDes interface and comprising: a first input transistor having a gate coupled to the summer output signal; a second input transistor configured to provide an internal reference voltage at its drain, the drain of the second input transistor being coupled to its gate; and a control circuit configured to control current flow in the replica summing circuit in response to a calibration signal output by the replica sampling circuit.

[0103] 2. The calibration circuit according to Clause 1, wherein the summer output signal has a voltage level defined by the integral of the current flow in the replica summing circuit over a time period.

[0104] 3. The calibration circuit according to Clause 2, wherein the time period is defined by a clock signal.

[0105] 4. The calibration circuit according to any one of clauses 1 to 3, wherein the current flow in the copy summing circuit is controlled by a current source configured by a calibration code provided by the control circuit.

[0106] 5. The calibration circuit according to Clause 4, wherein the current flow in the replica summing circuit is controlled by a current source configured based on tap coefficients defined for the decision feedback equalizer.

[0107] 6. The calibration circuit according to any one of clauses 1 to 5, wherein the control circuit is further configured to control the current flow in the summing circuit of the SerDes interface in response to the calibration signal output by the copy sampling circuit.

[0108] 7. The calibration circuit according to any one of clauses 1 to 6, wherein the control circuit is further configured to allow the same level of current to flow in the copy summing circuit and the summing circuit in the SerDes interface.

[0109] 8. An apparatus comprising: means for generating a summer output signal representing a common-mode voltage at an input of a serializer / deserializer (SerDes) interface, the means including a copy of a summing circuit disposed in the SerDes interface; means for comparing the summer output signal with an internal reference voltage in a copy of a sampling circuit in the SerDes interface, the internal reference voltage being provided by a diode-connected transistor; and means for controlling current flow in the copy of the summing circuit based on a calibration signal output by the copy sampling circuit.

[0110] 9. The apparatus according to Clause 8, wherein the summer output signal has a voltage level defined by the integration of the current flow in the copy of the summing circuit over a time period defined by a clock signal.

[0111] 10. The apparatus according to Clause 8 or Clause 9, wherein the component for controlling the current flow in the copy of the summing circuit comprises: a current source configured using a calibration code.

[0112] 11. The apparatus according to any one of clauses 8 to 10, wherein the component for controlling the current flow in the copy of the summing circuit comprises a current source configured based on tap coefficients defined for a decision feedback equalizer.

[0113] 12. The apparatus according to any one of clauses 8 to 11, wherein the current flow in the summing circuit of the SerDes interface is configured or adjusted in response to the calibration signal output by the copy sampling circuit.

[0114] 13. The apparatus according to any one of clauses 8 to 12, wherein the same level of current flows in the copy of the summing circuit and in the summing circuit of the SerDes interface.

[0115] 14. A method for calibrating a summing circuit, the method comprising: generating a summer output signal using a copy of the summing circuit in a serializer / deserializer (SerDes) interface, the summer output signal representing a common-mode voltage at an input of the SerDes interface; comparing the summer output signal with an internal reference voltage in a copy of a sampling circuit in the SerDes interface, the copy of the sampling circuit including: a first input transistor having a gate coupled to the summer output signal; and a second input transistor configured to provide the internal reference voltage at its drain, the drain of the second input transistor being coupled to its gate; and controlling current flow in the copy of the summing circuit in response to a calibration signal output by the copy of the sampling circuit.

[0116] 15. The method according to Clause 14, wherein the summer output signal has a voltage level defined by the integration of the current flow in the copy of the summing circuit over a time period.

[0117] 16. The method according to Clause 15, wherein the time period is defined by a clock signal.

[0118] 17. The method according to any one of clauses 14 to 16, wherein controlling the current flow in the copy of the summing circuit comprises: configuring the current source using a calibration code.

[0119] 18. The method according to any one of Clauses 14 to 17, wherein controlling the current flow in the copy of the summing circuit comprises: configuring the current source based on tap coefficients defined for the decision feedback equalizer.

[0120] 19. The method according to any one of Clauses 14 to 18, the method further comprising: controlling the current flow in the summing circuit of the SerDes interface in response to the calibration signal output by the replica sampling circuit.

[0121] 20. The method according to any one of clauses 14 to 19, the method further comprising: causing current of the same level to flow in the summing circuit of the copy of the summing circuit and the summing circuit of the SerDes interface.

[0122] 21. A calibration circuit comprising: a replica summer including a pair of summing input transistors, each summing input transistor having: a gate configured to receive an input signal representing a common-mode voltage input to an analog front-end circuit; a drain coupled to a summer output signal; and a source coupled to at least one summer source transistor configured to control current flowing in the pair of summing input transistors; and a replica sampling circuit having a pair of sampling input transistors including a first sampling input transistor comprising: a gate configured to receive the summer output signal; a source coupled to a sampling source transistor configured to control current flowing in each of the sampling input transistors; and a drain coupled to a first feedback signal; wherein a second sampling input transistor is a diode-connected transistor having a gate and a drain coupled to a second feedback signal.

[0123] 22. The calibration circuit according to Clause 21, wherein the first feedback signal and the second feedback signal are provided as differential inputs to a current source control circuit having a control output coupled to the gate of the at least one summer source transistor.

[0124] 23. The calibration circuit according to Clause 22, wherein the current source control circuit includes a current source configured using a calibration code.

[0125] 24. The calibration circuit according to Clause 22 or Clause 23, wherein the current source control circuit includes a current source configured based on tap coefficients defined for the decision feedback equalizer.

[0126] 25. The calibration circuit according to any one of clauses 21 to 24, wherein the replica summing circuit is at least a partial replica of the current summer of the serializer / deserializer (SerDes) interface, and wherein the replica sampling circuit is at least a partial replica of the sampler of the SerDes interface.

[0127] 26. The calibration circuit according to Clause 25, wherein current of the same level flows in a corresponding pair of transistors in the pair of summing input transistors and the current summer of the SerDes interface.

[0128] As used in this article, the phrase “at least one of” in a list of items refers to any combination of those items, including a single member. For example, “at least one of a, b, or c” is intended to cover a, b, c, ab, ac, bc, and abc, as well as any combination with multiple identical elements (e.g., aa, aaa, aab, aac, abb, acc, bb, bbb, bbb, bbc, cc, and ccc, or any other ordering of a, b, and c).

[0129] This disclosure is provided so that any person skilled in the art can make or use various aspects of it. Various modifications to this disclosure will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not intended to be limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A calibration circuit, the calibration circuit comprising: A replica summing circuit, which is a replica of the summing circuit in the serializer / deserializer (SerDes) interface and is configured to provide a summer output signal representing the common-mode voltage at the input of the SerDes interface; A replica sampling circuit, which is a replica of the sampling circuit in the SerDes interface and includes: A first input transistor having a gate coupled to the output signal of the summer; and A second input transistor, configured to provide an internal reference voltage at its drain, the drain of which is coupled to the gate of the second input transistor; and A control circuit configured to control the current flow in the replica summing circuit in response to a calibration signal output by the replica sampling circuit.

2. The calibration circuit of claim 1, wherein the summer output signal has a voltage level defined by the integral of the current flow in the replica summing circuit over a time period.

3. The calibration circuit according to claim 2, wherein the time period is defined by a clock signal.

4. The calibration circuit of claim 1, wherein the current flow in the replica summation circuit is controlled by a current source configured by a calibration code provided by the control circuit.

5. The calibration circuit of claim 4, wherein the current flow in the replica summing circuit is controlled by a current source configured based on tap coefficients defined for the decision feedback equalizer.

6. The calibration circuit of claim 1, wherein the control circuit is further configured to control the current flow in the summing circuit of the SerDes interface in response to the calibration signal output by the replica sampling circuit.

7. The calibration circuit of claim 6, wherein the control circuit is further configured to allow the same level of current to flow in the summing circuit in the copy summing circuit and the summing circuit in the SerDes interface.

8. A calibration circuit, the calibration circuit comprising: A replica summer, comprising a pair of summation input transistors, each summation input transistor having: A gate, configured to receive an input signal representing a common-mode voltage input to an analog front-end circuit. The drain, which is coupled to the summer output signal, and The source is coupled to at least one summer source transistor, which is configured to control the current flowing in the pair of summer input transistors; and A replica sampling circuit having a pair of sampling input transistors, the pair of sampling input transistors including a first sampling input transistor, the first sampling input transistor comprising: A gate, configured to receive the output signal of the summer. The source, coupled to a sampling source transistor, is configured to control the current flowing in each of the sampling input transistors. The drain, which is coupled to the first feedback signal, The second sampling input transistor is a diode-connected transistor, which has a gate and a drain coupled to the second feedback signal.

9. The calibration circuit of claim 8, wherein the first feedback signal and the second feedback signal are provided as differential inputs to a current source control circuit, the current source control circuit having a control output coupled to the gate of the at least one summer source transistor.

10. The calibration circuit according to claim 9, wherein the current source control circuit comprises: A current source configured using a calibration code.

11. The calibration circuit according to claim 9, wherein the current source control circuit comprises: A current source configured based on tap coefficients defined for a decision feedback equalizer.

12. The calibration circuit of claim 8, wherein the replica summing circuit is at least a partial replica of the current summer of the serializer / deserializer (SerDes) interface, and wherein the replica sampling circuit is at least a partial replica of the sampler of the SerDes interface.

13. The calibration circuit of claim 12, wherein current of the same level flows in corresponding pairs of transistors in the pair of summing input transistors and the current summer of the SerDes interface.

14. A method for calibrating a summing circuit, the method comprising: A copy of the summing circuit in the serializer / deserializer (SerDes) interface is used to generate the summer output signal, which represents the common-mode voltage at the input of the SerDes interface. The summer output signal is compared with an internal reference voltage in a copy of the sampling circuit in the SerDes interface, the copy of the sampling circuit including a first input transistor and a second input transistor, the first input transistor having a gate coupled to the summer output signal, the second input transistor being configured to provide the internal reference voltage at its drain, the drain of the second input transistor being coupled to the gate of the second input transistor; as well as The current flow in the copy of the summing circuit is controlled in response to a calibration signal output by the copy of the sampling circuit.

15. The method of claim 14, wherein the summer output signal has a voltage level defined by the integral of the current flow in the copy of the summing circuit over a time period.

16. The method of claim 15, wherein the time period is defined by a clock signal.

17. The method of claim 14, wherein controlling the current flow in the copy of the summing circuit comprises: Configure the current source using the calibration code.

18. The method of claim 14, wherein controlling the current flow in the copy of the summing circuit comprises: The current source is configured based on the tap coefficients defined for the decision feedback equalizer.

19. The method of claim 14, further comprising: The current flow in the summing circuit of the SerDes interface is controlled in response to the calibration signal output by the replica sampling circuit.

20. The method of claim 14, further comprising: The same level of current flows in the summing circuit of the copy of the summing circuit and the summing circuit of the SerDes interface.

Images