Stacked mram with super via structure

Abstract

A memory structure is provided, comprising a first level and a second level. The first level includes a plurality of first magnetoresistive random access memory (MRAM) cells, and the second level includes a plurality of second MRAM cells. Each second MRAM cell is located above and horizontally offset from each first MRAM cell. Each first MRAM cell is sandwiched between a bottom conductive via structure and a top conductive via structure, and each second MRAM cell is sandwiched between the bottom conductive via structure and the top conductive via structure.

Description

Background Technology

[0001] This application relates to semiconductor technology, and more particularly to non-volatile random access memory.

[0002] Magnetoresistive random access memory (MRAM) is a non-volatile random access memory technology in which data is stored by magnetic storage elements. These elements are typically formed by two ferromagnetic plates, each of which can be kept magnetized, separated by a thin dielectric layer (i.e., a tunneling barrier layer). One of the plates (i.e., the magnetic reference layer or pin layer) is a magnet with its magnetic moment direction set in a specific orientation; the magnetization of the other plate (i.e., the magnetic free layer) can be changed in at least two different directions, thus representing different digital states (such as 0 and 1) for memory applications. In MRAM, such an element can be called a magnetic tunnel junction (MTJ) structure. In a typical MTJ structure, the magnetization of the magnetic reference layer is fixed in one direction (e.g., pointing upwards), while the orientation of the magnetic free layer can be "switched" by some external force (such as a spin-transfer torque or magnetic field that generates a charge current). A small current (of any polarity) can be used to read the resistance of the device, which depends on the relative orientation of the magnetization of the magnetic free layer and the magnetic reference layer. The resistance is typically high when the magnetization is antiparallel, and low when they are parallel (although this can be reversed depending on the material).

[0003] One type of MRAM that can use the MTJ structure is Spin-Torque (STT) MRAM. Compared to conventional MRAM that uses a magnetic field to flip active elements, STT MRAM offers advantages such as lower power consumption and better scalability. In STT MRAM, spin-torque is used to flip (switch) the orientation of the magnetic free layer. For STT MRAM devices, the bit state of the MTJ memory element is switched or “written” using a current flowing through the MTJ structure. A current flowing downward through the MTJ structure makes the magnetic free layer parallel to the magnetic reference layer, while a current flowing upward through the MTJ structure makes the magnetic free layer antiparallel to the magnetic reference layer. Summary of the Invention

[0004] A memory structure is provided, comprising: a first level including a plurality of first MRAM cells; and a second level including a plurality of second MRAM cells. Each second MRAM cell is located above and horizontally offset from each first MRAM cell. Each first MRAM cell is sandwiched between a bottom conductive via structure and a top conductive supervia structure, and each second MRAM cell is sandwiched between the bottom conductive supervia structure and the top conductive via structure. In this application, the height (i.e., vertical length) of the conductive supervia structure is greater than the height of the normal conductive via structure.

[0005] In one aspect of this application, a memory structure is provided. In one embodiment of this application, the memory structure includes a first level comprising a plurality of first MRAM cells, wherein each of the plurality of first MRAM cells has a bottom surface in electrical contact with a first conductive via structure and a top surface in electrical contact with a second conductive via structure. The memory structure further includes a second level comprising a plurality of second MRAM cells, wherein each of the plurality of second MRAM cells is located above and horizontally offset from each of the plurality of first MRAM cells, wherein each of the plurality of second MRAM cells has a bottom surface in electrical contact with the first conductive via structure and a top surface in electrical contact with the second conductive via structure.

[0006] In another aspect of this application, a method for forming a memory structure is provided. In one embodiment, the method includes forming an interconnect layer having a plurality of conductive wiring structures embedded in an interconnect dielectric layer. Next, a first conductive structure is formed that is electrically contacted with every other conductive wiring structure of the plurality of conductive wiring structures. Then, a plurality of first MRAM cells are formed in the first layer, wherein each of the plurality of first MRAM cells has a bottom surface that is electrically contacted with one of the first conductive via structures. Next, a first conductive supervia structure is formed that is electrically contacted with the conductive wiring structure on which the first conductive via structure is not present. Then, a plurality of second MRAM cells are formed in a second layer located above the first layer, wherein each of the plurality of second MRAM cells is located above and horizontally offset from each of the plurality of first MRAM cells. After forming the second MRAM cells, a plurality of second conductive supervia structures are formed that are electrically contacted with the top surface of each of the plurality of first MRAM cells, and a plurality of second conductive via structures are formed that are electrically contacted with the top surface of each of the plurality of second MRAM cells. Attached Figure Description

[0007] Figure 1 This is a cross-sectional view of an exemplary structure that can be used according to embodiments of this application, the exemplary structure including an interconnect layer including conductive wiring structures embedded in a first interconnect dielectric layer.

[0008] Figure 2 This occurs after forming a dielectric capping layer on top of the interconnect layer and a second interconnect dielectric layer containing the first conductive via structure. Figure 1 A cross-sectional view of the exemplary structure shown.

[0009] Figure 3This is done after each first conductive via structure is recessed. Figure 2 A cross-sectional view of the exemplary structure shown.

[0010] Figure 4 This occurs after the first electrode material layer is formed on the surface of the second interconnect dielectric layer and on the surface of each recessed first conductive via structure. Figure 3 A cross-sectional view of the exemplary structure shown.

[0011] Figure 5 This is achieved after removing the first electrode material layer from the surface of the second interconnect dielectric layer while maintaining the first electrode material layer on the surface of each recessed first conductive via structure. Figure 4 The cross-sectional view of the exemplary structure shown shows that the retained first electrode material layer provides the first electrode.

[0012] Figure 6 This occurs after the first MTJ stack and the second electrode material layer are formed on top of the second interconnect dielectric layer. Figure 5 A cross-sectional view of the exemplary structure shown.

[0013] Figure 7 This is after patterning the second electrode material layer and the first MTJ stack to provide the second electrode and the first MTJ structure respectively, and forming the first encapsulation layer. Figure 6 A cross-sectional view of the exemplary structure shown.

[0014] Figure 8 This occurs after the formation of the third interconnect dielectric layer. Figure 7 A cross-sectional view of the exemplary structure shown.

[0015] Figure 9 This occurs after the formation of the first conductive supervia structure and the formation of the third electrode on the surface of the first conductive supervia structure. Figure 8 A cross-sectional view of the exemplary structure shown.

[0016] Figure 10 This occurs after the second MTJ structure and the fourth electrode are formed on top of the third electrode, and after the second encapsulation layer is formed. Figure 9 A cross-sectional view of the exemplary structure shown.

[0017] Figure 11 This occurs after the formation of the fourth interconnect dielectric layer. Figure 10 A cross-sectional view of the exemplary structure shown.

[0018] Figure 12 This occurs after additional interconnect dielectric material is formed on the fourth interconnect dielectric layer. Figure 11The cross-sectional view of the exemplary structure shown indicates that the additional dielectric material and the fourth dielectric layer together provide an uppermost interconnect dielectric layer covering the entire second encapsulation layer (including the portion of the second encapsulation layer located on top of the fourth electrode), and supervias and normal vias are formed in the uppermost interconnect dielectric layer.

[0019] Figure 13 This occurs after physically exposing each of the second and fourth electrodes. Figure 12 A cross-sectional view of the exemplary structure shown.

[0020] Figure 14 This is after a conductive layer has been formed on the surface of the uppermost interconnect dielectric layer and on the physically exposed surfaces of each of the second and fourth electrodes. Figure 13 A cross-sectional view of the exemplary structure shown.

[0021] Figure 15 This is done after removing the conductive layer from the surface of the uppermost interconnecting dielectric layer while maintaining the conductive layer on the physically exposed surfaces of each of the second and fourth electrodes. Figure 14 A cross-sectional view of the exemplary structure shown.

[0022] Figure 16 This is a top view depicting an MRAM array according to an embodiment of this application. Detailed Implementation

[0023] This application will now be described in more detail with reference to the following discussion and accompanying drawings. Note that the drawings are provided for illustrative purposes only and are therefore not drawn to scale. Also note that similar and corresponding elements are indicated by similar reference numerals.

[0024] In the following description, numerous specific details, such as particular structures, components, materials, dimensions, processing steps, and techniques, are set forth in order to provide an understanding of various embodiments of this application. However, those skilled in the art will recognize that various embodiments of this application can be practiced without these specific details. In other instances, well-known structures or processing steps have not been described in detail to avoid obscuring this application.

[0025] It will be understood that when a component (such as a layer, region, or substrate) is referred to as being "on" or "above" another component, it can be directly on the other component, or there may be intermediate components present. In contrast, when a component is referred to as being "directly on" or "above" another component, there are no intermediate components. It will also be understood that when a component is referred to as being "below" or "under" another component, it can be directly below or under the other component, or there may be intermediate components present. In contrast, when a component is referred to as being "directly below" or "under" another component, there are no intermediate components.

[0026] The terms “substantially,” “substantially similar,” “approximately,” or any other term indicating functional equivalence or similarity, refer to situations where differences in length, height, or orientation do not result in an actual difference between substantially similar variants that are explicitly stated (e.g., a phrase without the term “substantially similar”). In one embodiment, “substantially” (and its derivatives) means a difference due to generally accepted engineering or manufacturing tolerances of similar devices, such as a deviation of values ​​not exceeding 10% or a deviation of angles not exceeding 10°.

[0027] As the complexity of MTJ stacks continues to evolve, ion beam etching (IBE) has become the dominant patterning scheme for MRAMs. With MRAM pitch scaling towards higher-order nodes, MRAM patterning and reducing partial short circuits in the array become increasingly challenging due to the limitations of high-angle IBE (required for cleaning resputtered metal on the MTJ sidewalls) resulting from the shading of adjacent MTJ structures. Solutions to these problems are desired.

[0028] This paper proposes a stacked 1-transistor (1T) 1-MTJ MRAM method as a solution to the above problems. Notably, in this 1T 1MTJ MRAM method, the memory array is divided into two levels, which doubles the spacing between adjacent MTJ structures on the same level. This doubling of spacing, in turn, alleviates and, in some cases even eliminates, the barrier associated with resputtering metal on the sidewalls of the clean MTJ structures, which is typically observed at close MTJ spacing.

[0029] In the memory array of this application, doubling the spacing between adjacent MTJ structures on the same level provides an improved IBE patterning process window to clean the re-deposited metal on the sidewalls of the MTJ structures, which in turn reduces partial short circuits in the memory array. Furthermore, by targeting a 1T MTJ design at a speed maintained, MTJ density can be enhanced due to the horizontal offset provided by the second-level MTJ structure. Moreover, wiring resistance is maintained for both the first and second-level MTJ structures in this application; similar access resistance is provided for both levels. Additionally, this application provides a reduced level of photolithographic patterning to provide a two-level memory structure.

[0030] In one aspect of this application and as Figure 15 As shown, a memory structure is provided. In one embodiment of this application, the memory structure includes a first level (L1-MTJ) comprising a plurality of first MRAM cells, wherein each of the plurality of first MRAM cells has a bottom surface electrically contacting a first conductive via structure 22 and a top surface electrically contacting a second conductive supervia structure 52A. The memory structure also includes a second level (L2-MTJ) comprising a plurality of second MRAM cells, wherein each of the plurality of second MRAM cells is located above and horizontally offset from each of the plurality of first MRAM cells, wherein each of the plurality of second MRAM cells has a bottom surface electrically contacting a first conductive supervia structure 36 and a top surface electrically contacting a second conductive via structure 52B. Throughout this application, the conductive via structure is a normal via structure having a first height (i.e., vertical length), and the conductive supervia structure is a via structure having a second height (i.e., vertical length) greater than the first height. Such a memory structure exhibits an improved IBE patterning process window to clean the re-deposited metal on the sidewalls of the MTJ structure, which in turn reduces partial short circuits in the memory array and enhances MTJ density due to the horizontal offset provided by the second-level MTJ structure.

[0031] In some embodiments of this application (see, for example) Figure 15 The first conductive via structure 22 and the first conductive supervia structure 36 have substantially coplanar bottom surfaces, and the second conductive supervia structure 52A and the second conductive via structure 52B have substantially coplanar top surfaces. In such an embodiment, the wiring distance d1+d2 provided by the combination of the first conductive via structure 22 and the second conductive supervia structure 52A is substantially equal to the wiring distance d3+d4 provided by the combination of the first conductive supervia structure 36 and the second conductive via structure 52B. In the case where the combination of the first conductive via structure 22 and the second conductive supervia structure 52A exhibits substantially equal wiring distances (i.e., d1+d2 is substantially equal to d3+d4) with the combination of the first conductive supervia structure 36 and the second conductive via structure 52B, the combination of the first conductive via structure 22 and the second conductive supervia structure 52A is symmetrical to the combination of the first conductive supervia structure 36 and the second conductive via structure 52B. The symmetry between the combination of the first conductive via structure 22 and the second conductive supervia structure 52A and the combination of the first conductive supervia structure 36 and the second conductive via structure 52B ensures that the wiring resistance of the first and second level MTJ structures is equal. Therefore, similar access resistance is provided for both levels.

[0032] In some embodiments of this application (see, for example) Figure 15 Each of the plurality of first MRAM cells includes a first electrode 24, a first MTJ structure 26, and a second electrode 28.

[0033] In some embodiments of this application (see, for example) Figure 15 The first electrode 24 is in electrical contact with the first conductive through-hole structure 22, and the second electrode 28 is in electrical contact with the second conductive super-through-hole structure 52A.

[0034] In some embodiments of this application (see, for example) Figure 15 Each of the plurality of second MRAM cells includes a third electrode 38, a second MTJ structure 40, and a fourth electrode 42.

[0035] In some embodiments of this application (see, for example) Figure 15 The third electrode 38 is in electrical contact with the first conductive super-through hole structure 36, and the fourth electrode 42 is in electrical contact with the second conductive through hole structure 52B.

[0036] In some embodiments of this application (see, for example) Figure 15 The first conductive via structure 22 is in electrical contact with the conductive wiring structure 14, and the first conductive super-through structure 36 is in contact with another conductive wiring structure ( Figure 15 The intermediate conductive structure 14 shown is an electrical contact.

[0037] In some embodiments of this application (see, for example) Figure 15 Both the first electrode 24 and the third electrode 38 have a top surface that is connected to the sidewall via an inclined plane.

[0038] In some embodiments of this application, both the first MTJ structure 26 and the second MTJ structure 40 include a tunneling barrier layer sandwiched between the magnetic reference layer and the magnetic free layer. In some embodiments of this application, the magnetic free layer is located above the magnetic reference layer. In other embodiments of this application, the magnetic free layer is located below the magnetic reference layer.

[0039] In some embodiments of this application, the memory structure may further include diffusion barrier pads (see, for example, second diffusion barrier pad 20, third diffusion barrier pad 34 and fourth diffusion barrier pad 50) present along the sidewalls of each of the first conductive via structure 22, the first conductive supervia structure 36, the second conductive via structure 52B and the second conductive supervia structure 52A.

[0040] In some embodiments of this application (see, for example) Figure 15The memory structure may further include a first package pad 30L located near each of the plurality of first MRAM cells. In some embodiments of this application, the memory structure may even include a second package pad 44L located near each of the plurality of second MRAM cells.

[0041] In some embodiments of this application (see, for example) Figure 15 Multiple first MRAM cells exist in a different interconnect layer than multiple second MRAM cells.

[0042] In another aspect of this application (see, for example) Figures 1 to 15 A method for forming a memory structure is provided. In one embodiment, the method includes forming an interconnect level having a plurality of conductive wiring structures embedded in an interconnect dielectric layer. Next, a first conductive structure is formed that is electrically contacted with every other conductive wiring structure of the plurality of conductive wiring structures. Then, a plurality of first MRAM cells are formed in the first level, wherein each of the plurality of first MRAM cells has a bottom surface that is electrically contacted with one of the first conductive via structures. Next, a first conductive supervia structure is formed that is electrically contacted with a conductive wiring structure that does not have a first conductive via structure thereon. Then, a plurality of second MRAM cells are formed in a second level located above the first level, wherein each of the plurality of second MRAM cells is located above and horizontally offset from each of the plurality of first MRAM cells. After forming the second MRAM cells, a plurality of second conductive supervia structures are formed that are electrically contacted with the top surface of each of the plurality of first MRAM cells, and a plurality of second conductive via structures are formed that are electrically contacted with the top surface of each of the plurality of second MRAM cells.

[0043] These and other aspects of this application will now be described in more detail. Note that the accompanying drawings of this application illustrate memory device regions in which memory structures such as, for example, MRAM arrays will be formed. Non-memory device regions may be laterally located near the memory device regions shown in the accompanying drawings of this application. In this application, the memory structure will be formed in a back-end process (BEOL). The memory structure of this application can be used in various memory applications, including, for example, as an STTMRAM device.

[0044] First refer to Figure 1 The illustration shows exemplary structures that can be used according to embodiments of this application. Figure 1 The exemplary structure shown includes an interconnect layer that includes conductive wiring structures 14 embedded in a first interconnect dielectric layer 10. In some embodiments, and as shown in the figure... Figure 1As shown, a first diffusion barrier pad 12 may be present at least along the sidewall of each conductive wiring structure 14.

[0045] Figure 1 The interconnect levels illustrated herein may be located above at least one bottom metal level (not shown) and a front-end process (FEOL) level (also not shown). In some embodiments, the metal level may be an intermediate process (MOL) level. In other embodiments, the metal level may be at least one lower interconnect level of a multi-level interconnect structure. In further embodiments, the metal level may be a combination of an MOL level and at least one lower interconnect level of a multi-level interconnect structure. The metal level may include conductive wiring structures embedded in a dielectric material layer. The FEOL level may include a semiconductor substrate on which one or more semiconductor devices (such as transistors) are formed. The metal level and FEOL level may be formed using materials and techniques well known to those skilled in the art. To avoid obscuring the memory structure of this application, the materials and techniques used in providing the metal level and FEOL level are not described herein.

[0046] The first interconnect dielectric layer 10 may be composed of any interconnect dielectric material, including, for example, silicon dioxide, silsesquioxane, C-doped oxide (i.e., organosilicon), thermosetting polyarylene ether, or a multilayer structure thereof, wherein the C-doped oxide comprises atoms of Si, C, O, and H. The term "polyarylene" is used in this application to refer to aryl groups or inertly substituted aryl groups linked together by bonds, fused rings, or inert linking groups (such as, for example, oxygen, sulfur, sulfone, sulfoxide, carbonyl, etc.). The first interconnect dielectric layer 10 may be formed using a deposition process such as, for example, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), or spin coating.

[0047] The optional first diffusion barrier pad 12 is composed of a diffusion barrier material, such as, for example, Ta, TaN, Ti, TiN, Ru, RuN, RuTa, RuTaN, W, WN, or any other material that can be used as a barrier layer to prevent the diffusion of conductive material. The thickness of the first diffusion barrier pad 12 can vary. In one example, the thickness of the first diffusion barrier pad 12 is from 2 nm to 50 nm.

[0048] Each conductive wiring structure 14 is composed of a conductive metal or a conductive metal alloy. The conductive metal provided for each conductive wiring structure 14 may include, for example, copper (Cu), aluminum (Al), tungsten (W), cobalt (Co), ruthenium (Ru), nickel (Ni), iridium (Ir), or rhodium (Rh). Examples of conductive alloys provided for each conductive wiring structure 14 include Cu-Al alloys. The conductive wiring structure 14 may have metal wires, metal vias, or other similar features. Figure 1 The shape of the combination of metal wire and metal through hole shown.

[0049] The conductive wiring structure 14 can be formed using a damascene process well known to those skilled in the art. For example, the damascene process may include forming openings in the first interconnect dielectric layer 10. The openings can be formed by photolithography and etching. Photolithography includes forming a photoresist material on a stack of layers or material layers that need to be patterned, exposing the photoresist material to a desired illumination pattern, and subsequently developing the exposed photoresist material using a conventional photoresist developer. The developed photoresist material has the desired pattern, which is then transferred to the stack of layers or material layers that need to be patterned by etching. Etching may include dry etching and / or chemical wet etching. In one embodiment, a dry etching method (such as, for example, reactive ion etching (RIE), ion beam etching (IBE), plasma etching, or any combination thereof) can be used to transfer the pattern to the stack of layers or material layers that need to be patterned. In the illustrated embodiment, the etching etches through the entire first interconnect dielectric layer 10. In another embodiment, the etching may stop within the subsurface of the first interconnect dielectric layer 10. The developed photoresist material can be removed at any time after etching (including the initial etching or the entire etching process) using a conventional photoresist removal process.

[0050] If a first diffusion barrier liner 12 is present, the damascene process continues by forming a layer of one of the aforementioned diffusion barrier materials on the surface of the first interconnect dielectric layer 10 and within each opening. This layer of one of the aforementioned diffusion barrier materials can be formed by deposition processes, including, for example, CVD, PECVD, atomic layer deposition (ALD), physical vapor deposition (PVD), sputtering, chemical solution deposition, or plating. In some embodiments not shown, an optional plating seed layer can be formed on top of the diffusion barrier material layer, or, if the first diffusion barrier liner 12 is not used, an optional plating seed layer can be formed on the surface of the first interconnect dielectric layer 10 and within each opening. The optional plating seed layer can consist of Cu, Cu alloys, Ir, Ir alloys, Ru, Ru alloys (e.g., TaRu alloys), or any other suitable noble metal or noble metal alloy with a low metal plating overpotential. Typically, a Cu or Cu alloy plating seed layer is used when Cu metal is subsequently formed within at least one opening. The optional plating seed layer can have a thickness from 2 nm to 80 nm. Optional plating seed layers can be formed using conventional deposition processes, including, for example, CVD, PECVD, ALD, or PVD. Conductive metals or conductive metal alloys (all as described above) are formed in each opening formed in the first interconnect dielectric layer 10 and outside each opening. The conductive metals or conductive metal alloys can be formed using deposition processes such as, for example, CVD, PECVD, sputtering, chemical solution deposition, or plating. In one embodiment, a bottom-up plating process is used when forming the conductive metals or conductive metal alloys. After these various depositions, planarization processes (such as, for example, chemical mechanical polishing (CMP) and / or grinding) can be used to remove all excess material present outside each opening formed in the first interconnect dielectric layer 10 (i.e., diffusion barrier material, plating seed layer, and conductive metals or conductive metal alloys), thereby providing… Figure 1 The interconnection level shown.

[0051] In this application, a plurality of conductive wiring structures 14 are formed in the first interconnect dielectric layer 10. In this application, at least two, more typically three or more conductive wiring structures 14 are formed. In this application, each conductive wiring structure 14 has a top surface that is substantially coplanar with the top surface of the first interconnect dielectric layer 10. If a first diffusion barrier pad 12 is present, each conductive wiring structure 14 has a top surface that is substantially coplanar with both the top surface of the first diffusion barrier pad 12 and the top surface of the first interconnect dielectric layer 10.

[0052] Now for reference Figure 2 This illustrates the process after forming a dielectric capping layer 16 and a second interconnect dielectric layer 18 on top of the interconnect layer. Figure 1The exemplary structure shown includes a second interconnect dielectric layer comprising a first conductive via structure 22. In some embodiments, the dielectric overlay layer 16 is omitted. In some embodiments, and as shown, a second diffusion barrier pad 20 may be present along the sidewalls of the first conductive via structure 22 and optionally along the bottom wall of the first conductive via structure 22. In some embodiments, the second diffusion barrier pad 20 may be omitted. In this application, the first conductive via structure 22 is electrically contacted with each of the other underlying conductive structures 14, such as... Figure 2 As shown in the image.

[0053] When present, the dielectric capping layer 16 is composed of any dielectric capping material, such as, for example, silicon carbide (SiC), silicon nitride (Si3N4), silicon dioxide (SiO2), carbon-doped oxides, nitrogen and hydrogen-doped silicon carbide (SiC(N,H)), or a multilayer stack of at least one of the aforementioned dielectric capping materials. The dielectric capping material is typically different in composition from the interconnect dielectric material used in forming the first interconnect dielectric layer 10 and the second interconnect dielectric layer 18. The dielectric capping layer 16 can be formed using deposition processes such as, for example, CVD, PECVD, ALD, chemical solution deposition, or evaporation. When present, the dielectric capping layer 16 can have a thickness from 10 nm to 100 nm. Other thicknesses less than 10 nm or greater than 100 nm can also be used as the thickness of the dielectric capping layer 16.

[0054] The second interconnect dielectric layer 18 includes one of the aforementioned interconnect dielectric materials used in the first interconnect dielectric layer 10. In some embodiments, the interconnect dielectric material providing the second interconnect dielectric layer 18 is compositionally identical to the interconnect dielectric material providing the first interconnect dielectric layer 10. In other embodiments, the interconnect dielectric material providing the second interconnect dielectric layer 18 is compositionally different from the interconnect dielectric material providing the first interconnect dielectric layer 10. The second interconnect dielectric layer 18 can be formed using deposition processes such as, for example, CVD, PECVD, or spin coating. In some embodiments, planarization processes such as, for example, CMP and / or polishing can be performed after the deposition of the interconnect dielectric material providing the second interconnect dielectric layer 18.

[0055] The optional second diffusion barrier liner 20 may include one of the aforementioned diffusion barrier materials used for the optional first diffusion barrier liner 12. In some embodiments, the diffusion barrier material providing the optional second diffusion barrier liner 20 is compositionally identical to the diffusion barrier material providing the optional first diffusion barrier liner 12. In other embodiments, the diffusion barrier material providing the optional second diffusion barrier liner 20 is compositionally different from the diffusion barrier material providing the optional first diffusion barrier liner 12.

[0056] The first conductive via structure 22, present in the second interconnect dielectric layer 18, is composed of one of the aforementioned conductive metals or conductive metal alloys (hereinafter referred to as conductive materials) used in the conductive wiring structure 14. In some embodiments, the conductive material providing the first conductive via structure 22 is compositionally identical to the conductive material providing the conductive wiring structure 14. In other embodiments, the conductive material providing the first conductive via structure 22 is compositionally different from the conductive material providing the conductive wiring structure 14.

[0057] The first conductive via structure 22 and the optional second diffusion barrier pad 20 can be formed using the damascene process described above. Note that during the etching used in the damascene process, the dielectric capping layer 16 is opened, so that the topmost surface of the conductive wiring structure 14 is physically exposed. At this point in the process, each first conductive via structure 22 has a topmost surface that is substantially coplanar with the topmost surface of the second interconnect dielectric layer 18. If the second diffusion barrier pad 20 is present, each first conductive via structure 22 has a topmost surface that is substantially coplanar with the topmost surface of the second diffusion barrier pad 20 and the topmost surface of the second interconnect dielectric layer 18.

[0058] Now for reference Figure 3 This shows the result after each first conductive via structure 22 is recessed. Figure 2 The exemplary structure shown is illustrated. The first conductive via structure 22 can be recessed using a recess etching process that selectively removes the conductive material providing the first conductive via structure 22. After this recess, the recessed first conductive via structure 22 has a topmost surface located below at least the topmost surface of the second interlayer dielectric layer 18. Note that the recess etching does not remove any portion of the second interlayer dielectric layer 18 or any portion of the optional second diffusion barrier pad 20.

[0059] Now for reference Figure 4 This illustrates the formation of a first electrode material layer 24L on the surface of the second interconnect dielectric layer 18 and on the surface of each recessed first conductive via structure 22. Figure 3 The exemplary structure shown is illustrated. The first electrode material layer 24L is composed of a conductive electrode material, such as, for example, Ta, TaN, Ti, TiN, Ru, RuN, RuTa, RuTaN, Co, CoWP, CoN, W, WN, or any combination thereof. The first electrode material layer 24L can be formed by a deposition process such as, for example, sputtering, CVD, PECVD, ALD, or PVD.

[0060] Now for reference Figure 5 This illustrates the process of removing the first electrode material layer 24L from the surface of the second interconnect dielectric layer 18 while maintaining the first electrode material layer 24L on the surface of each recessed first conductive via structure 22. Figure 4 The exemplary structure shown includes a first electrode 24 provided by a retained first electrode material layer. Each formed first electrode 24 is directly located on the surface of one of the recessed first conductive via structures 22 in the underlying layer. This removal step in this application includes a planarization process, such as, for example, CMP. At this point in this application, both the first electrode 24 and the recessed first conductive via structure 22 are embedded in a second interconnect dielectric layer 18, and each first electrode 24 has a top surface that is substantially coplanar with the top surface of the second interconnect dielectric layer 18 and (if present) the top surface of a second diffusion barrier pad 20. In the illustrated embodiment, a second diffusion barrier pad 20 is present along the sidewall of each double-layer structure of the first electrode 24 and the recessed first conductive via structure 22 embedded in the second interconnect dielectric layer 18. Note that each first electrode 24 has a sidewall that is perpendicularly aligned with the sidewall of one of the recessed first conductive via structures 22 in the underlying layer.

[0061] Now for reference Figure 6 This illustrates the process after the formation of the first MTJ stack 26L and the second electrode material layer 28L on top of the second interconnect dielectric layer 18. Figure 5 The exemplary structure is shown. Note that a portion of the first MTJ stack 26L spans each of the first electrodes 24 present in the second interconnect dielectric layer 18 and an optional second diffusion barrier pad 20. The first MTJ stack 26L includes at least a tunneling barrier material layer located between the magnetic free layer and the magnetic reference (or fixed) layer (i.e., sandwiched between the magnetic free layer and the magnetic reference layer). For clarity, the various layers present in the first MTJ stack 26L are not shown individually in the accompanying drawings. In some embodiments, the first MTJ stack 26L is a top-fixed MTJ structure comprising, from bottom to top, a magnetic free layer, a tunneling barrier material layer, and a magnetic reference layer. In other embodiments, the MTJ stack 26L is a bottom-fixed MTJ structure comprising, from bottom to top, a magnetic reference layer, a tunneling barrier material layer, and a magnetic free layer. The first MTJ stack 26L may include other magnetic and non-magnetic materials well known to those skilled in the art.

[0062] The magnetic free layer of the first MTJ stack 26L has a magnetization that can change orientation relative to the magnetization orientation of the magnetic reference layer. The magnetic free layer can have a thickness from 0.3 nm to 3 nm; although other thicknesses are also possible and can be used as the thickness of the magnetic free layer. The magnetic free layer can consist of magnetic materials or stacks of magnetic materials well known to those skilled in the art. In some embodiments, the magnetic free layer comprises alloys and / or multilayer structures of cobalt, iron, cobalt-iron alloys, nickel, nickel-iron alloys, and cobalt-iron-boron alloys. In other embodiments, the magnetic free layer consists of an ordered magnetic alloy. By "ordered magnetic alloy," it refers to a magnetic alloy having a lattice structure in which atoms of one element occupy specific sites, and atoms of at least one other element occupy other sites. In one embodiment, the ordered magnetic alloy providing the magnetic free layer is a Hessler alloy. A Hessler alloy (or compound) is a magnetic intermetallic compound having a face-centered cubic crystal structure and an XYZ (half-Hessler) or X2YZ (full Hessler) composition, wherein X and Y are transition metals and Z is located in the p-block. Exemplary Hessler alloys that may be used in this application include, but are not limited to, Mn3Ge, Mn3Ga, Co2MnSi, Mn3Sn, AlMnGe, or Mn3Sb. In another embodiment, the ordered magnetic alloy providing the magnetic free layer is an L10 alloy. The term "L10 alloy" refers to an intermetallic compound having a body-centered tetragonal crystal structure, wherein one element occupies the corners of the lattice unit and another element occupies the body center. Exemplary L10 alloys that may be used in this application include, but are not limited to, MnAl or CoFe.

[0063] The tunneling barrier material layer of the first MTJ stack 26L is composed of an insulating material and is formed to a thickness sufficient to provide adequate tunneling resistance. Exemplary insulating materials for the tunneling barrier material layer include, but are not limited to, magnesium oxide, aluminum oxide, and titanium oxide, or materials with high electrical tunneling conductivity, such as semiconductors or low-bandgap insulators. The thickness of the tunneling barrier material layer will depend on the material chosen. In one example, the tunneling barrier material layer may have a thickness from 0.5 nm to 1.5 nm; although other thicknesses are also possible, as long as the thickness of the tunneling barrier material layer provides adequate tunneling resistance.

[0064] The magnetic reference layer of the first MTJ stack 26L has a fixed magnetization. The magnetic reference layer may be composed of a magnetic metal or a magnetic metal alloy (or a stack thereof), including one or more magnetic metals that exhibit high spin polarization at the tunneling barrier interface. In alternative embodiments, exemplary magnetic metals used to form the magnetic reference layer include iron, nickel, cobalt, chromium, boron, or manganese. Exemplary magnetic metal alloys may include the aforementioned exemplary magnetic metals used for the magnetic reference layer. In another embodiment, the magnetic reference layer may be a multilayer arrangement having: (1) a highly spin-polarized region formed of a metal and / or metal alloy using the aforementioned metals, and (2) a region composed of one or more materials exhibiting strong perpendicular magnetic anisotropy (PMA). Exemplary materials with strong PMA that may be used include metals such as cobalt, nickel, platinum, palladium, iridium, or ruthenium, and may be arranged as alternating layers. The strong PMA region may also include alloys exhibiting strong intrinsic or bulk (compared to interface) PMA, wherein exemplary alloys include cobalt-iron-terbium, cobalt-iron-gadolinium, cobalt-chromium-platinum, cobalt-platinum, cobalt-palladium, iron-platinum, and / or iron-palladium. The alloys may be arranged as alternating layers. In one embodiment, a combination of these materials and regions may also be used as a magnetic reference layer.

[0065] In some embodiments, the magnetic reference layer comprises a multilayer structure including a lower magnetic reference layer, a synthetic antiferromagnetic coupling layer, and an upper magnetic reference layer. The lower magnetic reference layer may be composed of one of the aforementioned magnetic materials used for the magnetic reference layer. The synthetic antiferromagnetic coupling layer may be composed of a non-magnetic material that couples the lower and upper magnetic layers of the multilayer structure, which can serve as the magnetic reference layer, in an antiparallel manner. Exemplary non-magnetic materials that can be used as the synthetic antiferromagnetic coupling layer include, but are not limited to, ruthenium (Ru), iridium (Ir), or rhodium (Rh). In one embodiment, the synthetic antiferromagnetic coupling layer may have a thickness from 0.2 nm to 1.2 nm; although other thicknesses are also possible and can be used as the thickness of the synthetic antiferromagnetic coupling layer. The upper magnetic reference layer may be composed of one of the aforementioned magnetic materials used for the magnetic reference layer. Typically, and in this multilayer structure embodiment, the upper magnetic reference layer differs in composition from the lower magnetic reference layer.

[0066] In some embodiments (not shown), an MTJ capping layer may be formed between the top layer of the first MTJ stack 26L and the second electrode material layer 28L. When present, the MTJ capping layer may consist of, for example, Nb, NbN, W, WN, Ta, TaN, Ti, TiN, Ru, Mo, Cr, V, Pd, Pt, Rh, Sc, Al, or other high-melting-point metals or conductive metal nitrides. The MTJ capping layer may have a thickness from 2 nm to 25 nm; other thicknesses are possible and may be used as the thickness of the MTJ capping layer in this application.

[0067] Various layers providing the first MTJ stack 26L can be formed by deposition processes, including but not limited to CVD, PECVD, PVD, ALD, molecular beam epitaxy (MBE), sputtering, or any combination thereof.

[0068] The second electrode material layer 28L may include one of the aforementioned conductive electrode materials used for the first electrode material layer 24L. In some embodiments, the conductive electrode material providing the second electrode material layer 28L is compositionally identical to the conductive electrode material providing the first electrode material layer 24L. In other embodiments, the conductive electrode material providing the second electrode material layer 28L is compositionally different from the conductive electrode material providing the first electrode material layer 24L. The second electrode material layer 28L may be formed by a deposition process, such as sputtering, CVD, PECVD, ALD, or PVD.

[0069] Now for reference Figure 7 The diagram illustrates the process after patterning the second electrode material layer 28L and the first MTJ stack 26L to provide the second electrode 28 and the first MTJ structure 26, respectively, and forming the first encapsulation layer 30L. Figure 6 The exemplary structure is shown. Patterning of the second electrode material layer 28L and the first MTJ stack 26L includes photolithography and etching. Etching is typically an IBE process; however, other types of etching, such as RIE, can also be used. In this embodiment, the etching is an angled IBE. Note that after the pattern of the developed photoresist is transferred to the second electrode material layer 28L, the developed photoresist is removed, and each remaining, unetched portion of the second electrode material layer 28L (i.e., each second electrode 28) serves as an etching mask during the subsequent etching of the first MTJ stack 26L. Each first MTJ structure 26 includes the remaining, i.e., unetched portion of the first MTJ stack 26L. Note that during etching, a portion of the second interconnect dielectric layer 18, the first electrode 24, and (if present) the second diffusion barrier pad 20 can be etched, as shown. Figure 8 As shown in the diagram. After the patterning process, each first electrode 24 may have a top surface connected to the sidewalls by a bevel. After the patterning process, the top surface of each first electrode 24 may be located above the top surface of the remaining second interconnect dielectric layer 18. Note that each second electrode 28 is located on the top surface of one of the first MTJ structures 26 in the bottom layer, which in turn is located on top of one of the first electrodes 24 in the bottom layer. The combination of each first electrode 24, the first MTJ structure 26, and the second electrode 28 forms the first MRAM cell of the structure. The first MRAM cell is located in the first level of the structure.

[0070] After performing the above patterning steps to provide the second electrode 28 and the first MTJ structure 26, a first encapsulation layer 30L is formed laterally around the second electrode 28, the first MTJ structure 26, and at least the upper portion of the first electrode 24. The first encapsulation layer 30L is also formed on the surface of the second interconnect dielectric layer 18. The first encapsulation layer 30L is composed of a dielectric material capable of providing passivation to each first MRAM cell. In one embodiment, the first encapsulation layer 30L is composed of silicon nitride. In another embodiment, the first encapsulation layer 30L may be composed of a dielectric material comprising silicon, carbon, and hydrogen atoms. In some embodiments, and in addition to carbon and hydrogen atoms, the dielectric material providing the first encapsulation layer 30L may also include at least one of nitrogen and oxygen atoms. In other embodiments, and in addition to silicon, nitrogen, carbon, and hydrogen atoms, the dielectric material providing the first encapsulation layer 30L may also include boron atoms. In one example, the first encapsulation layer 30L may be composed of an nBLOK dielectric material comprising silicon, carbon, hydrogen, nitrogen, and oxygen atoms. In an alternative example, the first encapsulation layer 30L may be composed of a SiBCN dielectric material comprising silicon, boron, carbon, hydrogen, and nitrogen atoms. The first encapsulation layer 30L can be formed by depositing a continuous layer of the dielectric material providing the first encapsulation layer 30L. This deposition may include, but is not limited to, CVD, PECVD, PVD, ALD, or spin coating. The first encapsulation layer 30L may have a thickness from 10 nm to 200 nm. Other thicknesses are possible and can be used as the thickness of the first encapsulation layer 30L.

[0071] Now for reference Figure 8 This shows the process after the formation of the third interconnect dielectric layer 32. Figure 7 The exemplary structure shown is illustrated. The third interconnect dielectric layer 32 includes one of the aforementioned interconnect dielectric materials used for the first interconnect dielectric layer 10. In some embodiments, the interconnect dielectric material providing the third interconnect dielectric layer 32 is compositionally identical to the interconnect dielectric material providing the first interconnect dielectric layer 10 and / or the second interconnect dielectric layer 18. In other embodiments, the interconnect dielectric material providing the third interconnect dielectric layer 32 is compositionally different from the interconnect dielectric material providing the first interconnect dielectric layer 10 and / or the second interconnect dielectric layer 18. The third interconnect dielectric layer 32 can be formed using deposition processes such as, for example, CVD, PECVD, or spin coating. Planarization processes such as, for example, CMP and / or polishing can be performed after the deposition of the interconnect dielectric material providing the third interconnect dielectric layer 32. At this point in the process, the third interconnect dielectric layer 32 has a top surface that is substantially coplanar with the top surface of the first encapsulation layer 30L present on top of the second electrode 28.

[0072] Now for reference Figure 9 This illustrates the process after forming the first conductive supervia structure 36 and forming the third electrode 38 on the surface of the first conductive supervia structure 36. Figure 8 The exemplary structure is shown. Note that the height of the first conductive via structure 36 is greater than the height of the recessed first conductive via structure 22. In some embodiments, a third diffusion barrier liner 34 is present along the sidewall of the subsequently formed first conductive via structure 36. In other embodiments, the third diffusion barrier liner 34 is omitted from the structure. Note that although... Figure 9 The formation of a single first conductive supervia structure 36 is shown, but multiple first conductive supervia structures will be formed in a manner that alternates laterally with the first conductive via 22.

[0073] The optional third diffusion barrier liner 34 may include one of the aforementioned diffusion barrier materials used for the optional first diffusion barrier liner 12. In some embodiments, the diffusion barrier material providing the optional third diffusion barrier liner 34 is compositionally identical to the diffusion barrier material providing the optional first diffusion barrier liner 12 and / or the optional second diffusion barrier liner 20. In other embodiments, the diffusion barrier material providing the optional third diffusion barrier liner 34 is compositionally different from the diffusion barrier material providing the optional first diffusion barrier liner 12 and / or the optional second diffusion barrier liner 20.

[0074] The first conductive via structure 36 is composed of one of the aforementioned conductive metals or conductive metal alloys (hereinafter referred to as conductive materials) used in the conductive wiring structure 14. In some embodiments, the conductive material providing the first conductive via structure 36 is compositionally identical to the conductive material providing the conductive wiring structure 14 and / or the first conductive via structure 22. In other embodiments, the conductive material providing the first conductive via structure 36 is compositionally different from the conductive material providing the conductive wiring structure 14 and / or the first conductive via structure 22.

[0075] The first conductive via structure 36 and an optional third diffusion barrier pad 34 can be formed using the above-described damascene process. In this damascene process, etching extends downwards to the surface of one of the conductive wiring structures 14, on which there is no recess in the first conductive via structure 22. Note that during the etching used in the damascene process, the dielectric capping layer 16 is reopened, so that the topmost surface of at least one conductive wiring structure 14 is physically exposed. The optional third diffusion barrier pad 34 and the initial via structure are then formed in the via opening provided by the above-described etching by deposition and planarization.

[0076] After forming the initial conductive via structure and the optional third diffusion barrier pad 34, a recess etching process as defined above when recessing the first conductive via structure 22 is performed to provide... Figure 9 The first conductive superhole structure 36 shown is illustrated.

[0077] After providing the first conductive supervia structure 36, the third electrode 38 is formed using the same basic processing steps as those used when forming the first electrode 24. That is, the third electrode 38 is formed by depositing a third electrode material layer (not shown) and then performing a planarization process. The third electrode 38 may include one of the aforementioned conductive electrode materials used for the first electrode material layer 24L. In some embodiments, the conductive electrode material providing the third electrode 38 is compositionally identical to the conductive electrode material providing the first electrode material layer 24L and / or the second electrode material layer 28L. In other embodiments, the conductive electrode material providing the third electrode 38 is compositionally different from the conductive electrode material providing the first electrode material layer 24L and / or the second electrode material layer 28L. At this point in the process, the third electrode 38 has a top surface that is substantially coplanar with the top surface of the third interconnect dielectric layer 32. Note that the top surface of the third electrode 38 is located above the top surface of each of the second electrodes 28.

[0078] Now for reference Figure 10 This illustrates the process after the second MTJ structure 40 and the fourth electrode 42 are formed on top of the third electrode 38, and the second encapsulation layer 44L is formed. Figure 9 The exemplary structure is shown. The second MTJ structure 40 includes the aforementioned magnetic and non-magnetic materials used in the first MTJ stack 26L. The second MTJ structure 40 includes at least a magnetic reference layer, a tunneling barrier material layer, and a magnetic free layer, all as previously defined. The second MTJ structure 40 can be a top-fixed or bottom-fixed MTJ structure configuration. Note that the materials and / or MTJ structure configuration of the second MTJ structure 40 do not need to be the same as those of the first MTJ stack 26L.

[0079] The fourth electrode 42 may include one of the aforementioned conductive electrode materials used in the first electrode material layer 24L. In some embodiments, the conductive electrode material providing the fourth electrode 42 is compositionally identical to the conductive electrode material providing the first electrode material layer 24L and / or the second electrode material layer 28L and / or the third electrode material layer. In other embodiments, the conductive electrode material providing the fourth electrode 42 is compositionally different from the conductive electrode material providing the first electrode material layer 24L and / or the second electrode material layer 28L and / or the third electrode material layer.

[0080] The second MTJ structure 40 and the fourth electrode 42 can be formed using the same process mentioned above for forming the first MTJ structure 26 and the second electrode 28. That is, the second MTJ structure 40 and the fourth electrode 42 can be formed by deposition, patterning, and etching. The etching again typically includes IBE etching with angled IBE etching as described above. Note that during etching, a portion of the third interlayer dielectric layer 32, the third electrode 38, and (if present) the third diffusion barrier pad 34 can be etched, as... Figure 10 As shown in the diagram. After the patterning process, the third electrode 38 may have a top surface connected to the sidewalls via bevels. After the patterning process, the top surface of the third electrode 38 may be located above the top surface of the remaining third interconnect dielectric layer 32. Note that the fourth electrode 42 is located on the top surface of the second MTJ structure 40 of the bottom layer, which in turn is located on top of one of the third electrodes 38 of the bottom layer. The combination of each third electrode 38, the second MTJ structure 40, and the fourth electrode 42 forms the second MRAM cell of the structure. Note that the second MRAM cell is located at a different interconnect level (i.e., the second level) than each first MRAM cell. Each second MRAM cell is horizontally offset from each first MRAM cell.

[0081] Following the patterning steps described above for providing the second MRAM cell, a second encapsulation layer 44L is formed laterally surrounding the second MRAM cell, which includes a fourth electrode 42, a second MTJ structure 40, and the upper portion of at least a third electrode 38. The second encapsulation layer 44L is also formed on the surface of the third interconnect dielectric layer 32 and on top of each second electrode 28. The second encapsulation layer 44L is composed of one of the dielectric materials described above for the first encapsulation layer 30L. The second encapsulation layer 44L may be composed of dielectric materials that are the same in composition as or different in composition from the first encapsulation layer 30L. The second encapsulation layer 44L can be formed using the same processing steps mentioned above for forming the first encapsulation layer 30L. The thickness of the second encapsulation layer 44L is within the range described above for the first encapsulation layer 30L. Note that on top of the second electrode 28, the encapsulation dielectric material will include the dielectric materials of both the first encapsulation layer 30L and the second encapsulation layer 44L. For simplicity, in Figures 10-12 In the image, only the second encapsulation layer 44L is shown directly above each second electrode 28.

[0082] Now for reference Figure 11 This shows the process after the formation of the fourth interconnect dielectric layer 46. Figure 10The exemplary structure shown is illustrated. The fourth interconnect dielectric layer 46 includes one of the aforementioned interconnect dielectric materials used for the first interconnect dielectric layer 10. In some embodiments, the interconnect dielectric material providing the fourth interconnect dielectric layer 46 is compositionally identical to the interconnect dielectric material providing the first interconnect dielectric layer 10 and / or the second interconnect dielectric layer 18 and / or the third interconnect dielectric layer 32. In other embodiments, the interconnect dielectric material providing the fourth interconnect dielectric layer 46 is compositionally different from the interconnect dielectric material providing the first interconnect dielectric layer 10 and / or the second interconnect dielectric layer 18 and / or the third interconnect dielectric layer 32. The fourth interconnect dielectric layer 46 can be formed using deposition processes such as, for example, CVD, PECVD, or spin coating. Planarization processes such as, for example, CMP and / or polishing can be performed after the deposition of the interconnect dielectric material providing the fourth interconnect dielectric layer 46. At this point in the process, the fourth interconnect dielectric layer 46 has a top surface that is substantially coplanar with the top surface of the second encapsulation layer 44L located on top of the fourth electrode 42.

[0083] Now for reference Figure 12 This illustrates the effect after additional interconnect dielectric material is formed on the fourth interconnect dielectric layer 46. Figure 11 The exemplary structure shown herein includes an additional dielectric material and a fourth dielectric layer 46 that together provide an uppermost interconnect dielectric layer 47 covering the entire second encapsulation layer 44L (including the portion of the second encapsulation layer 44L located on top of the fourth electrode 42), and a supervia 48A and a normal via 48B are formed in the uppermost interconnect dielectric layer 47.

[0084] The additional interconnect dielectric material formed on the fourth interconnect dielectric layer 46 is typically composed of the same dielectric material as the fourth interconnect dielectric layer 46. However, a dielectric material with a different composition from the fourth interconnect dielectric layer 46 can be used as the additional dielectric material. The additional dielectric material can be formed by deposition processes such as, for example, CVD, PECVD, or spin coating. The conductive supervia 48A and the normal via 48B are each openings that can be formed by photolithography and etching. Note that the height of the supervia 48A is greater than the height of the normal via 48B. The supervia 48A extends downward to the portion of the second packaging layer 44L located at the top of the second electrode 28.

[0085] Now for reference Figure 13 This illustrates the process after each of the second electrode 28 and the fourth electrode 42 has been physically exposed. Figure 12The exemplary structure is shown. This step of the application includes an etching process that selectively removes the dielectric material providing the second encapsulation layer 44L and the first encapsulation layer 30L. This etching provides an extended supervia 49A extending downward to the second electrode 28 and an extended normal via 49B extending to the fourth electrode 42. Note that this etching not only physically exposes the topmost surface of each of the second electrode 28 and the fourth electrode 42, but also physically exposes the upper sidewalls of each of the second electrode 28 and the fourth electrode 42, such as... Figure 13 As shown in the image.

[0086] Now for reference Figure 14 This illustrates the formation of a conductive layer 52L on the surface of the uppermost interconnect dielectric layer 47 and on the physically exposed surfaces of each of the second and fourth electrodes (i.e., within each of the extended supervia 49A and extended normal via 49B). Figure 13 The exemplary structure shown. In some embodiments, and as illustrated... Figure 14 As shown, a diffusion barrier pad 50L may be formed before the conductive layer 52L is formed. In other embodiments, the diffusion barrier pad 50L may be omitted from the structure.

[0087] The optional diffusion barrier liner 50L is composed of one of the diffusion barrier materials described above for the optional first diffusion barrier liner 12. The diffusion barrier material providing the optional diffusion barrier liner 50L may be the same in composition as or different in composition from the diffusion barrier material providing any of the aforementioned diffusion barrier liners. The optional diffusion barrier liner 50L can be formed by deposition processes such as, for example, CVD, PECVD, ALD, PVD, sputtering chemical solution deposition, or plating. The optional diffusion barrier liner 50L may have a thickness within the range described above for the optional first diffusion barrier liner 12.

[0088] The conductive layer 52L is composed of one of the aforementioned conductive materials (i.e., conductive metal or conductive metal alloy) used for the conductive wire structure 14. The conductive material providing the conductive layer 52L may be the same in composition as or different in composition from the conductive material providing any of the aforementioned conductive wiring structures (including conductive wiring structure 14, first conductive via structure 22, and first conductive super-via structure 36).

[0089] Now for reference Figure 15 This illustrates the removal of the conductive layer 52L from the surface of the uppermost interconnecting dielectric layer 47 while maintaining the conductive layer 52L on the physically exposed surfaces of each of the second electrode 28 and the fourth electrode 42. Figure 14The exemplary structure is shown. The retained conductive layer 52L present on top of each second electrode 28 may be referred to as a second conductive supervia structure 52A, and the retained conductive layer 52L present on top of each fourth electrode may be referred to herein as a second conductive via structure 52B. During the removal step used in providing the second conductive supervia structure 52A and the second conductive via structure 52B, an optional diffusion barrier liner 50L is removed from the top of the uppermost interconnect dielectric layer 47, while retaining the optional diffusion barrier liner 50L in each of the extended superconducting via openings and extended normal via openings. The retained optional diffusion barrier liner 50L provides an optional fourth diffusion barrier liner 50. Figure 15 The removal process mentioned in the exemplary structure shown is a planarization process such as CMP.

[0090] In this application, each first MRAM cell is located in the first level of the structure, while each second MRAM cell is located in the second level of the structure. Figure 15 (and subsequent) Figure 16 In the MRAM array, L1-MTJ represents the first-level MRAM cell (including the first electrode 24, the first MTJ structure 26, and the second electrode 28), while L2-MTJ represents the second-level MRAM cell (including the third electrode 38, the second MTJ structure 40, and the fourth electrode 42). Figure 15 As shown, the second level is at a higher interconnection level than the first level. Figure 16 An MRAM array according to an embodiment of this application is shown. The accompanying drawing shows a top view of two levels of the MTJ.

[0091] Although this application has been shown and described particularly with respect to preferred embodiments thereof, those skilled in the art will understand that foregoing and other changes in form and detail may be made without departing from the spirit and scope of this application. Therefore, this application is not intended to be limited to the exact form and detail described and shown, but rather to fall within the scope of the appended claims.

Claims

1. A memory structure, comprising: The first level includes a plurality of first magnetoresistive random access memory (MRAM) cells, wherein each of the plurality of first MRAM cells has a bottom surface in electrical contact with a first conductive via structure and a top surface in electrical contact with a second conductive supervia structure; and The second level includes a plurality of second MRAM cells, wherein each of the plurality of second MRAM cells is located above and horizontally offset from each of the plurality of first MRAM cells, wherein each of the plurality of second MRAM cells has a bottom surface in electrical contact with a first conductive via structure and a top surface in electrical contact with a second conductive via structure.

2. The memory structure according to claim 1, wherein, The first conductive via structure and the first conductive supervia structure have bottom surfaces that are substantially coplanar with each other, and the second conductive supervia structure and the second conductive via structure have top surfaces that are substantially coplanar with each other.

3. The memory structure according to claim 2, wherein, The wiring distance provided by the combination of the first conductive via structure and the second conductive supervia structure is substantially equal to the wiring distance provided by the combination of the first conductive supervia structure and the second conductive via structure.

4. The memory structure according to claim 1, wherein, Each of the plurality of first MRAM cells includes a first electrode, a first MTJ structure, and a second electrode.

5. The memory structure according to claim 4, wherein, The first electrode is in electrical contact with the first conductive via structure, and the second electrode is in electrical contact with the second conductive super-through structure.

6. The memory structure according to claim 5, wherein, Each of the plurality of second MRAM cells includes a third electrode, a second MTJ structure, and a fourth electrode.

7. The memory structure according to claim 6, wherein, The third electrode is in electrical contact with the first conductive superhole structure, and the fourth electrode is in electrical contact with the second conductive through-hole structure.

8. The memory structure according to claim 7, wherein, The first conductive via structure is in electrical contact with the conductive wiring structure, and the first conductive super-via structure is in electrical contact with another conductive wiring structure.

9. The memory structure according to claim 6, wherein, Both the first and third electrodes have a top surface that is connected to the sidewall via an inclined plane.

10. The memory structure according to claim 1, wherein, Both the first and second MTJ structures include a tunneling barrier layer sandwiched between a magnetic reference layer and a magnetic free layer.

11. The memory structure according to claim 10, wherein, The magnetic free layer is located above the magnetic reference layer.

12. The memory structure according to claim 10, wherein, The magnetic free layer is located below the magnetic reference layer.

13. The memory structure of claim 1, further comprising a diffusion barrier pad present along the sidewall of each of the first conductive via structure, the first conductive supervia structure, the second conductive via structure, and the second conductive supervia structure.

14. The memory structure of claim 1, further comprising a first packaging pad located near each of the plurality of first MRAM cells.

15. The memory structure of claim 14, further comprising a second packaging pad located near each of the plurality of second MRAM cells.

16. The memory structure according to claim 1, wherein, The plurality of first MRAM cells reside in a different interconnect layer than the plurality of second MRAM cells.

17. A method for forming a memory structure, the method comprising: An interconnect level is formed, the interconnect level having multiple conductive wiring structures embedded in an interconnect dielectric layer; A first conductive structure is formed that makes electrical contact with every other conductive wiring structure in the plurality of conductive wiring structures. A plurality of first magnetoresistive random access memory (MRAM) cells are formed in the first level, wherein each of the plurality of first MRAM cells has a bottom surface that is electrically in contact with one of the first conductive via structures; A first conductive superhole structure is formed to make electrical contact with a conductive wiring structure that does not include a first conductive via structure. A plurality of second MRAM cells are formed in a second level located above the first level, wherein each of the plurality of second MRAM cells is located above and horizontally offset from each of the plurality of first MRAM cells; and Multiple second conductive supervia structures and multiple second conductive via structures are formed, wherein the multiple second conductive supervia structures are in electrical contact with the top surface of each of the multiple first MRAM cells, and the multiple second conductive via structures are in electrical contact with the top surface of each of the multiple second MRAM cells.

18. The method according to claim 17, wherein, The first conductive via structure and the first conductive supervia structure have bottom surfaces that are substantially coplanar with each other, and the second conductive supervia structure and the second conductive via structure have top surfaces that are coplanar with each other.

19. The method according to claim 18, wherein, The wiring distance provided by the combination of the first conductive via structure and the second conductive supervia structure is substantially equal to the wiring distance provided by the combination of the first conductive supervia structure and the second conductive via structure.

20. The method of claim 17, wherein, Each of the plurality of first MRAM cells includes a first electrode, a first MTJ structure, and a second electrode.

21. The method according to claim 20, wherein, The first electrode is in electrical contact with the first conductive via structure, and the second electrode is in electrical contact with the second conductive super-through structure.

22. The method according to claim 21, wherein, Each of the plurality of second MRAM cells includes a third electrode, a second MTJ structure, and a fourth electrode.

23. The method according to claim 22, wherein, The third electrode is in electrical contact with the first conductive superhole structure, and the fourth electrode is in electrical contact with the second conductive through-hole structure.

24. The method of claim 17, wherein, Forming the plurality of first MRAM cells and forming the plurality of second MRAM cells includes an ion beam patterning process.

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