Chip mainboard current fluctuation anomaly detection method and system

Abstract

This invention relates to the field of electrical performance testing technology, specifically to a method and system for detecting abnormal current fluctuations on a chip motherboard. In this invention, a comparator circuit monitors the pulse width modulation signal of the voltage regulator control chip, enabling the triggering of current fluctuations to correspond to abrupt changes in the power supply regulation signal. A trigger channel determines the core processor's power domain identifier, and the microcontroller within the board management controller controls the analog-to-digital converter to switch the corresponding channel to a higher sampling frequency, ensuring the acquisition process targets the power domain where the fluctuation occurs. Furthermore, target spectral component data corresponding to the nominal switching frequency and the preset resonant frequency are extracted from the frequency domain spectral component sequence, generating abnormal current fluctuation detection results. This method serves to continuously trigger, locate, sample, analyze in the frequency domain, and determine abnormalities in transient current fluctuations on a server motherboard.

Description

Technical Field

[0001] This invention relates to the field of electrical performance testing technology, and in particular to a method and system for detecting abnormal current fluctuations on a chip motherboard. Background Technology

[0002] The chip motherboard current fluctuation anomaly detection method refers to the technical process of monitoring and identifying the current fluctuations generated by the motherboard during operation, which is used to identify the current fluctuation state in the motherboard circuit that deviates from the normal working reference.

[0003] Traditional methods for detecting abnormal current fluctuations on motherboards can monitor and identify current fluctuations during operation. However, when power supply fluctuations exist simultaneously in the CPU core power domain, CPU non-core power domain, and memory power domain on a server motherboard, there are challenges in timely capturing transient current fluctuation events from the pulse width modulation signal of the voltage regulator control chip and further locating the power domain corresponding to the abnormal fluctuations. Furthermore, when current fluctuations are short-lived and waveform changes are concentrated at specific frequency positions, relying solely on conventional current monitoring processes is prone to problems such as insufficient sampling frequency, unclear sampling targets, and inadequate extraction of abnormal spectral components. Summary of the Invention

[0004] The purpose of this invention is to overcome the shortcomings of the existing technology and to propose a method and system for detecting abnormal current fluctuations on a chip motherboard.

[0005] To achieve the above objectives, the present invention adopts the following technical solution: a method for detecting abnormal current fluctuations on a chip motherboard, used to detect abnormal current fluctuations on a server motherboard, comprising the following steps:

[0006] Monitor the pulse width modulation signal of the voltage regulator control chip on the motherboard to determine the transient current fluctuation event trigger signal and obtain the corresponding core processor power domain identifier.

[0007] The transient current fluctuation event trigger signal is sent to the analog-to-digital converter on the motherboard, the channel configuration status of the analog-to-digital converter is adjusted, and the core processor power domain identifier is combined to obtain the sampling configuration parameter set of the analog-to-digital converter;

[0008] Collect the timing current waveform sequence by referring to the sampling configuration parameter set;

[0009] The time-series current waveform sequence is used as the discrete-time signal input in the discrete Fourier transform, and the corresponding spectral component data is calculated to construct the frequency domain spectral component sequence.

[0010] Based on the frequency domain spectral component sequence, abnormal situations of current fluctuations on the chip motherboard are identified, and abnormality detection results are obtained.

[0011] As a further aspect of the present invention, the step of monitoring the pulse width modulation signal of the voltage regulator control chip on the motherboard, determining the transient current fluctuation event trigger signal from it, and obtaining the corresponding core processor power domain identifier includes:

[0012] The pulse width modulation signal of the voltage regulator control chip on the motherboard is monitored by a comparator circuit. The duty cycle value of the pulse width modulation signal at two consecutive sampling time points is obtained. Based on the time interval between the two sampling time points and the duty cycle value, the duty cycle change rate of the pulse width modulation signal is calculated, and the absolute value of the corresponding duty cycle change rate is obtained.

[0013] When the absolute value of the duty cycle change rate exceeds the preset duty cycle change rate threshold, a transient current fluctuation event is determined to have occurred, and a transient current fluctuation event trigger signal is generated. When the absolute value of the duty cycle change rate is less than or equal to the duty cycle change rate threshold, the comparator circuit continues to monitor the pulse width modulation signal.

[0014] When a transient current fluctuation event trigger signal is generated, the associated core processor power domain identifier is determined based on the comparator circuit channel of the output transient current fluctuation event trigger signal.

[0015] As a further aspect of the present invention, the step of sending the transient current fluctuation event trigger signal to the analog-to-digital converter on the motherboard, adjusting the analog-to-digital converter channel configuration state, and combining the core processor power domain identifier to obtain the sampling configuration parameter set of the analog-to-digital converter includes:

[0016] Based on the received transient current fluctuation event trigger signal, the microcontroller in the baseboard management controller on the motherboard generates a corresponding sampling mode switching instruction;

[0017] The sampling mode switching command is sent to the analog-to-digital converter on the motherboard, and the channel in the analog-to-digital converter on the motherboard corresponding to the power domain identifier of the core processor is switched from the first sampling frequency to the second sampling frequency, and the channel configuration status of the analog-to-digital converter is adjusted, wherein the second sampling frequency is higher than the first sampling frequency;

[0018] By combining the analog-to-digital converter channel configuration state with the corresponding core processor power domain identifier, a set of sampling configuration parameters for the analog-to-digital converter is obtained.

[0019] As a further aspect of the present invention, the reference sampling configuration parameter set, the time-series current waveform sequence collected includes:

[0020] Determine the target power domain pointed to by the core processor power domain identifier in the sampling configuration parameter set;

[0021] In the analog-to-digital converter channel configuration state, the target power domain is continuously sampled through the analog-to-digital converter channel according to the second sampling frequency and the preset sampling duration to obtain digital current data;

[0022] All the collected digital current data are extracted and arranged in chronological order to form a time-series current waveform sequence.

[0023] As a further aspect of the present invention, the step of using the time-series current waveform sequence as the discrete-time signal input in the discrete Fourier transform, calculating the corresponding spectral component data, and constructing the frequency domain spectral component sequence includes:

[0024] The time-series current waveform sequence is used as the discrete-time signal input in the discrete Fourier transform;

[0025] The microcontroller in the baseboard management controller on the motherboard performs frequency domain conversion calculations on the discrete-time signal input to obtain spectral component data.

[0026] By combining all the spectral component data, a frequency domain spectral component sequence is obtained.

[0027] As a further aspect of the present invention, the step of determining abnormal conditions of chip motherboard current fluctuations based on frequency domain spectral component sequences and obtaining abnormal detection results includes:

[0028] Obtain the nominal switching frequency and preset resonant frequency of the voltage regulator on the motherboard, and extract the target spectral component data corresponding to the nominal switching frequency and preset resonant frequency from the frequency domain spectral component sequence;

[0029] The sum of the squares of the real and imaginary parts of the target spectral component data is calculated and the square root is taken to obtain the amplitude of the spectral component data of the target spectral component data;

[0030] When the amplitude of the spectral component data exceeds a preset background noise level threshold, it is determined that there is an abnormal current fluctuation on the chip motherboard, and an abnormal current fluctuation detection result is generated.

[0031] A chip motherboard current fluctuation anomaly detection system is used to detect abnormal current fluctuations on a server motherboard. The system includes:

[0032] The fluctuation trigger determination module monitors the pulse width modulation signal of the voltage regulator control chip on the motherboard, determines the transient current fluctuation event trigger signal from it, and obtains the corresponding core processor power domain identifier.

[0033] The parameter determination module sends the transient current fluctuation event trigger signal to the analog-to-digital converter on the motherboard, adjusts the channel configuration status of the analog-to-digital converter, and combines the core processor power domain identifier to obtain the sampling configuration parameter set of the analog-to-digital converter.

[0034] The waveform acquisition module acquires a sequence of time-series current waveforms by referring to the sampling configuration parameter set.

[0035] The spectrum component construction module takes the time-series current waveform sequence as the discrete-time signal input in the discrete Fourier transform, calculates the corresponding spectrum component data, and constructs the frequency domain spectrum component sequence.

[0036] The anomaly detection module, based on the frequency domain spectral component sequence, determines abnormal fluctuations in the chip's motherboard current and obtains the anomaly detection results.

[0037] Compared with the prior art, the advantages and positive effects of the present invention are as follows:

[0038] In this invention, a comparator circuit monitors the pulse width modulation signal of the voltage regulator control chip and generates a transient current fluctuation event trigger signal based on the comparison between the absolute value of the duty cycle change rate and a preset duty cycle change rate threshold. This ensures that the triggering determination of current fluctuations corresponds to the abrupt change in the power supply regulation signal. The core processor power domain identifier is determined through the trigger channel, and the microcontroller in the board management controller controls the analog-to-digital converter to switch the corresponding channel to a higher sampling frequency, enabling the acquisition process to target the power domain where the fluctuation occurs. Furthermore, the acquired time-series current waveform sequence is frequency domain converted, and the target spectral component data corresponding to the nominal switching frequency and the preset resonant frequency are extracted from the frequency domain spectral component sequence. The current fluctuation anomaly detection result is generated based on the comparison between the amplitude of the spectral component data and a preset background noise level threshold. This process continuously triggers, locates, samples, performs frequency domain analysis, and determines anomalies in the transient current fluctuations of the server motherboard. Attached Figure Description

[0039] Figure 1 This is a flowchart of the method steps of the present invention;

[0040] Figure 2 This is a system module diagram of the present invention. Detailed Implementation

[0041] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0042] Please see Figure 1 This invention provides a technical solution: a method for detecting abnormal current fluctuations on a chip motherboard, used to detect abnormal current fluctuations on a server motherboard, comprising the following steps:

[0043] S1: Monitor the pulse width modulation signal of the voltage regulator control chip on the motherboard to determine the transient current fluctuation event trigger signal and obtain the corresponding core processor power domain identifier, including:

[0044] The pulse width modulation signal of the voltage regulator control chip on the motherboard is monitored by a comparator circuit. The duty cycle value of the pulse width modulation signal at two consecutive sampling time points is obtained. Based on the time interval between the two sampling time points and the duty cycle value, the duty cycle change rate of the pulse width modulation signal is calculated, and the absolute value of the corresponding duty cycle change rate is obtained.

[0045] First, the comparator circuit receives periodic voltage levels from the signal pins of the voltage regulator control chip. The comparator circuit is the hardware circuit that compares the input level with a reference level and outputs the channel status. The voltage regulator control chip is the chip that controls the power supply switching on and off of the server motherboard. The pulse width modulation signal is a periodic signal that represents the power supply regulation status by the proportion of the high-level duration to the complete cycle time. The duty cycle value refers to the proportion of the high-level duration to the complete cycle time. Next, the comparator circuit records the channel number, sampling time, complete cycle time, high-level duration, and duty cycle value at continuous sampling moments. Before processing, it discards samples with empty sampling times, empty channel numbers, complete cycle times of 0, and high-level durations greater than [a certain value]. For records with complete cycle time, duty cycle values ​​less than 0, and duty cycle values ​​greater than 100, if duplicate records exist at the same sampling time in the same channel, the first one written is retained. Then, two adjacent valid records in the same channel are taken, the previous duty cycle value is recorded as the initial duty cycle, the next duty cycle value is recorded as the final duty cycle, and the interval between the next sampling time and the previous sampling time is recorded as the sampling time interval. The duty cycle change rate = (final duty cycle - initial duty cycle) / sampling time interval. Next, the absolute value of the duty cycle change rate is taken. If the duty cycle change rate is less than 0, its opposite is taken as the current result. If the duty cycle change rate is equal to 0, 0 is taken as the current result. If the duty cycle change rate is greater than 0, the original value is taken as the current result. Finally, the absolute value of the duty cycle change rate is generated.

[0046] When the absolute value of the duty cycle change rate exceeds the preset duty cycle change rate threshold, a transient current fluctuation event is determined to have occurred, and a transient current fluctuation event trigger signal is generated. When the absolute value of the duty cycle change rate is less than or equal to the duty cycle change rate threshold, the comparator circuit continues to monitor the pulse width modulation signal.

[0047] The absolute value of the duty cycle change rate is read, and then the preset duty cycle change rate threshold stored in the register is read. The preset duty cycle change rate threshold refers to the boundary value between normal power supply regulation changes and sudden power supply changes. This threshold is determined during the motherboard debugging phase. Specifically, the server motherboard is subjected to idle load, rated load, and peak stable load in sequence. The comparator circuit collects the pulse width modulation signals of the corresponding channels in the CPU core power supply area, CPU non-core power supply area, and memory power supply area, respectively, and generates the absolute value of the duty cycle change rate of each channel in a certain manner. Records with missing sampling time, missing channel number, duty cycle values ​​exceeding the limit, and sampling time interval of 0 are discarded, and the maximum absolute value of the duty cycle change rate of each channel under normal power supply conditions is retained. Then, the sampling timing resolution and duty cycle of the comparator circuit are read. Duty cycle quantization resolution converts both to the same dimension as the absolute value of duty cycle change rate. A preset duty cycle change rate threshold is defined as: maximum absolute value of duty cycle change rate under normal power supply conditions + sampling timing resolution conversion value + duty cycle quantization resolution conversion value. Then, the current absolute value of duty cycle change rate is compared to this threshold. If the current absolute value of duty cycle change rate is greater than the threshold, a trigger level is output. The trigger level refers to the hardware level signal sent by the comparator circuit to subsequent sampling components. If the current absolute value of duty cycle change rate is equal to the threshold, no trigger level is output, and subsequent pulse width modulation signals are continued to be received. If the current absolute value of duty cycle change rate is less than the threshold, no trigger level is output, and subsequent pulse width modulation signals are continued to be received. Finally, a transient current fluctuation event trigger signal is generated, or the monitoring status continues.

[0048] When a transient current fluctuation event trigger signal is generated, the associated core processor power domain identifier is determined based on the comparator circuit channel of the output transient current fluctuation event trigger signal. The core processor power domain identifier includes the CPU core power domain identifier, the CPU non-core power domain identifier, and the memory power domain identifier.

[0049] After the trigger level appears, the comparator circuit channel number that generated the trigger level is read. The channel number refers to the marker assigned to each detection path during the motherboard wiring stage. Next, the channel mapping record stored in the motherboard register is read. The channel mapping record consists of the comparator circuit channel number and the power domain identifier. The power domain identifier is a marker used to distinguish the power supply areas of the server motherboard. The CPU core power domain identifier corresponds to the CPU execution core power supply area, the CPU non-core power domain identifier corresponds to the CPU internal non-execution core power supply area, and the memory power domain identifier corresponds to the memory power supply area. Then, the channel number that generated the trigger level is compared with the channel number in the channel mapping record item by item. If the number matches, the power domain identifier of that item is read. If the number does not match, the process moves to the next item. If all the numbers do not match, the trigger channel is recorded as an unmatched channel. Finally, the associated core CPU power domain identifier or unmatched channel record is generated.

[0050] S2: Send the transient current fluctuation event trigger signal to the analog-to-digital converter on the motherboard, adjust the analog-to-digital converter channel configuration status, combine the core processor power domain identifier, and obtain the sampling configuration parameter set of the analog-to-digital converter, including:

[0051] Based on the received transient current fluctuation event trigger signal, the microcontroller in the baseboard management controller on the motherboard generates the corresponding sampling mode switching instruction;

[0052] The trigger level, trigger channel number, and trigger time are sent to the microcontroller within the baseboard management controller (BMS). The BMS refers to the controller on the motherboard that manages the hardware status, while the microcontroller is the control unit that performs register reading, status recording, and configuration writing. The trigger time refers to the timing value corresponding to the occurrence of the trigger level. Next, the microcontroller reads the trigger records and discards records with empty trigger times, empty trigger channel numbers, or unidentifiable trigger level states. Then, a sampling mode switching flag is written when the trigger level is in an active state, and no sampling mode switching flag is written when the trigger level is in an inactive state. Next, the power domain identifier corresponding to the trigger channel number is read, and the target channel, switching state, and trigger time are written to the same instruction record. This reading and writing process is completed by the firmware within the microcontroller. The firmware source file is compiled after configuring the microcontroller model, register address, clock parameters, and storage address in the KeiluVision software, and then written to the microcontroller within the baseboard management controller. Finally, a sampling mode switching instruction or a non-switched record is generated.

[0053] The sampling mode switching command is sent to the analog-to-digital converter on the motherboard, which switches the channel in the analog-to-digital converter on the motherboard corresponding to the core processor power domain identifier from the first sampling frequency to the second sampling frequency, and adjusts the channel configuration status of the analog-to-digital converter. The second sampling frequency is higher than the first sampling frequency.

[0054] The sampling mode switching command is written to the analog-to-digital converter (ADC) configuration interface. The ADC is a device that converts analog current detection signals into digital current data. The channel refers to the input path through which the ADC receives current detection signals from different power supply areas. The first sampling frequency refers to the normal sampling frequency before triggering, and the second sampling frequency refers to the continuous sampling frequency after triggering. Next, the current first sampling frequency of the target channel is read. The process of setting the first sampling frequency involves collecting background current data from the target power supply area under normal motherboard power supply conditions, reading sampling records at different frequency levels of the ADC, eliminating frequency levels with missing sampling sequence numbers, missing sampling times, or interrupted channel data, retaining frequency levels that can continuously record background current changes, and writing the lowest value among the retained frequency levels into the normal sampling interface. The system first configures the first sampling frequency. Then, it reads the second sampling frequency. The process of setting the second sampling frequency involves reading the nominal switching frequency of the voltage regulator and the preset resonant frequency, and recording the larger of the two frequencies as the frequency of interest. The candidate value of the second sampling frequency is greater than the frequency of interest × 2. The system selects the frequency range that satisfies this relationship and continuously outputs digital current data from the frequency ranges supported by the analog-to-digital converter. Next, the two sampling frequencies are compared. When the second sampling frequency is greater than the first sampling frequency, the target channel sampling frequency is written as the second sampling frequency and the switching status is recorded. When the second sampling frequency is equal to the first sampling frequency, the frequency increase configuration is not written and the frequency is recorded as not increasing. When the second sampling frequency is less than the first sampling frequency, the frequency increase configuration is not written and the configuration source is recorded as incorrect. Finally, the analog-to-digital converter channel configuration status is generated.

[0055] By combining the channel configuration status of the analog-to-digital converter with the corresponding core processor power domain identifier, the sampling configuration parameter set of the analog-to-digital converter is obtained;

[0056] Read the analog-to-digital converter channel configuration status and power domain identifier. The channel configuration status refers to the target channel's sampling frequency, start / stop status, trigger time, and sampling duration record. The preset sampling duration refers to the length of time for continuous current data acquisition after triggering. Next, read the target channel number, power domain identifier, second sampling frequency, preset sampling duration, and trigger time. No sampling configuration record is generated if the target channel number is empty or the power domain identifier is empty. If the channel configuration status is "switched," continue writing the configuration record. If the channel configuration status is "frequency not increased," record the "no frequency increase" configuration. If the channel configuration status is "configuration source incorrect," record the configuration exception. The process of setting the sampling duration is as follows: during the motherboard debugging phase, the load is switched between the CPU core power supply area, the CPU non-core power supply area, and the memory power supply area. The current detection path records the current waveform after the trigger, reads the start time of the current fluctuation and the end time when the current returns to the background noise level range, and the duration of a single fluctuation = end time - start time. The preset sampling duration = the maximum value of the duration of a single fluctuation in each power domain + the time interval between adjacent sampling. Then, the target channel number, power domain identifier, second sampling frequency, preset sampling duration, trigger time, and channel configuration status are written into the same record, and finally, a sampling configuration parameter set is generated.

[0057] S3: Referring to the sampling configuration parameter set, the time-series current waveform sequence collected includes:

[0058] Determine the target power domain pointed to by the core processor power domain identifier in the sampling configuration parameter set;

[0059] The system reads the power domain identifiers from the sampling configuration parameter set and the motherboard power supply topology record. The power supply topology record refers to the corresponding record between the power domain identifier, the analog-to-digital converter channel, and the actual power supply detection position. The actual power supply detection position refers to the location where the current detection path connects to the server motherboard power supply circuit. Next, the power domain identifiers are compared item by item with the identifiers in the power supply topology record. If the identifiers match, the power supply detection position and target channel for that item are read. If the identifiers do not match, the system continues to compare the next item. Then, the target power supply area is determined based on the read identifiers. When the CPU core power domain identifier is read, the CPU core power supply area is used as the current target power domain result. When the CPU non-core power domain identifier is read, the CPU non-core power supply area is used as the current target power domain result. When the memory power domain identifier is read, the memory power supply area is used as the current target power domain result. If no matching identifier is read, an empty record is used as the current target power domain result. Finally, a target power domain or an empty target power domain record is generated.

[0060] In the analog-to-digital converter channel configuration state, the target power domain is continuously sampled through the analog-to-digital converter channel according to the second sampling frequency and the preset sampling duration to obtain digital current data; the preset sampling duration is set according to the length of time from the trigger time to the end time of the current fluctuation in the target power domain after the transient current fluctuation event occurs on the server motherboard.

[0061] The corresponding analog-to-digital converter (ADC) channel is selected based on the target power domain. The second sampling frequency and preset sampling duration are read. The current detection path refers to the hardware path that converts the current state in the power supply circuit into an analog current detection signal that the ADC can receive. The analog current detection signal refers to a continuously changing electrical signal, and the digital current data refers to the numerical record obtained by the ADC according to the sampling time. Then, starting from the trigger time, the sampling interval is 1 / second sampling frequency. The ADC reads the analog current detection signal of the target channel according to this sampling interval and writes the record after each conversion as the sampling sequence number, sampling time, target channel number, and current value. Then, the cumulative sampling time is compared. If the cumulative sampling time is less than the preset sampling duration, reading continues. If the cumulative sampling time is equal to the preset sampling duration, reading stops. If the cumulative sampling time is greater than the preset sampling duration, reading stops and records exceeding the duration range are discarded. Then, current records that cannot be converted into values, records with missing sampling times, and records with duplicate sampling sequence numbers are removed. If the sampling sequence number is duplicated, the earlier one is retained. Finally, digital current data is generated.

[0062] Extract all the collected digital current data and arrange them in chronological order to form a time-series current waveform sequence;

[0063] Read all digital current data retained within a preset sampling duration. Digital current data refers to the current value records obtained after the analog-to-digital converter performs discrete sampling on the analog current detection signal. The sampling time refers to the time record corresponding to each current value, and the sampling sequence number refers to the number arranged in the order of acquisition within the same channel. Then, arrange the records from earliest to latest according to the sampling time, and arrange the records with the same sampling time from smallest to largest according to the sampling sequence number. Next, check the sampling time interval between adjacent records. The time interval between adjacent records = the next sampling time - the previous sampling time. When the interval is equal to the sampling interval corresponding to the second sampling frequency, retain the adjacent relationship. When the interval is greater than the sampling interval, record the sampling gap. When the interval is less than the sampling interval, record the repeated sampling and retain the earlier written record. Then, write the sorted current values ​​into the sequence positions in chronological order. Each sequence position corresponds to a sampling time and a current value. Finally, generate a time-series current waveform sequence.

[0064] S4: Using the time-series current waveform sequence as the discrete-time signal input in the discrete Fourier transform, calculate the corresponding spectral component data, and construct the frequency domain spectral component sequence, including:

[0065] The time-series current waveform sequence is used as the discrete-time signal input in the discrete Fourier transform;

[0066] The system reads the time-series current waveform sequence and assigns a discrete-time node index to each current value according to the sampling time order. The discrete-time node index is an integer number that increments continuously from the starting sampling point. The discrete-time signal refers to the set of current values ​​arranged according to the discrete-time node index. Next, records with empty current values ​​and records with duplicate discrete-time node indices are removed. When duplicates occur, the earlier one is retained, and the data is rearranged according to the discrete-time node index. Then, the total number of data points is read. If the total number of data points is 0, the frequency domain conversion calculation is not performed. If the total number of data points is 1, the single-point input state is recorded. If the total number of data points is greater than 1, the sequence is sent to the Discrete Fourier Transform (DFT) calculation. The DFT is the process of converting discrete current values ​​arranged by time into complex components arranged by frequency position. This calculation is performed by the firmware within the microcontroller. The firmware source file is compiled after configuring the data storage area, fixed-point bit width, frequency index range, and result storage address in Keil uVision software, and then written to the microcontroller. Finally, it generates discrete-time signal input or non-conversion records.

[0067] The microcontroller within the motherboard's baseboard management controller performs frequency domain conversion on the discrete-time signal input to obtain spectral component data; the formula for calculating the spectral component data is as follows: In the formula, For spectral component data, These are data points in a time-series current waveform sequence. This represents the total number of data points in the time-series current waveform sequence. This is the discrete time node index of the corresponding data point in the time-series current waveform sequence. For frequency indexing in frequency domain conversion, is the base of the natural logarithm. The imaginary unit, Pi;

[0068] The microcontroller reads the discrete-time signal input. The microcontroller refers to the control unit within the baseboard management controller that performs frequency domain conversion calculations. The frequency index refers to the number of different frequency positions in the frequency domain, and the spectral component data refers to the complex number result corresponding to each frequency index, which consists of a real part and an imaginary part. Next, the firmware reads the total number of data points and allocates a storage location for the result for each frequency index. Then, for any frequency index, it reads the discrete-time node index and the corresponding current value one by one. The current value is then multiplied by a rotation factor determined by the frequency index, discrete-time node index, total number of data points, base of the natural logarithm, imaginary unit, and pi. The base of the natural logarithm is a fixed constant in the rotation factor, the imaginary unit is the unit that forms the imaginary part, and pi is the circumferential constant in the rotation factor. Then, all product results under the same frequency index are summed to obtain the corresponding real and imaginary parts, and the same process is repeated for all frequency indices. This calculation is performed in Keil. uVision is compiled and written into the microcontroller's firmware for execution. The inputs are discrete-time node indices and current values, and the outputs are written to the real part storage location and the imaginary part storage location, finally generating spectral component data.

[0069] Combine all spectral component data to obtain the frequency domain spectral component sequence;

[0070] Read all the spectral component data corresponding to the frequency indices. The spectral component data consists of the frequency index, real part, and imaginary part. The real part refers to the value of the complex number result in the real direction, and the imaginary part refers to the value of the complex number result in the imaginary direction. Next, check the integrity of each record. If the real part is missing, mark the record as incomplete. If the imaginary part is missing, mark the record as incomplete. If both the real and imaginary parts exist, retain the record. Then, retain the records in ascending order of frequency index. If the frequency index is repeated, retain the record that was calculated first. If the frequency index is missing, record the missing position. Then, write the arranged spectral component data into the same sequence in sequence. Finally, generate the frequency domain spectral component sequence.

[0071] S5: Based on the frequency domain spectral component sequence, determine abnormal conditions of current fluctuations on the chip motherboard, and obtain the following abnormality detection results:

[0072] Obtain the nominal switching frequency and preset resonant frequency of the voltage regulator on the motherboard, and extract the target spectral component data corresponding to the nominal switching frequency and preset resonant frequency from the frequency domain spectral component sequence;

[0073] The nominal switching frequency and preset resonant frequency of the voltage regulator are read. The voltage regulator is the device that converts the power input to the server motherboard into power for the processor and memory. The nominal switching frequency refers to the switching operating frequency specified in the voltage regulator control chip configuration register or the motherboard power supply design record. The preset resonant frequency refers to the oscillation frequency that needs to be considered in the power supply circuit. The process of setting the preset resonant frequency involves reading the inductance parameters, capacitance parameters, and equivalent parasitic parameters in the power supply circuit of the target power supply area. During the motherboard debugging phase, the load of the target power supply area is switched. The frequency domain spectrum component sequence after multiple load switching is obtained according to the aforementioned sampling and frequency domain conversion process. The frequency spectrum component sequence that appears repeatedly in multiple records and is different from the nominal switching frequency is read. The frequency position of the frequency is then compared with the frequency results corresponding to the inductance parameters, capacitance parameters, and equivalent parasitic parameters. If the comparison is consistent, the preset resonant frequency is written. Next, the frequency position corresponding to each frequency index in the frequency domain spectrum component sequence is read, and the frequency position is compared with the nominal switching frequency and the preset resonant frequency item by item. If the frequency position is consistent with the nominal switching frequency, the corresponding spectrum component data is extracted. If the frequency position is consistent with the preset resonant frequency, the corresponding spectrum component data is extracted. If the frequency position is inconsistent with both, the data of that frequency position is not extracted. If no corresponding frequency position is found, an empty record is used as the current target spectrum component result. Finally, target spectrum component data or an empty target spectrum component record is generated.

[0074] Calculate the sum of the squares of the real and imaginary parts of the target spectral component data and perform the square root operation to obtain the amplitude of the target spectral component data;

[0075] The process begins by reading the real and imaginary parts of the target spectral component data. The real part refers to the value of the target spectral component data in the real direction, and the imaginary part refers to the value of the target spectral component data in the imaginary direction. The amplitude of the spectral component data is a non-negative value determined by both the real and imaginary parts. Next, the numerical status of the real and imaginary parts is checked. If either the real or imaginary part is missing, amplitude calculation is not performed. If both the real and imaginary parts exist, processing continues. Finally, the amplitude is calculated according to the formula. , , , When both the real and imaginary parts are 0, 0 is taken as the current amplitude result. When at least one of the real and imaginary parts is not 0, the non-negative value after taking the square root is taken as the current amplitude result. This calculation is completed by the firmware in the microcontroller. The firmware source file is compiled and written to the microcontroller after configuring the real part input address, imaginary part input address and amplitude output address in the KeiluVision software. Finally, the amplitude of the spectrum component data of the target spectrum component data is generated.

[0076] When the amplitude of the spectral component data exceeds the preset background noise level threshold, it is determined that there is an abnormal current fluctuation on the chip motherboard, and an abnormal current fluctuation detection result is generated.

[0077] The target spectral component data amplitude is read, and a preset background noise level threshold is read. The preset background noise level threshold refers to the allowed background spectral amplitude boundary at the target frequency position under normal motherboard current fluctuations. The threshold setting process involves placing the server motherboard under idle load, rated load, and peak stable load, respectively, and collecting current data from the CPU core power supply area, CPU non-core power supply area, and memory power supply area. Current waveform sequences are formed in chronological order, and then the frequency domain spectral component sequence is obtained through the aforementioned frequency domain conversion process. The spectral component data amplitudes corresponding to the nominal switching frequency and the preset resonant frequency are extracted. Records with missing sampling times, missing channel numbers, missing real parts, missing imaginary parts, and missing frequency indices are removed. The remaining records are then used to obtain... The maximum amplitude of the spectral component data under normal power supply conditions is determined. Next, the current quantization resolution and channel noise floor records of the analog-to-digital converter are read and converted to the same dimension as the amplitude of the spectral component data. The preset background noise level threshold is calculated as: maximum amplitude of the spectral component data under normal power supply conditions + current quantization resolution converted value + channel noise floor converted value. Then, the current amplitude of the spectral component data is compared with the preset background noise level threshold. If the current amplitude of the spectral component data is greater than the threshold, it is determined that there is an abnormal current fluctuation on the chip motherboard. If the current amplitude of the spectral component data is equal to the threshold, it is determined that the abnormal triggering condition has not been met. If the current amplitude of the spectral component data is less than the threshold, it is determined that the abnormal triggering condition has not been met. Finally, an abnormal current fluctuation detection result or an abnormality record is generated.

[0078] Please see Figure 2 A chip motherboard current fluctuation anomaly detection system is used to detect abnormal current fluctuations on a server motherboard. The system includes:

[0079] The fluctuation trigger determination module monitors the pulse width modulation signal of the voltage regulator control chip on the motherboard, determines the transient current fluctuation event trigger signal from it, and obtains the corresponding core processor power domain identifier.

[0080] The parameter determination module sends the transient current fluctuation event trigger signal to the analog-to-digital converter on the motherboard, adjusts the channel configuration status of the analog-to-digital converter, and combines the core processor power domain identifier to obtain the sampling configuration parameter set of the analog-to-digital converter.

[0081] The waveform acquisition module acquires a sequence of time-series current waveforms by referring to the sampling configuration parameter set.

[0082] The spectrum component construction module takes the time-series current waveform sequence as the discrete-time signal input in the discrete Fourier transform, calculates the corresponding spectrum component data, and constructs the frequency domain spectrum component sequence.

[0083] The anomaly detection module, based on the frequency domain spectral component sequence, determines abnormal fluctuations in the chip's motherboard current and obtains the anomaly detection results.

[0084] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention in any other way. Any person skilled in the art may make changes or modifications to the above-disclosed technical content to create equivalent embodiments that can be applied to other fields. However, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the protection scope of the present invention.

Claims

1. A chip mainboard current fluctuation anomaly detection method for detecting abnormal current fluctuation of a server mainboard, characterized in that, Includes the following steps: Monitor the pulse width modulation signal of the voltage regulator control chip on the motherboard to determine the transient current fluctuation event trigger signal and obtain the corresponding core processor power domain identifier. The transient current fluctuation event trigger signal is sent to the analog-to-digital converter on the motherboard, the channel configuration status of the analog-to-digital converter is adjusted, and the core processor power domain identifier is combined to obtain the sampling configuration parameter set of the analog-to-digital converter; Collect the timing current waveform sequence by referring to the sampling configuration parameter set; The time-series current waveform sequence is used as the discrete-time signal input in the discrete Fourier transform, and the corresponding spectral component data is calculated to construct the frequency domain spectral component sequence. Based on the frequency domain spectral component sequence, abnormal situations of current fluctuations on the chip motherboard are determined, and abnormality detection results are obtained. The method of determining abnormal fluctuations in the chip motherboard current based on the frequency domain spectral component sequence, and obtaining abnormal detection results, includes: Obtain the nominal switching frequency and preset resonant frequency of the voltage regulator on the motherboard, and extract the target spectral component data corresponding to the nominal switching frequency and preset resonant frequency from the frequency domain spectral component sequence; The sum of the squares of the real and imaginary parts of the target spectral component data is calculated and the square root is taken to obtain the amplitude of the spectral component data of the target spectral component data; When the amplitude of the spectral component data exceeds a preset background noise level threshold, it is determined that there is an abnormal current fluctuation on the chip motherboard, and an abnormal current fluctuation detection result is generated.

2. The chip mainboard current fluctuation abnormality detection method according to claim 1, characterized by, The process of monitoring the pulse width modulation signal of the voltage regulator control chip on the motherboard, determining the transient current fluctuation event trigger signal from it, and obtaining the corresponding core processor power domain identifier includes: The pulse width modulation signal of the voltage regulator control chip on the motherboard is monitored by a comparator circuit. The duty cycle value of the pulse width modulation signal at two consecutive sampling time points is obtained. Based on the time interval between the two sampling time points and the duty cycle value, the duty cycle change rate of the pulse width modulation signal is calculated, and the absolute value of the corresponding duty cycle change rate is obtained. When the absolute value of the duty cycle change rate exceeds the preset duty cycle change rate threshold, a transient current fluctuation event is determined to have occurred, and a transient current fluctuation event trigger signal is generated. When the absolute value of the duty cycle change rate is less than or equal to the duty cycle change rate threshold, the comparator circuit continues to monitor the pulse width modulation signal. When a transient current fluctuation event trigger signal is generated, the associated core processor power domain identifier is determined based on the comparator circuit channel of the output transient current fluctuation event trigger signal.

3. The chip mainboard current fluctuation abnormality detection method according to claim 2, characterized by, The process of sending the transient current fluctuation event trigger signal to the analog-to-digital converter on the motherboard, adjusting the analog-to-digital converter channel configuration state, and combining the core processor power domain identifier to obtain the sampling configuration parameter set of the analog-to-digital converter includes: Based on the received transient current fluctuation event trigger signal, the microcontroller in the baseboard management controller on the motherboard generates a corresponding sampling mode switching instruction; The sampling mode switching command is sent to the analog-to-digital converter on the motherboard, and the channel in the analog-to-digital converter on the motherboard corresponding to the power domain identifier of the core processor is switched from the first sampling frequency to the second sampling frequency, and the channel configuration status of the analog-to-digital converter is adjusted, wherein the second sampling frequency is higher than the first sampling frequency; By combining the analog-to-digital converter channel configuration state with the corresponding core processor power domain identifier, a set of sampling configuration parameters for the analog-to-digital converter is obtained.

4. The chip mainboard current fluctuation abnormality detection method according to claim 3, characterized by, The reference sampling configuration parameter set includes the time-series current waveform sequence for acquisition: Determine the target power domain pointed to by the core processor power domain identifier in the sampling configuration parameter set; In the analog-to-digital converter channel configuration state, the target power domain is continuously sampled through the analog-to-digital converter channel according to the second sampling frequency and the preset sampling duration to obtain digital current data; All the collected digital current data are extracted and arranged in chronological order to form a time-series current waveform sequence.

5. The chip mainboard current fluctuation abnormality detection method according to claim 4, characterized by, The step of using the time-series current waveform sequence as the discrete-time signal input in the discrete Fourier transform, calculating the corresponding spectral component data, and constructing the frequency domain spectral component sequence includes: The time-series current waveform sequence is used as the discrete-time signal input in the discrete Fourier transform; The microcontroller in the baseboard management controller on the motherboard performs frequency domain conversion calculations on the discrete-time signal input to obtain spectral component data. By combining all the spectral component data, a frequency domain spectral component sequence is obtained.

6. The chip mainboard current fluctuation abnormality detection method according to claim 2, characterized by, The core processor power domain identifier includes the CPU core power domain identifier, the CPU non-core power domain identifier, and the memory power domain identifier.

7. The chip mainboard current fluctuation abnormality detection method according to claim 4, characterized by, The preset sampling duration is set according to the length of time from the trigger moment to the end moment of the current fluctuation in the target power domain after a transient current fluctuation event occurs on the server motherboard.

8. The chip mainboard current fluctuation abnormality detection method according to claim 5, characterized by, The formula for calculating the spectral component data is: ； In the formula, For spectral component data, These are data points in a time-series current waveform sequence. This represents the total number of data points in the time-series current waveform sequence. This is the discrete time node index for the corresponding data point in the time-series current waveform sequence. For frequency indexing in frequency domain conversion, is the base of the natural logarithm. The imaginary unit, Pi is the mathematical constant of a circle.

9. A chip motherboard current fluctuation anomaly detection system, used to detect abnormal current fluctuations on a server motherboard, characterized in that, The system includes: The fluctuation trigger determination module monitors the pulse width modulation signal of the voltage regulator control chip on the motherboard, determines the transient current fluctuation event trigger signal from it, and obtains the corresponding core processor power domain identifier. The parameter determination module sends the transient current fluctuation event trigger signal to the analog-to-digital converter on the motherboard, adjusts the channel configuration status of the analog-to-digital converter, and combines the core processor power domain identifier to obtain the sampling configuration parameter set of the analog-to-digital converter. The waveform acquisition module acquires a sequence of time-series current waveforms by referring to the sampling configuration parameter set. The spectrum component construction module takes the time-series current waveform sequence as the discrete-time signal input in the discrete Fourier transform, calculates the corresponding spectrum component data, and constructs the frequency domain spectrum component sequence. The anomaly detection module, based on the frequency domain spectral component sequence, determines abnormal fluctuations in the chip's motherboard current and obtains the anomaly detection results. The method of determining abnormal fluctuations in the chip motherboard current based on the frequency domain spectral component sequence, and obtaining abnormal detection results, includes: Obtain the nominal switching frequency and preset resonant frequency of the voltage regulator on the motherboard, and extract the target spectral component data corresponding to the nominal switching frequency and preset resonant frequency from the frequency domain spectral component sequence; The sum of the squares of the real and imaginary parts of the target spectral component data is calculated and the square root is taken to obtain the amplitude of the spectral component data of the target spectral component data; When the amplitude of the spectral component data exceeds a preset background noise level threshold, it is determined that there is an abnormal current fluctuation on the chip motherboard, and an abnormal current fluctuation detection result is generated.

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