Test circuit for accurate transistor leakage current measurement

Abstract

The present disclosure relates to a test circuit for accurate transistor leakage current measurement. A circuit (101) includes an amplifier (106), a first transistor (108), a second transistor (110), a set of transistors (112), a first switch (208) and a second switch (210), component circuitry (136), and a control circuit (130). The first transistor (108) and the second transistor (110) and the set of transistors (112) include a first current terminal, a second current terminal, and a control terminal, respectively. The first current terminal of the second transistor (110) is coupled to the first current terminal of the first transistor (108), and the control terminal of the second transistor (110) is coupled to the control terminal of the first transistor (108). The first current terminal of the set of transistors (112) is coupled to the control terminal of the set of transistors (112). A first current terminal of the first switch (208) is coupled to an input (122) of the amplifier (106), and a second terminal of the first switch (208) is coupled to the second current terminal of the set of transistors (112).

Description

[0001] Citation of relevant applications

[0002] This application claims priority and benefit to U.S. Provisional Application No. 63 / 771,974, filed March 14, 2025, entitled “Analog Front-End for Accurate Transistor Leakage Current Measurements,” the entire contents of which are incorporated herein by reference as if fully set forth herein. Technical Field

[0003] This disclosure generally relates to an integrated circuit, and more specifically, to a test circuit for accurate transistor leakage current measurement. Background Technology

[0004] An integrated circuit (IC) can be a semiconductor device that includes interconnecting devices such as transistors, diodes, resistors, capacitors, processors, or other component circuit systems that work together to enable the IC to perform various tasks. These tasks may include, for example, controlling electronic devices or performing device-specific logic operations. During manufacturing, the circuit utilizes one or more test structures on a silicon substrate to measure and characterize the electrical parameters associated with the devices on the IC. Summary of the Invention

[0005] In some examples, a circuit includes an amplifier, a first transistor, a second transistor, and a third transistor. The amplifier includes an output and an input. The first transistor includes a first current terminal, a second current terminal, and a control terminal. The control terminal of the first transistor is coupled to the output of the amplifier. The second transistor includes a current terminal and a control terminal. The current terminal of the second transistor is coupled to the first current terminal of the first transistor, and the control terminal of the second transistor is coupled to the control terminal of the first transistor and the output of the amplifier. The third transistor includes a first current terminal, a second current terminal, and a control terminal. The second current terminal of the third transistor is coupled to the input of the amplifier and the second current terminal of the first transistor. The control terminal of the third transistor is coupled to the first current terminal of the third transistor.

[0006] In some examples, a circuit includes an amplifier, a first transistor and a second transistor, a set of transistors, a first switch and a second switch. The amplifier includes an output and an input. The first transistor includes a first current terminal, a second current terminal, and a control terminal. The control terminal of the first transistor is coupled to the output of the amplifier. The second transistor includes a current terminal and a control terminal. The current terminal of the second transistor is coupled to the first current terminal of the first transistor, and the control terminal of the second transistor is coupled to the control terminal of the first transistor and the output of the amplifier. The set of transistors each includes a first current terminal, a second current terminal, and a control terminal, wherein the first current terminal of the set of transistors is coupled to the control terminal of the set of transistors. The first switch includes a first terminal and a second terminal. The first terminal of the first switch is coupled to the input of the amplifier, and the second terminal of the first switch is coupled to the second current terminal of the set of transistors. The second switch includes a first terminal and a second terminal. The first terminal of the second switch is coupled to the second current terminal of the first transistor, and the second terminal of the second switch is coupled to the second current terminal of the first set of transistors.

[0007] In some instances, a circuit includes an amplifier, a first transistor and a second transistor, a set of transistors, a first switch, at least one component circuit system, and control circuitry. The amplifier includes an output and an input. The first transistor includes a first current terminal, a second current terminal, and a control terminal. The second transistor includes a current terminal and a control terminal. The current terminal of the second transistor is coupled to the first current terminal of the first transistor, and the control terminal of the second transistor is coupled to the control terminal of the first transistor. The set of transistors each includes a first current terminal, a second current terminal, and a control terminal. The first current terminal of the set of transistors is coupled to the control terminal of the set of transistors. The first switch includes a first terminal and a second terminal. The first terminal of the first switch is coupled to the input of the amplifier, and the second terminal of the first switch is coupled to the second current terminal of the set of transistors. At least one component circuit system is coupled to the amplifier or the second transistor via the second switch. The control circuitry coupled to the first and second switches couples the set of transistors to the amplifier and decouples at least one component circuit system from the amplifier or the second transistor when switching from a normal operating mode to a test operating mode. Attached Figure Description

[0008] To gain a more complete understanding of this disclosure and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, in which:

[0009] Figure 1 A system for determining the leakage current in a circuit of a device under test (DUT) based on some examples.

[0010] Figure 2This is a system that includes test circuitry to determine the leakage current in a DUT, based on some examples.

[0011] Figure 3 This is a system that includes test circuitry based on some examples to determine the leakage current in various types of DUTs.

[0012] Figure 4 This is based on some examples of systems that include Miller capacitors in test circuits to determine the leakage current in various types of DUTs.

[0013] Figure 5 This is a system that includes bias current and test circuitry based on some examples to determine the leakage current in various types of DUTs.

[0014] Figure 6 This is a system that includes test circuitry and current-based absorption paths, based on some examples, to determine the leakage current in various types of DUTs.

[0015] Figure 7 This is a system that includes test circuitry and resistor-based absorption paths to determine leakage current in various types of DUTs, based on some examples.

[0016] Figure 8 This is a system that includes test circuitry and a programmable array to determine leakage current in various types of DUTs, based on some examples.

[0017] Figure 9 This is a system for calibrating amplifiers in a test circuit system, based on some examples, and for using programmable arrays to determine leakage current in various types of DUTs.

[0018] Figure 10 This is a system for calibrating current mirrors in a test circuit system, based on some examples, and for using programmable arrays to determine leakage current in various types of DUTs.

[0019] Figure 11 This document outlines the process flow for a circuit system containing test circuits to determine leakage current in various types of DUTs, based on some examples. Detailed Implementation

[0020] Unless otherwise indicated, corresponding marks and symbols in different drawings generally refer to corresponding parts. The drawings are drawn to clearly illustrate relevant aspects of the preferred embodiments, and the drawings are not necessarily drawn to scale.

[0021] ICs are made through a manufacturing process in which layers are continuously built onto a semiconductor wafer through material deposition, photolithography, etching, chemical mechanical planarization (CMP), and other steps. Semiconductor wafers are typically circular disk-shaped structures containing multiple die areas. Dies are typically square or rectangular, arranged in a grid pattern on the wafer's surface. Each die contains a separate circuit. Therefore, when the individual layers are fabricated, the disk-shaped wafer is diced into many dies. Each die is then packaged to form a "chip," allowing a single wafer to ultimately produce a large number of chips. Ideally, each die / chip will have identical electrical characteristics. However, in reality, due to small, uncontrollable variations during the manufacturing process, dies / chips exhibit small variations in their electrical characteristics. Manufacturing facilities strive to measure these variations as dies / chips are formed and continuously tune the manufacturing process to help ensure that the final dies / chips have electrical characteristics within acceptable limits.

[0022] To measure the electrical characteristics of different dies and wafers, fabs typically manufacture wafers that include commercial dies and separate test dies. Commercial dies contain the circuitry that will be packaged into chips ready for sale, while test dies contain test structures that allow the fab to characterize the electrical characteristics of devices (such as transistors) manufactured in the factory. After measuring the electrical characteristics, test dies are typically discarded or retained for archival purposes but are generally not sold.

[0023] One crucial electrical characteristic for ICs is leakage current. When an IC is in standby mode, leakage current is the primary cause of power consumption. Specifically, when an IC is powered off, the leakage current flowing through individual transistors in the circuit can be small and almost undetectable, ideally zero. Leakage current varies with voltage supply and temperature, making it even more difficult to detect transistor leakage current under low voltage supply and / or low temperature conditions.

[0024] Some aspects of this disclosure involve the understanding that including a test circuit system for measuring the leakage current of transistors on a commercial die has advantages. Specifically, in some examples provided in this disclosure, a single die includes a commercial component circuit system and also includes a test transistor or other device under test (DUT). The die also includes a test circuit system to measure and characterize the leakage current of the transistor and / or other DUT. Therefore, the die can switch between a “normal mode” and a “test mode,” in which the commercial component circuit system is used, and during the “test mode”, the leakage current of the transistor and / or other DUT is measured. The test mode can be used before and after deployment to the field, and the circuitry is configured to minimize the use of silicon die area.

[0025] Figure 1An example system 100 is shown, comprising circuitry 101 that can switch between a "normal mode" and a "test mode." In "normal mode," a commercial component circuitry system is used; during "test mode," leakage current of the DUT is measured. In this example, circuitry 101 may be an IC, a semiconductor die, or a chip containing a silicon die area with various component circuitry systems 136, 138. Component circuitry systems 136, 138 may be configured to provide functionality. In some examples, component circuitry systems 136, 138 may be a microprocessor; baseband processing circuitry; a direct current (DC) to DC converter; transmission circuitry, such as a radio frequency (RF) modulator; receiving circuitry, such as an RF demodulator; and / or radar circuitry, etc. A first pin (pin 1) 102 and a second pin (pin 2) 104 serve as contact points between component circuitry systems 136, 138 and external circuitry systems. Pins 102, 104 may be input pins, output pins, and / or bidirectional input / output (I / O) pins. The pins can be configured to couple to external circuitry, such as printed circuit boards, components for power connections, ground connections, data transmission, control / synchronization for dedicated functions associated with circuit 101, or other circuitry functions.

[0026] In addition to component circuit systems 136, 138 and pins 102, 104, circuit 101 further includes test circuit system 103, DUTs 112a to 112b (commonly or individually referred to as 112), DUT switches 118a to 118b (commonly or individually referred to as 118), mode switches 132a to 132b (commonly or individually referred to as 132), and control circuitry 130. DUTs 112 are arranged from different groups or subgroups of DUTs among a total number of DUTs, each subgroup having a different type of DUT or different characteristics than other groups or subgroups of DUTs on the circuit or chip. Test circuit system 103, DUT switches 118, mode switches 132, and control circuitry 130 are configured to work with test analyzer circuitry 116 and voltage supply 114 to apply various bias conditions to DUTs 112 to determine the current leakage of each different type of DUT. During normal operation, when no tests are being performed on the DUT, it can be coupled to the component circuitry. Test analyzer circuitry 116 and voltage supply 114 may be off-chip (e.g., coupled to circuitry within circuitry 101 via pins 102, 104), but in other instances, test analyzer circuitry 116 and / or voltage supply 114 may be included within circuitry 101 (e.g., on the same substrate and / or within the same package as other components of circuitry 101). Control circuitry 130 may be a processor or logic circuitry, or alternatively, may be a pin controlled by test analyzer circuitry 116 or other external circuitry (not depicted). In yet another instance, control circuitry 130 may be a fuse, register, or other memory element that can be set or blown (e.g., after a current leakage test has been completed).

[0027] Control circuit 130 changes the state of mode switches 132a and 132b based on whether the circuit is in "normal mode" or "test mode" of operation. In normal operation mode, control circuit 130 sets the state of mode switches 132a and 132b to couple component circuit systems 136 and 138 to first pin 102 and second pin 104, respectively. Therefore, in normal operation mode, the circuit uses component circuit systems 136 and 138 to perform its function and provides voltage and / or current to first pin 102 and / or second pin 104, and / or receives voltage and / or current from first pin 102 and / or second pin 104 to perform its function.

[0028] During the test operation mode, control circuit 130 changes the state of mode switches 132a and 132b and couples the first pin 102 (and therefore the test analyzer circuit 116) to the output of test circuit system 103 and the second pin 104 (and therefore the voltage supply 114) to the input of test circuit system 103. While the voltage supply 114 and test analyzer circuit 116 are coupled to test circuit system 103, control circuit 130 also closes one or more of the DUT switches 118 to measure the leakage current of DUT 112. For example, during a first time period, control circuit 130 may close the first DUT switch 118a while simultaneously opening the second DUT switch 118b. Subsequently, during this first time period, test analyzer circuit 116 and test circuit system 103 may apply various bias conditions to measure the current leakage of the first DUT subgroup 112a. During a second time period of the test mode, control circuit 130 may open the first DUT switch 118a while simultaneously closing the second DUT switch 118b. Subsequently, during this second time period, the test analyzer circuit 116 and the test circuit system 103 can apply various bias conditions to measure the current leakage of the second DUT subgroup 112b.

[0029] To achieve efficient testing, the test circuit system 103 may include analog components, such as an amplifier 106 and at least one pair of transistors (108, 110). Thus, the amplifier 106 shown includes a first input 122, a second input 124, and an output 120. The first transistor 108 and the second transistor 110 each include a first current terminal (first terminal) (1), a second current terminal (second terminal) (2), and a control terminal (C). The test circuit system 103 is coupled to DUT groups 112a, 112b via one or more DUT switches 118a, 118b. Each DUT switch 118 includes a first terminal (1) and a second terminal (2) and is controlled via control circuitry 130.

[0030] Advantageously, each DUT 112a or 112b may contain an integer number of identical or nearly identical transistors or other devices, where the integer can be any integer greater than zero, and one or more DUTs 112a or 112b or a subset of DUT subgroups (one or more of them) can be tested simultaneously in test mode. Typically, the integer is 100 or greater, because the current leakage of individual transistors is very small, so providing more transistors along the current paths in parallel within the DUT subgroup can help measure the leakage current of individual transistor types or a particular type of DUT 112a or 112b. In the illustrated example, two different types of DUTs (e.g., DUTs 112a, 112b) are shown, but any number of different types of DUTs may be included. More precisely, the first group of DUTs 112a may contain Ma transistors, each sharing the characteristics of the first group of transistors; and the second group of DUTs 112b may contain Mb transistors, each sharing the characteristics of the second group of transistors. For example, in some instances, the first DUT subgroup 112a may contain Ma = 100 or more transistors, and each of these Ma transistors in DUT 112a may be an n-channel MOSFET (nMOSFET) identical to the other Ma transistors, but with variations due to manufacturing tolerances. Similarly, the second DUT 112b may contain Mb = 100, fewer, or more transistors (where Mb may be equal to or different from Ma), and each of these Mb transistors in DUT 112b may be a p-channel MOSFET (pMOSFET) identical to the other Mb transistors, but with variations due to manufacturing tolerances. In other instances, each of the Ma transistors may be an n-channel MOSFET (nMOSFET) with a first width-to-length ratio (e.g., w / l = 1:1); and each of these Mb transistors may be an n-channel MOSFET (nMOSFET) with a second width-to-length ratio (e.g., w / l = 5:1). In other instances, each transistor in the first DUT subgroup can be a first type of transistor, such as a planar MOSFET, and each transistor in the second DUT 112b can be a second type of transistor, such as a finFET or a bipolar junction transistor (BJT). Thus, in each of the above instances, the first DUT 112a is a first transistor designed to have the same transistor characteristics as each other, and the second DUT 112b is a second transistor also designed to have the same characteristics as each other (although different from the characteristics of the first transistors).

[0031] Amplifier 106's first input 122 is coupled to the first terminals of DUT switches 118a and 118b and the second terminal of first transistor 108. Amplifier 106's second input 124 is coupled to a second mode switch 132b. Amplifier 106's output 120 is coupled to the control terminals of first transistor 108 and second transistor 110, wherein each of the control terminals of first transistor 108 and second transistor 110 is coupled to each other. The first terminal of first transistor 108 is coupled to the first terminal of second transistor 110, and both are coupled to VDD.

[0032] When closed, the DUT switch (e.g., 118a or 118b) couples the first input 122 of amplifier 106 to the second terminal of the selected DUT group (e.g., 112a or 112b, respectively). Within the first DUT subgroup 112a, the control terminals of Ma devices are coupled to ground (GND), such that the transistors in subgroup 112a have a gate-source voltage (VGS) that is normally zero (and / or less than the voltage threshold of the transistors in subgroup 112a), and the transistors in subgroup 112a are "turned off". Within the second DUT subgroup 112b, the control terminals of Mb devices are coupled to the second terminal of switch 118, such that the transistors in DUT group 112b have a source-gate voltage (VSG) that is normally zero (and / or less than the voltage threshold of the transistors in DUT group 112b), and the transistors in DUT group 112b are also "turned off". Therefore, because the transistors in DUTs 112a and 112b are “off”, the transistors are ready for current leakage measurement when the test circuit system 103 applies a drain-to-source (VDS) voltage to the transistors in DUTs 112a and 112b.

[0033] When circuit 101 is in test mode, the leakage current (e.g., Ioff at VDUT) of the selected DUT subgroup is measured via test analyzer circuit 116, which operates via probes or other contacts coupled to pins 102 and 104 of circuit 101. A voltage supply 114 coupled to the second pin 104 provides a forced voltage (V) to the test circuitry system 103 on circuit 101. Force The test analyzer circuit 116, coupled to the first pin 102, detects or senses the sense current (Isense) to measure and determine the leakage current at the selected DUT subgroup. Voltage V Force The response of the selected DUT subgroup is stimulated so that the test analyzer circuit 116 can observe the response in terms of current, voltage, or other parameters, thereby enabling verification of the DUT's functionality, performance, and compliance with specifications. If no additional current is present, the current at the sense current Isense at the first pin 102 is the leakage current multiplied by the current gain N.

[0034] In test operation mode, amplifier 106 receives V at its first input 124. Force Transistors 108 and 110 are driven with a 1:N current gain ratio, thereby providing a DUT voltage VDUT at the second terminal 2 of the selected DUT. VDUT typically tracks VForce, and N is an integer greater than one (e.g., 10, 100, 1,000, or other N integers). The first transistor 108 at the left mirror branch of the test circuit system 103 drives a current Ioff to the selected DUT. This current Ioff induces a corresponding leakage current in the selected DUT (e.g., 112a), and the voltage VDUT stabilizes at the forced voltage VForce. Force It can be further configured with the test circuit system 103 in closed-loop operation, such as Figure 2 Further description follows. The leakage current of the selected DUT group (e.g., 112a or 112b) can then be measured on the first pin 102, for example, as the Isense divided by the calibration gain N of transistors 108 and 110. The current leakage of individual transistors within the selected DUT group (e.g., within DUT 112a) can then be determined by dividing this leakage current by the number of transistors in the subgroup (e.g., by Ma when measuring the leakage current of DUT 112a).

[0035] When DUT 112 is de-energized or idle, test circuitry 103 operates to increase the current Ioff at the second terminal of DUT 112 to a measurable value for measurement by test analyzer circuitry 116. Because the leakage current varies with voltage supply 114, the more voltage supply 114 increases, the more leakage current appears at the drain terminal of DUT 112. To accurately characterize the leakage current of DUT 112, tests in test modes can be performed within a range of voltages and temperatures to target the measurable leakage current as a specific target value and evaluate the electrical behavior of DUT 112.

[0036] After the leakage current in the DUT group 112 is measured and characterized by the test analyzer circuit 116, the control circuit 130 can signal the DUT switch 118 and the mode switch 132 to return to the normal operating mode for field use, such as in a computer or another device for circuit-specific operations.

[0037] Advantageously, circuit 101 may comprise a single substrate having component circuit systems 136, 138 to provide functionality, and having a DUT 112 that allows measurement / characterization of leakage current for a variety of different DUTs. The presence of multiple identical or nearly identical transistors arranged in parallel current paths for the DUT subgroups allows for the measurement of larger leakage currents than methods with only one transistor per DUT type. Furthermore, because test circuit system 103 can have a large current gain, it limits the number of DUTs required to measure very low leakage currents, and thus promotes a small footprint that does not consume excessive area on the die. Therefore, Figure 1 The circuit 101 achieves a good balance, allowing manufacturers to include a DUT on commercial wafers to measure / characterize leakage current and reducing factory “waste” caused by discarded test chips. Furthermore, because each die on the wafer (not just test dies) can contain a DUT, this method also allows for a more uniform characterization of leakage current across the entire wafer compared to some other methods.

[0038] Figure 2 Another example system 200 is shown, which has a test circuit system as an analog test device on circuit 101 for measuring the leakage current of a DUT in a test mode. Circuit 101 includes DUT 202 and DUT 204. DUT 204 includes at least one device or transistor 206 to be tested, a first switch 208 and a second switch 210; and DUT 202 includes at least one transistor 216, a third switch 212 and a fourth switch 214. DUT 204 includes one or more transistors 206 or semiconductor devices that have different characteristics or parameters than one or more devices or one or more transistors 216 of DUT 202. Each DUT 202 or 204 may include a specific type of transistor device (e.g., an n-channel MOS (NMOS) transistor, a p-channel metal-oxide-semiconductor (PMOS) transistor, a transistor of the same size, or having specific transistor characteristics or types). For example, DUT 202 may include Figure 1 The M transistors 216 (also referred to as one or more transistors 112 or transistor devices) may be of a different type or characteristic than one or more transistors 206 on the DUT 204 on circuit 101. For example, one or more transistors 206 on the DUT 204 may be of a first size, type or characteristic different from one or more transistors 216 on the DUT 202.

[0039] DUTs 202 and 204 contain M devices or transistors 216 and 206 of different types, each transistor containing a first terminal (1), a second terminal (2), and a control terminal (C). The control terminals of transistors 216 and 206 of DUTs 202 and 204 are coupled to the first terminals of these same transistors 216 and 206, which are also coupled together between DUTs 202 and 204. A first switch 208 of DUT 204 contains a first terminal (1) and a second terminal (2), wherein the first terminal of the first switch 208 is coupled to the first input 122 of amplifier 106. The second terminal of the first switch 208 is coupled to the second terminal of transistor 206 of DUT 204. A second switch 210 of DUT 204 also contains a first terminal and a second terminal, wherein the first terminal of the second switch is coupled to the second terminal of transistor 108, and the second terminal of the second switch 210 is coupled to the second terminals of one or more transistors 206 of DUT 204.

[0040] DUT 202 includes Figure 1 The amplifier 102 comprises one or more transistors 216 (also referred to as one or more transistors 112), and at least one or more third switches 212 and fourth switches 214, each including a first terminal and a second terminal. The first terminal of the third switch 212 is coupled to the first input 122 of the amplifier 106 and the first terminal of the first switch 208. The second terminal of the third switch 212 is coupled to the second terminal of one or more transistors 216 in the DUT 202. The first terminal of the fourth switch 214 is coupled to the second terminal of the first transistor 108 and the first terminal of the second switch 210. The second terminal of the fourth switch 214 is coupled to the second terminal of one or more transistors 216 in the DUT 202.

[0041] The test circuit system 103 is configured with the DUT in a closed-loop configuration, operable to independently test M devices of each DUT 202, 204 in test mode. Control circuitry 130 signals one or more groups of devices of the DUT to be turned off via switches 208 to 214, while simultaneously activating one group of devices of the DUT and coupling it to the test circuit system 103 in a closed loop. For example, DUT 202 can be signaled to be turned on or activated by switches 212, 214, while DUT 204 can be signaled to be turned off or deactivated by switches 208 and 210. In this example, the leakage current of DUT 202 can be effectively measured using the test circuit system 103 in the test mode configuration. A first transistor 108 and a second transistor 110 are coupled to an amplifier 106, which operates to provide a target voltage on the DUT under test for measuring leakage current in the closed-loop configuration. For example, the target voltage Vsense may be approximately 1 volt or 0.75 volts at the drain terminal or second terminal of the transistor in DUT 202. For example, the leakage current on one or more devices or one or more transistors 216 may be mirrored and measured at first pin 102 as a measurable value of Isense resulting from the closed-loop configuration formed by transistors 108 and 110, amplifier 106, and DUT 202, while DUT 206 is decoupled or isolated and not tested.

[0042] The current gain N, acting as a gain factor, enables DUT 202 to be tested with fewer M DUTs or M devices in a reduced total area, while allowing the DC sensitivity of the drain of DUT 202 to reach the target voltage more quickly by operating in this closed-loop configuration. N can be any integer greater than one (e.g., less than, equal to, or greater than 256), and M can be different integers (one or greater than one) for DUT 202 and DUT 206 (e.g., DUT 202 can have 10 transistor devices, where M = 10, while at DUT 206, M equals 100).

[0043] Because Ioff, as the leakage current, no longer drives any external capacitance in the closed loop, the drain of DUT 202 accelerates and stabilizes to the target voltage for measuring the leakage current much faster than without amplifier 106. In other words, the removal of external capacitances that could be introduced from test analyzer circuit 116, parasitic capacitances on the chip or silicon die of circuit 101, chip package, printed circuit board (PCB), etc., allows the target voltage to stabilize more quickly at the drain terminal of DUT 202, and enables test analyzer circuit 116 to measure the leakage current at the target DUT more quickly. As shown, voltage scanning can be accelerated in a closed-loop configuration, thereby reducing the transient time before the drain or second terminal of the activated DUT stabilizes to the target. In this way, the leakage current of a specific set of devices with a first characteristic (e.g., transistor 216 of DUT 202) can be determined before isolating another set of devices (e.g., transistor 206 of DUT 204) of another DUT with a different characteristic into the closed-loop configuration. The leakage current can then be measured on the first pin 102, for example, as the Isense divided by the calibration gain N of transistors 108 and 110.

[0044] Figure 3 Another example system 300 is shown, which has a test circuit system serving as an analog test device on circuit 101 for measuring leakage current at each point in the DUT in a test mode. Circuit 101 includes DUT 202 and DUT 204. DUT 204 includes a first group 304 (one or more of M devices or transistors), a first switch 208 and a second switch 210, and DUT 202 includes a second group 302 of M devices or transistors, a third switch 212 and a fourth switch 214. DUT 204 includes one or more transistors 206 or semiconductor devices that have different characteristics or parameters than the transistors 216 of DUT 202, and vice versa. For example, the devices of a DUT may be NMOS transistors, PMOS transistors, transistors of the same size as other DUTs, MOSFET devices, bipolar junction transistor (BJT) devices, extended drain NMOS / PMOS devices, or other specific transistor characteristics or types that are different from those of other DUTs. For example, DUT 204 may include transistors 206 having different threshold voltages than those of transistors 216 in DUT 202, and measuring the leakage current of different DUTs separately can determine local variations between devices to measure the matching between them. Alternatively or additionally, a sufficient number of M devices can be used at each of the groups 302 and 304 to measure the average voltage threshold, so that local mismatches are averaged out or become negligible.

[0045] Figure 4Another example system 400 is shown, which has a test circuit system serving as an analog test device on circuit 401 for measuring leakage current at each point in the DUT in test mode. The test circuit system 403 of circuit 401 further includes a Miller capacitor 404 and a resistor 402 coupled together. The Miller capacitor 404 is coupled at a first terminal to the control terminal of the first transistor 108 and the output 120 of the amplifier, and at a second terminal to the resistor. The resistor is coupled to the drain of the first transistor or the second terminal. The voltage gain at the control terminals of the first transistor 108 and the second transistor 110 results in a higher effective input capacitance at the Miller capacitor 404, thus giving rise to the Miller capacitance, as Miller capacitor 404.

[0046] Miller capacitor 404 operates to make the output of amplifier 106 a more dominant pole in the transfer function of system 300 caused by the dynamic behavior of test circuit system 403 in a closed-loop configuration. The poles associated with the output of amplifier 106 activated in the closed-loop configuration and the drain or second terminal of the DUT are further separated in frequency than in the absence of Miller capacitor 404, resulting in a more stable system in test operation mode.

[0047] Figure 5 Another example system 500 is shown, which has a test circuit system as an analog test device on circuit 501 for measuring leakage current at each point in the DUT in test mode. System 500 includes transistor 502, transistor 504 and current source 506.

[0048] Transistors 502 and 504 include a first terminal, a second terminal, and a control terminal. The second terminal (e.g., a drain terminal) of transistor 502 is coupled to the second terminal of the first transistor 108. The first terminal of transistor 502 is coupled to the first terminal of the device of DUTs 202 and 204. The control terminal of transistor 502 is coupled to the second terminal of transistor 502. The second terminal of transistor 504 is coupled to the control terminal of transistor 504 and the current source 506. The first terminal of transistor 504 is coupled to the first terminal of transistor 502. The control terminal of transistor 504 is coupled to the control terminal of transistor 502. Transistors 502 and 504 are shown in this example as NMOS transistors, where the first terminal can be a source terminal, the second terminal can be a drain terminal, and the control terminal can be, for example, a gate terminal, but other devices can be used instead of, for example, BJTs or PMOS transistors.

[0049] The current source 506 coupled to transistors 504 and 502 ensures a certain operating point (referred to as V0 of transistors 108 and 110 in the current mirror configuration) by ensuring the minimum gate-source voltage minus the threshold voltage. GSTThe voltage operating point can be used to further increase or improve the matching between transistors 108 and 110, even at low leakage current levels. Without an operating point threshold, the V08 of transistors 108 and 110... GST The voltage can be very small, resulting in low leakage current, which leads to poor current matching between these transistors, and is a drawback when the leakage current becomes even smaller, especially at lower temperatures.

[0050] Current source 506 provides bias current to the closed-loop configuration in test mode by supplying a bias current (Ibias) to the drain terminal or second terminal of transistor 108, thereby operating to further make the output 120 of amplifier 106 a more dominant pole in the dynamic behavior transfer function of the system. The bias current Ibias (e.g., one microamp or other value) ensures that the second terminal of the DUT activated in the closed loop is at a higher frequency than the output of amplifier 106, regardless of the leakage current. The bias current can be greater than the leakage current to be measured, so system 500 can first calibrate the Isense at pin 102 with all DUTs disabled / deactivated to first measure the Isense caused by the bias current Ibias as a reference before measuring or characterizing, for example, the leakage current of DUT 202 or 204.

[0051] Figure 6 Another example system 600 is shown, which has a test circuit system as an analog test device on circuit 601 for measuring leakage current at each point in the DUT in test mode. System 600 includes transistor 602 and branch 604 as a current-based absorption path.

[0052] Transistor 602 includes a first terminal, a second terminal, and a control terminal. The second terminal of transistor 602 is coupled to the second terminal of second transistor 110 via branch 604. The control terminal of transistor 602 is coupled to the control terminal of transistor 504, and the first terminal of transistor 602 is coupled to the first terminal of transistor 504.

[0053] Branch 604 absorbs a bias current scaled by the current gain N from the first transistor 108 and the second transistor 110 into transistor 602, thereby removing the bias current from the sensing output that will be measured by the test analyzer circuit 116 at the first pin 102. Therefore, the test analyzer circuit 116 receives N times the leakage current at the DUT activated in a closed-loop configuration. Thus, transistor 602, coupled to the current source 506 via transistor 504, operates by absorbing a replica of the current bias Ibias generated by transistors 108 and 110, thereby multiplying the leakage current by the current gain at the first pin 102. Branch 604 coupled to transistor 602 (which in turn is coupled to the current source 506 via transistor 504) improves the accuracy of leakage current testing, becoming less dependent on the accuracy or resolution level of the test analyzer circuit 116.

[0054] Figure 7 Another example system 700 is shown, which has a test circuit system as an analog test device on circuit 701 for measuring leakage current at each point in the DUT in a test mode. System 700 includes a first resistor 702 having a first impedance and a second resistor 704 having a second impedance, the second impedance being different from the first impedance.

[0055] First resistor 702 and second resistor 704 each include a first terminal and a second terminal. The first terminal of first resistor 702 is coupled to the second terminal of first transistor 108. The second terminal of first resistor 702 is coupled to the first terminal and control terminal of transistors DUT 202 and 204. The first terminal of second resistor 704 is coupled to the drain of second transistor 110 via branch 604, which serves as a resistor-based absorption path. The second terminal of second resistor 704 is coupled to the second terminal of first resistor 702.

[0056] The impedance of resistor 702 can be scaled proportionally based on the current gain N of transistors 108 and 110. Resistors 702 and 704 are configured to generate a voltage supply V from voltage supply 114. Force The current formed by dividing the current gain by the impedance is expressed as: V Force / (N*R). V Force The voltage (V) at the drain or second terminal of DUT 202, 204 DUT Therefore, V DUT / (N*R) determines Ibias. Because the impedance of resistors 702 and 704 can be lower than that of the current source (e.g., Figure 5The output impedance of the current source 506 (or 6) allows for higher frequency poles at the drain or second terminal of the DUT 202 or 204, resulting in increased phase margin. In a closed-loop configuration, the poles of the system transfer function associated with the output of amplifier 106 and the drain or second terminal of the activated DUT can be further separated, providing greater stability and more accurate testing in test mode. Using resistors 702 and 704, leakage current stabilizes more quickly within the closed-loop configuration in test operation mode.

[0057] In this example, in test mode, amplifier 106 provides a forced voltage V to the second terminal of DUT 202 or 204. Force , as the target voltage V DS For example, the forced voltage V Force The bias current can be 0.75 to 1 volt. Subsequently, the bias current from the voltage on the DUT is provided through resistor 702 (N*R), such as 0.75 to 1 volt at the resistance value of resistor 702. With resistor 704 (with resistance R) and resistor 702 having a ratio or scale of N to each other, the bias current can be replicated in a current of N times, such that the bias current injected into the current mirror formed by transistors 108 and 110 can be canceled out for more accurate leakage measurement at the first pin 102.

[0058] Figure 8 Another example system 800 is shown, which has a test circuit system as an analog test device on circuit 101 for measuring leakage current at each point in the DUT in a test mode. System 800 includes a programmable array 802 of first transistors 108 coupled to test circuit system 803.

[0059] The programmable array 802 includes a first group of switches 804, a first group of transistors 806, a second group of switches 808, and a second group of transistors 810. Each of the first group of switches 804 and 808 includes a first terminal and a second terminal. Each of the first group of transistors 806 and 810 includes a first terminal, a second terminal, and a control terminal. The first terminals of the first group of switches 804 and 808 are coupled to the second terminals of the first group of transistors 806 and 810, respectively. The second terminals of the first group of switches 804 and 808 are coupled to the second terminal of a first transistor 808. The first terminals of the first group of transistors 806 and 810 are coupled to the first terminal of the first transistor 808.

[0060] The programmable array 802 can be configured based on DUTs 202 and 204, which are activated into a closed-loop configuration via switches, such that the configuration of transistors 108 and 110 is dynamic during operation. For example, a first set of transistors 806 and a second set of transistors 810 can be coupled in parallel to the first transistor 108. Depending on the value of N, which is the desired current gain between transistors 108 and 110, multiple transistors in the programmable array 802 can be activated or deactivated via switches 804 and 808, respectively. If a larger gain is desired from the left branch with transistor 108 to the right branch with transistor 110, fewer transistors can be connected via switches in the programmable array 802. However, to reduce N, the programmable array 802 is connected in parallel to transistor 108 on the left side. In this way, the current gain can be appropriately selected for a specific current range (e.g., 1 microamp or milliamp) entering the test analyzer circuit 116.

[0061] Although programmable array 802 is connected to transistor 108 on the left branch, alternatively or otherwise, another similar programmable array can be connected across transistor 110 in a similar configuration. In this configuration, for example, by activating or paralleling additional transistors while disconnecting the transistors in programmable array 802, the current gain N on the right side of transistor 110 can be increased. Specifically, on the DUT side at transistor 108, the stability of the closed-loop configuration can vary between different transistor types of different DUTs (depending on whether DUTs 202 and 204 are activated for testing), and between different temperatures. Leakage current varies exponentially with temperature, so adding programmability on the left side to match transistors 108 and 110 can enable the current density of the circuit to be maintained within a tighter range, resulting in a tighter gate-to-source voltage V. GS And achieve better matching.

[0062] Although the programmable array 802 of the system 800 coupled to transistor 108 and Figure 7 Resistors 702 and 704 of system 700 are shown together, but programmable array 802 may also be coupled to transistor 108 in any of the other configurations described in this disclosure. For example, resistors 702 and 704 may alternatively be replaced by a configuration of transistors 502, 504, or 602 and current source 506.

[0063] Figure 9An example system 900 for calibrating amplifier 106 is shown. In this example, system 900 includes a Schmitt trigger 902 and switches 904 through 912. Amplifier 106 has a calibration operating mode that enables calibration using an input offset voltage as a differential calibration voltage (Vos_cal) 906. The output 120 of amplifier 106 is disconnected from transistors 108 and 110 via switch 910 and coupled to comparator 902. For example, comparator 902 may be a Schmitt trigger that receives an analog signal from amplifier 106 and converts the analog signal into a square wave or digital output to calibrate amplifier 106 via calibration voltage 906. Switch 912 couples comparator 902 to a first pin 102, while switch 904 disconnects DUTs 202 and 204 from the calibration of amplifier 106. Switch 908 couples amplifier inputs 122 and 124 to a second pin 104 for receiving voltage supply. Subsequently, amplifier 106 is placed in an open loop by disconnecting the closed-loop operation from the DUT and test circuitry system 103 or 403. For example, the calibration signal sent to amplifier 106 can be scanned until the output of comparator 902 toggles. For example, the calibration offset can be less than 2 millivolts. By modifying the offset of amplifier 106, amplifier 106 can be calibrated to reduce the forced voltage V on pin 104 when in test mode. Force Errors that may result from forcing the DUT to 202 or 204.

[0064] Figure 10 An example system 1000 is shown for calibrating the coupling of a first transistor 108 and a second transistor 110 to each other, either at their gates or control terminals. In this document, a current mirror configuration may be coupled to a switch 1002, although not shown for simplicity. Figures 1 to 9 The components or test circuitry shown herein may be incorporated as in other descriptions containing this disclosure, and may be disabled for calibrating transistors 108, 110, 806, 810, etc., via switching components (not shown). Transistors 108 and 110 may be sized to have, for example, a 5% mismatch and include switches for measuring any mismatch and calibrating accordingly, further reducing any errors in current measurement at the second pin 104 during the process.

[0065] Figure 11An example process flow 1100 for testing DUT 202 or 204 in test mode is shown. At 1102, by activating a first set of switches 208, 210, 212, or 214 coupled to the DUT (e.g., 202, 204) and deactivating a second set of mode switches 132 coupled to component circuit systems 136, 138, circuitry (e.g., any of circuits 101 to 801) activates on-chip test circuitry systems 103, 403 in test mode via control circuitry 130. The device under test includes a set of transistors coupled to power supply pins via the first set of switches, and the test circuitry system includes an amplifier and a pair of transistors. At 1104, circuitry (e.g., any of circuits 101 to 801) supplies power to the test circuitry systems 103, 403 coupled to the DUT 202, 204 via a power supply pin or a second pin 104 coupled to amplifier 106. At 1106, the circuit supplies current to a set of transistors in a closed-loop configuration to the device under test (DUT) via a pair of transistors in the on-chip test circuitry system when component circuitry systems 136 and 138 are deactivated. At 1108, the circuit with test analyzer circuitry 116 determines the leakage current of DUT 202 and 204 via sensing pins or first pin 102 coupled to the pair of transistors in the test circuitry system, in response to a voltage supply, for example, at second pin 104.

[0066] In this specification, the term "coupled" may encompass a connection, communication, or signal path that achieves a functional relationship consistent with this specification. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first instance, device A is coupled to device B via a direct connection; or (b) in a second instance, if intermediate component C does not alter the functional relationship between device A and device B, then device A is coupled to device B via intermediate component C such that control signals generated by device B via device A are controlled by device A.

[0067] A device “configured to” perform a task or function may be configured by the manufacturer at manufacturing time (e.g., programmed and / or hardwired) to perform a function and / or may be configured (or reconfigured) by the user after manufacturing to perform a function and / or other additional or alternative functions. This configuration may be achieved through firmware and / or software programming of the device, through the construction and / or layout of hardware components and the interconnection of the device, or a combination thereof. In other cases, “configurable to” perform a task or function as described herein means that the hardware present in the device is suitable for being programmed after manufacturing to perform a function via firmware and / or software programming of the device, and that firmware and / or software were not included at manufacturing time.

[0068] As used herein, the terms “terminal,” “node,” “interconnect,” “pin,” and “lead” are used interchangeably. Unless specifically stated otherwise, these terms are generally used to refer to interconnections or ends between device elements, circuit elements, integrated circuits, devices, or other electronic or semiconductor components.

[0069] The circuits or devices described herein as containing certain components may be substantially adapted to be coupled to those components to form the described circuit system or device. For example, a structure described as containing one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage sources and / or current sources) may substantially contain only semiconductor elements within a single physical device (e.g., a semiconductor die and / or integrated circuit (IC) package), and may be adapted to be coupled to at least some of the said passive elements and / or sources to form the described structure during or after manufacturing, for example, by an end user and / or a third party.

[0070] While the use of specific transistors is described herein, other transistors (or equivalent devices) may be used alternatively with little or no change to the rest of the circuit system. For example, field-effect transistors, bipolar junction transistors (BJTs, such as NPN or PNP), insulated-gate bipolar transistors (IGBTs), and / or junction field-effect transistors (JFETs) may be used in place of or in combination with the devices described herein. The transistor may be a depletion-mode device, a drain-extended device, an enhancement-mode device, a natural transistor, or another type of device structure transistor. Furthermore, the device may be implemented on / above a silicon (Si) substrate, a silicon carbide (SiC) substrate, a gallium nitride (GaN) substrate, or a gallium arsenide (GaAs) substrate.

[0071] While some elements of the described examples are contained within the integrated circuit and others are external to the integrated circuit, in other examples, additional or fewer features may be incorporated into the integrated circuit. Furthermore, some or all features shown as external to the integrated circuit may be contained within the integrated circuit, and / or some features shown as internal to the integrated circuit may be incorporated externally. As used herein, the term "integrated circuit" means one or more circuits that are: (i) incorporated in / above a semiconductor substrate; (ii) incorporated in a single semiconductor package; (iii) incorporated in the same module; and / or (iv) incorporated in / on the same printed circuit board.

[0072] The use of the phrase "grounding" in the foregoing description includes chassis grounding, ground wire grounding, floating grounding, virtual grounding, digital grounding, general grounding, and / or any other form of grounding connection suitable for or applicable to the teachings of this description. Unless otherwise stated, the words "about," "approximately," or "substantially" preceding a value mean + / - 10% of the parameter. Within the scope of the claims, modifications may be made to the described examples, and other embodiments are possible.

Claims

1. A circuit comprising: An amplifier, which includes an output and an input; A first transistor includes a first current terminal, a second current terminal, and a control terminal, wherein the control terminal of the first transistor is coupled to the output of the amplifier; The second transistor includes a current terminal and a control terminal, the current terminal of the second transistor being coupled to the first current terminal of the first transistor, and the control terminal of the second transistor being coupled to the control terminal of the first transistor and the output of the amplifier; as well as A third transistor includes a first current terminal, a second current terminal, and a control terminal. The second current terminal of the third transistor is coupled to the input of the amplifier and the second current terminal of the first transistor, and the control terminal of the third transistor is coupled to the first current terminal of the third transistor.

2. The circuit according to claim 1, further comprising: A fourth transistor includes a first current terminal, a second current terminal, and a control terminal, wherein the control terminal of the fourth transistor is coupled to the control terminal of the third transistor and the first current terminal of the third transistor. A first switch includes a first terminal and a second terminal, the first terminal of the first switch being coupled to the input of the amplifier, and the second terminal of the first switch being coupled to the second current terminal of the fourth transistor; as well as The second switch includes a first terminal and a second terminal, the first terminal of the second switch being coupled to the second current terminal of the first transistor, and the second terminal of the second switch being coupled to the second current terminal of the fourth transistor.

3. The circuit according to claim 2, further comprising: A third switch includes a first terminal and a second terminal, wherein the first terminal of the third switch is coupled to the input of the amplifier and the first terminal of the first switch, and the second terminal of the third switch is coupled to the second current terminal of the third transistor. as well as A fourth switch includes a first terminal and a second terminal, the first terminal of the fourth switch being coupled to the second current terminal of the first transistor and the first terminal of the second switch, and the second terminal of the fourth switch being coupled to the second current terminal of the third transistor.

4. The circuit according to claim 2, further comprising: A set of third transistors coupled to the third transistor, the third transistor and the set of third transistors including a first characteristic; as well as A set of fourth transistors coupled to the fourth transistor, the fourth transistor and the set of fourth transistors including a second characteristic, wherein the first characteristic is different from the second characteristic.

5. The circuit according to claim 1, further comprising: A resistor comprising a first terminal and a second terminal, wherein the first terminal of the resistor is coupled to the second current terminal of the first transistor; as well as A capacitor comprising a first terminal and a second terminal, the first terminal of the capacitor being coupled to the control terminal of the first transistor, and the second terminal of the capacitor being coupled to the second terminal of the resistor.

6. The circuit according to claim 1, further comprising: A fifth transistor includes a first current terminal, a second current terminal, and a control terminal. The second current terminal of the fifth transistor is coupled to the second current terminal of the first transistor, the first current terminal of the fifth transistor is coupled to the first terminal of the third transistor, and the control terminal of the fifth transistor is coupled to the second current terminal of the fifth transistor. A sixth transistor includes a first current terminal, a second current terminal, and a control terminal, wherein the second current terminal of the sixth transistor is coupled to the control terminal of the sixth transistor, the first current terminal of the sixth transistor is coupled to the first current terminal of the fifth transistor, and the control terminal of the sixth transistor is coupled to the control terminal of the fifth transistor. as well as A current source coupled to the second current terminal of the sixth transistor.

7. The circuit of claim 6, wherein the current terminal of the second transistor is a first current terminal, the second transistor further includes a second current terminal, and the circuit further includes: A seventh transistor includes a first current terminal, a second current terminal, and a control terminal, wherein the second current terminal of the seventh transistor is coupled to the second current terminal of the second transistor, the control terminal of the seventh transistor is coupled to the control terminal of the sixth transistor, and the first current terminal of the seventh transistor is coupled to the first current terminal of the sixth transistor.

8. The circuit of claim 1, wherein the current terminal of the second transistor is a first current terminal, the second transistor further includes a second current terminal, wherein the input of the amplifier is a first input and the amplifier further includes a second input, the circuit further comprising: The first pin is coupled to the second current terminal of the second transistor; The second pin is coupled to the second input of the amplifier; A first resistor includes a first impedance, the first resistor includes a first terminal and a second terminal, the first terminal of the first resistor is coupled to a second current terminal of the first transistor, and the second terminal of the first resistor is coupled to the first current terminal of the third transistor and the control terminal of the third transistor. as well as A second resistor includes a second impedance. The second resistor includes a first terminal and a second terminal. The first terminal of the second resistor is coupled to the second current terminal and the first pin of the second transistor. The second terminal of the second resistor is coupled to the second terminal of the first resistor. The first impedance of the first resistor is different from the second impedance of the second resistor.

9. The circuit according to claim 1, further comprising: Programmable array, comprising: A first set of switches includes a first terminal and a second terminal, wherein the second terminal of the first set of switches is coupled to the second current terminal of the first transistor; The first group of transistors each includes a first current terminal and a second current terminal. Specifically, the first current terminal of the first group of transistors is coupled to the first current terminal of the first transistor, and the second current terminal of the first group of transistors is coupled to the first terminal of the first group of switches. The second set of switches includes a first terminal and a second terminal, wherein the second terminal of the second set of switches is coupled to the second current terminal of the first transistor; as well as The second group of transistors includes a first current terminal and a second current terminal. The first current terminal of the second group of transistors is coupled to the first current terminal of the first transistor, and the second current terminal of the second group of transistors is coupled to the first terminal of the second group of switches.

10. The circuit according to claim 1, wherein the first transistor is a first P-channel metal-oxide-semiconductor (PMOS) transistor, the second transistor is a second PMOS transistor, and the third transistor is a first N-channel metal-oxide-semiconductor (NMOS) transistor.

11. A circuit comprising: An amplifier, which includes an output and an input; A first transistor includes a first current terminal, a second current terminal, and a control terminal, wherein the control terminal of the first transistor is coupled to the output of the amplifier; The second transistor includes a current terminal and a control terminal, the current terminal of the second transistor being coupled to the first current terminal of the first transistor, and the control terminal of the second transistor being coupled to the control terminal of the first transistor and the output of the amplifier; A group of transistors, each comprising a first current terminal, a second current terminal, and a control terminal, wherein the first current terminal of the group of transistors is coupled to the control terminal of the group of transistors; A first switch includes a first terminal and a second terminal, the first terminal of the first switch being coupled to the input of the amplifier, and the second terminal of the first switch being coupled to the second current terminal of the set of transistors; as well as The second switch includes a first terminal and a second terminal, the first terminal of the second switch being coupled to the second current terminal of the first transistor, and the second terminal of the second switch being coupled to the second current terminal of the group of transistors.

12. The circuit of claim 11, wherein the group of transistors is a first group of transistors, the circuit comprising: The second group of transistors each includes a first current terminal and a second current terminal, wherein the first current terminal of the second group of transistors is coupled to the first current terminal of the first group of transistors. A third switch includes a first terminal and a second terminal, the first terminal of the third switch being coupled to the input of the amplifier, and the second terminal of the third switch being coupled to the second current terminal of the second group of transistors; as well as A fourth switch includes a first terminal and a second terminal, wherein the first terminal of the fourth switch is coupled to the second current terminal of the first transistor, and the second terminal of the fourth switch is coupled to the second current terminal of the second group of transistors, wherein the first group of transistors includes first transistor characteristics and the second group of transistors includes second transistor characteristics different from the characteristics of the first transistor.

13. The circuit of claim 12, comprising: A control circuit coupled to at least one of the following: the first switch, the second switch, the third switch, or the fourth switch, wherein the control circuit couples the first group of transistors to the amplifier, the first transistor, and the second transistor when switching from a normal operating mode to a test operating mode.

14. The circuit of claim 11, wherein the current terminal of the second transistor is a first current terminal, the second transistor further includes a second current terminal, and the circuit further includes: A first resistor includes a first impedance, the first resistor includes a first terminal and a second terminal, the first terminal of the first resistor is coupled to a second current terminal of the first transistor, and the second terminal of the first resistor is coupled to the first current terminal of the group of transistors. as well as A second resistor includes a second impedance. The second resistor includes a first terminal and a second terminal. The first terminal of the second resistor is coupled to the second current terminal of the second transistor, and the second terminal of the second resistor is coupled to the second terminal of the first resistor. The first impedance of the first resistor is proportional to the second impedance of the second resistor based on the gain factors of the first transistor and the second transistor.

15. The circuit of claim 11, wherein the current terminal of the second transistor is a first current terminal, the second transistor further includes a second current terminal, and the circuit further includes: Current source; A fifth transistor includes a first current terminal, a second current terminal, and a control terminal. The second current terminal of the fifth transistor is coupled to the second current terminal of the first transistor, the first current terminal of the fifth transistor is coupled to the first current terminal of the group of transistors, and the control terminal of the fifth transistor is coupled to the second current terminal of the fifth transistor. A sixth transistor includes a first current terminal, a second current terminal, and a control terminal. The second current terminal of the sixth transistor is coupled to the current source and the control terminal of the sixth transistor. The first current terminal of the sixth transistor is coupled to the first current terminal of the fifth transistor. The control terminal of the sixth transistor is coupled to the control terminal of the fifth transistor. as well as A seventh transistor includes a first current terminal, a second current terminal, and a control terminal. The second current terminal of the seventh transistor is coupled to the second current terminal of the second transistor. The control terminal of the seventh transistor is coupled to the control terminal of the fifth transistor and the control terminal of the sixth transistor. The first current terminal of the seventh transistor is coupled to the first current terminal of the fifth transistor and the first current terminal of the sixth transistor.

16. The circuit of claim 11, further comprising: Programmable array, comprising: A plurality of transistors, comprising a first transistor subgroup and a second transistor subgroup, the first transistor subgroup comprising a first current terminal and a second current terminal and the second transistor subgroup comprising a first current terminal and a second current terminal, wherein the first current terminal of the first transistor subgroup and the first current terminal of the second transistor subgroup are coupled to the first current terminal of the first transistor. as well as A plurality of switches, each comprising a first terminal and a second terminal, wherein the first terminal of the plurality of switches is coupled to a second current terminal of a first transistor subgroup and a second current terminal of a second transistor subgroup, and the second terminal of the plurality of switches is coupled to a second current terminal of the first transistor and a first current terminal of the group of transistors.

17. A circuit comprising: An amplifier, which includes an output and an input; The first transistor includes a first current terminal, a second current terminal, and a control terminal; A second transistor includes a current terminal and a control terminal, wherein the current terminal of the second transistor is coupled to the first current terminal of the first transistor, and the control terminal of the second transistor is coupled to the control terminal of the first transistor. A set of transistors, each comprising a first current terminal, a second current terminal, and a control terminal, wherein the first current terminal of the set of transistors is coupled to the control terminal of the set of transistors; A first switch includes a first terminal and a second terminal, the first terminal of the first switch being coupled to the input of the amplifier, and the second terminal of the first switch being coupled to the second current terminal of the set of transistors; At least one component circuit system is coupled to the amplifier or the second transistor via a second switch; as well as A control circuit coupled to the first switch and the second switch, wherein the control circuit, in a test operation mode, couples the set of transistors to the amplifier and decouples the at least one component circuit system from the amplifier or the second transistor.

18. The circuit of claim 17, wherein the current terminal of the second transistor is a first current terminal, the second transistor includes a second current terminal, and the circuit further includes: A Schmitt trigger includes a first terminal and a second terminal, the first terminal of the Schmitt trigger being coupled to the output of the amplifier, and the second terminal of the Schmitt trigger being coupled to the second transistor.

19. The circuit of claim 17, comprising: A first resistor includes a first terminal and a second terminal, the first terminal of the first resistor being coupled to the first terminal of the first switch, and the second terminal of the first resistor being coupled to the first current terminal of the group of transistors; as well as The second resistor includes a first terminal and a second terminal, wherein the first terminal of the second resistor is coupled to the second current terminal of the second transistor, and the second terminal of the second resistor is coupled to the second terminal of the first resistor.

20. The circuit of claim 17, further comprising: A resistor comprising a first terminal and a second terminal, wherein the first terminal of the resistor is coupled to the second current terminal of the first transistor; as well as A Miller capacitor includes a first terminal and a second terminal, wherein the first terminal of the Miller capacitor is coupled to the control terminal of the first transistor, and the second terminal of the Miller capacitor is coupled to the second terminal of the resistor.

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