Display panel and display device

Abstract

Embodiments of the present application provide a display panel and a display device. The display panel comprises an array substrate, the array substrate comprises a substrate, a plurality of pixel unit groups, a common signal line, a thin film transistor, a pixel electrode and a common electrode layer arranged on one side of the substrate; along a first direction, each pixel unit group comprises adjacent first and second pixel units; along a second direction, the thin film transistor comprises first and second transistors located on opposite sides of the first pixel unit; the common signal line is located between the first and second pixel units, the common signal line is connected with a switching layer, the switching layer is located at a corner of the second pixel unit close to the first transistor; at least part of the switching layer and the common electrode layer have a via, the switching layer and the common electrode layer are connected through the via; the orthographic projection of the switching layer on the substrate partially overlaps with the orthographic projection of the edge of the via on the substrate.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a display panel and display device. Background Technology

[0002] In a liquid crystal display (LCD) device, the liquid crystal display panel includes an array of pixel units. Each pixel unit may contain a thin film transistor (TFT) and a pixel electrode, and is connected to the TFT via data lines and gate lines to drive the pixel electrode in each pixel unit.

[0003] To reduce costs and increase production capacity, amorphous silicon (A-Si) products use a 0+4mask process with a dual-gate pixel design, which doubles the number of gate lines and halves the number of data lines, and correspondingly halves the number of driver units (ICs), thereby reducing costs and increasing production capacity.

[0004] However, the display panel also includes a common signal line and a common electrode layer. The common signal line needs to be connected to the common electrode layer. While ensuring the voltage stability of the common electrode layer, it is also necessary to avoid affecting the display effect of the display panel as much as possible. This problem urgently needs to be solved. Summary of the Invention

[0005] The purpose of this application is to provide a display panel and display device to solve the problems of uneven in-plane voltage of the common electrode layer and the impact of the connection between the common signal line and the common electrode layer on the display effect of the display panel. The specific technical solution is as follows:

[0006] A first aspect of this application provides a display panel, comprising: an array substrate, the array substrate including a substrate and a plurality of pixel unit groups, a common signal line, a thin film transistor, a pixel electrode and a common electrode layer disposed on one side of the substrate;

[0007] Along the first direction, each group of pixel units includes an adjacent first pixel unit and a second pixel unit;

[0008] Along the second direction, the thin-film transistor includes a first transistor and a second transistor located on opposite sides of the first pixel unit, and the pixel electrode includes a first pixel electrode and a second pixel electrode located in the first pixel unit and the second pixel unit, respectively. The first pixel electrode is connected to the first transistor, and an extension of the second pixel electrode toward the second transistor extends to the first pixel unit and is connected to the second transistor.

[0009] The common signal line is located between the first pixel unit and the second pixel unit and extends along the second direction. The common signal line is connected to a transition layer, which is located at the corner of the second pixel unit near the first transistor. At least a portion of the transition layer and the common electrode layer have vias, and the transition layer and the common electrode layer are connected through the vias. The orthographic projection of the transition layer on the substrate overlaps with the orthographic projection of the edge of the via on the substrate.

[0010] In some embodiments, the first pixel unit and the second pixel unit are spaced apart along the first direction;

[0011] Along the second direction, the first pixel unit and the second pixel unit are spaced apart, and two gate lines are included between two adjacent groups of the pixel units.

[0012] In some embodiments, the first pixel electrode includes a first electrode body and a first connecting electrode, the second pixel electrode includes a second electrode body and a second connecting electrode, the first electrode body and the second electrode body each include a first end and a second end opposite to each other along a second direction, the first connecting electrode is connected to the first end of the first electrode body and a first transistor, and the second connecting electrode is connected to the second end of the second electrode body and a second transistor respectively.

[0013] On one side of the second end of the first electrode body, the second connecting electrode extends to the corner of the first pixel unit in the same pixel unit group to form the extension segment; the transition layer is located at the corner of the second pixel unit adjacent to the common signal line and away from the first end of the second electrode body.

[0014] In some embodiments, the second end of the first electrode body is provided with a first notch to avoid the extension segment;

[0015] The first end of the second electrode body is provided with a second notch to avoid the transition layer, and the area surrounded by the orthogonal projection of the edge of the first notch on the substrate is the same as the area surrounded by the orthogonal projection of the edge of the second notch on the substrate.

[0016] In some embodiments, along the first direction, a data line is provided between two adjacent pixel unit groups, and the data line is spaced apart from the common signal line, and the data line and the common signal line are arranged on the same layer.

[0017] In some embodiments, a light-shielding layer is provided on the side of the common electrode layer away from the substrate, and the orthographic projections of the edges of the common signal line, the thin-film transistor, the extension segment, the transition layer, and the via on the substrate are all located within the orthographic projection range of the light-shielding layer on the substrate.

[0018] In some embodiments, the light-shielding layer includes a first pattern corresponding to the extension segment and a second pattern corresponding to the transition layer and the via, wherein the first pattern and the second pattern have the same orthographic projection area on the substrate, and the first pattern and the second pattern have equal orthographic projection areas and the same outline on the substrate.

[0019] In some embodiments, along the second direction, a via is provided between any one of the two transition layers corresponding to each pair of adjacent pixel unit groups and the common electrode layer.

[0020] In some embodiments, the transition layer includes a first segment and a second segment, the first segment being parallel to the common signal line, the orthographic projection of the first segment onto the substrate partially overlapping the orthographic projection of the common signal line onto the substrate, and the second segment having an angle with the first segment.

[0021] The orthographic projection of the edge of the via onto the substrate overlaps with the orthographic projection of the first segment and the second segment onto the substrate at the included angle.

[0022] In some embodiments, the display panel has a display area, and the display panel includes a color filter substrate opposite to the array substrate;

[0023] In the display area, the color filter substrate includes a plurality of pixel matrices arranged in an array, each pixel matrix includes a plurality of pixel unit groups, and each pixel matrix is ​​provided with an array of support pillars, the support pillars including a reference support pillar, at least one first main support pillar and a plurality of first auxiliary support pillars;

[0024] The reference support pillar is located at a first preset position of the pixel matrix, the first main support pillar is located at a second preset position of the pixel matrix, and the first auxiliary support pillar is located at a third preset position of the pixel matrix; the orthographic projection of the reference support pillar, the first main support pillar, and the first auxiliary support pillar onto the substrate is located within the orthographic projection range of the light-shielding layer onto the substrate.

[0025] The orthographic projection shape of the reference support column on the substrate is different from the orthographic projection shapes of the first main support column and the first auxiliary support column on the substrate.

[0026] In some embodiments, the reference support column and the first auxiliary support column have a first height along a direction perpendicular to the color filter substrate; the first main support column has a second height along a direction perpendicular to the color filter substrate, the second height being greater than the first height.

[0027] In some embodiments, the display panel surrounds a non-display area of ​​the display area, the non-display area including a first non-display area located on both sides of the display area along the first direction, and a second non-display area located on both sides of the display area along the second direction;

[0028] In the first non-display area, the substrate is stacked with a first support layer, a second support layer and a third support layer facing the color filter substrate; a second auxiliary support pillar is provided on one side of the color filter substrate facing the substrate, the second auxiliary support pillar is positioned corresponding to the third support layer, and there is a gap between the second auxiliary support pillar and the third support layer;

[0029] In the second non-display area, the first support layer and the third support layer are stacked on the side of the substrate facing the color filter substrate; a second main support pillar is provided on the side of the color filter substrate facing the substrate, the second main support pillar is positioned corresponding to the third support layer, and the side of the second main support pillar that is close to the third support layer abuts against it.

[0030] In some embodiments, both the first transistor and the second transistor include a gate, an active layer, and a first electrode layer; the first support layer, the second support layer, and the third support layer are respectively disposed in the same layer as the gate, the active layer, and the first electrode layer.

[0031] In some embodiments, the second auxiliary support column includes a plurality of first strip support columns and a plurality of first point support columns, wherein the plurality of first strip support columns and the plurality of first point support columns are arranged side by side along a second direction, and each of the first strip support columns extends along the second direction;

[0032] The second main support column includes a plurality of second strip support columns and a plurality of second point support columns. The plurality of second strip support columns and the plurality of second point support columns are arranged side by side along a first direction, and each second strip support column extends along the first direction.

[0033] In some embodiments, the first dot-shaped support column and the first strip-shaped support column are spaced apart along a direction away from the display area.

[0034] In some embodiments, the second auxiliary support column includes a plurality of first point support columns, and the array of the first point support columns is disposed in the first non-display area; the second main support column includes a plurality of second point support columns, and the array of the second point support columns is disposed in the second non-display area.

[0035] A second aspect of this application provides a display device including the display panel described in any of the first aspects.

[0036] Beneficial effects of the embodiments in this application:

[0037] The display panel and display device provided in this application embodiment, in this embodiment, the first pixel electrode of the first pixel unit in a row of pixel units along the first direction is connected to the first transistor on one side of the first pixel unit along the second direction, and the second pixel electrode of the second pixel unit is connected to the second transistor on the other side of the first pixel unit along the second direction, realizing a dual-gate design between two adjacent pixel units along the second direction. Correspondingly, the second pixel electrode has a portion extending to the connection between the first pixel unit and the second transistor as a "long connection end". The metal transition layer is located at the corner of the second pixel unit near the first transistor, that is, on the side of the second pixel electrode away from the "long connection end", to minimize the impact on the pixel opening of the second pixel unit. The common signal line connection transition layer is connected to the common electrode layer through a via, effectively enhancing the common voltage of the common electrode layer and improving the stability of the common voltage in the common electrode layer.

[0038] In addition, the projection of the transition layer onto the substrate overlaps with the projection of the via edge onto the substrate. In the manufacturing process of the display panel, this facilitates the formation of a "step" on the side of the via facing the substrate. That is, part of the via facing the substrate "overlaps" on the transition layer, while part does not "overlap" on the transition layer. After the subsequent fabrication of the thinner common electrode layer, the common electrode layer forms a "recess" at the via. This recess facilitates the diffusion of the alignment film, thereby enhancing the alignment force on the liquid crystal layer and further improving the display effect of the display panel.

[0039] Of course, implementing any product or method of this application does not necessarily require achieving all of the advantages described above at the same time. Attached Figure Description

[0040] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other embodiments can be obtained based on these drawings.

[0041] Figure 1A comparison chart of the 0+4mask process and the 6mask process;

[0042] Figure 2 This is a schematic diagram of a dual-gate architecture in some embodiments;

[0043] Figure 3 This is a schematic diagram of empty space feature points in some embodiments;

[0044] Figure 4 This is a schematic diagram of the second main support column at the edge of the display panel in some embodiments;

[0045] Figures 5a-5d This is a schematic diagram of the pixel unit design process in an embodiment of this application;

[0046] Figure 6 for Figure 5d Enlarged view of point A in the middle;

[0047] Figure 7 This is a schematic diagram of the light-shielding layer in an embodiment of this application;

[0048] Figure 8a Examples of this application Figure 7 Enlarged schematic diagram of the first type of pattern at point B;

[0049] Figure 8b Examples of this application Figure 7 Enlarged schematic diagram of the second type of first pattern at point B;

[0050] Figure 8c Examples of this application Figure 7 Enlarged schematic diagram of the third type of first pattern at point B;

[0051] Figure 8d Examples of this application Figure 7 Enlarged schematic diagram of the fourth type of first pattern at point B;

[0052] Figure 9 This is a schematic diagram illustrating the fabrication of the light-shielding layer in the array substrate according to an embodiment of this application;

[0053] Figure 10 This is a schematic diagram of a reference support column in the display area of ​​an embodiment of this application;

[0054] Figure 11 This is a schematic diagram of a display panel edge support structure according to an embodiment of this application;

[0055] Figure 12 This is a schematic cross-sectional view of the first non-display area according to an embodiment of this application;

[0056] Figure 13 for Figure 11 Detailed schematic diagram;

[0057] Figure 14 This is a schematic diagram of the second non-display area interface according to an embodiment of this application;

[0058] Figure 15 for Figure 13 Detailed schematic diagram;

[0059] Figure 16 This is a schematic diagram of another display panel edge support structure according to an embodiment of this application.

[0060] The reference numerals in the attached figures are as follows: Gate 1, Active layer 2, Source / drain 3, Pixel electrode 4, Passivation layer 5, Common electrode layer 6, Gate line 7, Data line 8, Support pillar 9, Vacant feature point 10, Pixel unit group 11, Common signal line 12, Substrate 20, First transistor 23, Second transistor 24, First pixel electrode 25, First electrode body 251, First connecting electrode 252, Second pixel electrode 26, Second electrode body 261, Second connecting electrode 262, Color filter substrate 30, Adapter Layer 31, first segment 311, second segment 312, via 32, first notch 41, second notch 42, light-shielding layer 51, first pattern 52, second pattern 53, reference support column 61, first main support column 62, first auxiliary support column 63, first support layer 71, second support layer 72, third support layer 73, second auxiliary support column 74, first strip support column 75, first point support column 76, second main support column 77, second strip support column 78, second point support column 79. Detailed Implementation

[0061] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art based on this application are within the scope of protection of this application.

[0062] refer to Figure 1 As shown, the 6mask process and the 0+4mask process are compared. In the fabrication of thin-film transistors, the 6mask process sequentially stacks the gate 1, active layer 2, source / drain 3, pixel electrode 4, passivation layer 5, and common electrode layer 6. In the 0+4mask process, the pixel electrode 4, gate 1, active layer 2, and source / drain 3 are patterned using a half-tone mask. The gate 1 and active layer 2 are fabricated using the same process flow (Half-Tone Gate Mask, HGA), and the source / drain 3 and pixel electrode 4 are fabricated using the same process flow (Source-Drain Half-Tone, SDT). The order of the remaining film layers remains unchanged.

[0063] In some embodiments, reference Figure 2 As shown, in the dual-gate architecture, adjacent pixel units are provided with two gate lines 7 along the column direction of the pixel unit, and adjacent pixel units share a data line 8 along the row direction of the pixel unit. The number of gate lines 7 is doubled, the number of data lines 8 is halved, and the number of corresponding driver units (ICs) is halved, thereby reducing costs. In a dual-gate architecture, it is generally necessary to connect the common signal line and the common electrode layer 6 located on different layers so that the common signal line provides a common voltage to the common electrode layer 6, thereby creating a voltage difference between the common electrode layer 6 and the pixel electrode 4. This voltage difference controls the deflection of the liquid crystal, causing the display panel to emit light. In related technologies, the common signal line is located at the edge of the display panel, and the in-plane voltage stability of the common electrode layer 6 is poor. If the common signal line is located in the display area of ​​the display panel, the via connecting the common signal line and the common electrode layer 6 is also located in the display area. However, due to the limitations of the manufacturing process, the via faces the substrate, and some vias may be completely covered by the common signal line, while others may be partially covered. After the thin common electrode layer 6 is fabricated, the recesses formed at the positions of the vias in the common electrode layer 6 are sometimes deep and sometimes shallow. Shallow recesses may affect the diffusion of the subsequent alignment film, resulting in bright spots at the corresponding locations, which affects the display effect of the display panel.

[0064] pass Figure 2 As can be seen, two pixel units share a signal line. Taking the two pixel units in the upper left corner as an example, the connection between the pixel electrode 4 of the right pixel unit and the thin film transistor needs to extend to the left pixel unit area. Accordingly, the pixel opening of the left pixel unit will be different from that of the right pixel unit, which will also affect the display effect of the display panel.

[0065] pass Figure 3 It is known that after the array substrate is fabricated, the array substrate and the color filter substrate need to be aligned and assembled. The array substrate is provided with support pillars 9 to provide sufficient support strength for the display panel. In related technologies, in order to enable the detection equipment to identify and locate, an empty feature point 10 is usually found on the color filter substrate. No support pillars 9 are fabricated for this empty feature point 10. Using the empty feature point 10 as a reference point to detect the alignment accuracy of the remaining support pillars 9 is relatively low.

[0066] refer to Figure 4 As shown, in the 6mask process, the edge of the display panel is supported by a uniform second main support pillar 77. After being prepared by the 0+4mask process, the film thickness is different on one side of the substrate. If the uniform second main support pillar 77 is continued to be used, the support height of the display panel will be inconsistent, causing the display panel to turn yellow and even affecting the display effect of the display panel.

[0067] Based on this, refer to Figure 5a , Figure 5b , Figure 5c , Figure 5d and Figure 6 As shown, this application embodiment provides a display panel, including an array substrate. The array substrate includes a substrate 20 and a plurality of pixel unit groups 11, a common signal line 12, a thin film transistor, a pixel electrode 4, and a common electrode layer 6 located on one side of the substrate 20. Along a first direction, each pixel unit group 11 includes an adjacent first pixel unit and a second pixel unit. Along a second direction, the thin film transistor includes a first transistor 23 and a second transistor 24 located on opposite sides of the first pixel unit. The pixel electrode 4 includes a first pixel electrode 25 and a second pixel electrode 26 located on the first pixel unit and the second pixel unit, respectively. The first pixel electrode 25 and the first... Transistor 23 is connected, and the extension of the second pixel electrode 26 toward the side of the second transistor 24 extends to the first pixel unit and is connected to the second transistor 24; the common signal line 12 is located between the first pixel unit and the second pixel unit and extends along the second direction. The common signal line 12 is connected to the transition layer 31. The transition layer 31 is located at the corner of the second pixel unit near the first transistor 23. At least a portion of the transition layer 31 and the common electrode layer 6 have a via 32. The transition layer 31 and the common electrode layer 6 are connected through the via 32. The orthographic projection of the transition layer 31 on the substrate 20 overlaps with the orthographic projection of the edge of the via 32 on the substrate 20.

[0068] In an exemplary embodiment, both the first transistor 23 and the second transistor 24 include a gate, an active layer, and a first electrode layer. The first electrode layer may include a source and a drain. The first pixel electrode 25 is connected to the source of the first transistor 23, and the second pixel electrode 26 is connected to the source of the second transistor 24.

[0069] In an exemplary implementation, reference Figures 5a-5d As shown in the embodiment of this application, the process of fabricating the display panel using the 0+4mask process is as follows: the gate 1 and the active layer 2 are fabricated through the same process, and the gate line 7 is fabricated simultaneously. Then, the first electrode layer and the pixel electrode 4 are fabricated through the same process, and the data line 8, the common signal line 12 and the transition layer 31 are fabricated simultaneously. Then, the passivation layer 5 is fabricated, and finally, the common electrode layer 6 is fabricated.

[0070] In an exemplary embodiment, the common signal line 12 and the adapter layer 31 are arranged on the same layer.

[0071] In an exemplary embodiment, a plurality of pixel unit groups 11 are arrayed on one side of the substrate 20. Along the second direction, a first transistor 23 and a second transistor 24 are provided on both sides of the first pixel unit. Correspondingly, along the second direction, two gate lines 7 are provided between two adjacent pixel unit groups 11.

[0072] In an exemplary embodiment, the thin-film transistor can be a low-temperature polysilicon (LTPS) thin-film transistor, in which the active layer is formed by polysilicon deposition, or it can be an oxide thin-film transistor (Oxide TFT), in which an oxide semiconductor is used as the active layer.

[0073] In an exemplary embodiment, the common signal line 12 is on a different layer than the common electrode layer 6.

[0074] In an exemplary embodiment, the first direction is perpendicular to the second direction. Preferably, the first direction can be a row direction and the second direction can be a column direction.

[0075] In an exemplary embodiment, a plurality of common signal lines 12 are provided between the first pixel unit and the second pixel unit along a first direction, and each common signal line 12 extends along a second direction.

[0076] In this embodiment, the first pixel electrode 25 of the first pixel unit in a row of pixel unit groups 11 along the first direction is connected to the first transistor 23 on one side of the first pixel unit along the second direction, and the second pixel electrode 26 of the second pixel unit is connected to the second transistor 24 on the other side of the first pixel unit along the second direction, realizing a dual-gate design between two adjacent pixel unit groups 11 along the second direction. Correspondingly, the second pixel electrode 26 has an extension portion extending to the connection between the first pixel unit and the second transistor 24 as a "long connection end". The metal transition layer 31 is located at the corner of the second pixel unit near the first transistor 23, that is, on the side of the second pixel electrode 26 away from the "long connection end", minimizing the impact on the pixel opening of the second pixel unit. The common signal line 12 is connected to the transition layer 31, and the transition layer 31 is connected to the common electrode layer 6 through the via 32, effectively enhancing the common voltage of the common electrode layer 6 and improving the stability of the common voltage in the common electrode layer 6.

[0077] In addition, the orthographic projection of the transition layer 31 onto the substrate 20 overlaps with the orthographic projection of the edge of the via 32 onto the substrate 20. In the manufacturing process of the display panel, this facilitates the formation of a "step" on the side of the via 32 facing the substrate 20. That is, the end of the via 32 facing the substrate 20 is partially "overlapped" on the transition layer 31, while the other part is not "overlapped" on the transition layer 31. After the thinner common electrode layer 6 is subsequently fabricated, the common electrode layer 6 forms a "recess" at the via 32. This recess facilitates the diffusion of the alignment film, thereby enhancing the alignment force on the liquid crystal layer and further improving the display effect of the display panel.

[0078] In some embodiments, reference Figure 5d As shown, along the first direction, the first pixel unit and the second pixel unit are spaced apart; along the second direction, the first pixel unit and the second pixel unit are spaced apart, and two gate lines 7 are included between two adjacent pixel unit groups 11.

[0079] In an exemplary embodiment, the first pixel unit is represented by A, the second pixel unit is represented by B, and the first pixel unit and the second pixel unit are arranged in ABABAB... along the first direction; and the first pixel unit and the second pixel unit are arranged in ABABAB... along the second direction.

[0080] It is understood that each first pixel unit controls a row of pixel units 11 along a first direction relative to the first transistor 23 and the second transistor 24 on both sides, and correspondingly, along a second direction, there are two gate lines 7 between two adjacent rows of pixel units 11.

[0081] In this embodiment, the first transistor 23 and the second transistor 24 are located on opposite sides of the first pixel unit along the second direction. By arranging the pixel unit and the second pixel unit at intervals along the first direction and along the second direction, the first transistor 23 and the second transistor 24 are staggered along the first direction, saving space occupied by the first transistor 23, the second transistor 24 and the gate line 7 along the second direction. This is beneficial to increasing the pixel aperture ratio of the first pixel unit and the second pixel unit and improving the display brightness of the display panel.

[0082] In some embodiments, the first pixel electrode 25 includes a first electrode body 251 and a first connecting electrode 252, and the second pixel electrode 26 includes a second electrode body 261 and a second connecting electrode 262. The first electrode body 251 and the second electrode body 261 each include a first end and a second end opposite to each other along a second direction. The first connecting electrode 252 is connected to the first end of the first electrode body 251 and the first transistor 23. The second connecting electrode 262 is connected to the second end of the second electrode body 261 and the second transistor 24, respectively. On one side of the second end of the first electrode body 251, the second connecting electrode 262 extends to the corner of the first pixel unit in the same pixel unit group 11 to form an extension segment. The transition layer 31 is located at the corner of the second pixel unit adjacent to the common signal line 12 and is away from one end of the second electrode body 261.

[0083] In an exemplary implementation, to Figure 5d Taking a pixel unit group 11 in the upper left corner as an example, the lower side of the first electrode body 251 and the second electrode body 261 is the first end, and the upper side of the first electrode body 251 and the second electrode body 261 is the second end; Figure 5d Taking a pixel unit in the middle of the top row as an example, the lower side of the first electrode body 251 and the second electrode body 261 is the first end, and the upper side of the first electrode body 251 and the second electrode body 261 is the second end.

[0084] In an exemplary embodiment, the first connecting electrode 252 serves as the long connecting end of the first pixel electrode 25, and the second connecting electrode 262 serves as the long connecting end of the second pixel electrode 26.

[0085] In this embodiment, the first connecting electrode 252 serves as the "long connecting end" of the first pixel electrode 25 and is connected to the first end of the first electrode body 251. The second connecting electrode 262 serves as the "long connecting end" of the second pixel electrode 26 and is connected to the second end of the second electrode body 261. This reduces the interference of the second pixel electrode 26 with the first pixel electrode 25 after the second pixel electrode 26 is connected to the second transistor 24 structure. That is, the extension of the second connecting electrode 262 avoids the first connecting electrode 252. At the same time, on the second end side of the first electrode body 251, the extension of the second connecting electrode 262 extends to the corner of the adjacent first pixel unit, minimizing the occupation of the extension on the first pixel unit. This is beneficial to increasing the pixel aperture ratio of the first pixel unit. The transition layer 31 is located at the corner of the second pixel unit adjacent to the common signal line 12 and is far away from the second electrode body 261. This allows the transition layer 31 and the via 32 to minimize the occupation of the second pixel unit while effectively enhancing the common voltage of the common electrode layer 6 and improving the stability of the common voltage in the common electrode layer 6.

[0086] In some embodiments, reference Figure 5d and Figure 6 As shown, the second end of the first electrode body 251 is provided with a first notch 41 that avoids the extension section; the first end of the second electrode body 261 is provided with a second notch 42 that avoids the transition layer 31. The area surrounded by the orthographic projection of the edge of the first notch 41 on the substrate 20 is the same as the area surrounded by the orthographic projection of the edge of the second notch 42 on the substrate 20.

[0087] In an exemplary embodiment, the first pixel electrode 25 and the second pixel electrode 26 are disposed in the same layer.

[0088] In an exemplary embodiment, the first pixel electrode 25, the second pixel electrode 26, the common signal line 12, and the transition layer 31 are disposed on the same layer.

[0089] In this embodiment, the first notch 41 is provided to prevent the second pixel electrode 26 from short-circuiting with the first pixel electrode 25, so that the first pixel unit can be displayed normally. At the same time, it prevents the second pixel electrode 26 from affecting the normal display of the first pixel unit. The second notch 42 is provided to prevent the second pixel electrode 26 from short-circuiting with the common signal line 12 through the transition layer 31, so that the second pixel unit can be displayed normally. The area surrounded by the orthographic projection of the edge of the first notch 41 on the substrate 20 is the same as the area surrounded by the orthographic projection of the edge of the second notch 42 on the substrate 20, so that the pixel openings of the first pixel unit and the second pixel unit are as similar as possible. This is beneficial to the consistency of the display screen and avoids the pixel opening difference of the first pixel unit and the second pixel unit being too large, which would cause uneven brightness of the display screen.

[0090] In some embodiments, reference Figure 5b and Figure 6 As shown, along the first direction, a data line 8 is provided between two adjacent pixel unit groups 11. The data line 8 and the common signal line 12 are spaced apart and are arranged on the same layer.

[0091] In an exemplary embodiment, the first electrode layer includes a source and a drain. The source of the first transistor 23 is connected to the first pixel electrode 25, the source of the second transistor 24 is connected to the second pixel electrode 26, and the data line 8 is connected to the drain of the first transistor 23 and the second transistor 24, respectively.

[0092] In an exemplary embodiment, the data line 8 is connected to the drain of the first transistor 23 and the second transistor 24 of a row of pixel unit groups 11 arranged along the second direction.

[0093] In this embodiment, the data line 8 and the common signal line 12 are spaced apart, increasing the number of common signal lines 12 in the display area of ​​the display panel. This facilitates the uniform transmission of the common voltage to the common electrode layer 6 while effectively avoiding interference with the arrangement of the data line 8. At the same time, the display panel in this embodiment is fabricated using a 0+4 mask process, with the common signal line 12 and the data line 8 arranged in the same layer, reducing the number of mask processes in the fabrication of the array substrate and improving the fabrication efficiency of the display panel.

[0094] In some embodiments, reference Figure 7 , Figure 8a , Figure 8b , Figure 8c , Figure 8d and Figure 9 As shown, a light-shielding layer 51 is provided on the side of the common electrode layer 6 away from the substrate 20. The orthographic projections of the common signal line 12, thin film transistor, extension section and transition layer 31 on the substrate 20 are all located within the orthographic projection range of the light-shielding layer 51 on the substrate 20.

[0095] In an exemplary embodiment, a light-shielding layer 51 is provided on the side of the common electrode layer 6 away from the substrate 20. The light-shielding layer 51 has a light-transmitting opening. Both the first pixel unit and the second pixel unit have pixel openings. The edge of the light-transmitting opening is located within the orthogonal projection range of the substrate 20, i.e., the light-transmitting opening is less than or equal to the pixel opening.

[0096] In an exemplary embodiment, the orthogonal projections of the gate line 7 and the data line 8 onto the substrate 20 are also located within the orthogonal projection range of the light-shielding layer 51 onto the substrate 20.

[0097] In this embodiment, the orthographic projections of the extension segment and the transition layer 31 onto the substrate 20 are both located within the orthographic projection range of the light-shielding layer 51 onto the substrate 20. That is, the light-shielding layer 51 covers the extension segment, the transition layer 31, and the via 32, effectively preventing light leakage caused by the extension segment in the first pixel unit, and light leakage caused by the transition layer 31 and the via 32 in the second pixel unit.

[0098] In some embodiments, the light-shielding layer 51 includes a first pattern 52 corresponding to the extension segment and a second pattern 53 corresponding to the transition layer 31 and the via 32. The first pattern 52 and the second pattern 53 have the same orthogonal projection area on the substrate 20, and the first pattern 52 and the second pattern 53 have the same orthogonal projection area and the same outline on the substrate 20.

[0099] In an exemplary embodiment, the orthographic projection outlines of the first pattern 52 and the second pattern 53 onto the substrate 20 can be of any shape, for example... Figure 8a The right trapezoid shown Figure 8b The rectangle shown Figure 8c The arc or shown Figure 8d The triangle and rectangle shapes shown are easier to control and make it easier to adjust the light transmission differences of different pixels. The arc shape can increase the light transmission opening area while ensuring light blocking, thereby improving the light transmittance. The triangle has a greater impact on the light transmission opening, but the actual light blocking effect is better.

[0100] In this embodiment, the first pattern 52 and the second pattern 53 have the same orthogonal projection area on the substrate 20, so that the light-transmitting openings of the first pixel unit and the second pixel unit are as similar as possible, which further improves the consistency of the display screen and avoids uneven brightness of the display screen caused by excessive difference in the light-transmitting openings of the first pixel unit and the second pixel unit.

[0101] In some embodiments, along the second direction, a via 32 is provided between any one of the two transition layers 31 corresponding to each of two adjacent pixel unit groups 11 and the common electrode layer 6.

[0102] In an exemplary implementation, such as Figure 5d and Figure 6 As shown, in the two rows of pixel unit groups 11, each row of pixel unit group 11 includes a transition layer 31. A via 32 can be disposed in the upper row of pixel unit group 11, or in the lower row of pixel unit group 11, or partially disposed in both rows. Preferably, the via 32 is partially disposed in the upper row of pixel unit group 11 and partially disposed in the lower row of pixel unit group 11. For example… Figure 5d The six pixel unit groups include six first pixel units and six second pixel units, and three vias 32 are provided, one of which is located in the upper row of pixel unit group 11, and the other two are located in the lower row of pixel unit group 11.

[0103] In this embodiment, along the second direction, a via 32 is provided between any one of the two transition layers 31 corresponding to each pair of adjacent pixel unit groups 11 and the common electrode layer 6. That is, along the second direction, each pair of adjacent pixel unit groups 11 shares a via 32 to realize the connection between the common signal line 12 and the common electrode layer 6, ensuring the uniformity of the common voltage in the plane of the common electrode layer 6 while minimizing the number of vias 32. At the same time, the transition layer 31 is connected to the common signal line 12, and the transition layer 31 is retained in the position where there is no via 32, so that the length or cross-sectional area of ​​each common signal line 12 is the same or similar, effectively ensuring that the load of each common signal line 12 is the same, and further improving the uniformity of the common voltage transmitted to the common electrode layer 6.

[0104] In some embodiments, reference Figure 6As shown, the transition layer 31 includes a first segment 311 and a second segment 312. The first segment 311 is parallel to the common signal line 12. The orthographic projection of the first segment 311 on the substrate 20 overlaps with the orthographic projection of the common signal line 12 on the substrate 20. The second segment 312 has an angle with the first segment 311. The edge of the via 32 overlaps with the orthographic projection of the first segment 311 and the second segment 312 at the angle on the substrate 20.

[0105] In an exemplary embodiment, the included angle can be greater than 45° and less than 135°, and preferably, the included angle is 90°.

[0106] In an exemplary embodiment, the transition layer 31 is L-shaped when projected onto the substrate 20.

[0107] In an exemplary embodiment, the extension direction of the first segment 311 is the same as the extension direction of the common signal line 12.

[0108] In this embodiment, the first segment 311 and the second segment 312 have an included angle, and the orthographic projection of the edge of the via 32 onto the substrate 20 overlaps with the orthographic projection of the first segment 311 and the second segment 312 onto the substrate 20 at the included angle. In the manufacturing process of the display panel, this facilitates the formation of a "step" on the side of the via 32 facing the substrate 20 by the transition layer 31. That is, one end of the via 32 facing the substrate 20 is "overlapped" on the transition layer 31, while the other end is not "overlapped" on the transition layer 31. After the thinner common electrode layer 6 is subsequently prepared, the common electrode layer 6 forms a "recess" at the via 32. This recess is beneficial for the diffusion of the alignment film.

[0109] It is understandable that, due to limitations in process precision, if the orthographic projection of the transition layer 31 onto the substrate 20 is not L-shaped, some vias 32 facing the substrate 20 may be completely covered by the transition layer 31, while others may be partially covered. After the common electrode layer 6 is fabricated, the side of the common electrode layer 6 away from the substrate 20 may have varying depths at the vias 32. Deeper depressions correspond to effective diffusion of the alignment film, while shallower depressions prevent diffusion of the alignment film, resulting in uneven display quality or bright spots.

[0110] In some embodiments, the common electrode layer 6 is provided with an alignment film (not shown in the figure) on the side away from the substrate 20, and the edge of the via 32 is located within the orthogonal projection range of the alignment film on the substrate 20.

[0111] In an exemplary embodiment, the alignment film is made of polyimide (PI).

[0112] In this embodiment, the via 32 and the transition layer 31 in the above embodiment facilitate the effective diffusion of the alignment film on the side of the common electrode layer 6 away from the substrate 20. The effective diffusion of the alignment film provides alignment force for the liquid crystal molecules, so that the liquid crystal molecules form a uniform pretilt angle. The first pixel electrode 25 and the second pixel electrode 26 generate a voltage difference with the common electrode layer 6, and the voltage difference controls the orderly deflection of the liquid crystal.

[0113] In some embodiments, reference Figure 10 , Figure 11 and Figure 16 As shown, the display panel has a display area AA and includes a color filter substrate 30 opposite to the array substrate. In the display area AA, the color filter substrate 30 includes a plurality of periodically arrayed pixel matrices. Each pixel matrix has an array of support pillars, including a reference support pillar 61, at least one first main support pillar 62, and a plurality of first auxiliary support pillars 63. The reference support pillar 61 is located at a first preset position of the pixel matrix, the first main support pillar 62 is located at a second preset position of the pixel matrix, and the first auxiliary support pillar 63 is located at a third preset position of the pixel matrix. The orthographic projections of the reference support pillar 61, the first main support pillar 62, and the first auxiliary support pillar 63 onto the substrate 20 are located within the orthographic projection range of the light-shielding layer 51 onto the substrate 20. The orthographic projection shape of the reference support pillar 61 onto the substrate 20 is different from the orthographic projection shapes of the first main support pillar 62 and the first auxiliary support pillar 63 onto the substrate 20.

[0114] In an exemplary embodiment, the first main support post 62 and the first auxiliary support post 63 can be cylinders, and the orthographic projection shape of the first main support post 62 and the first auxiliary support post 63 on the substrate 20 is circular. The reference support post 61 can be a prism, and the orthographic projection shape of the reference support post 61 on the substrate 20 can be a triangle, a rectangle, a polygon, etc.

[0115] In an exemplary embodiment, the number of first main support pillars 62 in each pixel matrix is ​​less than the number of first auxiliary support pillars 63.

[0116] In an exemplary embodiment, in each pixel matrix, the first pixel unit and the second pixel unit are considered as a unified pixel unit, such as... Figure 9 As shown, the leftmost position between the first row of pixel units and the second row of pixel units is the first preset position; or the rightmost position between the first row of pixel units and the second row of pixel units is the first preset position. This application does not make a specific limitation on this, as long as the first preset position in each pixel matrix is ​​consistent.

[0117] In an exemplary embodiment, each pixel matrix may have one first main support pillar 62, two main support pillars, or more. The number of first main support pillars 62 can vary depending on the size of the pixel matrix. Figure 9 As shown, a first main support column 62 is set between the second and third row pixel units, corresponding to the second column pixel unit, and another first main support column 62 is set between the fifth and sixth row pixel units, corresponding to the eighth column pixel unit.

[0118] In an exemplary implementation, in each pixel matrix, such as Figure 9 As shown, apart from the first preset position and the second preset position, the first auxiliary support column 63 can be set at any position between pixel units.

[0119] In this embodiment, by setting a reference support column 61 at a first preset position, the detection and identification device can easily identify and locate the device by using the position of the reference support column 61. Using the reference support column 61 as a reference coordinate facilitates the preparation of the first main support column 62 and the first auxiliary support column 63, and also facilitates the identification and inspection of the first main support column 62 and the first auxiliary support column 63, ensuring that the height of the first main support column 62 and the first auxiliary support column 63 meets the requirements.

[0120] In addition, by referring to the setting of the support column 61, compared with the empty feature point 10, the internal support density of the display panel is increased, and the overall support strength of the display panel is enhanced.

[0121] In some alternative embodiments, the reference support post 61 has a first length along a first direction and a second length along a second direction, wherein the absolute value of the difference between the first length and the second length is greater than 5 μm.

[0122] In an exemplary embodiment, the orthographic projection shape of the reference support post 61 onto the substrate is rectangular, and the difference between the length and width of the rectangle is greater than 5 μm.

[0123] In this embodiment, by ensuring that the absolute value of the difference between the first length and the second length is greater than 5 μm, the reference support column 61 is made more convenient for the detection and identification device to identify and locate it.

[0124] In some embodiments, the reference support column 61 and the first auxiliary support column 63 have a first height along a direction perpendicular to the color filter substrate 30; the first main support column 62 has a second height along a direction perpendicular to the color filter substrate 30, and the second height is greater than the first height.

[0125] In this embodiment, the reference support column 61 and the first auxiliary support column 63 have the same height. In addition to serving as a reference point to facilitate identification and positioning by the detection equipment, the reference support column 61 is also used as the first auxiliary support column 63, together with the first auxiliary support column 63 to improve the support strength of the display panel in the display area.

[0126] In some embodiments, reference Figure 11 , Figure 12 , Figure 13 , Figure 14 and Figure 15 As shown, the display panel has a non-display area surrounding the display area AA. The non-display area includes a first non-display area located on both sides of the display area along a first direction, and a second non-display area located on opposite sides of the display area along a second direction. In the first non-display area, a first support layer 71, a second support layer 72, and a third support layer 73 are stacked on the substrate 20 facing the color filter substrate 30. A second auxiliary support pillar 74 is provided on the side of the color filter substrate 30 facing the substrate 20. The second auxiliary support pillar 74 corresponds to the third support layer 73, and there is a gap between the second auxiliary support pillar 74 and the third support layer 73. In the second non-display area, the first support layer 71 and the third support layer 73 are stacked on the substrate 20 facing the color filter substrate 30. A second main support pillar 77 is provided on the side of the color filter substrate 30 facing the substrate 20. The second main support pillar 77 corresponds to the third support layer 73, and the side of the second main support pillar 77 adjacent to the third support layer 73 abuts against it.

[0127] In some embodiments, the first transistor 23 and the second transistor 24 each include a gate, an active layer and a first electrode layer; the first support layer 71, the second support layer 72 and the third support layer 73 are respectively disposed in the same layer as the gate, the active layer and the first electrode layer.

[0128] In an exemplary embodiment, the first electrode layer includes a source and a drain.

[0129] In an exemplary embodiment, the first support layer 71, the second support layer 72, and the third support layer 73 are made of the same material as the gate, the active layer, and the first electrode layer, respectively.

[0130] In an exemplary embodiment, the first non-display area can be the border area located on the left and right sides of the display area.

[0131] In an exemplary embodiment, the second non-display area can be the border area located on the upper and lower sides of the display area.

[0132] In this embodiment, a 0+4mask process with a dual-gate pixel design is used. In the second non-display area, there is no second support layer 72 between the first support layer 71 and the third support layer 73. The second main support pillar 77 abuts against the side of the third support layer 73 that is close to it, that is, along the direction perpendicular to the color filter substrate 30. The setting of the second main support pillar 77 makes the support height of the second non-display area correspond to the support height of the display area, so as to avoid the risk of yellowing of the display panel due to uneven support height and the risk of ineffective cell assembly. In the display area, transistor structures are fabricated on the side of the array substrate facing the color filter substrate 30, with the gate, active layer, and first electrode layer patterned to form them respectively. In the first non-display area, no patterning is required, and the corresponding film layers of the gate, active layer, and first electrode layer are retained, forming the first support layer 71, the second support layer 72, and the third support layer 73 respectively. Compared to the second non-display area, in the first non-display area, on the side of the array substrate facing the color filter substrate 30, the second support layer 72 (active layer) remains between the first support layer 71 (gate) and the third support layer 73 (first electrode layer). If the first non-display area continues to use a taller support pillar, it will lead to... The thickness of the first non-display area of ​​the display panel is greater than that of the display area, making it impossible to effectively form the display panel. Furthermore, during the cell assembly process, the support height of the non-display area must not exceed the support height of the display area. A second auxiliary support pillar 74 is provided on the side of the color filter substrate 30 facing the substrate 20. The second auxiliary support pillar 74 corresponds to the first support layer 71, and there is a gap between the second auxiliary support pillar 74 and the third support layer 73. This ensures that the support height of the first non-display area matches the support height of the second non-display area, avoiding the risk of yellowing and ineffective cell assembly caused by uneven support heights in the first and second non-display areas of the display panel.

[0133] It is understandable that the gate line 7 extends along the first direction, and each gate line 7 is connected to a thin film transistor. Correspondingly, in the first non-display area on both sides of the display area along the first direction, there will be a second support layer 72 remaining between the first support layer 71 and the third support layer 73.

[0134] In some embodiments, reference Figure 11 As shown, the second auxiliary support column 74 includes a plurality of first strip support columns 75 and a plurality of first point support columns 76, all of which are arranged side by side along a second direction, and each first strip support column 75 extends along the second direction; the second main support column 77 includes a plurality of second strip support columns 78 and a plurality of second point support columns 79, all of which are arranged side by side along a first direction, and each second strip support column 78 extends along the first direction.

[0135] In an exemplary embodiment, the first strip support column 75 is closer to the edge of the display panel than the first dot support column 76, and the second strip support column 78 is closer to the edge of the display panel than the second dot support column 79.

[0136] In this embodiment, multiple first strip-shaped support columns 75 and multiple first point-shaped support columns 76 are arranged side by side along a second direction. This allows the first strip-shaped support columns 75 and the first point-shaped support columns 76 to effectively support the first non-display area while increasing the support strength in the first non-display area. Furthermore, the first point-shaped support columns 76 and the first strip-shaped support columns 75 are arranged side by side along a direction away from the display area. Each first strip-shaped support column 75 extends along the second direction, so that the first strip-shaped support column 75 is closer to the edge of the display panel than the first point-shaped support columns 76. The first strip-shaped support columns 75 effectively prevent the frame adhesive at the edge of the display panel from overflowing into the display area, protecting the film layers and devices in the display area, while ensuring the display effect of the display panel. The second strip-shaped support column 78 has the same function as the first strip-shaped support column 75, and the second point-shaped support column 79 has the same function as the first point-shaped support column 76, which will not be described again here.

[0137] In some embodiments, the first dot-shaped support column 76 and the first strip-shaped support column 75 are spaced apart along a direction away from the display area; the second dot-shaped support column 79 and the second strip-shaped support column 78 are spaced apart.

[0138] In this embodiment, it is not limited to Figure 10 The diagram shows only one row of first strip support columns 75 and only one row of first dot support columns 76, and not only one row of second strip support columns 78 and only one row of second dot support columns 79. Depending on the application requirements of the display panel, for applications with lower requirements for bezel width, such as larger display panels, multiple rows of first dot support columns 76 and first strip support columns 75 can be spaced apart along the first direction, and multiple rows of second dot support columns 79 and second strip support columns 78 can be spaced apart along the second direction to improve the support strength of the first non-display area and the second non-display area.

[0139] In some embodiments, reference Figure 16 As shown, the second auxiliary support column 74 includes a plurality of first point support columns 76, and the array of first point support columns 76 is arranged in the first non-display area; the second main support column 77 includes a plurality of second point support columns 79, and the array of second point support columns 79 is arranged in the second non-display area.

[0140] In this embodiment, by setting an array of first dot-shaped support columns 76 in the first non-display area and setting an array of second dot-shaped support columns 79 in the second non-display area, the support uniformity of the non-display area is improved.

[0141] Based on the same inventive concept, a second aspect of the embodiments of this application provides a display device, including the display panel described in any of the above embodiments. The specific structure and beneficial effects of the display panel have been described in detail above, and therefore will not be repeated here.

[0142] It should be noted that, in addition to the display panel, the display device also includes other necessary components, such as the bezel. Those skilled in the art can make corresponding additions according to the specific usage requirements of the display device, which will not be elaborated here.

[0143] The display device can also be an emerging wearable device, such as a virtual reality device or an augmented reality device; or it can be a traditional electronic device, such as a mobile phone, computer, television, camcorder, or vehicle display. These will not be listed exhaustively here. In the embodiments of this application, the display device includes a liquid crystal display device, such as a liquid crystal display (LCD).

[0144] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0145] The various embodiments in this specification are described in a related manner. The same or similar parts between the various embodiments can be referred to each other. Each embodiment focuses on describing the differences from other embodiments.

[0146] The above description is merely a preferred embodiment of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application are included within the scope of protection of this application.

Claims

1. A display panel, characterized in that, include: An array substrate, comprising a substrate and a plurality of pixel unit groups, a common signal line, a thin film transistor, a pixel electrode and a common electrode layer disposed on one side of the substrate; Along the first direction, each group of pixel units includes an adjacent first pixel unit and a second pixel unit; Along the second direction, the thin-film transistor includes a first transistor and a second transistor located on opposite sides of the first pixel unit, and the pixel electrode includes a first pixel electrode and a second pixel electrode located in the first pixel unit and the second pixel unit, respectively. The first pixel electrode is connected to the first transistor, and an extension of the second pixel electrode toward the second transistor extends to the first pixel unit and is connected to the second transistor. The common signal line is located between the first pixel unit and the second pixel unit and extends along the second direction. The common signal line is connected to a transition layer, which is located at the corner of the second pixel unit near the first transistor. At least a portion of the transition layer and the common electrode layer have a via, and the transition layer and the common electrode layer are connected through the via; The orthographic projection of the transition layer onto the substrate overlaps with the orthographic projection of the via edge onto the substrate.

2. The display panel according to claim 1, characterized in that, Along the first direction, the first pixel unit and the second pixel unit are spaced apart; Along the second direction, the first pixel unit and the second pixel unit are spaced apart, and two gate lines are included between two adjacent groups of the pixel units.

3. The display panel according to claim 1, characterized in that, The first pixel electrode includes a first electrode body and a first connecting electrode, and the second pixel electrode includes a second electrode body and a second connecting electrode. The first electrode body and the second electrode body each include a first end and a second end that are opposite to each other along a second direction. The first connecting electrode is connected to the first end of the first electrode body and a first transistor, and the second connecting electrode is connected to the second end of the second electrode body and a second transistor, respectively. On one side of the second end of the first electrode body, the second connecting electrode extends to the corner of the first pixel unit in the same pixel unit group to form the extension segment; the transition layer is located at the corner of the second pixel unit adjacent to the common signal line and away from the first end of the second electrode body.

4. The display panel according to claim 3, characterized in that, The second end of the first electrode body is provided with a first notch to avoid the extension section; The first end of the second electrode body is provided with a second notch to avoid the transition layer, and the area surrounded by the orthogonal projection of the edge of the first notch on the substrate is the same as the area surrounded by the orthogonal projection of the edge of the second notch on the substrate.

5. The display panel according to claim 1, characterized in that, Along the first direction, a data line is provided between two adjacent pixel unit groups, and the data line is spaced apart from the common signal line, and the data line and the common signal line are arranged on the same layer.

6. The display panel according to claim 1, characterized in that, A light-shielding layer is provided on the side of the common electrode layer away from the substrate. The orthographic projection of the edges of the common signal line, the thin film transistor, the extension segment, the transition layer, and the via onto the substrate is all located within the orthographic projection range of the light-shielding layer onto the substrate.

7. The display panel according to claim 6, characterized in that, The light-shielding layer includes a first pattern corresponding to the extension segment and a second pattern corresponding to the transition layer and the via. The first pattern and the second pattern have the same orthographic projection area on the substrate, and the first pattern and the second pattern have equal orthographic projection areas and the same outline on the substrate.

8. The display panel according to claim 1, characterized in that, Along the second direction, a via is provided between any one of the two transition layers corresponding to each pair of adjacent pixel unit groups and the common electrode layer.

9. The display panel according to claim 1, characterized in that, The transition layer includes a first segment and a second segment. The first segment is parallel to the common signal line. The orthographic projection of the first segment onto the substrate partially overlaps with the orthographic projection of the common signal line onto the substrate. The second segment has an angle with the first segment. The orthographic projection of the edge of the via onto the substrate overlaps with the orthographic projection of the first segment and the second segment onto the substrate at the included angle.

10. The display panel according to claim 6, characterized in that, The display panel has a display area, and the display panel includes a color filter substrate opposite to the array substrate; In the display area, the color filter substrate includes a plurality of pixel matrices arranged in an array, each pixel matrix includes a plurality of pixel unit groups, and each pixel matrix is ​​provided with an array of support pillars, the support pillars including a reference support pillar, at least one first main support pillar and a plurality of first auxiliary support pillars; The reference support column is located at a first preset position in the pixel matrix, the first main support column is located at a second preset position in the pixel matrix, and the first auxiliary support column is located at a third preset position in the pixel matrix. The orthographic projections of the reference support pillar, the first main support pillar, and the first auxiliary support pillar onto the substrate are located within the orthographic projection range of the light-shielding layer onto the substrate. The orthographic projection shape of the reference support column on the substrate is different from the orthographic projection shapes of the first main support column and the first auxiliary support column on the substrate.

11. The display panel according to claim 10, characterized in that, The reference support column and the first auxiliary support column have a first height along a direction perpendicular to the color filter substrate; the first main support column has a second height along a direction perpendicular to the color filter substrate, and the second height is greater than the first height.

12. The display panel according to claim 10, characterized in that, The display panel surrounds a non-display area of ​​the display area, the non-display area including a first non-display area located on both sides of the display area along the first direction, and a second non-display area located on both sides of the display area along the second direction; In the first non-display area, the substrate is stacked with a first support layer, a second support layer and a third support layer facing the color filter substrate; a second auxiliary support pillar is provided on one side of the color filter substrate facing the substrate, the second auxiliary support pillar is positioned corresponding to the third support layer, and there is a gap between the second auxiliary support pillar and the third support layer; In the second non-display area, the first support layer and the third support layer are stacked on the side of the substrate facing the color filter substrate; a second main support pillar is provided on the side of the color filter substrate facing the substrate, the second main support pillar is positioned corresponding to the third support layer, and the side of the second main support pillar that is close to the third support layer abuts against it.

13. The display panel according to claim 12, characterized in that, Both the first transistor and the second transistor include a gate, an active layer, and a first electrode layer; the first support layer, the second support layer, and the third support layer are respectively disposed in the same layer as the gate, the active layer, and the first electrode layer.

14. The display panel according to claim 12, characterized in that, The second auxiliary support column includes a plurality of first strip support columns and a plurality of first point support columns. The plurality of first strip support columns and the plurality of first point support columns are arranged side by side along the second direction, and each first strip support column extends along the second direction. The second main support column includes a plurality of second strip support columns and a plurality of second point support columns. The plurality of second strip support columns and the plurality of second point support columns are arranged side by side along a first direction, and each second strip support column extends along the first direction.

15. The display panel according to claim 14, characterized in that, Along a direction away from the display area, the first dot-shaped support column and the first strip-shaped support column are spaced apart; the second dot-shaped support column and the second strip-shaped support column are spaced apart.

16. The display panel according to claim 14, characterized in that, The second auxiliary support column includes a plurality of first point support columns, and the array of the first point support columns is disposed in the first non-display area; the second main support column includes a plurality of second point support columns, and the array of the second point support columns is disposed in the second non-display area.

17. A display device, characterized in that, Includes the display panel as described in any one of claims 1-16.

Images