Display panel, preparation method thereof and display device

Abstract

The application provides a display panel, a preparation method thereof and a display device. The display panel comprises a substrate, a display area and a non-display area; a first transistor group comprising a first transistor structure is located in the non-display area, the first transistor structure comprises a first gate electrode, a first active layer, a first electrode layer, a second active layer and a second gate electrode which are arranged away from the substrate, and the first electrode layer is connected with a first gate line and a second gate line; a second transistor group is located in the display area and comprises a second transistor structure and a third transistor structure which are arranged side by side, the second transistor structure comprises a third gate electrode, a third active layer and a second electrode layer which are arranged away from the substrate; the third transistor structure comprises a third electrode layer, a fourth active layer and a fourth gate electrode which are arranged away from the substrate; the first gate electrode and the third gate electrode are arranged in the same layer as the first gate line, the third gate electrode is connected with the first gate line, the second gate electrode and the fourth gate electrode are arranged in the same layer as the second gate line, and the fourth gate electrode is connected with the second gate line.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a display panel, a method for manufacturing the same, and a display device. Background Technology

[0002] In liquid crystal displays (LCDs), as resolution and refresh rate increase, pixel charging time is drastically compressed, while the single-gateline driving architecture severely restricts the improvement of resolution and refresh rate.

[0003] Multi-Gate Driving technology emerged, the core of which is to divide one gate line per row into multiple independently driven gate lines, such as two gate lines (Dual Gate), four gate lines (Quad Gate), etc., with each gate line controlling the corresponding pixel unit in one row.

[0004] However, multi-gateline driving leads to a significant increase in the layout area of ​​the array substrate row driving thin film transistors (GOA TFTs) and capacitors located in the non-display area, resulting in a larger bezel of the display panel. At the same time, the complexity of the GOA circuit in the display area increases significantly, and the parallel arrangement of multiple gatelines may cause crosstalk or compress the pixel aperture ratio. Summary of the Invention

[0005] The purpose of this application is to provide a display panel, its manufacturing method, and a display device to solve the problems of large bezel area occupied by GOA TFTs and gate lines squeezing pixel openings. The specific technical solution is as follows:

[0006] A first aspect of this application provides a display panel including a substrate having a display area and a non-display area surrounding the display area;

[0007] The first transistor group includes at least one first transistor structure located in the non-display area. The first transistor structure includes a first gate, a first active layer, a first electrode layer, a second active layer, and a second gate disposed away from the substrate. The first electrode layer is connected to a first gate line and a second gate line.

[0008] At least one second transistor group is located in the display area, including a second transistor structure and a third transistor structure. The second transistor structure includes a third gate, a third active layer, and a second electrode layer disposed away from the substrate. The third transistor structure is disposed in parallel with the second transistor structure and includes a third electrode layer, a fourth active layer, and a fourth gate disposed away from the substrate.

[0009] The first gate and the third gate are disposed on the same layer as the first gate line, and one third gate is connected to at least one first gate line. The second gate and the fourth gate are disposed on the same layer as the second gate line, and one fourth gate is connected to at least one second gate line.

[0010] In some embodiments, in the non-display area, a first capacitor and a second capacitor are arranged in parallel with the first transistor structure. The first capacitor includes a first metal layer and a second metal layer disposed away from the substrate. The second capacitor includes a second metal layer and a third metal layer disposed away from the substrate. The second metal layer is connected to the first electrode layer.

[0011] The first metal layer is disposed on the same layer as the first gate, the second metal layer is disposed on the same layer as the first electrode layer, and the third metal layer is disposed on the same layer as the second gate; a first via is provided between the first metal layer and the third metal layer, and a first transition layer is provided in the first via, and the first transition layer is connected to the first metal layer and the third metal layer respectively.

[0012] In some embodiments, in the display area, the substrate is provided with an array of pixel units;

[0013] Along the first direction, at least one first gate line and at least one second gate line are provided between adjacent pixel unit groups, and the second transistor structure and the third transistor structure are respectively located between adjacent pixel unit groups; along the second direction, the pixel unit group includes adjacent first pixel units and second pixel units, and the second transistor structure and the third transistor structure correspond to the first pixel unit and the second pixel unit respectively; the first direction and the second direction intersect.

[0014] In some embodiments, one first transistor group corresponds to a row of pixel unit groups arranged along the second direction and the second transistor group.

[0015] In some embodiments, the second transistor structure and the third transistor structure are spaced apart along the second direction.

[0016] In some embodiments, the first active layer and the third active layer are disposed on the same layer; the first electrode layer, the second electrode layer and the third electrode layer are disposed on the same layer; the second active layer and the fourth active layer are disposed on the same layer; a first interlayer dielectric layer is provided between the first electrode layer and the second active layer, and the first interlayer dielectric layer extends from the non-display area to the display area.

[0017] In some embodiments, the first transistor structure includes a second transition layer, a second via is provided between the second active layer and the first electrode layer, the second transition layer is located in the second via, and the second transition layer is connected to the first electrode layer and the second active layer respectively.

[0018] The third transistor structure includes a third transition layer, a third via between the fourth active layer and the third electrode layer, the third transition layer being located within the third via, and the third transition layer being connected to the third electrode layer and the fourth active layer respectively.

[0019] In some embodiments, the second transition layer is edge-connected to the second active layer;

[0020] The third transition layer is connected to the edge of the fourth active layer.

[0021] In some embodiments, the second transition layer and the third transition layer are disposed on the same layer as the second gate and the fourth gate.

[0022] In some embodiments, a second interlayer dielectric layer and a planarization layer are sequentially provided on the side of the fourth gate away from the substrate, and the second interlayer dielectric layer and the planarization layer extend from the display area to the non-display area;

[0023] In the display area, a common electrode layer is provided on the side of the planarization layer away from the substrate.

[0024] In some embodiments, a passivation layer is provided on the side of the planarization layer away from the substrate.

[0025] The first pixel unit is provided with a first pixel electrode, which is located on the side of the passivation layer away from the substrate. A fourth via is provided between the first pixel electrode and the second electrode layer. A fourth transition layer is provided in the fourth via, and the fourth transition layer is connected to the first pixel electrode and the second electrode layer respectively.

[0026] The second pixel unit is provided with a second pixel electrode, which is located on the side of the passivation layer away from the substrate. A fifth via is provided between the second pixel electrode and the third transition layer. A fifth transition layer is provided in the fifth via, and the fifth transition layer is connected to the second pixel electrode and the third transition layer respectively.

[0027] In some embodiments, the orthographic projection of the first pixel electrode onto the substrate at least partially overlaps with the orthographic projection of the common electrode layer onto the substrate.

[0028] The orthographic projection of the second pixel electrode onto the substrate at least partially overlaps with the orthographic projection of the common electrode layer onto the substrate.

[0029] A second aspect of this application provides a method for manufacturing a display panel, applicable to the display panel described in any one of the first aspects, comprising:

[0030] A substrate is provided, the substrate having a display area and a non-display area surrounding the display area;

[0031] In the non-display area, a first transistor group is fabricated, including at least one first transistor structure. The first transistor structure includes a first gate, a first active layer, a first electrode layer, a second active layer, and a second gate disposed away from the substrate. The first electrode layer is connected to a first gate line and a second gate line.

[0032] In the display area, at least one second transistor group is fabricated. The second transistor group includes a second transistor structure and a third transistor structure. The second transistor structure includes a third gate, a third active layer, and a second electrode layer disposed away from the substrate. The third transistor structure is disposed in parallel with the second transistor structure and includes a third electrode layer, a fourth active layer, and a fourth gate disposed away from the substrate.

[0033] The first gate and the third gate are disposed on the same layer as the first gate line, and one third gate is connected to at least one first gate line. The second gate and the fourth gate are disposed on the same layer as the second gate line, and one fourth gate is connected to at least one second gate line.

[0034] In some embodiments, a second insulating layer is provided between the second gate and the second active layer. The second insulating layer extends from the non-display area to the display area. The second insulating layer is located between the second gate and the second active layer, and between the fourth gate and the fourth active layer. The second insulating layer is patterned to form a second gate insulating layer and a fourth gate insulating layer, respectively.

[0035] The orthographic projection of the second gate onto the substrate is located within the orthographic projection range of the second gate insulating layer onto the substrate, and the orthographic projection of the fourth gate insulating layer onto the substrate is located within the orthographic projection range of the fourth gate onto the substrate.

[0036] In some embodiments, a second insulating layer is provided between the second gate and the second active layer, the second insulating layer extending from the non-display area to the display area, the second insulating layer being located between the second gate and the second active layer, and between the fourth gate and the fourth active layer, and the first active layer, the second active layer, the third active layer and the fourth active layer being conductive on the side of the second insulating layer away from the substrate.

[0037] A third aspect of this application provides a display device including the display panel described in any of the first aspects.

[0038] Beneficial effects of the embodiments in this application:

[0039] The display panel and its manufacturing method and display device provided in the embodiments of this application include at least one first transistor structure in the first transistor group set in the non-display area. The first gate in each first transistor structure serves as the bottom gate and forms an independent GOA TFT with the first active layer and the first electrode layer. The second gate serves as the top gate and forms an independent GOA TFT with the first electrode layer and the second active layer. The two independent TFTs are stacked along the direction away from the substrate, which reduces the space occupied by a single TFT in the non-display area along the plane of the substrate, which is beneficial to improving the narrow bezel of the display panel.

[0040] Meanwhile, each first transistor structure has a first gate line and a second gate line connected to its first electrode layer. The first gate, the first gate line and the third gate are arranged on the same layer, and the first gate line is connected to the third gate. The second gate, the second gate line and the fourth gate are arranged on the same layer, and the second gate line is connected to the fourth gate. The first gate line and the second gate line are located on different layers, which reduces the number of first gate lines and second gate lines arranged on the same layer in multi-gate line driving. This helps to reduce the planar space occupied by multiple first gate lines and multiple second gate lines arranged on the same layer, reduce the process difficulty, increase the pixel aperture ratio, and improve the display brightness of the display panel.

[0041] Of course, implementing any product or method of this application does not necessarily require achieving all of the advantages described above at the same time. Attached Figure Description

[0042] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other embodiments can be obtained based on these drawings.

[0043] Figure 1 Here are schematic diagrams of the GOA TFT in some embodiments;

[0044] Figure 2 for Figure 1 Enlarged schematic diagram of the first transistor group arrangement;

[0045] Figure 3 for Figure 1 Schematic diagram of the grid line arrangement in the central display area;

[0046] Figure 4 for Figure 1Schematic diagram of the grid lines and pixel openings in the central display area;

[0047] Figure 5 This is a cross-sectional view of the display panel in an embodiment of this application;

[0048] Figure 6 This is a schematic diagram of the first transistor group arrangement in an embodiment of this application;

[0049] Figure 7 This is a schematic diagram of the arrangement of the first and second gate lines in the display area in an embodiment of this application;

[0050] Figures 8a-8f This is a schematic diagram of a display panel manufacturing process in an embodiment of this application;

[0051] Figures 9a-9b This is a schematic diagram of another display panel manufacturing process in an embodiment of this application.

[0052] The reference numerals in the attached figures are as follows: Gate line 1, GOA TFT 2, Pixel aperture 3, Display area AA, Non-display area BB, Substrate 11, First transistor group 12, First transistor structure 13, Second transistor structure 14, Third transistor structure 15, First gate 21, First active layer 22, First electrode layer 23, First source 231, First drain 232, Second active layer 24, Second gate 25, Third gate 31, Third active layer 32, Second electrode layer 33, Second source 331, Second drain 332, First gate line 34, Second gate line 35, Third electrode layer 41, Third source 411, Third drain 412, Fourth active layer 42, Fourth gate 43, First Metal layer 51, second metal layer 52, third metal layer 53, first via 54, first transition layer 55, first pixel unit 61, second pixel unit 62, first pixel electrode 63, second pixel electrode 64, common electrode layer 65, first direction Y, second direction X, first interlayer dielectric layer 71, second interlayer dielectric layer 72, planarization layer 73, passivation layer 74, first insulating layer 75, second insulating layer 76, second gate insulating layer 77, fourth gate insulating layer 78, second transition layer 81, second via 82, third transition layer 83, third via 84, fourth transition layer 85, fourth via 86, fifth transition layer 87, fifth via 88. Detailed Implementation

[0053] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art based on this application are within the scope of protection of this application.

[0054] refer to Figure 1, Figure 2 As shown, in multi-gateline driven products, especially in the design of laptops and televisions, the increase in the number of gate lines 1 in the display area will lead to a corresponding increase in the number of GOA TFTs 2 and capacitors responsible for the gate output signal (Gout) of each gate line 1 in the non-display area. For example... Figure 1 , Figure 3 and Figure 4 The four gate lines 1 are driven, and four GOA TFTs 2 and capacitors are arranged in parallel accordingly, such as Figure 1 , Figure 2 As shown, in order to ensure the output effect of each gate line 1, the size of GOA TFT2 is usually designed to be relatively large, which together with the capacitor occupies a large area of ​​the non-display area (bezel), resulting in a large bezel of the display panel.

[0055] In addition, for multi-gateline driving structures, due to the process limitations of the spacing between metal layers, the larger the number of gate lines 1 in the multi-gateline driving structure, the greater the compression of the pixel aperture 3, that is, the smaller the pixel aperture ratio, which affects the display effect of the display panel, specifically manifested as reduced display brightness. (See reference...) Figure 4 As shown, four gate lines 1 are driven. In order to maximize the aperture ratio of the pixels, the four gate lines adopt a zigzag routing method. Compared with straight routing, the zigzag routing increases the length of gate line 1, which further increases the resistance and power consumption of gate line 1.

[0056] Based on this, refer to Figure 5 , Figure 6 and Figure 7As shown, this application embodiment provides a display panel, including a substrate 11, the substrate 11 having a display area AA and a non-display area BB surrounding the display area AA; a first transistor group 12, including at least one first transistor structure 13, located in the non-display area BB, the first transistor structure 13 including a first gate 21, a first active layer 22, a first electrode layer 23, a second active layer 24 and a second gate 25 disposed away from the substrate 11, the first electrode layer 23 being connected to a first gate line 34 and a second gate line 35; at least one second transistor group, located in the display area AA, including a second transistor structure 14. The third transistor structure 15 and the second transistor structure 14 include a third gate 31, a third active layer 32 and a second electrode layer 33 disposed away from the substrate 11. The third transistor structure 15 and the second transistor structure 14 are arranged in parallel and include a third electrode layer 41, a fourth active layer 42 and a fourth gate 43 disposed away from the substrate 11. The first gate 21, the third gate 31 and the first gate line 34 are disposed on the same layer. One third gate 31 is connected to at least one first gate line 34. The second gate 25, the fourth gate 43 and the second gate line 35 are disposed on the same layer. One fourth gate 43 is connected to at least one second gate line 35.

[0057] In an exemplary embodiment, the substrate 11 can be a rigid substrate. This rigid substrate can be, for example, a glass substrate such as PMMA (Polymethylmethacrylate). The substrate 11 can also be a flexible substrate. For example, this flexible substrate can be a PET (Polyethylene terephthalate), PI (Polyimide), or PEN (Polyethylene naphthalate dimethyl acid glycol ester) substrate.

[0058] In an exemplary embodiment, the number of first transistor structures 13 is the same as the number of second transistor groups. For example, one first transistor structure 13 corresponds to one second transistor group, and two second transistor structures 14 correspond to two second transistor groups. Each second transistor group includes a second transistor structure 14 and a third transistor structure 15.

[0059] In an exemplary embodiment, at least one first transistor structure 13 is arranged side by side along the plane of the substrate 11.

[0060] In an exemplary embodiment, the first electrode layer 23 includes a first source 231 and a first drain 232, the second electrode layer 33 includes a second source 331 and a second drain 332, and the third electrode layer 41 includes a third source 411 and a third drain 412.

[0061] In an exemplary embodiment, in the first transistor structure 13, the first gate 21, the first active layer 22 and the first electrode layer 23 form a thin-film transistor, and the second gate 25, the second active layer 24 and the first electrode layer 23 form another thin-film transistor.

[0062] In an exemplary embodiment, the first transistor structure 13 is a GOA TFT, which provides gate output signals to the second transistor structure 14 through the first gate line 34 and the second gate line 35, respectively. That is, a first transistor structure 13 can drive the corresponding second transistor structure 14 or the corresponding third transistor structure 15 independently.

[0063] In an exemplary embodiment, the second transistor structure 14 and the third transistor structure 15 are pixel transistor structures, respectively.

[0064] In this embodiment, the first transistor group 12 disposed in the non-display area BB includes at least one first transistor structure 13. The first gate 21 in each first transistor structure 13 serves as the bottom gate and forms an independent GOA TFT with the first active layer 22 and the first electrode layer 23. The second gate 25 serves as the top gate and forms an independent GOA TFT with the first electrode layer 23 and the second active layer 24. The two independent TFTs are stacked along the direction away from the substrate 11, which reduces the space occupied by a single TFT in the non-display area BB along the plane direction of the substrate 11, which is beneficial to improving the narrow bezel of the display panel.

[0065] Meanwhile, each first transistor structure 13 has a first gate line 34 and a second gate line 35 connected to its first electrode layer 23. The first gate 21, the first gate line 34 and the third gate 31 are arranged on the same layer and the first gate line 34 is connected to the third gate 31. The second gate 25, the second gate line 35 and the fourth gate 43 are arranged on the same layer and the second gate line 35 is connected to the fourth gate 43. The first gate line 34 and the second gate line 35 are located on different layers, which reduces the number of first gate lines 34 and second gate lines 35 arranged on the same layer in multi-gate line driving. This helps to reduce the planar space occupied by multiple first gate lines 34 and multiple second gate lines 35 arranged on the same layer, reduce the process difficulty, increase the pixel aperture ratio, and improve the display brightness of the display panel.

[0066] In addition, the first gate 21 and the third gate 31 are disposed on the same layer, and the second gate 25 and the fourth gate 43 are disposed on the same layer. The first gate 21 is formed by patterning the metal layer while the third gate 31 is also formed, and the second gate 25 is formed by patterning the metal layer while the fourth gate 43 is also formed. This reduces the process steps of separately fabricating the second gate 25 and the third gate 31, and improves the fabrication efficiency of the display panel.

[0067] When the first transistor structure 13 is greater than one, reference Figure 6 and Figure 7 As shown, there are two first transistor structures 13, and correspondingly two second transistor groups, such as two second transistor structures 14 and two third transistor structures 15. The third gate 31 of one second transistor structure 14 is connected to one first transistor structure 13 through a first gate line 34, and the third gate 31 of the other second transistor structure 14 is connected to the other first transistor structure 13 through a first gate line 34. The connection between the fourth gate 43 and the second gate line 35 is similar, and will not be described again here.

[0068] In some embodiments, a first capacitor and a second capacitor are arranged in parallel with the first transistor structure 13. The first capacitor includes a first metal layer 51 and a second metal layer 52 disposed away from the substrate 11. The second capacitor includes a second metal layer 52 and a third metal layer 53 disposed away from the substrate 11. The second metal layer 52 is connected to the first electrode layer 23. The first metal layer 51 is disposed in the same layer as the first gate 21, the second metal layer 52 is disposed in the same layer as the first electrode layer 23, and the third metal layer 53 is disposed in the same layer as the second gate 25. A first via 54 is provided between the first metal layer 51 and the third metal layer 53. A first transition layer 55 is provided in the first via 54. The first transition layer 55 is connected to the first metal layer 51 and the third metal layer 53 respectively.

[0069] In an exemplary embodiment, the first capacitor and the second capacitor share the second metal layer 52.

[0070] In an exemplary embodiment, the orthographic projections of the first metal layer 51 and the third metal layer 53 onto the substrate 11 at least partially overlap, and the orthographic projection of the second metal layer 52 onto the substrate 11 is located within the orthographic projection range of the first metal layer 51 and the third metal layer 53 onto the substrate 11.

[0071] In an exemplary embodiment, the first metal layer 51 and the first gate 21 are made of the same material, the second metal layer 52 and the first electrode layer 23 are made of the same material, and the third metal layer 53 and the second gate 25 are made of the same material.

[0072] In this embodiment, the first metal layer 51 and the third metal layer 53 are connected by the first transition layer 55, and the second metal layer 52 is connected to the second electrode layer 33, so that the two GOA TFTs in the first transistor structure 13 correspond to two capacitors, namely the first capacitor and the second capacitor. The second electrode layer 33 is connected to the second metal layer 52 to charge the first capacitor and the second capacitor. When the first transistor structure 13 is turned on, the first capacitor and the second capacitor discharge, which prolongs the potential holding time in the second transistor structure 14 or the third transistor structure 15, effectively avoiding attenuation during the scanning signal transmission, which would cause uneven charging of pixel units, brightness differences, and a decrease in response speed. Moreover, the first metal layer 51, the second metal layer 52, and the third metal layer 53 are arranged in a direction away from the substrate 11, that is, the first capacitor and the second capacitor are stacked in a direction away from the substrate 11, which effectively reduces the space occupied by the non-display area BB, which is beneficial to achieving a narrow bezel of the display panel.

[0073] Simultaneously, the first metal layer 51 is disposed on the same layer as the first gate 21, the second metal layer 52 is disposed on the same layer as the first electrode layer 23, and the third metal layer 53 is disposed on the same layer as the second gate 25. While the metal layers are patterned to form the first gate 21, the first electrode layer 23, and the second gate 25, the first metal layer 51, the second metal layer 52, and the third metal layer 53 are formed respectively. This satisfies the requirements for the fabrication of the first capacitor and the second capacitor, while reducing the number of process steps and improving the fabrication efficiency of the display panel.

[0074] In some embodiments, the substrate 11 is provided with an array of pixel unit groups (not shown in the figure). Along the first direction Y, at least one first gate line 34 and at least one second gate line 35 are provided between adjacent pixel unit groups. The second transistor structure 14 and the third transistor structure 15 are respectively located between adjacent pixel unit groups. Along the second direction X, the pixel unit group includes adjacent first pixel unit 61 and second pixel unit 62. The second transistor structure 14 and the third transistor structure 15 correspond to the first pixel unit 61 and the second pixel unit 62 respectively. The first direction Y and the second direction X intersect.

[0075] In an exemplary embodiment, the first direction Y is the column direction of the pixel unit group, and the second direction X is the row direction of the pixel unit group.

[0076] In an exemplary embodiment, the number of first gate lines 34 and second gate lines 35 is related to the number of first transistor structures 13. For example, if there is one first transistor structure 13, there is one first gate line 34 and one second gate line 35. If there are two first transistor structures 13, there can be at least one first gate line 34 and at least one second gate line 35.

[0077] In this embodiment, the second transistor structure 14 and the third transistor structure 15 correspond to the first pixel unit 61 and the second pixel unit 62, respectively, so that the first gate line 34 and the second gate line 35 located in different layers drive different pixel units, and the number of pixel units corresponding to each first gate line 34 and each second gate line 35 is uniform, which is beneficial to the average response speed and brightness of the first pixel unit 61 and the second pixel unit 62.

[0078] In an exemplary implementation, reference Figure 6 and Figure 7 As shown, two first transistor groups 12 are respectively connected to two first gate lines 34 and two second gate lines 35. In two adjacent pixel unit groups along the second direction X, one first gate line 34 is connected to the third gate 31 of the second transistor structure 14 in one pixel unit group, and the other first gate line 34 is connected to the third gate 31 of the second transistor structure 14 in the other pixel unit group. The second gate line 35 is connected in the same way, which will not be described in detail here.

[0079] In some embodiments, a first transistor group 12 corresponds to a row of pixel units arranged along the second direction X and a second transistor group.

[0080] In an exemplary embodiment, the first transistor group 12 is located on one side of the display area AA along the first direction Y.

[0081] In this embodiment, a first transistor group 12 acts as a group of GOA TFTs to drive the second transistor group corresponding to a row (row) of pixel units.

[0082] In some embodiments, the second transistor structure 14 and the third transistor structure 15 are spaced apart along the second direction X.

[0083] In an exemplary embodiment, the second transistor structure 14 is denoted as A and the third transistor structure 15 is denoted as B. Then, along the second direction X, the second transistor structure 14 and the third transistor structure 15 are arranged in the pattern ABABAB...

[0084] In this embodiment, the second transistor structure 14 and the third transistor structure 15 are spaced apart along the second direction X. Correspondingly, the first pixel unit 61 and the second pixel unit 62 are spaced apart along the second direction X. This facilitates the uniform arrangement of the second transistor structure 14 and the third transistor structure 15 on the array substrate and reduces the processing difficulty of the array substrate.

[0085] In some embodiments, the first active layer 22 and the third active layer 32 are disposed on the same layer; the first electrode layer 23, the second electrode layer 33 and the third electrode layer 41 are disposed on the same layer; the second active layer 24 and the fourth active layer 42 are disposed on the same layer; a first interlayer dielectric layer 71 is provided between the first electrode layer 23 and the second active layer 24, and the first interlayer dielectric layer 71 extends from the non-display area BB to the display area AA.

[0086] In an exemplary embodiment, the first interlayer dielectric layer 71 extends from the non-display area BB to the display area AA. Meanwhile, the first gate 21 and the third gate 31 are disposed on the same layer, the second gate 25 and the fourth gate 43 are disposed on the same layer, the first active layer 22 and the third active layer 32 are disposed on the same layer, the first electrode layer 23, the second electrode layer 33 and the third electrode layer 41 are disposed on the same layer, and the second active layer 24 and the fourth active layer 42 are disposed on the same layer. Accordingly, the first interlayer dielectric layer 71 is provided on the side of the second electrode layer 33 away from the substrate 11 and between the third electrode layer 41 and the fourth active layer 42.

[0087] In an exemplary embodiment, the first interlayer dielectric layer 71 effectively insulates the first active layer 22 and the second active layer 24.

[0088] In this embodiment, the first gate 21 and the third gate 31 are disposed on the same layer, the second gate 25 and the fourth gate 43 are disposed on the same layer, and the first active layer 22 and the third active layer 32 are disposed on the same layer; the first electrode layer 23, the second electrode layer 33 and the third electrode layer 41 are disposed on the same layer; the second active layer 24 and the fourth active layer 42 are disposed on the same layer. The first active layer 22 is patterned and the third active layer 32 is patterned and formed simultaneously, the second active layer 24 is patterned and the fourth active layer 42 is patterned and formed simultaneously, and the first electrode layer 23 is patterned and the second electrode layer 33 and the third electrode layer 41 are patterned and formed simultaneously. In other words, while the first transistor structure 13 is being fabricated, the second transistor structure 14 and the third transistor structure 15 are also being fabricated accordingly, reducing the process steps of separately fabricating the third active layer 32, the fourth active layer 42, the second electrode layer 33 and the third electrode layer 41, and improving the fabrication efficiency of the display panel.

[0089] In some embodiments, the first transistor structure 13 includes a second transition layer 81, a second via 82 is provided between the second active layer 24 and the first electrode layer 23, the second transition layer 81 is located within the second via 82, and the second transition layer 81 is connected to the first electrode layer 23 and the second active layer 24 respectively; the third transistor structure 15 includes a third transition layer 83, a third via 84 is provided between the fourth active layer 42 and the third electrode layer 41, the third transition layer 83 is located within the third via 84, and the third transition layer 83 is connected to the third electrode layer 41 and the fourth active layer 42 respectively.

[0090] In an exemplary embodiment, a second gate insulating layer 77 is provided between the second gate 25 and the second active layer 24, and a fourth gate insulating layer 78 is provided between the fourth gate 43 and the third active layer 32. The second gate insulating layer 77 and the fourth gate insulating layer 78 are disposed in the same layer.

[0091] In an exemplary embodiment, the second via 82 penetrates the second gate insulating layer 77 and the first interlayer dielectric layer 71, and the third via 84 penetrates the fourth gate insulating layer 78 and the first interlayer dielectric layer 71.

[0092] In this embodiment, a first interlayer dielectric layer 71 is provided between the first electrode layer 23 and the second active layer 24. The first electrode layer 23 and the second active layer 24 are connected through a second transition layer 81, so that the second gate 25, the second active layer 24 and the first electrode layer 23 constitute a thin-film transistor driving the corresponding second transistor structure 14. Similarly, a first interlayer dielectric layer 71 is provided between the third electrode layer 41 and the third active layer 32. The fourth active layer 42 and the third electrode layer 41 are connected through a third transition layer 83, so that the third gate 31, the fourth active layer 42 and the third electrode constitute a second transistor structure 14 for driving the second pixel unit 62.

[0093] In some embodiments, the second transition layer 81 is edge-connected to the second active layer 24; the third transition layer 83 is edge-connected to the fourth active layer 42.

[0094] In this embodiment, the second active layer 24 is connected to the edge of the second transition layer 81. The second active layer 24 is located between the first electrode layer 23 (first source 231 and first drain 232), which is beneficial for the second active layer 24 to form a channel between the first electrode layers 23. Similarly, the third transition layer 83 is connected to the edge of the fourth active layer 42. The fourth active layer 42 is located between the third electrode layer 41 (third source 411 and third drain 412), which is beneficial for the fourth active layer 42 to form a channel between the third electrode layers 41.

[0095] In some embodiments, the second transition layer 81 and the third transition layer 83 are disposed on the same layer as the second gate 25 and the fourth gate 43.

[0096] In an exemplary embodiment, during the fabrication of the second gate 25 and the fourth gate 43, a metal layer is prepared by magnetron sputtering. The metal layer is deposited into the second opening and the third opening to form the second transition layer 81 and the third transition layer 83, respectively. The metal layer is then patterned to form the second gate 25 and the fourth gate 43, respectively.

[0097] In an exemplary embodiment, the second transition layer 81 is made of the same material as the second gate 25, and the third transition layer 83 is made of the same material as the fourth gate 43.

[0098] In this embodiment, the second transition layer 81 and the third transition layer 83 are disposed on the same layer as the second gate 25 and the fourth gate 43. During the fabrication of the corresponding metal layers of the second gate 25 and the fourth gate 43, the fabrication of the second transition layer 81 and the third transition layer 83 is completed. Then, the metal layers are patterned to form the second gate 25 and the fourth gate 43, reducing the process steps of fabricating the second transition layer 81 and the third transition layer 83 separately and improving the fabrication efficiency of the display panel.

[0099] In some embodiments, a second interlayer dielectric layer 72 and a planarization layer 73 are sequentially provided on the side of the fourth gate 43 away from the substrate 11, and the second interlayer dielectric layer 72 and the planarization layer 73 extend from the display area AA to the non-display area BB; in the display area AA, a common electrode layer 65 is provided on the side of the planarization layer 73 away from the substrate 11.

[0100] In an exemplary embodiment, the material of the second interlayer dielectric layer 72 may be the same as or different from the material of the first interlayer dielectric layer 71.

[0101] In an exemplary embodiment, the second interlayer dielectric layer 72 and the planarization layer 73 extend from the display area AA to the non-display area BB. That is, the first transistor structure 13, the second transistor structure 14 and the third transistor structure 15 are all provided with the second interlayer dielectric layer 72 and the planarization layer 73 on the side away from the substrate 11.

[0102] In this embodiment, the common electrode layer 65 is provided to facilitate the formation of an electric field with the pixel electrode and control the liquid crystal deflection.

[0103] In some embodiments, a passivation layer 74 is provided on the side of the planarization layer 73 away from the substrate 11. A first pixel unit 61 is provided with a first pixel electrode 63, which is located on the side of the passivation layer 74 away from the substrate 11. A fourth via 86 is provided between the first pixel electrode 63 and the second electrode layer 33. A fourth transition layer 85 is provided in the fourth via 86 and is connected to the first pixel electrode 63 and the second electrode layer 33, respectively. A second pixel unit 62 is provided with a second pixel electrode 64, which is located on the side of the passivation layer 74 away from the substrate 11. A fifth via 88 is provided between the second pixel electrode 64 and the third transition layer 83. A fifth transition layer 87 is provided in the fifth via 88 and is connected to the second pixel electrode 64 and the third electrode layer 41, respectively.

[0104] In an exemplary embodiment, the passivation layer 74 is made of an inorganic non-metallic material.

[0105] In an exemplary embodiment, the fourth via 86 penetrates the passivation layer 74, the planarization layer 73, the second interlayer dielectric layer 72, and the first interlayer dielectric layer 71 to the second electrode layer 33. The fifth via 88 penetrates the passivation layer 74, the planarization layer 73, and the second interlayer dielectric layer 72 to the third electrode layer 41.

[0106] In an exemplary embodiment, the first pixel electrode 63 can be connected to the second drain 332 through the fourth transition layer 85, or to the second source 331 through the fourth transition layer 85. The second pixel electrode 64 can be connected to the third drain 412 through the third transition layer 83 and the fifth transition layer 87, or to the third source 411 through the fifth transition layer 87.

[0107] In this embodiment, the fourth transition layer 85 is connected to the first pixel electrode 63 and the second electrode layer 33 respectively, so that the first transistor structure 13 drives the second transistor structure 14 corresponding to the first pixel unit 61 through the first gate line 34. Similarly, the fifth transition layer 87 is connected to the second pixel electrode 64 and the third transition layer 83 respectively, that is, the second pixel electrode 64 is connected to the third electrode layer 41, so that the first transistor structure 13 drives the third transistor structure 15 corresponding to the second pixel unit 62 through the second gate line 35. The first pixel electrode 63 and the second pixel electrode 64 generate an electric field with the common electrode layer 65 respectively, driving the deflection of the liquid crystal. In addition, the fifth transition layer 87 is connected to the second pixel electrode 64 and the third transition layer 83 respectively, reducing the depth of the fifth via 88, which is beneficial to simplifying the process flow of the display panel and improving the yield of the display panel.

[0108] In some embodiments, the orthographic projection of the first pixel electrode 63 onto the substrate 11 at least partially overlaps with the orthographic projection of the common electrode layer 65 onto the substrate 11; the orthographic projection of the second pixel electrode 64 onto the substrate 11 at least partially overlaps with the orthographic projection of the common electrode layer 65 onto the substrate 11.

[0109] In this embodiment, the orthographic projection of the first pixel electrode 63 on the substrate 11 at least partially overlaps with the orthographic projection of the common electrode layer 65 on the substrate 11; the orthographic projection of the second pixel electrode 64 on the substrate 11 at least partially overlaps with the orthographic projection of the common electrode layer 65 on the substrate 11, so that an electric field is effectively formed between the first pixel electrode 63 and the second pixel electrode 64 and the common electrode layer 65 respectively, thereby controlling the deflection of the liquid crystal.

[0110] It should be noted that the display panel structure provided in this application is not limited to liquid crystal display panels (LCDs). Any display panel integrating a GOA driving circuit and utilizing multi-gate line driving technology is applicable. For example, it can be applied to various display products with gate driving integrated circuits, such as organic light-emitting diode (OLED) display panels, quantum dot active-matrix (QLED) display panels, and active-matrix organic light-emitting diode (AMOLED) display panels. Those skilled in the art can adjust the film material in the first transistor group 12 and the second transistor group, as well as the number of first gate lines 34 and second gate lines 35, according to the actual display device type; all of these adjustments fall within the protection scope of this application. Based on the same inventive concept, a second aspect of this application provides a display panel manufacturing method, applicable to the display panel described in any of the above embodiments, comprising:

[0111] S101. A substrate 11 is provided, the substrate 11 having a display area AA and a non-display area BB surrounding the display area AA.

[0112] S102. In the non-display area BB, a first transistor group 12 is fabricated, including at least one first transistor structure 13. The first transistor structure 13 includes a first gate 21, a first active layer 22, a first electrode layer 23, a second active layer 24 and a second gate 25 disposed away from the substrate 11. The first electrode layer 23 is connected to a first gate line 34 and a second gate line 35.

[0113] S103. In the display area AA, at least one second transistor group is fabricated. The second transistor group includes a second transistor structure 14 and a third transistor structure 15 arranged in parallel. The second transistor structure 14 includes a third gate 31, a third active layer 32 and a second electrode layer 33 disposed away from the substrate 11. The third transistor structure 15 is arranged in parallel with the second transistor structure 14 and includes a third electrode layer 41, a fourth active layer 42 and a fourth gate 43 disposed away from the substrate 11. The first gate 21 and the third gate 31 are disposed in the same layer as the first gate line 34, and one third gate 31 is connected to at least one first gate line 34. The second gate 25 and the fourth gate 43 are disposed in the same layer as the second gate line 35, and one fourth gate 43 is connected to at least one second gate line 35.

[0114] Specifically, refer to Figure 8aAs shown, a metal layer is first deposited and patterned on the substrate 11 to form a first gate 21, a first metal layer 51, and a third gate 31, respectively. The first gate 21 and the third gate 31 serve as the bottom gates of the first transistor structure 13 and the second transistor structure 14, respectively. They can also be used as light-shielding pads and metal traces for the first transistor structure 13, the second transistor structure 14, and the third transistor structure 15, for example, the metal layer located at the corresponding position of the third transistor structure 15.

[0115] In an exemplary embodiment, the first gate 21, the first metal layer 51, and the third gate 31 can be any one of the following materials: copper (Cu), aluminum (Al), titanium (Ti), molybdenum (Mo), or an alloy of any one of the following materials: copper, aluminum, titanium, molybdenum. For smaller display panels, the first gate 21, the first metal layer 51, and the third gate 31 can be made of aluminum (Al) or aluminum alloys.

[0116] refer to Figure 8b As shown, an inorganic non-metallic layer is then deposited over the entire surface as a first insulating layer 75. For example, a first gate insulating layer is formed on the side of the first gate 21 away from the substrate 11, and a third gate insulating layer is formed on the side of the second transistor structure 14 away from the substrate 11. Then, oxide is deposited and patterned on the side of the gate insulating layer away from the substrate 11 to form the first active layer 22 of the first transistor structure 13 and the third active layer 32 of the second transistor structure 14, respectively.

[0117] In an exemplary embodiment, the first insulating layer 75 (the first gate insulating layer and the third gate insulating layer) may be made of inorganic insulating materials such as silicon oxide (SiO2), silicon nitride (SiNx) or silicon oxynitride (SiON), or organic insulating materials such as polyimide (PI).

[0118] In an exemplary embodiment, the first active layer 22 and the third active layer 32 may be made of oxide materials with high mobility, such as indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), or indium zinc tin oxide (IZTO).

[0119] refer to Figure 8cAs shown, metal layers are deposited and patterned on the side of the first active layer 22 and the third active layer 32 away from the substrate 11 to form the first electrode layer 23 of the first transistor structure 13, the second metal layer 52, the second electrode layer 33 of the second transistor structure 14, and the third electrode layer 41 of the third transistor structure 15. The first electrode layer 23 includes a first source 231 and a first drain 232, the second electrode layer 33 includes a second source 331 and a second drain 332, and the third electrode layer 41 includes a third source 411 and a third drain 412. An inorganic non-metallic layer is deposited on the side of the first electrode layer 23, the second electrode layer 33, and the third electrode layer 41 away from the substrate 11 as a first interlayer dielectric layer 71.

[0120] In an exemplary embodiment, the first electrode layer 23, the second electrode layer 33, and the third electrode layer 41 can also be made of any one of the following materials: copper (Cu), aluminum (Al), titanium (Ti), molybdenum (Mo), or an alloy of any one of the following materials: copper, aluminum, titanium, molybdenum.

[0121] refer to Figure 8d As shown, an oxide layer is deposited and patterned on the side of the first interlayer dielectric layer 71 away from the substrate 11 to form the second active layer 24 of the first transistor structure 13 and the fourth active layer 42 of the third transistor structure 15, respectively. An inorganic non-metallic layer is deposited on the side of the second active layer 24 and the fourth active layer 42 away from the substrate 11 as the second insulating layer 76.

[0122] In an exemplary embodiment, the second active layer 24 and the fourth active layer 42 can also be made of oxide materials with high mobility, such as indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), or indium zinc tin oxide (IZTO).

[0123] In an exemplary embodiment, the inorganic non-metallic layer can also be made of inorganic insulating materials such as silicon oxide (SiO2), silicon nitride (SiNx) or silicon oxynitride (SiON), or organic insulating materials such as polyimide (PI).

[0124] refer to Figure 8eAs shown, a first via 54 is formed by penetrating the second insulating layer 76, the first interlayer dielectric layer 71, and the first insulating layer 75 to the first metal layer 51. In the non-display area BB, a second via 82 is formed by penetrating the second insulating layer 76 and the first interlayer dielectric layer 71 to the first electrode layer 23. In the display area AA, a third via 84 is formed by penetrating the second insulating layer 76 and the first interlayer dielectric layer 71 to the third electrode layer 41. A metal layer is deposited on the side of the second insulating layer 76 away from the substrate 11. The metal layer is deposited to the first via 54, the second via 82, and the third via 84 to form the first transition layer 55, the second transition layer 81, and the third transition layer 83, respectively. At the same time, the metal layer is patterned to form the second gate 25, the third metal layer 53, and the fourth gate 43.

[0125] Then, using the second gate 25, the first metal layer 51, the fourth gate 43, the second transition layer 81, and the third transition layer 83 as masks, the second insulating layer 76 is etched to form the second gate insulating layer 77 between the second gate 25 and the second active layer 24 in the first transistor structure 13, and the fourth gate insulating layer 78 between the fourth gate 43 and the fourth active layer 42 in the third transistor structure 15. The second active layer 24 and the fourth active layer 42 are then made conductive to achieve better conduction.

[0126] In an exemplary embodiment, the second gate 25, the third metal layer 53, the fourth gate 43, the first transition layer 55, the second transition layer 81, and the third transition layer 83 can be any one of copper (Cu), copper alloy, aluminum (Al), or aluminum alloy.

[0127] refer to Figure 8f As shown, a second interlayer dielectric layer 72 and a planarization layer 73 are fabricated on the side of the second gate 25 away from the substrate 11. A common electrode layer 65 is fabricated in the display area AA. Then, a passivation layer 74 is fabricated on the side of the common electrode layer 65 away from the substrate 11. A fourth via 86 is formed by penetrating the passivation layer 74, the planarization layer 73, the second interlayer dielectric layer 72, and the first interlayer dielectric layer 71 to the second electrode layer 33. A fifth via 88 is formed by penetrating the passivation layer 74, the planarization layer 73, and the second interlayer dielectric layer 72 to the third transition layer 83. A metal layer is deposited on the side of the planarization layer 73 away from the substrate 11. The metal layer is deposited to the fourth via 86 and the fifth via 88 to form the fourth transition layer 85 and the fifth transition layer 87, respectively. At the same time, the metal layer is patterned to form the first pixel electrode 63 and the second pixel electrode 64.

[0128] In some embodiments, reference Figure 8d and Figure 8fAs shown, a second insulating layer 76 is provided between the second gate 25 and the second active layer 24. The second insulating layer 76 extends from the non-display area BB to the display area AA. The second insulating layer 76 is located between the second gate 25 and the second active layer 24, and between the fourth gate 43 and the fourth active layer 42. The second insulating layer 76 is patterned to form a second gate insulating layer 77 and a fourth gate insulating layer 78, respectively. The orthographic projection of the second gate 25 onto the substrate 11 is located within the orthographic projection range of the second gate insulating layer 77 onto the substrate 11, and the orthographic projection of the fourth gate 43 onto the substrate 11 is located within the orthographic projection range of the fourth gate insulating layer 78 onto the substrate 11.

[0129] In this embodiment, after the fabrication of the second gate 25, the third metal layer 53, the fourth gate 43, the first transition layer 55, the second transition layer 81, and the third transition layer 83 are completed, the second insulating layer 76 is patterned, and the excess second insulating layer 76 is removed to form the second gate insulating layer 77 and the fourth gate insulating layer 78.

[0130] In some embodiments, reference Figure 9a , Figure 9b As shown, a second insulating layer 76 is provided between the second gate 25 and the second active layer 24. The second insulating layer 76 extends from the non-display area BB to the display area AA. The second insulating layer 76 is located between the second gate 25 and the second active layer 24, and between the fourth gate 43 and the fourth active layer 42. On the side of the second insulating layer 76 away from the substrate 11, the second active layer 24, the third active layer 32, and the fourth active layer 42 are respectively conductive. Figure 9a As indicated by the middle arrow.

[0131] Understandable, Figure 9a Previous preparation steps and Figure 8e The previous preparation steps are the same. Figure 9b Preparation steps and Figure 8f The preparation steps are the same, so they will not be repeated here.

[0132] In this embodiment, compared to Figure 8e In the embodiment shown, the second insulating layer 76 is retained as a whole without large-area removal. The second active layer 24, the third active layer 32, and the fourth active layer 42 are conductiveized using a doping process, which helps to improve the conductive effect of the first active layer 22, the second active layer 24, the third active layer 32, and the fourth active layer 42, and further enhances the driving capability of the first transistor structure 13, the second transistor structure 14, and the third transistor structure 15.

[0133] Based on the same inventive concept, a third aspect of the embodiments of this application provides a display device, including the display panel described in any of the above embodiments. The specific structure and beneficial effects of the display panel have been described in detail above, and therefore will not be repeated here.

[0134] It should be noted that, in addition to the display panel, the display device also includes other necessary components, such as the color filter substrate and the frame. Those skilled in the art can make corresponding additions according to the specific usage requirements of the display device, which will not be elaborated here.

[0135] Display devices can also be emerging wearable devices, such as virtual reality devices and augmented reality devices. Display devices can also be traditional electronic devices, such as mobile phones, computers, televisions, camcorders, and in-vehicle displays. These will not be listed exhaustively here. In the embodiments of this application, the display device includes a liquid crystal display device, such as a liquid crystal monitor.

[0136] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0137] The various embodiments in this specification are described in a related manner. The same or similar parts between the various embodiments can be referred to each other. Each embodiment focuses on describing the differences from other embodiments.

[0138] The above description is merely a preferred embodiment of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application are included within the scope of protection of this application.

Claims

1. A display panel, characterized by, Includes a substrate having a display area and a non-display area surrounding the display area; The first transistor group includes at least one first transistor structure located in the non-display area. The first transistor structure includes a first gate, a first active layer, a first electrode layer, a second active layer, and a second gate disposed away from the substrate. The first electrode layer is connected to a first gate line and a second gate line. At least one second transistor group is located in the display area, including a second transistor structure and a third transistor structure. The second transistor structure includes a third gate, a third active layer, and a second electrode layer disposed away from the substrate. The third transistor structure is disposed in parallel with the second transistor structure and includes a third electrode layer, a fourth active layer, and a fourth gate disposed away from the substrate. The first gate and the third gate are disposed on the same layer as the first gate line, and one third gate is connected to at least one first gate line. The second gate and the fourth gate are disposed on the same layer as the second gate line, and one fourth gate is connected to at least one second gate line.

2. The display panel of claim 1, wherein, In the non-display area, a first capacitor and a second capacitor are arranged in parallel with the first transistor structure. The first capacitor includes a first metal layer and a second metal layer disposed away from the substrate. The second capacitor includes a second metal layer and a third metal layer disposed away from the substrate. The second metal layer is connected to the first electrode layer. The first metal layer is disposed on the same layer as the first gate, the second metal layer is disposed on the same layer as the first electrode layer, and the third metal layer is disposed on the same layer as the second gate; a first via is provided between the first metal layer and the third metal layer, and a first transition layer is provided in the first via, and the first transition layer is connected to the first metal layer and the third metal layer respectively.

3. The display panel of claim 1, wherein, In the display area, the substrate is provided with an array of pixel units; Along the first direction, at least one first gate line and at least one second gate line are provided between adjacent pixel unit groups, and the second transistor structure and the third transistor structure are respectively located between adjacent pixel unit groups; along the second direction, the pixel unit group includes adjacent first pixel units and second pixel units, and the second transistor structure and the third transistor structure correspond to the first pixel unit and the second pixel unit respectively; the first direction and the second direction intersect.

4. The display panel of claim 3, wherein, One of the first transistor groups corresponds to a row of pixel unit groups arranged along the second direction and the second transistor group.

5. The display panel of claim 3, wherein, Along the second direction, the second transistor structure and the third transistor structure are spaced apart.

6. The display panel according to claim 1, characterized in that, The first active layer and the third active layer are disposed in the same layer; the first electrode layer, the second electrode layer and the third electrode layer are disposed in the same layer; the second active layer and the fourth active layer are disposed in the same layer; a first interlayer dielectric layer is provided between the first electrode layer and the second active layer, and the first interlayer dielectric layer extends from the non-display area to the display area.

7. The display panel according to claim 3, characterized in that, The first transistor structure includes a second transition layer, a second via is provided between the second active layer and the first electrode layer, the second transition layer is located in the second via, and the second transition layer is connected to the first electrode layer and the second active layer respectively; The third transistor structure includes a third transition layer, a third via between the fourth active layer and the third electrode layer, the third transition layer being located within the third via, and the third transition layer being connected to the third electrode layer and the fourth active layer respectively.

8. The display panel according to claim 7, characterized in that, The second transition layer is edge-connected to the second active layer; The third transition layer is connected to the edge of the fourth active layer.

9. The display panel according to claim 7, characterized in that, The second and third transition layers are disposed on the same layer as the second gate and the fourth gate.

10. The display panel according to claim 7, characterized in that, The fourth gate is provided with a second interlayer dielectric layer and a planarization layer on the side away from the substrate, and the second interlayer dielectric layer and the planarization layer extend from the display area to the non-display area; In the display area, a common electrode layer is provided on the side of the planarization layer away from the substrate.

11. The display panel according to claim 10, characterized in that, A passivation layer is provided on the side of the planarization layer away from the substrate. The first pixel unit is provided with a first pixel electrode, which is located on the side of the passivation layer away from the substrate. A fourth via is provided between the first pixel electrode and the second electrode layer. A fourth transition layer is provided in the fourth via, and the fourth transition layer is connected to the first pixel electrode and the second electrode layer respectively. The second pixel unit is provided with a second pixel electrode, which is located on the side of the passivation layer away from the substrate. A fifth via is provided between the second pixel electrode and the third transition layer. A fifth transition layer is provided in the fifth via, and the fifth transition layer is connected to the second pixel electrode and the third transition layer respectively.

12. The display panel according to claim 11, characterized in that, The orthographic projection of the first pixel electrode onto the substrate at least partially overlaps with the orthographic projection of the common electrode layer onto the substrate. The orthographic projection of the second pixel electrode onto the substrate at least partially overlaps with the orthographic projection of the common electrode layer onto the substrate.

13. A method for manufacturing a display panel, characterized in that, Applied to the display panel according to any one of claims 1-12, comprising: A substrate is provided, the substrate having a display area and a non-display area surrounding the display area; In the non-display area, a first transistor group is fabricated, including at least one first transistor structure. The first transistor structure includes a first gate, a first active layer, a first electrode layer, a second active layer, and a second gate disposed away from the substrate. The first electrode layer is connected to a first gate line and a second gate line. In the display area, at least one second transistor group is fabricated. The second transistor group includes a second transistor structure and a third transistor structure. The second transistor structure includes a third gate, a third active layer, and a second electrode layer disposed away from the substrate. The third transistor structure is disposed in parallel with the second transistor structure and includes a third electrode layer, a fourth active layer, and a fourth gate disposed away from the substrate. The first gate and the third gate are disposed on the same layer as the first gate line, and one third gate is connected to at least one first gate line. The second gate and the fourth gate are disposed on the same layer as the second gate line, and one fourth gate is connected to at least one second gate line.

14. The method according to claim 13, characterized in that, A second insulating layer is provided between the second gate and the second active layer. The second insulating layer extends from the non-display area to the display area. The second insulating layer is located between the second gate and the second active layer, and between the fourth gate and the fourth active layer. The second insulating layer is patterned to form a second gate insulating layer and a fourth gate insulating layer, respectively. The orthographic projection of the second gate onto the substrate is located within the orthographic projection range of the second gate insulating layer onto the substrate, and the orthographic projection of the fourth gate insulating layer onto the substrate is located within the orthographic projection range of the fourth gate onto the substrate.

15. The method according to claim 13, characterized in that, A second insulating layer is provided between the second gate and the second active layer. The second insulating layer extends from the non-display area to the display area. The second insulating layer is located between the second gate and the second active layer, and between the fourth gate and the fourth active layer. The first active layer, the second active layer, the third active layer and the fourth active layer are respectively conductive on the side of the second insulating layer away from the substrate.

16. A display device, characterized in that, Includes the display panel as described in any one of claims 1-12.

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