control circuit

Abstract

A control circuit suitable for bridging a host device and a plurality of storage devices is provided. The control circuit includes a bridge controller and a disk array controller. The bridge controller includes an uplink port interface circuit, a downlink port interface circuit, and a routing circuit. The uplink port interface circuit couples the host device and the routing circuit based on a first transmission specification. The downlink port interface circuit couples the routing circuit and the plurality of storage devices based on a second transmission specification. The disk array controller couples the routing circuit and the downlink port interface circuit. The disk array controller accesses the plurality of storage devices through the downlink port interface circuit, thereby improving the performance of data access.

Description

Technical Field

[0001] This invention relates to a control circuit, and more particularly to a control circuit suitable for bridging a host device and multiple storage devices. Background Technology

[0002] Based on various transmission standards, a host can access one or more terminal devices via a bridging circuit. These terminal devices can be, for example, high-speed non-volatile memory (NVMe) devices. These NVMe devices can be arranged into logical arrays to form a redundant array of independent disks (RAID). RAID is also known as a disk array.

[0003] However, current bridging circuits require external devices such as switches or control units to bridge the host and multiple NVMe devices to achieve RAID functionality. Consequently, the host cannot directly access one or more NVMe devices through the bridging circuit, reducing data access efficiency. Summary of the Invention

[0004] This invention provides a control circuit suitable for bridging host devices and multiple storage devices, and can avoid the need for external devices to implement RAID functionality to improve data access efficiency.

[0005] The control circuit of this embodiment includes a bridge controller and a disk array controller. The bridge controller includes an uplink port interface circuit, a downlink port interface circuit, and a routing circuit. The uplink port interface circuit is used to couple a host device and the routing circuit based on a first transmission standard. The downlink port interface circuit is used to couple the routing circuit and multiple storage devices based on a second transmission standard. The disk array controller is coupled to the routing circuit and the downlink port interface circuit. The disk array controller is used to access multiple storage devices through the downlink port interface circuit.

[0006] Based on the above, the control circuit of the embodiment of the present invention integrates the bridge controller and the disk array controller, enabling the host device to access multiple storage devices to achieve RAID function without the need for external devices, thereby improving the efficiency of data access.

[0007] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description

[0008] Figure 1 This is a circuit block diagram of a control circuit according to an embodiment of the present invention;

[0009] Figure 2 This is a circuit block diagram of a control circuit according to another embodiment of the present invention;

[0010] Figure 3 This is a circuit block diagram of a control circuit according to another embodiment of the present invention.

[0011] Explanation of reference numerals in the attached figures

[0012] 100, 300, 500: Control circuit;

[0013] 110, 310, 510: Bridge controllers;

[0014] 111, 511: Routing circuit;

[0015] 112, 512: Uplink port interface circuit;

[0016] 113, 513: Downlink port interface circuit;

[0017] 120, 320, 520: Disk array controllers;

[0018] 201: Connector;

[0019] 210: Main unit;

[0020] 221~22N, 221~224: Storage devices;

[0021] 710: Connector circuit;

[0022] 711: Control adapter;

[0023] 712: Time Management Unit;

[0024] 713: Channel adapter;

[0025] 714: USB adapter;

[0026] 715: PCIe adapter;

[0027] 720: Enhanced ultra-high-speed functional circuit;

[0028] 721: Virtual NVMe Host;

[0029] 722: USB 2.0 device controller;

[0030] 723: USB 3.2 device controller;

[0031] 731: Multiplexer;

[0032] 732: USB 3.2 PCS circuit;

[0033] 733: Multiplexer;

[0034] 741~742: PCIe switch controller;

[0035] 743: PCIe physical layer circuitry;

[0036] P1~P5: Transmission path. Detailed Implementation

[0037] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same component reference numerals are used in the drawings and description to denote the same or similar parts.

[0038] Figure 1 This is a circuit block diagram of a control circuit according to an embodiment of the present invention. (Reference) Figure 1 The control circuit 100 is suitable for bridging the host device 210 and multiple storage devices 211-22N, where N is a positive integer greater than 1. The control circuit 100 can be coupled to the host device 210 based on a first transmission standard and can be coupled to the multiple storage devices 211-22N based on a second transmission standard. The first transmission standard is different from the second transmission standard.

[0039] In this embodiment, the multiple storage devices 211-22N may be, for example, high-speed non-volatile memory (NVMe) devices. These storage devices 211-22N are arranged into a logical array to form a redundant array of independent disks (RAID).

[0040] In this embodiment, the host device 210 can directly access one or more storage devices 211-22N through the control circuit 100 to implement RAID functionality. The host device 210 can be, for example, an electronic device such as a mobile phone, computer, tablet computer, laptop computer, or desktop computer.

[0041] exist Figure 1 In this embodiment, the control circuit 100 includes a bridge controller 110 and a disk array controller (i.e., RAID controller) 120. The bridge controller 110 is coupled to the disk array controller 120.

[0042] In detail, the bridging controller 110 includes a routing circuit 111, an upstream facing port (UFP) interface circuit 112, and a downstream facing port (DFP) interface circuit 113. The upstream facing port interface circuit 112 is used to couple the host device 210 and the routing circuit 111 according to a first transmission standard. The downstream facing port interface circuit 113 is used to couple the routing circuit 111 and a plurality of storage devices 211~22N according to a second transmission standard.

[0043] In other words, routing circuit 111 is used to transmit data conforming to different transmission specifications. For example, routing circuit 111 receives data from host device 210 through uplink port interface circuit 112. The data conforms to a first transmission specification. Routing circuit 111 converts the data into data conforming to a second transmission specification. Routing circuit 111 also outputs data conforming to the second transmission specification to multiple storage devices 211~22N or to disk array controller 120 through downlink port interface circuit 113.

[0044] In this embodiment, the disk array controller 120 and the bridge controller 110 are integrated in the same circuit architecture. That is, the disk array controller 120 is not coupled to the input / output terminals (e.g., downlink port interface circuit 113) of the bridge controller 110 via a transmission line (or transmission interface) as an external component.

[0045] Specifically, the disk array controller 120 is coupled to the routing circuit 111 and the downstream port interface circuit 113. Thus, the disk array controller 120 can access the data output by the routing circuit 111. The data conforms to the second transmission standard. The disk array controller 120 can also access multiple storage devices 211~22N through the downstream port interface circuit 113 to implement RAID functionality.

[0046] It is worth mentioning that by integrating the disk array controller 120 and the bridge controller 110, the control circuit 100 can avoid the need for external switches or control units, allowing the host device 210 to directly access multiple storage devices 211-22N through the control circuit 100 to achieve RAID functionality. In this way, the control circuit 100 can improve the efficiency of data access.

[0047] Figure 2 This is a circuit block diagram of a control circuit according to another embodiment of the present invention. (Reference) Figure 2The control circuit 300 is adapted to bridge the host device 210 and multiple storage devices 221-224, the number of which is merely illustrative. The host device 210 can be coupled to the control circuit 300 via its own connector 201, and can directly access the multiple storage devices 221-224 through the control circuit 300 to implement RAID functionality. The connector 201 can be, for example, a Universal Serial Bus Type-C (USB Type-C) connector.

[0048] In this embodiment, the plurality of storage devices 221-224 may be, for example, NVMe devices. These storage devices 221-224 include at least one solid-state drive (SSD) and at least one hard disk drive (HDD). That is, each storage device 221-224 may be, for example, an SSD or an HDD.

[0049] exist Figure 2 In this embodiment, the control circuit 300 includes a bridge controller 310 and a disk array controller 320. The bridge controller 310 and the disk array controller 320 can be deduced from the relevant description of the control circuit 100.

[0050] In this embodiment, the control circuit 300 uses its uplink port interface circuit (not shown) Figure 2 The device is coupled to host device 210 based on a first transmission specification and is used to transmit data conforming to the first transmission specification. The first transmission specification includes Universal Serial Bus (USB) specifications (e.g., USB4 specification) or Thunderbolt (TBT) specifications (e.g., TBT5 specification).

[0051] In this embodiment, the bridging controller 310 may be, for example, a USB4 bridging controller. Alternatively, the bridging controller 310 may be, for example, a TBT accessory controller compatible with TBT specifications such as TBT3, TBT4, and TBT5.

[0052] In this embodiment, the control circuit 300 also utilizes a downlink port interface circuit (not shown) therein. Figure 2 This allows for the coupling of multiple storage devices 221-224 based on a second transport specification, and is used to transmit data conforming to the second transport specification. The second transport specification includes the High-Speed ​​Peripheral Component Interconnect (PCI Express, PCIe) specification.

[0053] In other words, the first transmission interface between connector 201 and control circuit 300 conforms to the USB4 or TBT specification. The first transmission interface can be, for example, a USB Type-C cable. Furthermore, the second transmission interface between control circuit 300 and each storage device 221-224 conforms to the PCIe specification. The second transmission interface can be, for example, a Serial Advanced Technology Attachment (SATA) interface, a Serial Attached SCSI (SAS) interface, or a Non-Volatile Memory Express (NVMe) interface.

[0054] It should be noted that the bridge controller 310 and the disk array controller 320 are located on the same chip. That is, the bridge controller 310 and the disk array controller 320 are integrated into the same controller. The controller can be implemented, for example, as an integrated circuit. Thus, the control circuit 300 can not only realize data transmission functions compliant with various transmission standards (i.e., USB4 / TBT and PCIe), but also realize RAID functions.

[0055] Furthermore, since the control circuit 300 does not require an external PCIe switch and / or RAID controller to provide RAID functionality, the control circuit 300 can reduce the cost of RAID applications for the host device 210.

[0056] Figure 3 This is a circuit block diagram of a control circuit according to another embodiment of the present invention. (Reference) Figure 3 The control circuit 500 is suitable for bridging the host device 210 and multiple storage devices 221-224. The control circuit 500 includes a bridge controller 510 and a disk array controller 520. The bridge controller 510 includes a routing circuit 511, an uplink port interface circuit 512, and a downlink port interface circuit 513. The routing circuit 511, uplink port interface circuit 512, downlink port interface circuit 513, and disk array controller 520 can be deduced by referring to the relevant descriptions of control circuits 100 and 300.

[0057] In this embodiment, the routing circuit 511 includes an adapter circuit 710 and an Enhanced SuperSpeed ​​function circuit 720. The adapter circuit 710 may be, for example, a device router supporting USB specifications such as USB3 and USB4, and TBT specifications such as TBT3, TBT4, and TBT5. The Enhanced SuperSpeed ​​function circuit 720 may be, for example, a module circuit supporting the USB 3.2 specification to implement the Enhanced SuperSpeed ​​transmission function.

[0058] Specifically, the adapter circuit 710 is coupled to the uplink port interface circuit 512 and the disk array controller 520. The adapter circuit 710 is used to convert data conforming to the USB4, USB3, TBT, or PCIe specifications and to transmit the converted data.

[0059] In detail, the adapter circuit 710 includes a control adapter 711, a time management unit (TMU) 712, a channel adapter 713, a USB adapter 714, and a PCIe adapter 715. The time management unit 712 is coupled to multiple adapters 711 and 713-715. The time management unit 712 is used to synchronize these adapters 711 and 713-715. The control adapter 711 is also coupled to the channel adapter 713, the USB adapter 714, and the PCIe adapter 715. The control adapter 711 is used to control these adapters 713-715.

[0060] In addition, channel adapter 713 is also coupled to upstream port interface circuitry 512. Channel adapter 713 is used to process (including convert) data conforming to the USB4 / TBT specification, compatible USB specifications, or PCIe specifications, and to transmit the processed data. USB adapter 714 is also coupled to enhanced high-speed function circuitry 720 via upstream port interface circuitry 512. USB adapter 714 is used to process data conforming to the USB3 or PCIe specifications, and to transmit the processed data. PCIe adapter 715 is also coupled to disk array controller 520. PCIe adapter 715 is used to process data conforming to the PCIe, USB3, or USB4 / TBT specifications, and to transmit the processed data.

[0061] In this embodiment, the enhanced high-speed function circuit 720 is coupled to the uplink port interface circuit 512, the disk array controller 520, and the downlink port interface circuit 513. The enhanced high-speed function circuit 720 is used to convert data conforming to the USB3 or PCIe specifications and transmit the converted data.

[0062] In detail, the enhanced high-speed function circuitry 720 includes a Virtual High-Speed ​​Non-Volatile Memory (NVM Express, NVMe) host 721, a USB 2.0 device controller 722, and a USB 3.2 device controller 723. The Virtual NVMe host 721 is coupled to the USB 2.0 device controller 722, the USB 3.2 device controller 723, the disk array controller 320, and the downstream port interface circuitry 513. The Virtual NVMe host 721 controls the USB 2.0 device controller 722 and the USB 3.2 device controller 723, and assigns the desired access target among the multiple storage devices 221-224.

[0063] In addition, the USB 2.0 device controller 722 is also coupled to the upstream port interface circuit 512. The USB 2.0 device controller 722 is used to process data conforming to the USB2 or PCIe specification and to transmit the processed data. The USB 3.2 device controller 723 is also coupled to the USB adapter 714 via the upstream port interface circuit 512. The USB 3.2 device controller 723 is used to process data conforming to the USB3 or PCIe specification and to transmit the processed data.

[0064] In this embodiment, the uplink port interface circuit 512 includes a demultiplexer 731, a USB 3.2 Physical Coding Sub-layer (PCS) circuit 732, and a multiplexer 733. The input of the demultiplexer 731 is coupled to connector 201. Multiple outputs of the demultiplexer 731 are coupled to channel adapter 713 and the USB 3.2 PCS circuit 732. The USB 3.2 PCS circuit 732 is also coupled to an input of the multiplexer 733. Another input of the multiplexer 733 is coupled to a USB adapter 714. The output of the multiplexer 733 is coupled to a USB 3.2 device controller 723.

[0065] In RAID applications, the uplink port interface circuit 512 has multiple transmission paths P1 to P4 between the connector 201 and the routing circuit 511. These transmission paths P1 to P4 support USB specifications such as USB3 and USB4, as well as TBT specifications such as TBT3, TBT4, and TBT5.

[0066] In detail, in transmission path P1, the uplink port interface circuit 512 transmits data conforming to the USB4 specification between connector 201 and adapter circuit 710 via the sideband (SB) channel (i.e., SBTX / RX).

[0067] In transmission path P2, the uplink port interface circuit 512 couples connector 201 and channel adapter 713 together via multiplexer 731 to transmit USB 3.2 compliant data between connector 201 and adapter circuit 710. Alternatively, the uplink port interface circuit 512 couples connector 201 and USB 3.2 device controller 723 together via multiplexer 731, USB 3.2 PCS circuit 732, and multiplexer 733. Thus, in transmission path P2, the uplink port interface circuit 512 transmits USB 3.2 compliant data between connector 201 and enhanced ultra-high speed function circuit 720.

[0068] In transmission path P3, the uplink port interface circuit 512 transmits data conforming to the USB2 specification between connector 201 and USB2.0 device controller 722 via the data channel (i.e., D+ / D-).

[0069] In this embodiment, the downlink port interface circuit 513 includes multiple PCIe switch controllers 741-742 and a PCIe physical layer circuit 743. The PCIe switch controller 741 may be, for example, a PCIe uplink switch controller. The PCIe switch controller 742 may be, for example, a PCIe downlink switch controller. These PCIe switch controllers 741-742 are coupled to the disk array controller 520 and the routing circuit 511, and are also coupled to the PCIe physical layer circuit 743.

[0070] In RAID applications, the downlink port interface circuit 513 has multiple transmission paths P4-P5 between the routing circuit 511 and multiple storage devices 221-224. These transmission paths P4-P5 support the PCIe specification.

[0071] In detail, in transmission path P4, the PCIe switch controller 741 processes data compliant with the PCIe specification and transmits the processed data between the virtual NVMe host 721 and the PCIe physical layer circuitry 743. In transmission path P5, the PCIe switch controller 742 processes data compliant with the PCIe specification and transmits the processed data between the PCIe physical layer circuitry 743 and the PCIe adapter 715. Thus, the processed data conforms to the PCIe specification and is accessed by the PCIe physical layer circuitry 743 to multiple storage devices 221-224.

[0072] It should be noted that the disk array controller 520 can be integrated with multiple PCIe switch controllers 741-742 in the same circuit module. This reduces the layout area of ​​the control circuitry 500, thereby lowering production costs.

[0073] In summary, the control circuit of this invention integrates the disk array controller and the bridge controller onto the same chip, thereby eliminating the need for additional external devices in RAID applications and improving data access efficiency. The control circuit also reduces layout area, thus lowering production costs.

[0074] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A control circuit, characterized in that, Suitable for bridging host devices and multiple storage devices, including: A bridging controller includes an uplink port interface circuit, a downlink port interface circuit, and a routing circuit, wherein the uplink port interface circuit is used to couple the host device and the routing circuit according to a first transmission standard, and the downlink port interface circuit is used to couple the routing circuit and the plurality of storage devices according to a second transmission standard; and A disk array controller, coupled to the routing circuit and the downlink port interface circuit, is used to access the plurality of storage devices through the downlink port interface circuit.

2. The control circuit according to claim 1, characterized in that, The bridge controller and the disk array controller are located on the same chip.

3. The control circuit according to claim 1, characterized in that, The first transmission specification includes the Universal Serial Bus (USB) specification or the Thunderbolt (TBT) specification.

4. The control circuit according to claim 1, characterized in that, The second transmission specification includes the PCI Express (PCIe) specification.

5. The control circuit according to claim 1, characterized in that, The downlink port interface circuit includes: Multiple PCIe switch controllers are coupled to the disk array controller and the routing circuitry; and The PCIe physical layer circuit is coupled to the plurality of PCIe switch controllers.

6. The control circuit according to claim 1, characterized in that, The routing circuit includes: The adapter circuit, coupled to the uplink port interface circuit and the disk array controller, is used to convert data conforming to the USB4, USB3, TBT, or PCIe specifications for transmission of the converted data; and An enhanced high-speed function circuit, coupled to the uplink port interface circuit, the disk array controller, and the downlink port interface circuit, is used to convert data conforming to the USB3 or PCIe specifications for transmission of converted data.

7. The control circuit according to claim 6, characterized in that, The adapter circuit includes: Channel adapter, coupled to the uplink port interface circuit; The USB adapter is coupled to the enhanced ultra-high-speed function circuit through the uplink port interface circuit; A PCIe adapter, coupled to the disk array controller; and A control adapter is coupled to the channel adapter, the USB adapter, and the PCIe adapter.

8. The control circuit according to claim 7, characterized in that, The enhanced ultra-high-speed functional circuit includes: USB 2.0 device controller, coupled to the uplink port interface circuit; USB 3.2 device controller, coupled to the USB adapter via the uplink port interface circuit; and A virtual high-speed non-volatile memory (NVM Express, NVMe) host is coupled to the USB 2.0 device controller, the USB 3.2 device controller, the disk array controller, and the downstream port interface circuitry.

9. The control circuit according to claim 8, characterized in that, The uplink port interface circuit includes: USB 3.2 Physical Coding Sub-layer (PCS) circuitry; A multiplexer having an input coupled to the host device, and multiple outputs coupled to the channel adapter and the USB 3.2 PCS circuitry; and A multiplexer having multiple inputs coupled to the USB adapter and the USB 3.2 PCS circuit, and an output of the multiplexer coupled to the USB 2.0 device controller.

10. The control circuit according to claim 1, characterized in that, The plurality of storage devices includes at least one of a solid-state disk (SSD) and at least one hard disk drive (HDD).

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