Electromagnetic attack protection circuit and chip comprising same, electromagnetic attack protection method

Abstract

The application discloses an electromagnetic attack protection circuit, a chip comprising the same and an electromagnetic attack protection method. The electromagnetic attack protection circuit according to the embodiment of the application comprises a coil, a first branch, a second branch and an AND gate. The coil is arranged on one side of a to-be-protected circuit. The first branch is connected with the coil and has a first output end. The second branch is connected with the coil and has a second output end. The input ends of the AND gate are connected with the first output end and the second output end respectively. When the output signal of the output end of the AND gate is inverted, it is indicated that the to-be-protected circuit is subjected to an electromagnetic attack. The electromagnetic attack protection circuit according to the embodiment of the application and the chip comprising the same and the electromagnetic attack protection method can quickly and accurately realize the protection against electromagnetic attack.

Description

Technical Field

[0001] This invention relates to the field of electromagnetic attack protection technology, and in particular to an electromagnetic attack protection circuit, a chip including the circuit, and an electromagnetic attack protection method. Background Technology

[0002] With the rapid development of information technology, the security of chips, as core components of modern electronic devices, has become an increasingly important concern. Electromagnetic attacks targeting chips, as a covert and highly destructive attack method, have gradually become a hot research topic in the field of information security.

[0003] Electromagnetic attacks on chips are a type of fault injection attack, and their core principle is based on electromagnetic induction. Attackers use an electromagnetic injection probe to generate a high-voltage transient electromagnetic field, causing transient induced voltages and currents within the target chip. This alters the voltages of the chip's internal logic gates, leading to timing, data, or functional errors. Attackers can then use these errors to analyze sensitive information within the chip. Because electromagnetic attacks do not require removing the chip package and can be launched from flexible locations, they are difficult to defend against. Currently, there is a lack of reliable and high-performance electromagnetic attack protection solutions.

[0004] Therefore, there is a need for a new electromagnetic attack protection circuit, including the chip therein, and an electromagnetic attack protection method that can overcome the shortcomings of the existing technology. Summary of the Invention

[0005] In view of the above problems, the purpose of this invention is to provide an electromagnetic attack protection circuit and a chip including the circuit, as well as an electromagnetic attack protection method, so as to quickly and accurately achieve electromagnetic attack protection.

[0006] According to one aspect of the present invention, an electromagnetic attack protection circuit is provided, comprising:

[0007] A coil, wherein the coil is disposed on one side of the circuit to be protected;

[0008] The first branch is connected to the coil and has a first output terminal;

[0009] A second branch, connected to the coil, having a second output terminal; and

[0010] An AND gate, wherein the input terminals of the AND gate are respectively connected to the first output terminal and the second output terminal.

[0011] When the output signal of the AND gate flips, it indicates that the circuit to be protected is subjected to an electromagnetic attack.

[0012] Optionally, the first branch includes a second MOSFET, and the second branch includes a third MOSFET;

[0013] The electromagnetic attack protection circuit also includes:

[0014] A first current source provides a first current; one end of the first current source is connected to the first end of the coil.

[0015] A first MOSFET, wherein a first terminal of the first MOSFET is connected to a second terminal of the coil; and a third terminal of the first MOSFET is connected to a second terminal of the coil.

[0016] A second current source provides a second current; one end of the second current source is connected to the first end of the second MOSFET.

[0017] The second terminal of the second MOSFET is connected to the second terminal of the first MOSFET, and the third terminal of the second MOSFET is connected to the second terminal of the coil.

[0018] A third current source provides a third current; one end of the third current source is connected to the first end of the third MOS transistor.

[0019] The second terminal of the third MOS transistor is connected to the second terminal of the first MOS transistor, and the third terminal of the third MOS transistor is connected to the second terminal of the coil; the first terminal of the third MOS transistor is also connected to the second output terminal.

[0020] An inverter, wherein the first terminal of the inverter is connected to the first terminal of the second MOS transistor, and the second terminal of the inverter is connected to the first output terminal.

[0021] Optionally, the size ratio of the first MOSFET, the second MOSFET, and the third MOSFET is a 1:1:1 mirror circuit;

[0022] The second MOS transistor and 1.5 times the first current, and the third MOS transistor and 0.5 times the first current constitute a current comparator.

[0023] Optionally, the electromagnetic attack protection circuit further includes:

[0024] A control unit is connected to the first current source to control the magnitude of the first current.

[0025] Optionally, the coil is arranged around the circuit to be protected, and the circuit to be protected is located inside the coil;

[0026] At least one of the first MOSFET, the second MOSFET, the third MOSFET, the first current source, the second current source, the third current source, the inverter, and the AND gate is located outside the coil.

[0027] Optionally, the electromagnetic attack protection circuit further includes:

[0028] A safety unit is connected to the output terminal of the AND gate. When the output signal at the output terminal of the AND gate undergoes a signal flip, the safety unit performs a safety operation on the circuit to be protected.

[0029] Optionally, the coil includes:

[0030] Coil body; and

[0031] A connector, one end of which is connected to the coil body.

[0032] The coil body includes at least one selected from rectangular coils, circular coils, elliptical coils, and irregular coils.

[0033] Optionally, the coil is arranged around the circuit to be protected;

[0034] The coil includes at least a first coil portion and a second coil portion, wherein the axial direction of the first coil portion is along a first direction, and the axial direction of the second coil portion is along a second direction; the first direction and the second direction are not parallel.

[0035] According to another aspect of the present invention, a chip is provided comprising:

[0036] The electromagnetic attack protection circuit described above,

[0037] The chip includes the circuit to be protected; when the output signal at the output terminal of the AND gate undergoes a signal flip, the circuit to be protected is operated safely.

[0038] According to another aspect of the present invention, an electromagnetic attack protection method is provided, applied to the electromagnetic attack protection circuit described above, the electromagnetic attack protection method comprising the following steps:

[0039] The coil detects whether a changing magnetic field exists;

[0040] When the coil detects a changing magnetic field, the output signal at the output terminal of the AND gate flips.

[0041] When the output signal at the output terminal of the AND gate flips, the circuit to be protected is operated safely.

[0042] The electromagnetic attack protection circuit and the chip and electromagnetic attack protection method provided in the embodiments of the present invention have a coil with a first output terminal and a second output terminal. The AND gate outputs according to the output of the first output terminal and the second output terminal. When the output signal of the AND gate flips, it indicates that the circuit to be protected has been attacked. It can quickly and accurately determine electromagnetic attacks and realize electromagnetic attack protection.

[0043] Furthermore, the protection circuit has a simple structure, low cost, and reliable performance.

[0044] Furthermore, the arrangement of the first to third MOSFETs and the first to third current sources enables the detection of electromagnetic attacks on electromagnetic coils of different polarities. Under electromagnetic attacks of different polarities, the output of the gate is consistent, the signal is simple, and the difficulty of protection operation is reduced.

[0045] Furthermore, by adjusting the magnitude of the first current, the sensitivity of electromagnetic attack detection can be adjusted, making it applicable to a wide range of situations.

[0046] Furthermore, the coil is arranged around the circuit to be protected, while the rest of the protective circuit is arranged outside the coil, which can accurately protect the circuit to be protected.

[0047] Furthermore, the coil includes a first coil section and a second coil section in different directions, enabling the detection of electromagnetic attacks in different directions, thus providing more comprehensive electromagnetic protection. Attached Figure Description

[0048] The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the invention with reference to the accompanying drawings, in which:

[0049] Figure 1 A schematic diagram of an electromagnetic attack protection circuit according to an embodiment of the present invention is shown;

[0050] Figure 2 A schematic diagram of an electromagnetic attack protection circuit according to an embodiment of the present invention is shown;

[0051] Figure 3 A schematic diagram illustrating an application scenario of an electromagnetic attack protection circuit according to an embodiment of the present invention is shown.

[0052] Figure 4 A schematic diagram of the structure of a chip according to an embodiment of the present invention is shown. Detailed Implementation

[0053] Various embodiments of the invention will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by the same or similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale. Furthermore, certain well-known parts may not be shown in the drawings.

[0054] The specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings and examples. Many specific details of the invention, such as the structure, materials, dimensions, processing techniques, and methods of the components, are described below to provide a clearer understanding of the invention. However, as those skilled in the art will understand, the invention may be implemented without following these specific details.

[0055] It should be understood that when describing the structure of a component, when referring to a layer or region as being "above" or "on top of" another layer or region, it can mean that it is directly above the other layer or region, or that it contains other layers or regions between it and the other layer or region. Furthermore, if the component is flipped over, that layer or region will be located "below" or "under" the other layer or region.

[0056] Figure 1 A schematic diagram of an electromagnetic attack protection circuit according to an embodiment of the present invention is shown. Figure 1 As shown, the electromagnetic attack protection circuit according to an embodiment of the present invention includes a coil 100, a first branch 200, a second branch 300, and an AND gate 400.

[0057] Specifically, coil 100 is located on one side of the circuit to be protected.

[0058] The first branch 200 is connected to the coil 100, and the first branch 200 has a first output terminal.

[0059] The second branch 300 is connected to the coil 100, and the second branch 300 has a second output terminal.

[0060] The input terminals of AND gate 400 are connected to the first output terminal and the second output terminal, respectively. When the output signal of AND gate 400 flips, it indicates that the circuit to be protected has been subjected to an electromagnetic attack.

[0061] In an optional embodiment of the present invention, the electromagnetic attack protection circuit further includes a safety unit (not shown in the figure). The safety unit is connected to the output terminal of AND gate 400. When the output signal of AND gate 400 flips, the safety unit performs a safety operation on the circuit to be protected. Specifically, when an electromagnetic attack (changing magnetic field) exists near coil 100 (near the circuit to be protected), an induced current is generated in coil 100. The induced current flows through the first branch 200 and the second branch 300, respectively, thereby outputting electrical signals at the first output terminal and the second output terminal, respectively. The electrical signals output by the first output terminal and the second output terminal are different when coil 100 generates an induced current and when it does not. During the process from no induced current to induced current, the output signal of AND gate 400 will flip (e.g., from high level to low level). When the output signal of AND gate 400 flips, it is determined that the circuit to be protected has been subjected to an electromagnetic attack, and the safety unit performs a safety operation on the circuit to be protected. The safety operation includes, for example, power-off and reset operations.

[0062] In an optional embodiment of the present invention, the coil 100 includes a coil body and a connector. The coil body may be a single-layer or multi-layer winding, and its shape may be at least one of a rectangular coil, a circular coil, an elliptical coil, and an irregular coil. One end of the connector is connected to the coil body, and the other end is connected to other devices or grounded. For example, both ends of the coil body are connected to connectors. Optionally, the coil 100 is an on-chip inductor, which may be at least one of a single-turn inductor structure, a multi-turn planar inductor structure, and a multi-layer three-dimensional inductor structure. The single-turn inductor structure and the multi-turn planar inductor structure can be implemented using any one layer of the chip mask layer. The multi-layer three-dimensional inductor is implemented using two or more layers of the chip mask, with the layers connected through vias.

[0063] In an optional embodiment of the invention, the coil 100 is arranged around the circuit to be protected. The coil 100 includes at least a first coil portion and a second coil portion. The axial direction of the first coil portion is along a first direction, and the axial direction of the second coil portion is along a second direction; the first and second directions are not parallel. The arrangement of the first and second coil portions ensures that electromagnetic attacks from all directions can be detected.

[0064] Figure 2 A schematic diagram of an electromagnetic attack protection circuit according to an embodiment of the present invention is shown. Figure 2 As shown, the electromagnetic attack protection circuit according to an embodiment of the present invention includes a coil 100, an AND gate 400, a first current source 510, a second current source 520, a third current source 530, a first MOS transistor 610, a second MOS transistor 620, a third MOS transistor 630, a first node 710, a second node 720, a third node 730, and an inverter 800.

[0065] Specifically, the first branch includes a second MOS (Metal-Oxide-Semiconductor Field-Effect Transistor), and the second branch includes a third MOS.

[0066] One end of the first current source 510 is connected to the first end of the coil 100, and the first current source 510 provides a first current. The other end of the first current source 510 is grounded, for example.

[0067] The first terminal of the first MOSFET 610 is connected to the second terminal of the coil 100; the third terminal of the first MOSFET 610 is connected to the second terminal of the coil 100.

[0068] One end of the second current source 520 is connected to the first end of the second MOSFET 620, and the second current source 520 provides a second current. The other end of the second current source 520 is grounded, for example.

[0069] The second terminal of the second MOSFET 620 is connected to the second terminal of the first MOSFET 610, and the third terminal of the second MOSFET 620 is connected to the second terminal of the coil 100.

[0070] One end of the third current source 530 is connected to the first end of the third MOSFET 630, and the third current source 530 provides the third current. The other end of the third current source 530 is grounded.

[0071] The second terminal of the third MOSFET 630 is connected to the second terminal of the first MOSFET 610, and the third terminal of the third MOSFET 630 is connected to the second terminal of the coil 100. The first terminal of the third MOSFET 630 is also connected to the second output terminal.

[0072] The first terminal of inverter 800 is connected to the first terminal of the second MOSFET 620, and the second terminal of inverter 800 is connected to the first output terminal.

[0073] Optionally, for Figure 2 The first MOSFET 610, the second MOSFET 620, and the third MOSFET 630 are all N-type MOSFETs, with the first terminal being the drain, the second terminal being the source, and the third terminal being the gate.

[0074] Optionally, the dimensions of the first MOSFET 610, the second MOSFET 620, and the third MOSFET 630 are in a 1:1:1 mirror circuit ratio. The second MOSFET 620 and 1.5 times the first current, and the third MOSFET 630 and 0.5 times the first current, constitute a current comparator.

[0075] Optionally, the electromagnetic attack protection circuit also includes a control unit. The control unit is connected to the first current source 510 to control the magnitude of the first current. By adjusting the magnitude of the first current, the sensitivity of the coil 100 can be adjusted.

[0076] Optionally, the coil 100 is arranged around the circuit to be protected, with the circuit to be protected located inside the coil 100. At least one of the first MOSFET 610, the second MOSFET 620, the third MOSFET 630, the first current source 510, the second current source 520, the third current source 530, the inverter 800, and the AND gate 400 is located outside the coil 100.

[0077] Figure 3 A schematic diagram illustrating an application scenario of an electromagnetic attack protection circuit according to an embodiment of the present invention is shown. Combined with... Figure 2 and Figure 3 As shown, when the attacking device performs an electromagnetic attack, it may use a millimeter-sized electromagnetic coil probe 900 close to the surface of the chip (the circuit to be protected / coil 100) to launch the attack. When the attacking electromagnetic field passes through the coil 100, an electric potential will be generated in the coil 100 according to the law of electromagnetic induction.

[0078] When there is no electromagnetic attack, the electromagnetic coil probe 900 of the attacking device does not generate a high-frequency electromagnetic field, and the coil 100 is equivalent to a DC conductor.

[0079] The size ratio of M1 (first MOSFET):M2 (second MOSFET):M3 (third MOSFET) is a 1:1:1 mirror circuit. M2 and 1.5*I0 (first current), and M3 and 0.5*I0 constitute a current comparator.

[0080] Without electromagnetic interference, the voltage across coil 100 is 0. The voltage at the first node is 0 (low level), the voltage at the second node is high (as a 1 input for AND gate 400), and the voltage at the third node is high (as a 1 input for AND gate 400). The output of AND gate 400 is Detect=1.

[0081] When an electromagnetic attack occurs, the electromagnetic coil probe 900 generates a high-voltage, high-frequency electromagnetic field. Because the magnetic field is directional, the coil 100 will have voltages in different directions at different times. When the electromagnetic attack causes the second terminal of coil 100 to be positive and the first terminal to be negative, the drain voltage of the first MOSFET increases, and the current in the first MOSFET decreases; the currents in the second and third MOSFETs also decrease. Therefore, the voltage at the first node remains constant, the voltage at the second node is high (for an AND gate, this is input 1), and the voltage at the third node flips from high to low. The output of the AND gate 400 flips from 1 (high level) to 0 (low level). At this point, an electromagnetic attack is detected, and an alarm signal is issued. After the alarm signal is transmitted to the chip's digital system, sensitive data clearing and reset operations are performed on the chip.

[0082] When an electromagnetic attack causes the second terminal of coil 100 to be negative and the first terminal to be positive, the drain voltage of the first MOSFET decreases, and the current in the first MOSFET increases; the currents in the second and third MOSFETs also increase. Therefore, the voltage at the first node becomes high (from 0 to 1), the voltage at the second node changes from high to low, and the voltage at the third node remains high. The output of the AND gate 400 flips from 1 (high level) to 0 (low level). At this point, an electromagnetic attack is detected, and an alarm signal is issued. After the alarm signal is transmitted to the chip's digital system, sensitive data clearing and reset operations are performed on the chip.

[0083] According to another aspect of the present invention, a chip is provided. The chip includes the electromagnetic attack protection circuit described above. The chip includes a circuit to be protected, which performs safe operation when the output signal at the output terminal of an AND gate undergoes a signal flip.

[0084] Figure 4 A schematic diagram of the chip structure according to an embodiment of the present invention is shown. Figure 4 As shown, in one specific embodiment, the chip has pads 1 and a die 8. The pads 1 are connected to external devices via bonding lines 9. The chip has an overall circuit module area 2, and at least a portion of the overall circuit module area 2 has a circuit to be protected 7.

[0085] The coil 100 is arranged around the circuit to be protected 7, and the coil body of the coil 100 is connected to the AND gate 400 via the connector (signal connection line) 6.

[0086] According to another aspect of the present invention, an electromagnetic attack protection method is provided. This electromagnetic attack protection method is applied to the electromagnetic attack protection circuit described above and includes the following steps:

[0087] The coil detects whether a changing magnetic field exists;

[0088] When the coil detects a changing magnetic field, the output signal at the output terminal of the AND gate flips.

[0089] When the output signal at the output terminal of the AND gate flips, a safe operation is performed on the circuit to be protected.

[0090] The electromagnetic attack protection circuit and chip including the same, and the electromagnetic attack protection method according to embodiments of the present invention, use an equivalent electromagnetic coil to form local protection for the sensitive area of ​​the chip, which can be integrated into the digital sensitive area. The circuit layout is flexible, the area is small, and the power consumption is low. Combined with the positive and negative coupling voltage detection method, electromagnetic protection can be accurately achieved.

[0091] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0092] As described above, these embodiments of the present invention do not exhaustively cover all details, nor do they limit the invention to the specific embodiments described. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to effectively utilize the invention and its modifications. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. An electromagnetic attack protection circuit, comprising: A coil, wherein the coil is disposed on one side of the circuit to be protected; The first branch is connected to the coil and has a first output terminal; A second branch, connected to the coil, having a second output terminal; and An AND gate, wherein the input terminals of the AND gate are respectively connected to the first output terminal and the second output terminal. When the output signal of the AND gate flips, it indicates that the circuit to be protected is subjected to an electromagnetic attack.

2. The electromagnetic attack protection circuit of claim 1, wherein, The first branch includes a second MOSFET, and the second branch includes a third MOSFET; The electromagnetic attack protection circuit also includes: A first current source provides a first current; one end of the first current source is connected to the first end of the coil. A first MOSFET, wherein a first terminal of the first MOSFET is connected to a second terminal of the coil; and a third terminal of the first MOSFET is connected to a second terminal of the coil. A second current source provides a second current; one end of the second current source is connected to the first end of the second MOSFET. The second terminal of the second MOSFET is connected to the second terminal of the first MOSFET, and the third terminal of the second MOSFET is connected to the second terminal of the coil. A third current source provides a third current; one end of the third current source is connected to the first end of the third MOS transistor. The second terminal of the third MOS transistor is connected to the second terminal of the first MOS transistor, and the third terminal of the third MOS transistor is connected to the second terminal of the coil; the first terminal of the third MOS transistor is also connected to the second output terminal. An inverter, wherein the first terminal of the inverter is connected to the first terminal of the second MOS transistor, and the second terminal of the inverter is connected to the first output terminal.

3. The electromagnetic attack protection circuit of claim 2, wherein, The size ratio of the first MOSFET, the second MOSFET, and the third MOSFET is a 1:1:1 mirror circuit. The second MOS transistor and 1.5 times the first current, and the third MOS transistor and 0.5 times the first current constitute a current comparator.

4. The electromagnetic attack protection circuit of claim 2, wherein, The electromagnetic attack protection circuit also includes: A control unit is connected to the first current source to control the magnitude of the first current.

5. The electromagnetic attack protection circuit of claim 2, wherein, The coil is arranged around the circuit to be protected, and the circuit to be protected is located inside the coil; At least one of the first MOSFET, the second MOSFET, the third MOSFET, the first current source, the second current source, the third current source, the inverter, and the AND gate is located outside the coil.

6. The electromagnetic attack protection circuit of claim 1, wherein, The electromagnetic attack protection circuit also includes: A safety unit is connected to the output terminal of the AND gate. When the output signal at the output terminal of the AND gate undergoes a signal flip, the safety unit performs a safety operation on the circuit to be protected.

7. The electromagnetic attack protection circuit of claim 1, wherein, The coil includes: Coil body; and A connector, one end of which is connected to the coil body. The coil body includes at least one selected from rectangular coils, circular coils, elliptical coils, and irregular coils.

8. The electromagnetic attack protection circuit according to claim 1, wherein, The coil is arranged around the circuit to be protected; The coil includes at least a first coil portion and a second coil portion, wherein the axial direction of the first coil portion is along a first direction, and the axial direction of the second coil portion is along a second direction; the first direction and the second direction are not parallel.

9. A chip, comprising: Electromagnetic attack protection circuit as described in any one of claims 1-8, The chip includes the circuit to be protected; when the output signal at the output terminal of the AND gate undergoes a signal flip, the circuit to be protected is operated safely.

10. An electromagnetic attack protection method, applied to an electromagnetic attack protection circuit as described in any one of claims 1-8, the electromagnetic attack protection method comprising the following steps: The coil detects whether a changing magnetic field exists; When the coil detects a changing magnetic field, the output signal at the output terminal of the AND gate flips. When the output signal at the output terminal of the AND gate flips, the circuit to be protected is operated safely.

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