Timing analysis method and apparatus, and electronic device

Abstract

The embodiment of the application provides a timing analysis method, device and electronic equipment, wherein voltage distribution data of internal devices of a chip is obtained according to chip design data, the voltage distribution data is used to represent working voltages of the internal devices of the chip in different time periods; the voltage distribution data is fed back to a static timing analysis process, timing analysis for the chip is performed, and timing analysis results are obtained. By segmenting and cutting the time-varying characteristics of the internal dynamic voltage drop of the chip, and feeding the dynamic voltage distribution data into the static timing analysis process, the timing parameters of the devices are dynamically adjusted, the static timing analysis results are closer to the actual chip behavior, the technical problem that the traditional static timing analysis cannot cover the dynamic voltage fluctuation is solved, and the accuracy of the timing analysis results is improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a timing analysis method, apparatus and electronic device. Background Technology

[0002] In the field of advanced semiconductor chip design, especially in the design flow of high-performance digital chips (such as 4G / 5G SoC chips, high-performance CPUs, GPUs, AI chips, and baseband chips), static timing analysis (STA) is a core step in ensuring the correctness of chip functionality and performance. The timing paths within the chip must meet strict timing constraints; otherwise, chip functionality may fail or performance may be substandard.

[0003] In existing technologies, timing analysis mainly relies on static voltage drop assumptions (e.g., ±10%). For example, timing convergence is performed based on the combination of worst-case process corner worst-case voltage drops to cover the worst-case timing scenarios.

[0004] However, the aforementioned timing analysis methods in the prior art cannot reflect the time-varying characteristics of voltage distribution in actual chips, resulting in inaccurate timing analysis results. Summary of the Invention

[0005] This application provides timing analysis methods, apparatus, and electronic devices to improve the accuracy of timing analysis results.

[0006] In a first aspect, embodiments of this application provide a timing analysis method, including:

[0007] Based on the chip design data, voltage distribution data of the internal devices of the chip is obtained. The voltage distribution data is used to characterize the operating voltage of the internal devices of the chip in different time periods. The voltage distribution data is obtained by segmenting the dynamic voltage distribution file based on the time-varying characteristics of the dynamic voltage distribution file of the internal devices of the chip. The voltage distribution data is fed back to the static timing analysis process to perform timing analysis for the chip and obtain timing analysis results.

[0008] In one possible implementation, the chip design data includes at least one of an SDC constraint file, a design netlist, and a post-simulation parameter file of the design layout; obtaining voltage distribution data of the internal devices of the chip based on the chip design data includes: inputting the chip design data into a static timing analysis tool to obtain time window information of the internal devices of the chip; inputting the time window information into a voltage simulation tool to generate a dynamic voltage distribution file, wherein the dynamic voltage distribution file characterizes the voltage drop distribution of each internal device of the chip under a target time window, wherein the target time window is the time window when the overall voltage drop of the chip is the maximum and / or greater than a voltage drop threshold; and generating voltage distribution data based on the dynamic voltage distribution file.

[0009] In one possible implementation, generating voltage distribution data based on the dynamic voltage distribution file includes: performing waveform simulation based on the dynamic voltage distribution file to obtain a voltage drop waveform; obtaining a time interval based on the changing trend of the voltage drop waveform; dividing the voltage drop waveform into at least two consecutive segments based on the time interval, and performing voltage simulation on each segment to obtain the operating voltage of the internal device of the chip within the corresponding time interval; and generating voltage distribution data based on the operating voltage of the internal device of the chip within the corresponding time interval.

[0010] In one possible implementation, feeding back the voltage distribution data to a static timing analysis process to perform timing analysis on the chip and obtain timing analysis results includes: processing the voltage distribution data based on a target strategy to obtain timing information of the internal devices of the chip, wherein the timing information represents the actual operating voltage of the internal devices of the chip; feeding back the timing information of the internal devices of the chip to the static timing analysis process to perform timing verification and obtain timing analysis results; wherein the target strategy includes at least one of the following: calling a library characterization tool, calling the interpolation function of a static timing analysis tool, or calling a simulation circuit simulator tool.

[0011] In one possible implementation, the step of processing the voltage distribution data based on the target strategy to obtain the timing information of the internal devices of the chip includes: performing library characterization tools on the internal devices of the chip in the high-power region; performing interpolation functions on the internal devices of the chip in the low-power region; and performing simulation circuit simulator tools on the devices of the critical path.

[0012] In one possible implementation, the step of processing the voltage distribution data based on the target strategy to obtain the timing information of the internal devices of the chip includes: acquiring a standard cell library; and re-characterizing the standard cell library based on the operating voltage of each internal device of the chip according to the voltage distribution data to generate the timing information of the internal devices of the chip.

[0013] In one possible implementation, the step of processing the voltage distribution data based on the target strategy to obtain the timing information of the internal devices of the chip includes: based on the voltage distribution data, calling the interpolation function of a static timing analysis tool to perform interpolation calculations on the operating voltage of each internal device of the chip to obtain the updated operating voltage corresponding to each internal device of the chip; and generating the timing information of the internal devices of the chip based on the updated operating voltage corresponding to each internal device of the chip.

[0014] In one possible implementation, the step of processing the voltage distribution data based on the target strategy to obtain the timing information of the internal devices of the chip includes: based on the voltage distribution data, calling a simulation circuit simulator tool to perform single-point or multi-point timing simulation on the reference cells corresponding to each internal device of the chip to generate reference coefficients; configuring the reference coefficients on the timing attributes of the internal devices of the chip to generate the timing information of the internal devices of the chip.

[0015] Secondly, embodiments of this application provide a timing analysis apparatus, comprising:

[0016] The acquisition module is used to obtain voltage distribution data of internal devices of the chip based on chip design data. The voltage distribution data is used to characterize the operating voltage of the internal devices of the chip in different time periods. The voltage distribution data is obtained by segmenting the dynamic voltage distribution file based on the time-varying characteristics of the dynamic voltage distribution file of the internal devices of the chip.

[0017] The configuration module is used to feed back the voltage distribution data to the static timing analysis process, perform timing analysis on the chip, and obtain timing analysis results.

[0018] In one possible implementation, the chip design data includes at least one of an SDC constraint file, a design netlist, and a post-simulation parameter file of the design layout; the acquisition module is specifically used for: inputting the chip design data into a static timing analysis tool to obtain time window information of the internal devices of the chip; inputting the time window information into a voltage simulation tool to generate a dynamic voltage distribution file, wherein the dynamic voltage distribution file characterizes the voltage drop distribution of each internal device of the chip under a target time window, wherein the target time window is the time window when the overall voltage drop of the chip is the maximum and / or greater than a voltage drop threshold; and generating voltage distribution data based on the dynamic voltage distribution file.

[0019] In one possible implementation, when the acquisition module generates voltage distribution data based on the dynamic voltage distribution file, it is specifically used to: perform waveform simulation based on the dynamic voltage distribution file to obtain a voltage drop waveform; obtain a time interval based on the changing trend of the voltage drop waveform; cut the voltage drop waveform into at least two consecutive segments based on the time interval, and perform voltage simulation on each segment to obtain the operating voltage of the internal device of the chip within the corresponding time interval; and generate voltage distribution data based on the operating voltage of the internal device of the chip within the corresponding time interval.

[0020] In one possible implementation, the configuration module is specifically used to: process the voltage distribution data based on a target strategy to obtain timing information of the internal devices of the chip, the timing information representing the actual operating voltage of the internal devices of the chip; feed back the timing information of the internal devices of the chip to the static timing analysis process for timing verification to obtain timing analysis results; wherein, the target strategy includes at least one of the following: calling a library characterization tool, calling the interpolation function of a static timing analysis tool, and calling a simulation circuit simulator tool.

[0021] In one possible implementation, the configuration module is specifically used to: execute library characterization tools for chip internal devices in high-power regions; execute interpolation functions for chip internal devices in low-power regions; and execute simulation circuit simulator tools for devices in critical paths.

[0022] In one possible implementation, when the configuration module processes the voltage distribution data based on the target strategy to obtain the timing information of the internal devices of the chip, it is specifically used to: acquire a standard cell library; and, based on the voltage distribution data, re-characterize the standard cell library based on the operating voltage of each internal device of the chip to generate the timing information of the internal devices of the chip.

[0023] In one possible implementation, when the configuration module processes the voltage distribution data based on the target strategy to obtain the timing information of the internal devices of the chip, it is specifically used to: based on the voltage distribution data, call the interpolation function of the static timing analysis tool to perform interpolation calculation on the operating voltage of each internal device of the chip to obtain the updated operating voltage corresponding to each internal device of the chip; and generate the timing information of the internal devices of the chip based on the updated operating voltage corresponding to each internal device of the chip.

[0024] In one possible implementation, when the configuration module processes the voltage distribution data based on the target strategy to obtain the timing information of the internal devices of the chip, it is specifically used to: based on the voltage distribution data, call a simulation circuit simulator tool to perform single-point or multi-point timing simulation on the reference cells corresponding to each internal device of the chip to generate reference coefficients; configure the reference coefficients on the timing attributes of the internal devices of the chip to generate the timing information of the internal devices of the chip.

[0025] Thirdly, embodiments of this application provide an electronic device, including: a memory and a processor;

[0026] The memory stores computer-executed instructions;

[0027] The processor executes computer execution instructions stored in the memory, causing the processor to perform the first aspect and / or various possible implementations of the first aspect as described above.

[0028] Fourthly, embodiments of this application provide a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, are used to implement the first aspect and / or various possible implementations of the first aspect.

[0029] Fifthly, embodiments of this application provide a computer program product, including a computer program that, when executed by a processor, implements the first aspect and / or various possible implementations of the first aspect.

[0030] The timing analysis method, apparatus, and electronic device provided in this application obtain voltage distribution data of internal devices of a chip based on chip design data. This voltage distribution data characterizes the operating voltage of the internal devices of the chip in different time periods. The voltage distribution data is then fed back to a static timing analysis process to perform timing analysis on the chip, yielding timing analysis results. By segmenting the time-varying characteristics of the dynamic voltage drop within the chip and feeding the dynamic voltage distribution data back into the static timing analysis process, the timing parameters of the devices are dynamically adjusted. This makes the static timing analysis results closer to the actual chip behavior, solving the technical problem that traditional static timing analysis cannot cover dynamic voltage fluctuations and improving the accuracy of timing analysis results. Attached Figure Description

[0031] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0032] Figure 1 A schematic diagram of a chip design and manufacturing process provided in this application;

[0033] Figure 2 Flowchart of the timing analysis method provided in this application Figure 1 ;

[0034] Figure 3 for Figure 2 A flowchart illustrating the specific implementation of step S101 in the illustrated embodiment;

[0035] Figure 4 for Figure 3 A flowchart illustrating the specific implementation of step S1013 in the illustrated embodiment;

[0036] Figure 5 Flowchart of the timing analysis method provided in this application Figure 2 ;

[0037] Figure 6 This is a flowchart illustrating a time series analysis method provided in this embodiment.

[0038] Figure 7 This is a schematic diagram of the structure of a timing analysis device provided in an embodiment of this application;

[0039] Figure 8 A schematic diagram of the structure of the electronic device provided in this application.

[0040] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0041] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0042] First, let me explain the terms used in this application:

[0043] Static timing analysis is a verification method that calculates and analyzes the delays of all timing paths within a chip to verify whether the circuit meets timing constraints such as setup time and hold time. It does not require dynamic simulation of the circuit; instead, it analyzes based on the static circuit structure and timing parameters. It is characterized by its high speed and comprehensive coverage, making it a core tool for timing verification in chip design.

[0044] Voltage drop (IR drop): This refers to the voltage loss that occurs when current flows through the metal traces and vias of the power supply network due to resistance, causing the actual operating voltage of the internal components of the chip to be lower than the nominal power supply voltage. Dynamic voltage drop refers to the voltage fluctuation caused by the dynamic changes in current over time during chip operation.

[0045] Timing Window (TW): This refers to the time interval within a clock cycle during which each device inside a chip may switch signals. It is used to determine the time range of power consumption and current changes of the device.

[0046] Dynamic Voltage Distribution (DVD) file: This is a data file that records the actual operating voltage of each device inside the chip within a specific time window. It includes information such as device instantiation name, called standard cell name, and operating voltage.

[0047] Figure 1 This application provides a schematic diagram of a chip design and manufacturing process, such as... Figure 1 As shown, the chip design and manufacturing chain typically includes several key stages: early planning, front-end design, back-end physical design, approval analysis, wafer fabrication, packaging and testing, and mass production and delivery. The approval analysis stage is crucial to ensure that the timing of the chip designed in the early stages meets design requirements, thus guaranteeing that the manufactured chip meets functional and performance requirements. In this stage, based on the constraints and guidelines provided by the semiconductor manufacturer (Foundry), static timing analysis is used to check whether the entire chip (Full Chip) meets timing requirements in various application scenarios, specifically whether the timing slack is greater than 0. If the timing slack is less than 0, it indicates the presence of timing violations in the chip's timing paths. Before the final chip design is submitted to the semiconductor manufacturer, the final static timing analysis must ensure that there are no timing violations in the timing paths. Only if the final design meets the requirements can the chip be taped out. Otherwise, the produced chip may have a low yield or even fail, resulting in significant losses for the company. The timing analysis method provided in this application can be applied to the aforementioned approval analysis stage to generate accurate timing analysis results.

[0048] Based on the scenario description above, in existing technologies, static timing analysis in the approval analysis stage mainly relies on static voltage drop assumptions (e.g., ±10%) for timing analysis. For example, timing convergence is performed based on the worst-case process corner's worst voltage drop combination to cover the worst-case timing scenario. However, the voltage drop of internal chip devices changes over time, and the voltage drop of each device does not always remain within ±10%. This means that the device performance cannot be directly characterized in static timing analysis, leading to biases in timing calculations and the risk of failure.

[0049] The timing analysis method provided in this application segments the time-varying characteristics of the dynamic voltage drop inside the chip and feeds the dynamic voltage distribution data back into the static timing analysis process, thereby dynamically adjusting the timing parameters of the device and solving the technical problem that traditional static timing analysis cannot cover dynamic voltage fluctuations.

[0050] The technical solution of this application and how the technical solution of this application solves the above-mentioned technical problems are described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will now be described with reference to the accompanying drawings.

[0051] Figure 2 Flowchart of the timing analysis method provided in this application Figure 1 ,like Figure 2 As shown, the method includes:

[0052] Step S101: Based on the chip design data, obtain the voltage distribution data of the internal devices of the chip. The voltage distribution data is used to characterize the operating voltage of the internal devices of the chip in different time periods. The voltage distribution data is obtained by segmenting the dynamic voltage distribution file based on the time-varying characteristics of the dynamic voltage distribution file of the internal devices of the chip.

[0053] For example, the entity performing this step can be an electronic device (such as a computer, server, etc.) or a timing analysis system (software program product), which can run within the aforementioned electronic device. Taking a timing analysis system as an example, it first acquires various design data after the chip design is completed, and then uses timing analysis and voltage simulation tools to calculate the operating voltage of each device inside the chip during different operating time periods, forming voltage distribution data.

[0054] Chip design data refers to files generated during the chip design process that describe circuit structure, constraints, and parasitic parameters. Examples include SDC constraint files, Design Netlists (DNs), and Standard Parasitic Extraction Format (SPEF) files. Voltage distribution data is a structured dataset where each record corresponds to a device. It typically includes three core fields: device identifier, time period, and operating voltage. For instance, the record "DFF1,100ns-200ns,0.85V" indicates that flip-flop DFF1 operates at 0.85V during the 100ns to 200ns time period. Here, ns represents nanoseconds.

[0055] Furthermore, in one possible implementation, the chip design data includes at least one of the following: an SDC constraint file, a design netlist, and a post-design layout simulation parameter file; such as... Figure 3 As shown, the specific implementation of step S101 includes:

[0056] Step S1011: Input the chip design data into the static timing analysis tool to obtain the timing window information of the internal components of the chip;

[0057] Step S1012: Input the time window information into the voltage simulation tool to generate a dynamic voltage distribution file. The dynamic voltage distribution file represents the voltage drop distribution of each chip's internal devices under the target time window. The target time window is the time window when the overall voltage drop of the chip is the maximum and / or greater than the voltage drop threshold.

[0058] Step S1013: Generate voltage distribution data based on the dynamic voltage distribution file.

[0059] For example, firstly, in step S1011, the user imports the prepared SDC constraint file, design netlist, and SPEF file into the static timing analysis tool. Through the runtime timing analysis command, the tool automatically calculates and outputs the timing window information for all devices within the chip. The SDC constraint file is a text file describing the chip's timing constraints, including clock cycles, input / output delays, multi-cycle paths, and other constraint information. The design netlist is a file describing the connection relationships between devices in the circuit, containing instantiation information and interconnection relationships for all devices. The SPEF file is a standard parasitic parameter exchange format file, containing the resistance and capacitance parasitic parameters of all connections in the circuit. The timing window information refers to the earliest and latest signal transition times for each device; for example, "DFF1,50ns,70ns" indicates that the signal transition time of DFF1 is between 50ns and 70ns.

[0060] Subsequently, in step S1012, the system imports the time window information output by the static timing analysis tool into the voltage (IR) simulation tool, and at the same time imports the chip's power consumption waveform data. Based on the time window and power consumption waveform, the tool identifies the time period with the largest overall voltage drop of the chip as the target time window, and then performs detailed voltage simulation on this time period to generate a dynamic voltage distribution file.

[0061] In one possible implementation, the target time window is the period with the largest overall average voltage drop of the chip; in another, the target time window is the period with the largest number of devices in the chip exhibiting a voltage drop exceeding 15%; and in yet another, the target time window is the period corresponding to a key application scenario specified by the user. The dynamic voltage distribution file is a binary or text file output by the voltage simulation tool, containing information such as the operating voltage and current density of each device within the target time window.

[0062] Next, in step S1013, the system parses the dynamic voltage distribution file, extracts the operating voltage information of each device, and organizes it according to time periods to generate structured voltage distribution data.

[0063] In the above embodiment steps, by accurately identifying the time period with the most severe voltage drop during chip operation and obtaining the detailed voltage distribution within that time period, the technical effect is to ensure that subsequent timing analysis can cover the worst voltage scenario and avoid missing timing violations caused by sudden local voltage drops.

[0064] Furthermore, in one possible implementation, such as Figure 4 As shown, the specific implementation of step S1013 includes:

[0065] Step S1013-1: Perform waveform simulation based on the dynamic voltage distribution file to obtain the voltage drop waveform;

[0066] Step S1013-2: Obtain the time interval based on the changing trend of the voltage drop waveform;

[0067] Step S1013-3: Based on the time interval, cut the voltage drop waveform into at least two consecutive segments, and perform voltage simulation on each segment to obtain the operating voltage of the internal devices of the chip within the corresponding time interval;

[0068] Step S1013-4: Generate voltage distribution data based on the operating voltage of the internal components of the chip within the corresponding time interval.

[0069] For example, firstly, in step S1013-1, the system performs full-cycle waveform simulation based on the voltage data in the dynamic voltage distribution file and the chip's power consumption model to obtain a continuous waveform showing the overall average voltage drop of the chip changing over time.

[0070] Next, in step S1013-2, the system analyzes the changing trend of the voltage drop waveform and determines the time interval based on the severity of the voltage change. The more drastic the voltage change, the shorter the time interval; the more gradual the voltage change, the longer the time interval.

[0071] In one possible implementation, a fixed time interval, such as 100ns, is used; in another possible implementation, an adaptive time interval is used, which is dynamically adjusted according to the voltage change rate; in yet another possible implementation, the time interval is manually set by the user according to the chip's operating frequency and the application scenario.

[0072] The time interval refers to the length of time it takes to cut a continuous voltage drop waveform into multiple segments. For example, 100ns means that the waveform is cut into multiple continuous segments of 100ns each.

[0073] Next, in step S1013-3, the system cuts the voltage drop waveform into multiple continuous time segments according to a determined time interval, and then performs voltage simulation on each time segment to calculate the operating voltage of all devices in each segment.

[0074] Finally, in step S1013-4, the system integrates the device operating voltage data of all time segments to generate complete voltage distribution data containing multiple time periods.

[0075] Furthermore, in one possible implementation, the above steps further include: calculating the voltage change rate, dynamically adjusting the time interval based on the voltage change rate, and using a finer-grained time interval in regions where the voltage change rate exceeds a preset threshold. For example,

[0076] The system calculates the first derivative of the voltage drop waveform in real time as the voltage change rate. When the voltage change rate exceeds a preset threshold (e.g., 0.01V / ns), the time interval in that region is reduced to half of its original value, for example, from 100ns to 50ns. When the voltage change rate is below the preset threshold, the time interval is restored to its original value.

[0077] For example, in the rising and falling edge regions of the voltage drop waveform, where the voltage change rate is high, a time interval of 50 ns is used; in the plateau region where the voltage drop is relatively stable, a time interval of 100 ns is used.

[0078] The input and output of the above steps will be described below with a more specific embodiment. For example,

[0079] During the execution of step S1013-1, the input is: dynamic voltage distribution file; the output is: the overall average voltage drop waveform of the chip from 0ns to 1000ns.

[0080] During the execution of step S1013-2, the input is the voltage drop waveform; the output is a time interval of 100ns for the region with a smooth voltage change and a time interval of 50ns for the region with a sharp voltage change.

[0081] During the execution of step S1013-3, the inputs are: time interval and voltage drop waveform; the outputs are: device operating voltage data for 12 time segments.

[0082] During the execution of step S1013-4, the input is: working voltage data for 12 time segments; the output is: complete voltage distribution data for 12 time segments.

[0083] In the above embodiment steps, the details of dynamic voltage changes are captured by segmenting the voltage drop waveform; the technical effect is that, while ensuring simulation accuracy, the huge amount of computation required to simulate the entire cycle point by point is avoided, thus achieving a balance between accuracy and efficiency.

[0084] Step S102: Feed back the voltage distribution data to the static timing analysis process, perform timing analysis for the chip, and obtain the timing analysis results.

[0085] For example, in this step, the system adjusts the timing parameters of the device according to the voltage distribution data using an appropriate target strategy, and then imports the adjusted timing parameters into a static timing analysis tool to perform timing verification and obtain the final timing analysis results.

[0086] The target strategy refers to the method of converting voltage distribution data into time series parameters, including three types: calling library characterization tools, calling the interpolation function of static timing analysis tools, and calling the simulation circuit simulator tool (SPICE) for simulation. Each of the three methods has its own advantages and disadvantages in terms of accuracy and computational resource consumption: library characterization has the highest accuracy but the largest amount of computation, interpolation has the smallest amount of computation but the lowest accuracy, and the simulation circuit simulator tool has simulation accuracy and computational cost in between.

[0087] The above-described embodiments accurately reflect the impact of dynamic voltage drop in timing analysis, making the static timing analysis results closer to the actual timing behavior of the chip during operation, thus improving the accuracy of timing verification.

[0088] Furthermore, in one possible implementation, step S102 is specifically implemented as follows:

[0089] Step S102A: Execute library characterization tools for internal chip devices in high-power regions; execute interpolation functions for internal chip devices in low-power regions; execute simulation circuit simulator tools for devices in critical paths.

[0090] For example, in this step, a hybrid strategy of partitioning and classification is adopted. Different processing methods are selected based on the power consumption level of the region where the device is located and the importance of the path, in order to achieve the best balance between accuracy and efficiency. Among them, high power consumption regions refer to areas in the chip where the average voltage drop exceeds 12%. Voltage changes in these regions have a significant impact on timing and require high-precision timing parameters. Low power consumption regions refer to areas in the chip where the average voltage drop is less than 8%. Voltage changes in these regions have a smaller impact on timing and can be achieved using more efficient interpolation methods. Critical paths refer to paths with a timing margin of less than 10%. These paths are high-risk areas for timing violations and require the most accurate timing parameters.

[0091] In one possible implementation, high-power regions occupy 20% of the total chip area and are represented using a library; low-power regions occupy 75% of the total chip area and are represented using interpolation; devices on the critical path account for 5% of the total number of devices and are simulated using a simulation circuit simulator tool. The computational cost of this combined strategy is only about 25% of that of full library representation, but the accuracy is close to that of full library representation.

[0092] The following example, using a more specific application scenario, illustrates the execution process of step S102A:

[0093] Inputs: Voltage distribution data, chip layout partitioning information, critical path report;

[0094] Processing: Perform library characterization on 200,000 devices in the core region (high power) of the AI ​​accelerator; perform interpolation on 750,000 devices in the peripheral region (low power) of the chip; and perform simulation using simulation circuit simulator tools on 50,000 devices along 100 critical paths.

[0095] Output: Updated timing information for all devices.

[0096] Through the steps of the above embodiments, while ensuring the accuracy of timing analysis in critical areas and critical paths, the consumption of computing resources is minimized, achieving an optimal balance between accuracy and efficiency, enabling this solution to be applied to timing signature of large-scale advanced process chips.

[0097] The timing analysis method provided in this application obtains voltage distribution data of internal chip components based on chip design data. This voltage distribution data characterizes the operating voltage of internal chip components within different time periods. The voltage distribution data is then fed back to a static timing analysis process to perform timing analysis on the chip, yielding timing analysis results. By segmenting the dynamic voltage drop waveform, voltage distribution data for different time periods is obtained. A hybrid strategy of partitioning and classification is then used to feed this voltage distribution data back into the static timing analysis process. This embodiment solves the technical problem that traditional static timing analysis cannot cover dynamic voltage fluctuations, significantly improving the accuracy of timing analysis results. Simultaneously, through segmentation and the hybrid strategy, computational resource consumption is effectively controlled, meeting the timing approval requirements of large-scale chips at advanced process nodes.

[0098] Figure 5 Flowchart of the timing analysis method provided in this application Figure 2 ,like Figure 5 As shown, in this embodiment... Figure 2 Based on the previous embodiment, step S102 has been further refined, and the method includes:

[0099] Step S201: Input the chip design data into the static timing analysis tool to obtain the timing window information of the internal components of the chip.

[0100] Step S202: Input the time window information into the voltage simulation tool to generate a dynamic voltage distribution file. The dynamic voltage distribution file represents the voltage drop distribution of each internal device of the chip under the target time window. The target time window is the time window when the overall voltage drop of the chip is the maximum and / or greater than the voltage drop threshold.

[0101] Step S203: Perform waveform simulation based on the dynamic voltage distribution file to obtain the voltage drop waveform.

[0102] Step S204: Obtain the time interval based on the changing trend of the voltage drop waveform.

[0103] Step S205: Based on the time interval, cut the voltage drop waveform into at least two consecutive segments, and perform voltage simulation on each segment to obtain the operating voltage of the internal devices of the chip within the corresponding time interval.

[0104] Step S206: Generate voltage distribution data based on the operating voltage of the internal components of the chip within the corresponding time interval.

[0105] The specific implementation of steps S201 to S206 has been described in previous embodiments and will not be repeated here. The purpose of the above embodiments is to generate complete voltage distribution data containing multiple time periods, providing a comprehensive and accurate voltage data foundation for subsequent timing parameter adjustments.

[0106] Step S207: In response to the target strategy, call the library characterization tool to obtain the standard cell library, and re-characterize the standard cell library based on the operating voltage of each chip's internal device according to the voltage distribution data, and generate the timing information of the chip's internal device.

[0107] For example, in this step, when library characterization is selected as the target strategy, the system first obtains the original standard cell library provided by Foundry, and then, based on the actual operating voltage of each device in the voltage distribution data, calls the library characterization tool to re-characterize the standard cell corresponding to each device and generate the timing parameters under that voltage.

[0108] The standard cell library is a library file provided by Foundry containing timing and power consumption parameters of various basic logic units (such as AND gates, OR gates, flip-flops, etc.), which is the basis for static timing analysis. Re-characterization refers to re-simulating the timing parameters such as delay and toggle time of the standard cell for a specific operating voltage to generate a new library file.

[0109] In one possible implementation, the system groups devices with the same operating voltage, performs a single characterization of the standard cell corresponding to each group, and then applies the generated timing parameters to all devices in that group to reduce redundant calculations. For example, if 1000 DFF flip-flops all operate at 0.85V, the system only needs to characterize the DFF cell at 0.85V once and then apply the result to all 1000 flip-flops.

[0110] The implementation method provided by the above embodiments can obtain the most accurate timing parameters of the device under the actual operating voltage, achieve the highest timing analysis accuracy, and accurately capture the impact of voltage changes on device performance.

[0111] Step S208: In response to the target strategy of calling the interpolation function of the static timing analysis tool, based on the voltage distribution data, the interpolation function of the static timing analysis tool is called to perform interpolation calculation on the operating voltage of each chip internal device to obtain the updated operating voltage corresponding to each chip internal device, and based on the updated operating voltage corresponding to each chip internal device, the timing information of the chip internal device is generated.

[0112] For example, in the steps of this embodiment, when interpolation is selected as the target strategy, the system imports the operating voltage of each device in the voltage distribution data into the static timing analysis tool, and then enables the voltage interpolation function of the static timing analysis tool. Based on the timing parameters of multiple voltage points already existing in the original standard cell library, the tool calculates the timing parameters of the device under the actual operating voltage through linear interpolation or nonlinear interpolation.

[0113] In one possible implementation, a linear interpolation method is used, assuming that the device delay is linearly related to the voltage; in another possible implementation, a second-order polynomial interpolation method is used, which can more accurately reflect the nonlinear relationship between the device delay and the voltage.

[0114] The following example illustrates the specific implementation process of step S208 using an application scenario. For instance, the input to this step is the original standard cell library (containing timing parameters for two voltage points, 0.8V and 0.9V) and voltage distribution data (DFF1 operating voltage 0.85V). Then, a static timing analysis tool is called to calculate the delay parameters at 0.85V based on the delay parameters at 0.8V and 0.9V through linear interpolation. Finally, the interpolated delay parameters of the DFF cell at 0.85V are output.

[0115] In this embodiment, the timing parameters of the device under the actual operating voltage are obtained quickly, achieving the goal of fast calculation speed and low resource consumption, which is suitable for low power consumption areas where high accuracy is not required.

[0116] Step S209: In response to the target strategy of calling the simulation circuit simulator tool, based on the voltage distribution data, the simulation circuit simulator tool is called to perform single-point or multi-point timing simulation on the reference cells corresponding to the internal devices of each chip, and a reference coefficient is generated; the reference coefficient is configured on the timing attributes of the internal devices of the chip to generate the timing information of the internal devices of the chip.

[0117] In this embodiment, when the simulation circuit simulator tool is selected as the target strategy, the system calls the simulation circuit simulator tool to perform timing simulation on the reference cell corresponding to the device under the actual operating voltage. Then, the simulation results are compared with the timing parameters under the standard approval voltage to calculate the Derate coefficient. Finally, the Derate coefficient is configured for the device in the static timing analysis tool.

[0118] Single-point simulation refers to simulation under only a set of typical input toggle times and output load conditions to generate a unified Derate coefficient; multi-point simulation refers to simulation under multiple different input toggle times and output load conditions to generate multiple Derate coefficients corresponding to the input parameters, resulting in higher accuracy.

[0119] In one possible implementation, multi-point simulation is used for devices on the critical path to generate a two-dimensional Derate coefficient table related to input toggle time and output load; single-point simulation is used for devices on non-critical paths to generate a unified Derate coefficient.

[0120] In a more specific embodiment, the inputs to step S209 are the reference cell simulation circuit simulator tool netlist, voltage distribution data (DFF1 operating voltage 0.85V), and standard check voltage 0.9V; then, the simulation circuit simulator tool is called to simulate the propagation delay of the DFF cell at 0.85V as 0.22ns and at 0.9V as 0.2ns; the Derate coefficient is calculated as 0.22ns / 0.2ns = 1.1; then, the Derate coefficient of DFF1 is output as 1.1. After configuration in static timing analysis, the delay of DFF1 will be multiplied by 1.1 to generate timing information of the internal devices of the chip.

[0121] The steps in this embodiment obtain high-precision timing parameters of critical path devices, making the accuracy close to that of library representations, but with a computational load far less than that of library representations. This approach balances accuracy and computational load, making it particularly suitable for timing analysis of critical paths.

[0122] Step S210: Feed back the timing information of the internal devices of the chip to the static timing analysis process for timing verification, and obtain the timing analysis results.

[0123] For example, after the previous processing steps to generate timing information, the system imports the timing information of all devices generated by the three methods mentioned above into a static timing analysis tool, replacing the original timing parameters. Then, it runs a complete timing approval process, checking the setup and hold time margins of all timing paths, and generating a final timing analysis report. Optionally, the timing analysis report will list all paths with timing violations, along with detailed timing information for each path, including start point, end point, delay composition, and margin, for designers to perform timing optimization to complete the approval analysis processing stage.

[0124] In one possible implementation, the timing analysis results include, specifically, the inputs to step S210 are the updated timing information of all devices, SDC constraint file, design netlist, and SPEF file; then, a static timing analysis tool is run to perform full-chip timing check-in and generate a timing analysis report. The timing analysis report shows that there are 5 paths with setup time violations, with the maximum violation Tns.

[0125] Figure 6 This is a flowchart illustrating a timing analysis method provided in this embodiment. The following is a description of the process. Figure 6 The timing analysis method provided in this embodiment will be further described, such as... Figure 6 As shown, the processing steps include:

[0126] S1: Obtain the inputs required for static timing analysis, such as the design netlist, SDC constraints, and SPEF file.

[0127] S2: Output the time windows of each device unit in the design through static timing analysis tools.

[0128] S3: Use voltage simulation tools to extract the voltage drop distribution of all devices over a period of time based on the power consumption waveform.

[0129] S4: A DVD file output by the voltage tool describing the voltage distribution.

[0130] S5: The simulation circuit simulator tool simulates and obtains a complete PCB board-level chip voltage drop waveform.

[0131] S6: Set time interval

[0132] S7: Determine if all time periods have been visited. If yes, end the process; otherwise, proceed to step S8.

[0133] S8: The voltage simulation tool simulates the voltage drop distribution of all devices within the time period Tn.

[0134] S9: A DVD file output by the voltage simulation tool, describing the voltage distribution over a time period Tn.

[0135] S10: Characterization tools re-characterize / static timing analysis tools interpolate internally / simulation circuit simulator tools provide single-point or multi-point simulation timing information.

[0136] S11: Generate a new library / new timing information / timing change coefficient.

[0137] S12: Generate timing analysis results. Return to step S7.

[0138] The steps described above are explained below with reference to previous embodiments. For example, this process is an iterative loop, where the system processes each time segment sequentially until all time segments have been processed. For each time segment, the voltage distribution is first obtained through voltage simulation. Then, a suitable strategy is used to generate timing information. Finally, timing analysis is performed and the results are recorded. After all time segments have been processed, the system summarizes the timing analysis results for all time segments, identifies the worst-case timing violations, and uses this as the final timing approval result.

[0139] For example, the voltage drop waveform is divided into 5 time periods, and the system processes these 5 time periods T1 to T5 sequentially, generating corresponding timing analysis results for each time period. If the most serious timing violation is found in time period T3, then the final timing verification result will be based on the result of time period T3.

[0140] The technical objective of this process is to cover all possible voltage scenarios and ensure that the timing signature results can reflect the timing behavior of the chip at any operating moment. The technical effect is to completely solve the timing signature risk caused by dynamic voltage fluctuations and significantly improve the mass production yield of the chip.

[0141] This embodiment details three specific implementation methods for feeding back voltage distribution data into the static timing analysis process and provides a complete pseudo-dynamic static timing analysis workflow. By flexibly utilizing library representation, interpolation, and simulation using circuit simulator tools, a balance can be achieved between different accuracy and efficiency requirements. This embodiment accurately reflects the time-varying characteristics of dynamic voltage drop into timing analysis, making the static timing analysis results closer to actual chip behavior, and providing a reliable solution for chip timing approval at advanced process nodes.

[0142] Figure 7 This is a schematic diagram of the structure of a timing analysis device provided in an embodiment of this application, as shown below. Figure 7 As shown, the timing analysis device 40 provided in this embodiment includes:

[0143] The acquisition module 401 is used to obtain the voltage distribution data of the internal devices of the chip based on the chip design data. The voltage distribution data is used to characterize the operating voltage of the internal devices of the chip in different time periods.

[0144] The configuration module 402 is used to feed back voltage distribution data to the static timing analysis process, perform timing analysis on the chip, and obtain timing analysis results.

[0145] In one possible implementation, the chip design data includes at least one of an SDC constraint file, a design netlist, and a post-simulation parameter file of the design layout. The acquisition module 401 is specifically used for: inputting the chip design data into a static timing analysis tool to obtain time window information of the internal devices of the chip; inputting the time window information into a voltage simulation tool to generate a dynamic voltage distribution file, which characterizes the voltage drop distribution of each internal device of the chip under a target time window, wherein the target time window is the time window when the overall voltage drop of the chip is maximum and / or greater than a voltage drop threshold; and generating voltage distribution data based on the dynamic voltage distribution file.

[0146] In one possible implementation, when the acquisition module 401 generates voltage distribution data based on the dynamic voltage distribution file, it is specifically used to: perform waveform simulation based on the dynamic voltage distribution file to obtain a voltage drop waveform; obtain a time interval based on the changing trend of the voltage drop waveform; cut the voltage drop waveform into at least two consecutive segments based on the time interval, and perform voltage simulation on each segment to obtain the operating voltage of the internal devices of the chip within the corresponding time interval; and generate voltage distribution data based on the operating voltage of the internal devices of the chip within the corresponding time interval.

[0147] In one possible implementation, the configuration module 402 is specifically used to: process voltage distribution data based on a target strategy to obtain timing information of internal devices in the chip, wherein the timing information characterizes the actual operating voltage of the internal devices in the chip; feed back the timing information of the internal devices in the chip to the static timing analysis process for timing verification, and obtain timing analysis results; wherein the target strategy includes at least one of the following: calling a library characterization tool, calling the interpolation function of a static timing analysis tool, or calling a simulation circuit simulator tool.

[0148] In one possible implementation, the configuration module 402 is specifically used to: execute library characterization tools for chip internal devices in high-power regions; execute interpolation functions for chip internal devices in low-power regions; and execute simulation circuit simulator tools for devices in critical paths.

[0149] In one possible implementation, when the configuration module 402 processes voltage distribution data based on the target strategy to obtain timing information of the internal devices of the chip, it is specifically used to: acquire a standard cell library; and, based on the voltage distribution data, re-characterize the standard cell library based on the operating voltage of each internal device of the chip to generate timing information of the internal devices of the chip.

[0150] In one possible implementation, when the configuration module 402 processes voltage distribution data based on the target strategy to obtain timing information of internal devices of the chip, it is specifically used to: based on the voltage distribution data, call the interpolation function of the static timing analysis tool to perform interpolation calculation on the operating voltage of each internal device of the chip to obtain the updated operating voltage corresponding to each internal device of the chip; and generate timing information of internal devices of the chip based on the updated operating voltage corresponding to each internal device of the chip.

[0151] In one possible implementation, when the configuration module 402 processes voltage distribution data based on the target strategy to obtain timing information of the internal devices of the chip, it is specifically used to: based on the voltage distribution data, call the simulation circuit simulator tool to perform single-point or multi-point timing simulation on the reference cells corresponding to each internal device of the chip to generate reference coefficients; configure the reference coefficients on the timing attributes of the internal devices of the chip to generate timing information of the internal devices of the chip.

[0152] The timing analysis device 40 provided in this embodiment can execute the method provided in the above method embodiment. Its implementation principle and technical effect are similar, and will not be described in detail here.

[0153] Figure 8 A schematic diagram of the structure of the electronic device provided in this application. Figure 8 As shown, the electronic device 50 provided in this embodiment includes at least one processor 501 and a memory 502. Optionally, the device 50 further includes a communication component 503. The processor 501, memory 502, and communication component 503 are connected via a bus 504.

[0154] In a specific implementation, at least one processor 501 executes computer execution instructions stored in memory 502, causing at least one processor 501 to perform the above-described method.

[0155] The specific implementation process of processor 501 can be found in the above method embodiments, and its implementation principle and technical effect are similar. It will not be repeated here.

[0156] In the above embodiments, it should be understood that the processor can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), etc. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in this invention can be directly implemented by a hardware processor, or implemented by a combination of hardware and software modules within the processor.

[0157] The memory may include random access memory (RAM) and may also include non-volatile memory (NVM), such as at least one disk storage device.

[0158] The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of illustration, the buses shown in the accompanying drawings are not limited to a single bus or a single type of bus.

[0159] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the above-described method.

[0160] This application also provides a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, implement the above-described method.

[0161] The aforementioned readable storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk. The readable storage medium can be any available medium accessible to a general-purpose or special-purpose computer.

[0162] An exemplary readable storage medium is coupled to a processor, enabling the processor to read information from and write information to the readable storage medium. Of course, the readable storage medium can also be a component of the processor. The processor and the readable storage medium can reside in an Application Specific Integrated Circuit (ASIC). Alternatively, the processor and the readable storage medium can exist as discrete components in the device.

[0163] The division of units is merely a logical functional division; in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be indirect coupling or communication connection through some interfaces, devices, or units, and may be electrical, mechanical, or other forms.

[0164] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0165] In addition, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0166] If a function is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0167] Those skilled in the art will understand that all or part of the steps of the above-described method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When executed, the program performs the steps of the above-described method embodiments; and the aforementioned storage medium includes various media capable of storing program code, such as ROM, RAM, magnetic disks, or optical disks.

[0168] Finally, it should be noted that other embodiments of the invention will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This invention is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein, and is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of the invention is limited only by the appended claims.

Claims

1. A method of timing analysis, characterized by, include: Based on the chip design data, voltage distribution data of the internal devices of the chip is obtained. The voltage distribution data is used to characterize the operating voltage of the internal devices of the chip in different time periods. The voltage distribution data is obtained by segmenting the dynamic voltage distribution file based on the time-varying characteristics of the dynamic voltage distribution file of the internal devices of the chip. The voltage distribution data is fed back to the static timing analysis process to perform timing analysis on the chip and obtain the timing analysis results.

2. The method of claim 1, wherein, The chip design data includes at least one of the following: constraint file, design netlist, and post-simulation parameter file of design layout. The step of obtaining voltage distribution data of internal components of the chip based on chip design data includes: Input the chip design data into a static timing analysis tool to obtain the timing window information of the internal components of the chip. The time window information is input into a voltage simulation tool to generate a dynamic voltage distribution file. The dynamic voltage distribution file characterizes the voltage drop distribution of each internal device of the chip under the target time window. The target time window is the time window when the overall voltage drop of the chip is the maximum and / or greater than the voltage drop threshold. Based on the dynamic voltage distribution file, voltage distribution data is generated.

3. The method of claim 2, wherein, The step of generating voltage distribution data based on the dynamic voltage distribution file includes: Based on the dynamic voltage distribution file, waveform simulation is performed to obtain the voltage drop waveform; The time interval is obtained based on the changing trend of the voltage drop waveform; The voltage drop waveform is cut into at least two consecutive segments based on the time interval, and voltage simulation is performed on each segment to obtain the operating voltage of the internal devices of the chip within the corresponding time interval. Voltage distribution data is generated based on the operating voltage of the internal components of the chip within the corresponding time interval.

4. The method according to claim 1, characterized in that, The step of feeding back the voltage distribution data to the static timing analysis process to perform timing analysis on the chip and obtain timing analysis results includes: The voltage distribution data is processed based on the target strategy to obtain the timing information of the internal devices of the chip, and the timing information represents the actual operating voltage of the internal devices of the chip. The timing information of the internal devices of the chip is fed back to the static timing analysis process to perform timing verification and obtain timing analysis results; The target strategy includes at least one of the following: Call the library characterization tools, call the interpolation function of the static timing analysis tools, and call the simulation circuit simulator tools.

5. The method according to claim 4, characterized in that, The step of processing the voltage distribution data based on the target strategy to obtain the timing information of the internal devices of the chip includes: The library characterization tool is executed for internal chip devices in high-power regions; the interpolation function is executed for internal chip devices in low-power regions; and the simulation circuit simulator tool is executed for devices in the critical path.

6. The method according to claim 4, characterized in that, The step of processing the voltage distribution data based on the target strategy to obtain the timing information of the internal devices of the chip includes: Obtain the standard cell library; Based on the voltage distribution data, the standard cell library is re-characterized based on the operating voltage of each chip's internal devices, and timing information of the chip's internal devices is generated.

7. The method according to claim 4, characterized in that, The step of processing the voltage distribution data based on the target strategy to obtain the timing information of the internal devices of the chip includes: Based on the voltage distribution data, the interpolation function of the static timing analysis tool is called to interpolate and calculate the operating voltage of the internal devices of each chip, so as to obtain the updated operating voltage of the internal devices of each chip. Based on the updated operating voltage corresponding to each internal device of the chip, the timing information of the internal devices of the chip is generated.

8. The method according to claim 4, characterized in that, The step of processing the voltage distribution data based on the target strategy to obtain the timing information of the internal devices of the chip includes: Based on the voltage distribution data, the simulation circuit simulator tool is called to perform single-point or multi-point timing simulation on the reference units corresponding to the internal devices of each chip, and reference coefficients are generated. The reference coefficient is configured on the timing attributes of the internal devices of the chip to generate the timing information of the internal devices of the chip.

9. A time series analysis device, characterized in that, include: The acquisition module is used to obtain voltage distribution data of the internal devices of the chip based on the chip design data. The voltage distribution data is used to characterize the operating voltage of the internal devices of the chip in different time periods. The configuration module is used to feed back the voltage distribution data to the static timing analysis process, perform timing analysis on the chip, and obtain timing analysis results.

10. An electronic device, characterized in that, include: Memory, processor; The memory stores computer-executed instructions; The processor executes computer execution instructions stored in the memory, causing the processor to perform the method as described in any one of claims 1-8.

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