A machine learning based high efficiency integrated circuit design for test method
Patent Information
- Application Number
- CN202610910138.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-06-23
- Publication Date
- 2026-09-15
Smart Images
Figure CN122759040A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of integrated circuit testability design technology, specifically relating to a high-efficiency integrated circuit testability design method based on machine learning. Background Technology
[0002] As the scale and integration of integrated circuits continue to increase, the internal logic structure, clock structure, and test structure of chips are becoming increasingly complex. To ensure fault detection capabilities after chip manufacturing, design for testability (CBT) is typically introduced during the design phase. In existing integrated circuit design flows, CBT solutions usually rely on design rules, engineering experience, or default strategies of EDA tools. While this approach can meet basic test coverage requirements, it often struggles to simultaneously balance test efficiency and test power consumption when dealing with large-scale, complex circuits. For example, increasing test points to improve fault detection capabilities may reduce the number of test vectors, but it may also introduce additional area and routing burden; adjusting scan cell assignments to balance scan chains may improve test shift efficiency, but it may not necessarily reduce peak power consumption during the test capture phase; setting low-power constraints to reduce test power consumption may lead to an increase in the number of test vectors or a decrease in fault detection efficiency.
[0003] Furthermore, test power consumption exhibits distinct spatiotemporal distribution characteristics. Some nodes switch frequently but have light loads, contributing little to peak power consumption; others switch infrequently but have heavy loads, potentially causing significant power surges within specific capture windows; and in some regions, multiple medium-power nodes may switch over within the same capture window, creating localized power hotspots. Traditional design-for-test (DTPT) flows often struggle to integrate logical connectivity, initial DTPT configuration, and test power distribution for unified evaluation, resulting in a lack of comprehensive prediction of the number of subsequent test vectors, peak test power consumption, and design costs when selecting candidate test structures or constraints.
[0004] For high-performance or low-power chips, excessively high peak power consumption during testing can cause issues such as IR-drop, localized overheating, timing anomalies, or false failures in test modes. If the power consumption is found to be unacceptable after the testability structure (TestSimple) has been inserted, it is usually necessary to readjust the test points, scan chain, capture clock, or test vector generation constraints, resulting in multiple iterations and increasing design cycle and verification costs. Especially when backend implementation constraints gradually tighten, later modifications to the TestSimple can also have a cascading effect on area, routing, and timing.
[0005] Therefore, there is an urgent need for a high-efficiency integrated circuit testability design method based on machine learning to solve the above problems. Summary of the Invention
[0006] The purpose of this invention is to provide a high-efficiency integrated circuit testability design method based on machine learning, which solves the technical problems in the prior art where, when generating and adjusting integrated circuit testability design schemes, it is impossible to predict and evaluate candidate testability design operations based on logic connection relationships, initial testability design schemes, and test power consumption distribution. This leads to difficulties in coordinating the number of test vectors, peak test power consumption, and design costs, resulting in strong blind insertion of testability structures, high test power consumption risks, and low design iteration efficiency.
[0007] To achieve the above objectives, the present invention adopts the following technical solution: A high-efficiency integrated circuit testability design method based on machine learning includes: Step 1: Based on the logic connection relationship of the integrated circuit under test, the initial testability design scheme, and the test power distribution, construct a testability feature map; Step 2: Based on the preset testability design change rules, generate candidate testability design operations in the testability feature map, where each candidate testability design operation corresponds to changing a testability design configuration in the initial testability design scheme; Step 3: Input the testability feature map and candidate testability design operations into the machine learning prediction model to determine the predicted value of test vector reduction, the predicted value of test peak power consumption reduction, and the predicted value of design cost corresponding to each candidate testability design operation. Step 4: Based on the predicted values of test vector reduction, test peak power reduction, and design cost prediction, select the target testability design operation set from the candidate testability design operations. The target testability design operation set satisfies the following conditions: the number of predicted test vectors is less than the number of initial test vectors, and the predicted test peak power is less than the initial test peak power. Step 5: Generate testability design implementation constraints based on the target testability design operation set, and complete the insertion of testability structures and generation of test vectors according to the testability design implementation constraints; Step 6: Verify the integrated circuit after the testability structure insertion is completed, obtain the actual number of test vectors and the actual peak power consumption, and use the actual number of test vectors and the actual peak power consumption as feedback samples to update the machine learning prediction model.
[0008] Furthermore, a testability feature map is constructed. The specific method is as follows: the gate-level netlist of the integrated circuit under test under the initial testability design scheme is parsed, the cell instance or the specified output terminal of the cell instance is taken as the graph node, the connection relationship formed between cell instances along the signal propagation direction is taken as the directed edge, and the configuration code determined by the initial testability design scheme and the power weight determined by the test power distribution are written into the corresponding graph node to obtain the testability feature map.
[0009] Furthermore, according to the preset testability design change rules, the specific method is as follows: read the configuration code and power consumption weight of each graph node in the testability feature graph, determine the graph node whose configuration code meets the preset changeable conditions as the node to be changed, and generate candidate testability design operations for each node to be changed according to the preset configuration item change table. The candidate testability design operations include the node to be changed identifier, the configuration item to be changed, and the changed configuration value.
[0010] Furthermore, candidate testability design operations are generated in the testability feature graph. The specific method is as follows: taking the node to be changed as the operation object, the set of associated nodes that have a signal propagation relationship with the node to be changed is determined according to the directed edges, the node to be changed identifier, the set of associated nodes, the changed configuration item and the changed configuration value are combined into an operation description, and the operation description that meets the preset design constraints is determined as a candidate testability design operation.
[0011] Furthermore, the predicted test vector reduction value corresponding to each candidate testability design operation is determined by: converting the candidate testability design operation into an operation code, and inputting the operation code and the node features of the corresponding graph nodes in the testability feature map into the machine learning prediction model to obtain the number of predicted test vectors after executing the candidate testability design operation; the difference between the initial number of test vectors and the predicted number of test vectors is determined as the predicted test vector reduction value.
[0012] Furthermore, the predicted reduction value of the test peak power consumption corresponding to each candidate testability design operation is determined by the following method: converting the candidate testability design operation into an operation code, determining the power consumption feature based on the power consumption weight of the graph node corresponding to the candidate testability design operation, inputting the operation code and power consumption feature into a machine learning prediction model to obtain the predicted test peak power consumption after executing the candidate testability design operation; and determining the difference between the initial test peak power consumption and the predicted test peak power consumption as the predicted reduction value of the test peak power consumption.
[0013] Furthermore, the predicted design cost value corresponding to each candidate testability design operation is determined by the following method: converting the candidate testability design operation into an operation code, and generating a cost feature based on the node characteristics of the graph node corresponding to the candidate testability design operation, the changed configuration item, and the changed configuration value; inputting the operation code and cost feature into a machine learning prediction model to obtain the predicted design resource consumption after executing the candidate testability design operation; and determining the predicted design cost value based on the predicted design resource consumption.
[0014] Furthermore, the target testable design operation set is selected from the candidate testable design operations. The specific method is as follows: based on the predicted value of test vector reduction, the predicted value of test peak power consumption reduction, and the predicted value of design cost, the candidate testable design operations are evaluated for benefits according to a preset objective function. Under the conditions that the number of predicted test vectors is less than the number of initial test vectors, the predicted test peak power consumption is less than the initial test peak power consumption, and the preset design constraints are met, the candidate testable design operations whose benefit evaluation results meet the preset selection conditions are determined as the target testable design operation set.
[0015] Furthermore, testability design implementation constraints are generated based on the target testability design operation set. The specific method is as follows: read the change object, the changed configuration item, and the changed configuration value corresponding to each target testability design operation in the target testability design operation set; determine the testability structure insertion position based on the change object; generate the corresponding testability structure insertion constraints and test vector generation constraints based on the changed configuration item and the changed configuration value; and write the testability structure insertion position, testability structure insertion constraints, and test vector generation constraints into the constraint file to obtain the testability design implementation constraints.
[0016] Furthermore, the feature is that the integrated circuit after the testability structure insertion is completed is verified. The specific method is as follows: the testability structure connectivity verification and test vector simulation are performed on the integrated circuit after the testability structure insertion is completed; after the verification is passed, the test vector generation results are counted to obtain the actual number of test vectors, and the circuit power consumption under the action of the test vectors is analyzed to obtain the actual peak power consumption; feedback samples are generated based on the actual number of test vectors, the actual peak power consumption, and the corresponding target testability design operation set, and the machine learning prediction model is updated using the feedback samples.
[0017] In summary, due to the adoption of the above technical solution, the beneficial effects of the present invention are: 1. This invention constructs a testability feature map based on the logic connection relationship of the integrated circuit under test, the initial testability design scheme, and the test power consumption distribution, and writes the configuration code and power consumption weight into the corresponding graph nodes. This makes the testability design evaluation no longer rely solely on a single rule or human experience, but can simultaneously reflect the circuit structure, test configuration status, and test power consumption characteristics, thereby improving the accuracy and relevance of candidate testability design operation generation. 2. This invention inputs the testability feature map and candidate testability design operations into a machine learning prediction model to predict the test vector reduction effect, the test peak power consumption reduction effect, and the design cost, respectively. This enables the system to predict the implementation effect of different change operations before the testability structure is actually inserted, thereby reducing the area, wiring, and timing overhead caused by blindly inserting test structures. 3. This invention selects a set of target testability design operations that meet the requirements of reducing the number of test vectors, reducing peak power consumption, and preset design constraints based on the prediction results. After inserting the testability structure, the machine learning prediction model is updated using the actual number of test vectors and the actual peak power consumption, forming a closed-loop optimization process of prediction, implementation, verification, and feedback. This reduces the number of design iterations and improves the efficiency and engineering applicability of integrated circuit testability design. Attached Figure Description
[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0019] Figure 1 The diagram illustrates the steps of a high-efficiency integrated circuit testability design method based on machine learning according to the present invention. Figure 2 A flowchart illustrating the construction process of the testability feature map of the present invention is shown; Figure 3 A flowchart illustrating the generation process of the candidate testability design operation of the present invention is shown. Detailed Implementation
[0020] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0021] This embodiment uses an integrated circuit under test (ICD) as an example. The ICD has undergone logic synthesis and includes a gate-level netlist, an initial design for testability (DPT), and a power consumption distribution obtained from simulation based on the initial test vectors. The initial DPT may include scan chain partitioning, test point configuration, capture clock grouping, test mode control signal configuration, and test vector generation parameters.
[0022] For ease of description, the gate-level netlist of the integrated circuit under test is denoted as N, the initial testability design scheme is denoted as D0, the initial number of test vectors is denoted as V0, and the initial peak power consumption is denoted as P0. The testability feature graph constructed from the integrated circuit under test is denoted as G=(X,E), where X is the set of graph nodes and E is the set of directed edges.
[0023] like Figure 1The method for high-efficiency integrated circuit testability design based on machine learning, as shown, specifically includes the following steps: Step 1: Based on the logic connection relationship of the integrated circuit under test, the initial testability design scheme, and the test power distribution, construct a testability feature map; like Figure 2 As shown, a testability feature map G is constructed based on the logic connection relationship of the integrated circuit under test, the initial testability design scheme, and the test power distribution. Specifically, the gate-level netlist N of the integrated circuit under test (ICD) under the initial design for testability (D0) is analyzed, and the cell instances in the gate-level netlist are used as graph nodes. These cell instances can be flip-flops, combinational logic gates, scan multiplexers, test control units, clock-gated units, or candidate cells into which test points can be inserted. For the connections formed between cell instances along the signal propagation direction, corresponding directed edges are established. For hierarchical netlists, the hierarchical ports can be expanded first, and then the connection edges between the actual driver units and the actual load units can be established. For scan paths, the connection relationships in the scan input to scan output direction can also be written as supplementary edges into the testability feature graph. The testability feature graph constructed in this way not only reflects the functional logic propagation relationship, but also reflects the scan propagation relationship in the test structure. Each graph node Write node features Node characteristics At least include configuration coding and power consumption weight Among them, configuration coding This is used to indicate the testability configuration status of the graph node in the initial testability design scheme D0, such as whether it belongs to a scan chain, its scan chain number, whether an observation test point has been configured, whether a control test point has been configured, its capture clock group, and whether it is subject to test mode gating constraints. In this embodiment, to ensure that the power consumption weight not only reflects whether a single graph node flips, but also reflects the actual contribution of that flip to the peak power consumption during testing, the graph node... Power consumption weight Set by switching rate Load-related quantities and local power consumption concentration The comprehensive characteristic quantity determined jointly.
[0024] Among them, graph nodes This corresponds to a cell instance in the gate-level netlist or a specified output of that cell instance. For a cell instance with multiple outputs, each output can be treated as a separate graph node, or the main output associated with the test mode can be selected as the feature acquisition object for that graph node.
[0025] Graph Node Switching rate under the influence of the initial test vector , is used to indicate how frequently a graph node undergoes a valid logical flip during the initial test vector set T0.
[0026] In one implementation, the initial test vector set T0 is divided into multiple capture windows. , ... The starting sampling time of the h-th capture window is denoted as . The end time of sampling is recorded as Graph nodes exist The output logic value at time is denoted as ,exist The output logic value at time is denoted as .
[0027] For the h-th capture window If the graph nodes A change in the output logic value from 0 to 1 or from 1 to 0 within the capture window is considered a valid switch. Definition: , representing a graph node In the capture window A valid handover occurs within the timeframe, i.e. ; , representing a graph node In the capture window No effective handover occurred within the period, i.e. .
[0028] This embodiment only counts valid logic flips at the boundaries of the capture window, excluding logic flips generated during the scan-shift phase. This processing ensures that the switching rate characteristics correspond to the peak capture power consumption, avoiding interference from high-frequency flips during the scan-shift process that could affect peak power consumption determination.
[0029] The h-th capture window The window power consumption is denoted as , This is obtained from the gate-level power consumption analysis results under the initial test vector. The maximum window power consumption in each capture window is denoted as... The h-th capture window Window weight Determined according to the following formula: in, This is the preset peak window magnification factor, with a value greater than 0; Graph Node Switching rate under the influence of the initial test vector Determined according to the following formula: The resulting switching rate The peak window weighted switching rate is used. When a graph node performs a valid handover within the high-power capture window, the switching rate is adjusted accordingly. Its contribution is greater than its contribution when an effective switch occurs within the low-power capture window.
[0030] Graph Node Load-related quantities Used to characterize the load intensity driven when a node in the graph undergoes a valid logical flip.
[0031] Load-related quantities With switching rate Different meanings: Switching rate Reflects the frequency of flipping, load-related quantities This reflects whether the load generated by each flip is heavy.
[0032] In one implementation, load-related quantities According to the graph nodes The output load capacitance, the number of direct fan-outs, and the additional test structure load in the test mode are jointly determined. The test structure load includes additional loads introduced in the test mode such as scan multiplexers, test points, test control signal branches, and low-power gated logic, specifically expressed as follows: in, Represents graph nodes The output load capacitor, Represents graph nodes The direct fan-out quantity. Represents graph nodes The number of additional test structure loads driven in test mode. , and This represents the maximum value of the parameter corresponding to each node in the measurability feature graph. When a certain maximum value is zero, that term is set to zero. This is the normalized load-related quantity; the larger the value, the stronger the graph node. The heavier the electrical load and test structure load during a flip, the greater the load.
[0033] Local power consumption concentration Used to represent graph nodes Does a concentrated flipping phenomenon exist within the local area? Specifically, using graph nodes... Centered on the graph, the set of associated nodes is determined based on the directed edges in the measurability feature graph, and it is statistically analyzed whether multiple graph nodes in this neighborhood frequently undergo effective switching within the same or similar capture windows. If graph nodes... If a graph node and its neighboring nodes are concentrated and flipped within a high-power capture window, then the region where the node is located is considered to have a high local power concentration. The neighborhood range can be determined based on graph distance; or, when physical layout information is available, it can be determined in conjunction with physical distance. For graph nodes The set of associated nodes, determined by the directed edges in the measurability feature graph, may include nodes related to the graph. Predecessor and successor nodes whose distance does not exceed the preset map distance, while using the switching rate. Window weights in and effective switching flag Based on this, the concentration of power consumption in local areas Determined according to the following formula: in, Represents graph nodes Did a valid switch occur within the h-th capture window? Representing neighboring nodes The load-related quantity, when When it is zero, =0, if graph node If a valid handover occurs within the high-power capture window, and its neighboring nodes also flip within the same capture window, then... Larger; if the graph nodes Although a flip occurs, if neighboring nodes do not flip synchronously, or if synchronous flips mainly occur within the low-power capture window, then... The concentration of power consumption in the local area is relatively small. Therefore, the concentration of power consumption in the local area is low. It can reflect local power consumption hotspots, rather than just the switching behavior of a single node.
[0034] Power consumption weight Used to represent graph nodes The contribution of power consumption to peak power consumption in test mode, power consumption weight. The power weight is determined by switching rate, load-related parameters, and power concentration in local areas. Using formula This indicates that a, b, and c are preset weight coefficients, and a + b + c = 1. Norm() represents normalization.
[0035] Step 2: Based on the preset testability design change rules, generate candidate testability design operations in the testability feature map, where each candidate testability design operation corresponds to changing a testability design configuration in the initial testability design scheme; like Figure 3 As shown, according to the preset testability design change rules, candidate testability design operations are generated in the testability feature map G, where each candidate testability design operation corresponds to an modification of the initial testability design scheme. One of the testability design configurations was changed.
[0036] Specifically, reading the measurability feature map Nodes in each diagram Configuration coding and power consumption weight According to the configuration code Determine whether the node in the diagram belongs to the category of nodes where testability design configuration changes are permitted. If the node in the diagram... The corresponding cell instance is not a hard macro boundary cell, nor is it a reserved cell for which test structures are prohibited from insertion, and its configuration coding... If this indicates that the graph node has a modifiable testability design configuration, then the graph node will be... This node has been identified as a node to be changed.
[0037] In one implementation, the preset changeable conditions include at least one of the following: graph nodes No observation test points were configured, but the location is in a logic region where fault observability is insufficient; graph node No control test points were configured, but the area is located in a logic region with insufficient fault controllability; Graph node The length of the scan chain exceeds or falls below the preset equalization range; graph nodes The capture clock group to which it belongs has a high power weight under the initial test vector; or a graph node. Power consumption weight Power consumption weight is greater than the preset power consumption weight threshold. The decision to change is not made solely based on configuration codes; the actual assessment must be made in conjunction with the configuration codes. This avoids misclassifying high-power nodes that cannot be inserted into test structures as changeable nodes.
[0038] After identifying the nodes to be changed, candidate testability design operations are generated for each node according to a preset configuration item change table. The preset configuration item change table records the testability design configuration items that are allowed to be changed and their corresponding changed configuration values. The testability design configuration items include at least one of the following: observation test point configuration, control test point configuration, scan chain affiliation configuration, capture clock grouping configuration, test mode gating configuration, and test vector generation low-power constraint configuration. For the graph nodes to be changed The generated candidate testability design operation can be represented as ,in This indicates a graph node. The generated t-th candidate testability design operation, express Node identifier, This indicates the configuration item that has been changed. This indicates the changed configuration value. For graph nodes The set of associated nodes is used as the operation object. The predecessor node is traced along the directed edge in the signal input direction, and the successor node is extended along the directed edge in the signal output direction. Predecessor and successor nodes that have a signal propagation relationship are considered as a set of associated nodes; Will The components are combined into an operation description, and it is determined whether the operation description meets the preset design constraints. The preset design constraints include at least one of the following: timing constraints, scan chain length constraints, clock domain boundary constraints, number of test points constraints, test control signal fan-out constraints, and hard macro boundary constraints.
[0039] For example, if If it is located on a cross-clock domain path, it will not be configured as a cross-clock capture test point; if the node to be changed If the timing margin of the path is lower than a preset margin threshold, no control test point operation that would increase the combined path delay will be generated. If the length of a scan chain has reached a preset upper limit, no operation will be generated to incorporate a new scan unit into that scan chain. After the above screening, operation descriptions that meet the preset design constraints are determined as candidate testability design operations. All candidate testability design operations constitute the candidate testability design operation set O, denoted as... , where m represents the number of candidate testability design operations.
[0040] Step 3: Input the testability feature map and candidate testability design operations into the machine learning prediction model to determine the predicted value of test vector reduction, the predicted value of test peak power consumption reduction, and the predicted value of design cost corresponding to each candidate testability design operation. Before the machine learning prediction model is used to predict candidate testability design operations, the processor constructs a training sample library. This training sample library includes testability design samples from multiple historical integrated circuits, and / or samples formed from the same integrated circuit at different testability design iteration stages. Each training sample includes a historical gate-level netlist, a historical initial testability design scheme, historical test power distribution, a historical testability feature map constructed from the above data, a set of historical candidate testability design operations or historical target testability design operations, and the actual number of test vectors, actual peak power consumption, and actual design resource usage after executing the corresponding testability design operation.
[0041] Specifically, the actual number of test vectors after performing the design for testability (BPT) operation is used as the supervision label for the test vector prediction branch; the actual peak power consumption after performing the BPT operation is used as the supervision label for the peak power consumption prediction branch; and the actual design resource consumption after performing the BPT operation is used as the supervision label for the design cost prediction branch. The actual design resource consumption includes at least one of the following: the number of new test points, the area of new logic units, the complexity of scan chain adjustments, the number of new fan-outs in test control signals, and the number of new rules in the constraint file.
[0042] Input the testability feature map G and the candidate testability design operation set O into the machine learning prediction model to determine the predicted value of test vector reduction, the predicted value of test peak power reduction, and the predicted value of design cost corresponding to each candidate testability design operation.
[0043] For any candidate testability design operation First, convert it into operation code. Operation codes are used to transform discrete configuration change information in candidate testability design operations into input features that can be recognized by machine learning prediction models. Specifically, operation codes can be generated based on the identifier of the node to be changed, the configuration item being changed, the changed configuration value, and the aggregated features of the associated node set, for example... ,in This indicates encoding processing, which can include one-hot encoding, integer encoding, normalized concatenation, or embedded encoding.
[0044] In one implementation, candidate testability design operation Act on graph nodes The node characteristics of this graph are: The set of associated nodes is The aggregation feature of the set of associated nodes is represented as: in Represents the set of associated nodes Chinese map nodes Node characteristics, This indicates the number of graph nodes in the set of associated nodes.
[0045] The machine learning prediction model can employ graph neural network models, multilayer perceptron models, gradient boosting tree models, or models formed by combining graph feature extraction networks and regression prediction networks. In this embodiment, the machine learning prediction model is preferably a model with a shared graph feature extraction layer and multiple prediction output branches.
[0046] During training, the machine learning prediction model employs a multi-task supervised training approach for parameter updates. Let Vk be the actual number of test vectors corresponding to the k-th training sample, Pk be the actual peak power consumption, and Ck be the actual design resource usage. The predicted number of test vectors, predicted peak power consumption, and predicted design resource usage output by the machine learning prediction model are respectively... , and The model training loss function L is determined according to the following formula: Where MSE represents mean squared error, α, β, and γ represent the weighting coefficients of the test vector prediction loss, test peak power prediction loss, and design cost prediction loss, respectively, δ represents the regularization weighting coefficient, and R(θ) represents the regularization term for the model parameter θ. Through the above loss function, the machine learning prediction model can simultaneously learn the impact of candidate testability design operations on the number of test vectors, test peak power consumption, and design resource consumption.
[0047] The shared graph feature extraction layer is used to extract the correlation features between logical connection relationships, testability configuration state and test power distribution from the testability feature graph G; multiple prediction output branches are used to output the number of predicted test vectors, the peak power consumption of the predicted test and the design resource usage, respectively.
[0048] Before the machine learning prediction model is applied for the first time, a training sample library is constructed. This training sample library includes multiple historical integrated circuits or multiple historical testability design iteration samples of the same integrated circuit. Each training sample includes a historical testability feature map, historical candidate testability design operations, the actual number of test vectors after executing the historical candidate testability design operation, the actual peak power consumption during testing, and the actual design resource consumption. The actual number of test vectors, the actual peak power consumption during testing, and the actual design resource consumption are used as supervision labels for the test vector prediction branch, the peak power consumption prediction branch, and the design cost prediction branch, respectively, to train the machine learning prediction model.
[0049] For candidate testability design operations The machine learning prediction model outputs the number of predicted test vectors after performing the candidate testability design operation, denoted as . Trial vectors reduce predicted values Using formula It means that among them Indicates the initial number of test vectors, if This indicates the execution of candidate testability design operations. It is expected that this will reduce the number of test vectors; if This indicates that the candidate testability design operation does not contribute positively to the number of test vectors, or may lead to an increase in the number of test vectors. To determine the predicted reduction in peak power consumption during testing, the operation is first designed based on candidate testability. Corresponding graph nodes Power consumption weight Determine power consumption characteristics. To ensure that power consumption characteristics reflect both the power consumption contribution of the operating node itself and the power consumption level of its neighborhood, power consumption characteristics utilize... It is confirmed that, among them, Represents the set of associated nodes Chinese map nodes The power consumption weight. This power consumption feature still uses the power consumption weight obtained in step one. There was no reintroduction of an independent power consumption evaluation system. Operation code and power consumption characteristics Input the machine learning prediction model to obtain the execution of candidate testability design operations. The predicted peak power consumption after the test is denoted as Test peak power consumption reduced predicted value ,in, This indicates the initial peak power consumption during testing. This indicates that the candidate design-for-testability operation is expected to reduce peak power consumption during testing; if This indicates that the candidate testability design operation may not reduce the peak power consumption during testing, or may even cause the peak power consumption during testing to increase.
[0050] The determination of the predicted design cost is based on the candidate testability design operation. Corresponding graph nodes The node characteristics, the changed configuration items, and the generation cost characteristics of the changed configuration values. , represented as , Operation code and cost characteristics Input the machine learning prediction model to obtain the predicted design resource consumption after performing the candidate testability design operation, denoted as . Predicted design resource usage can include at least one of the following: the number of new test points, the area of new logic units, the complexity of scan chain adjustments, the number of new fan-outs in test control signals, and the number of new rules in the constraint file. Based on the predicted design resource usage... Determine the predicted design cost ,For example: ,in This indicates normalization. The normalized predicted design cost. The larger the value, the higher the area, routing, test control, or implementation complexity required for the candidate testability design operation.
[0051] Step 4: Based on the predicted values of test vector reduction, test peak power reduction, and design cost prediction, select the target testability design operation set from the candidate testability design operations. The target testability design operation set satisfies the following conditions: the number of predicted test vectors is less than the number of initial test vectors, and the predicted test peak power is less than the initial test peak power. Based on the predicted values of test vector reduction, the predicted values of test peak power consumption reduction, and the predicted values of design cost, the target testability design operation set is selected from the candidate testability design operations.
[0052] Candidate testability design operations are screened for effectiveness. Candidate operations that do not reduce the number of test vectors or the peak power consumption after execution are not given priority. Candidate operations that can improve the number of test vectors or the peak power consumption but cause the design cost to significantly exceed the preset constraints are not directly added to the target testability design operation set.
[0053] After the validity screening is completed, the remaining candidate testability design operations are evaluated for their benefits according to the evaluation rules corresponding to the preset objective function. This evaluation rule does not compare a single predicted value, but comprehensively considers the following factors: the contribution of the candidate operation to the reduction of the number of test vectors, the contribution of the candidate operation to the reduction of peak power consumption, the design resource consumption introduced by the candidate operation, whether the candidate operation applies to high-power weight nodes or power-concentrated regions, and whether the candidate operation improves the controllability or observability of difficult-to-test logic regions.
[0054] In one implementation, candidate testability design operations are categorized into high-priority, medium-priority, and low-priority operations. If a candidate operation simultaneously results in a significant reduction in both the number of test vectors and peak power consumption, and the corresponding design cost is within acceptable limits, it is classified as a high-priority operation. If a candidate operation significantly improves only one of the number of test vectors or peak power consumption, but the other still meets the non-degradation requirement, it is classified as a medium-priority operation. If a candidate operation offers only a small improvement or requires a high design cost to implement, it is classified as a low-priority operation.
[0055] The target testability design operation set is formed step by step according to priority. For each candidate operation to be added, it is determined whether it has a configuration conflict with the already selected target testability design operations. The configuration conflict includes: multiple candidate operations acting on the same configuration item of the same graph node but with different configuration values after modification; multiple candidate operations assigning the same scan unit to different scan chains; the capture clock groups corresponding to multiple candidate operations being mutually exclusive; or multiple candidate operations repeatedly inserting the same functional test structure in the same logic cone.
[0056] If a configuration conflict exists, the candidate operation with higher overall benefits, lower design costs, or more significant improvement in peak power consumption during testing is retained. If no configuration conflict exists, it is further determined whether the operation combination formed after adding the candidate operation still satisfies the preset design constraints. The preset design constraints include scan chain length constraints, number of test points constraints, test control signal fan-out constraints, timing margin constraints, clock domain boundary constraints, and hard macro boundary constraints.
[0057] During the formation of the target testability design operation set, a marginal benefit assessment is performed. If a candidate operation has a high benefit when evaluated individually, but its contribution to the incremental reduction of the number of test vectors or the reduction of peak power consumption when added to the existing target operations is small, then it is not added to the target testability design operation set. This process avoids repeatedly inserting test structures with similar benefits in the same local area, thereby reducing unnecessary area and wiring overhead.
[0058] When selecting the target testability design operation set, the processor sequentially attempts to add candidate testability design operations according to the benefit evaluation results, generating a temporary operation set after each addition. The configuration encoding of the corresponding graph nodes is updated based on the temporary operation set to obtain a temporary testability feature map. The temporary testability feature map and the temporary operation set encoding are input into a machine learning prediction model to obtain the combined predicted test vector count, combined predicted test peak power consumption, and combined predicted design cost after executing the temporary operation set. A candidate testability design operation is added to the target testability design operation set only if the combined predicted test vector count is less than the initial test vector count, the combined predicted test peak power consumption is less than the initial test peak power consumption, and the combined predicted design cost does not exceed a preset design cost threshold.
[0059] The final set of target testability design operations should satisfy the following conditions: under the prediction results of the machine learning prediction model, after executing the set of target testability design operations, the number of test vectors of the integrated circuit under test is less than the initial number of test vectors, and the peak power consumption during testing is less than the initial peak power consumption during testing. Simultaneously, there are no unexecutable configuration conflicts among the target operations in the target testability design operation set, and the overall design cost is within the allowable range of the preset design constraints.
[0060] Through the above selection method, this embodiment makes a comprehensive trade-off between test efficiency, test power consumption and design cost, so that the final selected set of target testability design operations is more suitable for subsequent engineering implementation.
[0061] Step 5: Generate testability design implementation constraints based on the target testability design operation set, and complete the insertion of testability structures and generation of test vectors according to the testability design implementation constraints; Based on the target testability design operation set, testability design implementation constraints are generated, and testability structure insertion and test vector generation are completed according to the testability design implementation constraints.
[0062] The system reads the change object, the changed configuration item, and the changed configuration value corresponding to each target testability design operation in the target testability design operation set. The change object is used to locate the specific unit instance, port, scan unit, test control node, or capture clock control node in the gate-level netlist; the changed configuration item is used to determine the type of testability design action to be performed; and the changed configuration value is used to determine the specific insertion method, connection method, or constraint content.
[0063] When the target testability design operation configures observation test points, the insertion position of the observation test points is determined based on the changed object, and observation test point insertion constraints are generated. These constraints include the observed node, the observation test point type, the test mode enable condition, and the connection relationship with the scan observation path.
[0064] When the design for testability involves configuring control test points, the insertion location of the control test points is determined based on the changed object, and control test point insertion constraints are generated. These constraints include the controlled node, the source of control values in the test mode, the bypass conditions in the functional mode, and the corresponding test control signal connection method.
[0065] When the target testability design operation involves adjusting scan chain affiliation, the target scan chain is determined based on the changed configuration values, and scan chain reorganization constraints are generated. These constraints include scan cell identifiers, target scan chain numbers, scan chain connection sequences, and scan chain length limits. This process can improve scan chain balance or reduce test relocation costs without compromising the accessibility of the original scan structure.
[0066] When the target testability design operation involves adjusting the capture clock group, a capture clock group constraint is generated based on the changed configuration value. This constraint is used to limit the activation relationship of different capture clock groups during the test capture phase, preventing high-power regions from concentrating and flipping within the same capture window, thereby reducing the risk of peak power consumption during testing.
[0067] When the target testability design operation generates low-power constraints for test vectors, test vector generation constraints are generated based on the changed object and its associated node set. These constraints may include low-power padding constraints, local logic cone padding value limits, capture window switching limits, and test mode gating control conditions.
[0068] The testability structure insertion location, testability structure insertion constraints, and test vector generation constraints are written into a constraint file to obtain the testability design implementation constraints. This constraint file can be a unified constraint file, or it can be split into a structure insertion constraint file and a test vector generation constraint file according to the tool workflow.
[0069] The structure insertion constraint is input into the Design for Testability (DPT) insertion tool to perform DPT structure insertion on the integrated circuit under test, resulting in the inserted gate-level netlist. Then, the inserted gate-level netlist and test vector generation constraints are input into the test vector generation tool to generate the corresponding test vector set.
[0070] For target testability design operations that specific EDA tools cannot directly recognize, they are converted into equivalent tool command sequences. For example, observation test point configuration is converted into a test point insertion command, scan chain attribution adjustment is converted into a scan chain reorganization command, and capture clock group configuration is converted into a low-power ATPG clock constraint command. This conversion only changes the implementation expression and does not change the technical meaning of the target testability design operation.
[0071] Step 6: Verify the integrated circuit after the testability structure insertion is completed, obtain the actual number of test vectors and the actual peak power consumption, and use the actual number of test vectors and the actual peak power consumption as feedback samples to update the machine learning prediction model.
[0072] The integrated circuit after the testability structure insertion is completed is verified to obtain the actual number of test vectors and the actual peak power consumption. The actual number of test vectors and the actual peak power consumption are then used as feedback samples to update the machine learning prediction model.
[0073] Perform testability and structural connectivity verification on the inserted gate-level netlist. This verification confirms that the newly added or adjusted scan chains, observation test points, control test points, test control signals, test mode gating units, and capture clock grouping constraints can all be correctly accessed and controlled in test mode.
[0074] The connectivity verification of the testability structure includes: checking whether the connection between the scan chain input and the scan chain output is continuous; checking whether the newly added test point is connected to a valid test control signal; checking whether the test mode enable signal can cover the corresponding test structure; checking whether the capture clock group is consistent with the test vector generation constraint; and checking whether the newly added test structure in the functional mode is in a bypass state or a non-interference state.
[0075] After the connectivity verification of the testability structure is passed, test vector simulation is performed on the test vector set. Test vector simulation confirms that the generated test vectors can be correctly applied to the inserted gate-level netlist and obtain effective fault detection results. After the test vector simulation passes, the number of vectors in the test vector set is counted and taken as the actual number of test vectors.
[0076] Power consumption analysis is performed on the switching activity data generated by the test vector simulation to obtain the inserted test power consumption distribution, and the actual test peak power consumption is determined from it. The actual test peak power consumption can be determined by the power consumption statistics of each capture window, or it can be calculated by a gate-level power analysis tool based on the switching activity file, cell power consumption model, and timing window information.
[0077] Feedback samples are generated based on the actual number of test vectors, the actual peak power consumption during testing, and the corresponding target testability design operation set.
[0078] After the feedback sample is generated, the processor appends it to the training sample library instead of directly replacing the original training samples. The processor compares the previously output predicted test vector count, predicted peak power consumption, and predicted design resource usage of the machine learning prediction model with the verified actual test vector count, actual peak power consumption, and actual design resource usage to obtain the test vector prediction error, peak power consumption prediction error, and design cost prediction error.
[0079] When the test vector prediction error exceeds the preset test vector error threshold, the test peak power consumption prediction error exceeds the preset power consumption error threshold, the design cost prediction error exceeds the preset cost error threshold, or the number of new feedback samples reaches the preset update number threshold, the processor uses the new feedback samples to perform incremental training or periodic retraining on the machine learning prediction model; when none of the above errors exceed the corresponding threshold, the processor saves the feedback samples in the training sample library as subsequent periodic training samples.
[0080] The feedback sample is used to record the actual effects of the target testability design operation set under the real tool flow. If the tool flow can also output the actual increase in area, changes in scan chain length, changes in test control signal fan-out, or changes in timing margin, the above data can also be written into the feedback sample as auxiliary feedback information.
[0081] Feedback samples do not directly replace the original training samples, but are appended to the training sample library. When the error between the predicted number of test vectors and the actual number of test vectors, or the error between the predicted peak power consumption and the actual peak power consumption, exceeds a preset error threshold, the processor uses the newly added feedback samples to incrementally train or periodically retrain the machine learning prediction model to reduce the prediction bias of the model for similar circuit structures and similar testability design operations.
[0082] The machine learning prediction model is updated using feedback samples. During the update, the model's previous predictions for the target testability design operation set are compared with the actual results obtained from validation. The model parameters are adjusted based on the comparison results so that the model's subsequent predictions for similar circuit structures, similar power distributions, and similar testability design operations are closer to the results of actual tool execution.
[0083] Through this feedback update process, this embodiment forms a closed-loop process from candidate operation generation, prediction and evaluation, target operation selection, engineering constraint implementation to verification feedback. This closed-loop process can gradually correct the judgment bias of the machine learning prediction model on the number of test vectors, peak power consumption, and design cost, thereby improving the stability and engineering applicability of subsequent integrated circuit testability design schemes.
[0084] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the scope of the technology disclosed in the present invention, based on the technical solution and inventive concept of the present invention, should be covered within the scope of protection of the present invention.
[0085] The preferred embodiments of the present invention disclosed above are merely illustrative of the invention. These preferred embodiments do not exhaustively describe all details, nor do they limit the invention to specific implementations. Clearly, many modifications and variations can be made based on the content of this specification. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to better understand and utilize the invention. The invention is limited only by the claims and their full scope and equivalents.
Claims
1. A machine learning based high efficiency integrated circuit design for test method, comprising: include: Step 1: Based on the logic connection relationship of the integrated circuit under test, the initial testability design scheme, and the test power distribution, construct a testability feature map; Step 2: Based on the preset testability design change rules, generate candidate testability design operations in the testability feature map, where each candidate testability design operation corresponds to changing a testability design configuration in the initial testability design scheme; Step 3: Input the testability feature map and candidate testability design operations into the machine learning prediction model to determine the predicted value of test vector reduction, the predicted value of test peak power consumption reduction, and the predicted value of design cost corresponding to each candidate testability design operation. Step 4: Based on the predicted values of test vector reduction, test peak power reduction, and design cost prediction, select the target testability design operation set from the candidate testability design operations. The target testability design operation set satisfies the following conditions: the number of predicted test vectors is less than the number of initial test vectors, and the predicted test peak power is less than the initial test peak power. Step 5: Generate testability design implementation constraints based on the target testability design operation set, and complete the insertion of testability structures and generation of test vectors according to the testability design implementation constraints; Step 6: Verify the integrated circuit after the testability structure insertion is completed, obtain the actual number of test vectors and the actual peak power consumption, and use the actual number of test vectors and the actual peak power consumption as feedback samples to update the machine learning prediction model.
2. The method of claim 1, wherein, The testability feature map is constructed by parsing the gate-level netlist of the integrated circuit under test under the initial testability design scheme, taking the cell instance or the specified output terminal of the cell instance as the graph node, taking the connection relationship formed between the cell instances along the signal propagation direction as the directed edge, and writing the configuration code determined by the initial testability design scheme and the power weight determined by the test power distribution into the corresponding graph node to obtain the testability feature map.
3. The method of claim 1, wherein, According to the preset testability design change rules, the specific method is as follows: read the configuration code and power consumption weight of each graph node in the testability feature graph, determine the graph node whose configuration code meets the preset changeable conditions as the node to be changed, and generate candidate testability design operations for each node to be changed according to the preset configuration item change table.
4. The method of claim 3, wherein, The specific method for generating candidate testability design operations is as follows: taking the node to be changed as the operation object, determining the set of associated nodes that have a signal propagation relationship with the node to be changed based on the directed edges, combining the node identifier to be changed, the set of associated nodes, the changed configuration item, and the changed configuration value into an operation description, and determining the operation description that meets the preset design constraints as the candidate testability design operations.
5. The method of claim 1, wherein, The method for determining the test vector reduction prediction value corresponding to each candidate testability design operation is as follows: convert the candidate testability design operation into an operation code, and input the operation code and the node features of the corresponding graph node in the testability feature map into the machine learning prediction model to obtain the number of predicted test vectors after executing the candidate testability design operation; the difference between the initial number of test vectors and the predicted number of test vectors is determined as the test vector reduction prediction value.
6. The method of claim 1, wherein, The method for determining the predicted reduction in peak power consumption for each candidate design-testable operation is as follows: the candidate design-testable operation is converted into an operation code, and the power consumption feature is determined according to the power consumption weight of the graph node corresponding to the candidate design-testable operation. The operation code and power consumption feature are input into a machine learning prediction model to obtain the predicted peak power consumption after executing the candidate design-testable operation. The difference between the initial peak power consumption and the predicted peak power consumption is determined as the predicted reduction in peak power consumption.
7. The method of claim 1, wherein, The specific method for determining the predicted design cost value corresponding to each candidate testability design operation is as follows: convert the candidate testability design operation into an operation code, and generate a cost feature based on the node characteristics of the graph node corresponding to the candidate testability design operation, the changed configuration item, and the changed configuration value. The operation code and cost features are input into the machine learning prediction model to obtain the predicted design resource consumption after performing the candidate testability design operation; the predicted design cost is determined based on the predicted design resource consumption.
8. The method of claim 1, wherein, The specific method for selecting the target testability design operation set is as follows: evaluate the benefits of candidate testability design operations according to the preset objective function, and determine the candidate testability design operations whose benefit evaluation results meet the preset selection conditions as the target testability design operation set.
9. The method of claim 1, wherein, The specific method for generating testability design implementation constraints is as follows: read the change object, changed configuration item and changed configuration value of each target testability design operation in the target testability design operation set, determine the testability structure insertion position according to the change object, and generate testability structure insertion constraints and test vector generation constraints.
10. The method of claim 1, wherein, The integrated circuit after the testability structure insertion is completed is verified. The specific method is as follows: the connectivity of the testability structure is verified and the test vector is simulated; after the verification is passed, the test vector generation results are counted to obtain the actual number of test vectors, and the power consumption of the circuit under the action of the test vectors is analyzed to obtain the actual peak power consumption. Feedback samples are generated based on the actual number of test vectors, the actual peak power consumption during testing, and the corresponding target testability design operation set.