Interface chip, semiconductor memory device, and memory system

Abstract

Embodiments of the present application relate to an interface chip, a semiconductor memory device, and a memory system, which improve access speed to a memory chip. The interface chip according to the present application is capable of connecting with a memory chip and a memory controller, the memory chip including a plurality of memory cells and a word line connected to the plurality of memory cells, and the interface chip has a control section that, when receiving a first command for data readout issued from the memory controller, transmits a second command corresponding to the first command to the memory chip to cause the memory chip to perform a readout operation, and after the memory chip ends the readout operation, transmits a fourth command for data output to the memory chip before receiving a third command for data output issued from the memory controller.

Description

Technical Field

[0001] One embodiment of the present invention relates to an interface chip, a semiconductor storage device, and a memory system. Background Technology

[0002] The controller issues data output commands to memory chips such as flash memory, and the memory chip prepares to output data corresponding to the column address recorded in the data output command (default). During the default period, the controller cannot access the memory chip, thus hindering the improvement of memory chip access speed. Summary of the Invention

[0003] Therefore, one embodiment of the present invention provides an interface chip, a semiconductor memory device, and a memory system for improving access speed to memory chips.

[0004] To address the aforementioned problem, according to one embodiment of the present invention, an interface chip is provided. This interface chip is capable of connecting to a memory chip and a memory controller. The memory chip includes a plurality of memory cells and word lines connected to the plurality of memory cells.

[0005] The interface chip includes a control unit. When the control unit receives a first instruction for data reading issued from the memory controller, it sends a second instruction corresponding to the first instruction to the memory chip to cause the memory chip to perform a read operation. When the memory chip finishes the read operation, before receiving a third instruction for data output issued from the memory controller, it sends a fourth instruction for data output to the memory chip. Attached Figure Description

[0006] Figure 1 This is a block diagram of the memory system in this embodiment.

[0007] Figure 2 This is a block diagram of the semiconductor memory device included in the memory system of this embodiment.

[0008] Figure 3 This is a block diagram of the NAND chip CP0 within the semiconductor memory device included in the memory system of this embodiment.

[0009] Figure 4 This is a block diagram showing the configuration of the NAND chip included in the memory system of this embodiment from the perspective of memory.

[0010] Figure 5 This is a circuit diagram of the memory cell array in the memory plane included in the memory system of this embodiment.

[0011] Figure 6This diagram illustrates the data readout method using a common protocol.

[0012] Figure 7A This diagram represents the signals CLE or ALE input to the CLE or ALE terminal, the signals WE input to the WE terminal, and the commands / addresses or data on the DQ bus when selecting the normal protocol.

[0013] Figure 7B This is a diagram showing the signals CA_CLK, CA[1], and CA[0] input to the WE, CLE, and ALE terminals when selecting the SCA protocol.

[0014] Figure 8A This is a diagram showing the readout and data transfer periods when one channel is connected to two NAND chips.

[0015] Figure 8B This is a diagram showing the readout and data transfer periods when one channel is connected to eight NAND chips.

[0016] Figure 9 This is a block diagram showing the internal structure of the I / F chip in this embodiment.

[0017] Figure 10A This is a schematic timing diagram of the memory system in this embodiment.

[0018] Figure 10B This is a timing diagram of a comparative memory system.

[0019] Figure 11 This is a diagram showing the connection relationship between the memory controller, I / F chip, and two NAND chips in the first specific example.

[0020] Figure 12 This is the timing diagram for the first specific example.

[0021] Figure 13 This is a diagram showing the connection relationship between a comparative memory controller and two NAND chips.

[0022] Figure 14 This is a timing diagram for a comparative example.

[0023] Figure 15 This is a diagram showing the connection relationship between the memory controller, I / F chip, and two NAND chips in the second specific example.

[0024] Figure 16 This is the timing diagram for the second specific example.

[0025] Figure 17 This is the timing diagram for the third specific example.

[0026] Figure 18 This is a diagram showing the connection relationship between the memory controller, I / F chip, and two NAND chips in the fourth specific example.

[0027] Figure 19 This is the timing diagram for the fourth specific example.

[0028] Figure 20A This is a diagram illustrating a first installation example of the semiconductor memory device according to this embodiment.

[0029] Figure 20B This is a diagram illustrating a second mounting example of the semiconductor memory device according to this embodiment.

[0030] Figure 20C This is a diagram illustrating a third mounting example of the semiconductor memory device according to this embodiment. Detailed Implementation

[0031] Hereinafter, embodiments of the interface chip, semiconductor memory device, and memory system will be described with reference to the accompanying drawings. The description will focus on the main components of the interface chip, semiconductor memory device, and memory system; however, the interface chip, semiconductor memory device, and memory system may contain components and functions not shown or described. The following description does not exclude components and functions not shown or described.

[0032] Figure 1 This is a block diagram of the memory system in this embodiment.

[0033] The memory system 100 includes a semiconductor memory device 200 and a memory controller 300. The memory system 100 is controlled by a host device (hereinafter referred to as "host") 400. The memory system 100 processes request signals received from the host 400. The memory system 100 may be, for example, an SSD (solid-state drive), a USB (Universal Serial Bus) memory, an MMC (Multi-Media Card), or an SD card. TM Card. Host 400, for example, a digital camera or personal computer.

[0034] The semiconductor memory device 200, as described below, includes, for example, an interface chip (hereinafter referred to as an I / F chip) and a NAND chip, and stores data non-volatilely. Multiple NAND chips may also be disposed within the semiconductor memory device 200.

[0035] The memory controller 300 receives request signals from the host 400 via the host bus. The type of host bus and the request signals transmitted via the host bus depend on the application applied to the memory system 100. In the case of an SSD in the memory system 100, the host bus may be, for example, SAS (Serial Attached SCSI), SATA (Serial ATA), or PCIe. TM The interface is either Programmable Communications Interface Express (PCIe), or UFS (Universal Flash Storage) standard. If the memory system 100 is a USB memory, USB is used as the host bus. If the memory system 100 is an MMC, the eMMC standard interface is used as the host bus. If the memory system 100 is an SD card... TM In the case of a card, use SD. TM The standard interface serves as the host bus. In this specification, the memory controller 300 is sometimes referred to as the controller.

[0036] The memory controller 300 controls the semiconductor memory device 200 based on request signals received from the host 400. Therefore, the memory controller 300 is connected to the semiconductor memory device 200 via a NAND bus. The NAND bus transmits and receives signals according to the NAND interface. Specific examples of these signals include chip enable signals CEn0 and CEn1, instruction latch enable signal CLE, address latch enable signal ALE, write enable signal WEn, read enable signals REn and RE, write protection signal WPn, data strobe signals DQS and DQSn, input / output signal DQ, ready / busy signal RBn, and SCA (Separate Command Address) toggle signal SCA.

[0037] Signals CEn0 and CEn1 are used to activate the NAND chip within the semiconductor memory device 200, for example, when at a low ("L") level. Furthermore, "activated" means that the signal (or logic) is in a valid (active) state. Signal CLE indicates that signal DQ is an instruction, for example, when at a high ("H") level. Signal ALE indicates that signal DQ is an address, for example, when at an "H" level. Signal WEn is used to acquire received signals into the semiconductor memory device 200, for example, when at a low level. Whenever WEn is triggered, the semiconductor memory device 200 acquires signal DQ. Signals REn and RE are used to cause the memory controller 300 to read data from the semiconductor memory device 200. Signal REn is the inverted signal of signal RE. Whenever signals REn and RE are triggered, the semiconductor memory device 200 outputs signal DQ to the memory controller 300. Signal WPn is used to disable writing or erasing in the semiconductor memory device 200, for example, when at a low level. Signals CEn0, CEn1, CLE, ALE, WEn, REn, RE, and WPn are sent from the memory controller 300 to the semiconductor memory device 200.

[0038] Signals DQS and DQSn are used to control the transmission and reception timing of signal DQ. Signal DQSn is the inverted signal of signal DQS. For example, when writing data, signals DQS and DQSn, along with signal DQ reflecting the written data, are sent from memory controller 300 to semiconductor memory device 200. Semiconductor memory device 200 can receive the written data by synchronously receiving signal DQ when receiving signals DQS and DQSn. Conversely, when reading data, signals DQS and DQSn, along with the read data DQ, are sent from semiconductor memory device 200 to memory controller 300. Signals DQS and DQSn are generated based on the signal REn. Memory controller 300 synchronously receives read data DQ when receiving signals DQS and DQSn.

[0039] The input / output signal DQ is, for example, an 8-bit signal (hereinafter referred to as DQ0 to DQ7 when it is necessary to distinguish the 8 signals DQ, and simply referred to as signal DQ when it is not necessary to distinguish them). The input / output signal DQ is the entity of data transmitted and received between the semiconductor storage device 200 and the memory controller 300, and includes, for example, instructions CMD, addresses ADD, write data or read data DAT, and status information STS. In this specification, the bus for transmitting the input / output signal DQ is referred to as the DQ bus. Buses used for transmitting signals, such as the DQ bus, are also called signal lines.

[0040] Signal RBn' indicates whether the semiconductor memory device 200 is in a busy or ready state; for example, it is low when the semiconductor memory device 200 is in a busy state. When signal RBn' is in a ready state, the semiconductor memory device 200 can receive instructions from the memory controller 300; when signal RBn' is in a busy state, the semiconductor memory device 200 cannot receive instructions from the memory controller 300. Signal RBn' is sent from the semiconductor memory device 200 to the memory controller 300.

[0041] The SCA signal specifies whether to switch from the normal protocol to the SCA protocol. For example, a low SCA signal selects the normal protocol, and a high SCA signal selects the SCA protocol. The functions of the CLE, ALE, and WEn signals change between the normal and SCA protocols. In the normal protocol selection, the CLE signal is used to indicate that the input / output signal DQ is a command, the ALE signal is used to indicate that the input / output signal DQ is an address, and the WEn signal is used, for example, to acquire the DQ signal on the rising edge. In the SCA protocol selection, the CLE and ALE signals are used to transmit commands or addresses, and the WEn signal is used, for example, to acquire the CLE and ALE signals on both the rising and falling edges.

[0042] The memory controller 300 includes a host interface circuit (host I / F) 310, a memory interface circuit (memory I / F) 320, a ROM (read-only memory) 330, a CPU (central processing unit) 340, and a RAM (random access memory) 350.

[0043] The host interface circuit 310 is connected to the host 400 via the host bus and is responsible for communication between the memory controller 300 and the host 400.

[0044] The memory interface circuit 320 is connected to the semiconductor memory device 200 via the NAND bus and is responsible for communication between the memory controller 300 and the semiconductor memory device 200.

[0045] ROM330 stores firmware (programs) for enabling the memory controller 300 to perform various operations, as well as some functions of the host interface circuit 310 and the memory interface circuit 320. The firmware is configured to enable the memory controller 300 to perform the operations described in each embodiment.

[0046] CPU 340 controls the overall operation of memory controller 300. For example, when CPU 340 receives a read-related request signal from host 400, it causes memory interface circuit 320 to issue a read instruction to semiconductor storage device 200 based on the request signal. CPU 340 performs the same action when it receives a write-related request signal from host 400.

[0047] RAM 350 is used as the operating area of ​​CPU 340. RAM 350 is, for example, a semiconductor memory such as DRAM or SRAM. RAM 350 stores, for example, the firmware. The firmware is loaded into RAM 350 by memory controller 300, for example, immediately after the memory system 100 is powered on.

[0048] (Composition of semiconductor memory device 200)

[0049] use Figure 2 The configuration of the semiconductor memory device 200 will be described. Figure 2 This is a block diagram of the semiconductor memory device 200 included in the memory system 100 of this embodiment.

[0050] The semiconductor memory device 200 includes an I / F chip 210 and multiple NAND chips CP0 and CP1. The number of NAND chips CP0 and CP1 is arbitrary. The I / F chip 210 is connected to the memory controller 300 via a NAND bus and is responsible for communication between the memory controller 300 and the NAND chips CP0 and CP1. The NAND chips CP0 and CP1 are NAND flash memory. The NAND chips CP0 and CP1 are controlled by the memory controller 300. The I / F chip 210 can also constitute a semiconductor device independently.

[0051] Figure 2 The example shown is that the memory controller 300 sends different signals CEn0 and CEn1 to each NAND chip, but the memory controller 300 can also send a common signal CEn to multiple NAND chips. Figure 2 This example illustrates sending signal CEn0 to NAND chip CP0 and signal CEn1 to NAND chip CP1. When sending a common signal CEn to multiple NAND chips, each of NAND chips CP0 and CP1 is selected based on a specified signal CEn and the address of the NAND chip. Signal RBn includes signals RBn0 and RBn1 corresponding to NAND chips CP0 and CP1, respectively. Signal SCA includes signals SCA0 and SCA1 corresponding to NAND chips CP0 and CP1, respectively. Furthermore, the number of signals RBn is the same as the number of NAND chips disposed within the semiconductor memory device 200.

[0052] I / F chip 210 receives signals CEn0, CEn1, CLE, ALE, WEn, REn, RE, WPn, DQS, DQSn, and DQ from memory controller 300. I / F chip 210 transmits the received signals CLE, ALE, WEn, REn, RE, WPn, DQS, DQSn, and DQ to NAND chips CP0 and CP1 via data bus DB. I / F chip 210 transmits the received signal CEn0 to NAND chip CP0. I / F chip 210 transmits the received signal CEn1 to NAND chip CP1.

[0053] I / F chip 210 receives signals DQS, DQSn, and DQ from NAND chips CP0 and CP1. I / F chip 210 then sends the received signals DQS, DQSn, and DQ to memory controller 300.

[0054] NAND chip CP0 sends signal RBn0 to I / F chip 210. I / F chip 210 sends signal RBn'0 corresponding to NAND chip CP0 to memory controller 300. NAND chip CP1 sends signal RBn1 to I / F chip 210. I / F chip 210 sends signal RBn'1 corresponding to NAND chip CP1 to memory controller 300.

[0055] Data is written to one of the NAND chips selected from CP0 and CP1. Data is also read from one of the NAND chips selected from CP0 and CP1.

[0056] (The composition of NAND chip CP0)

[0057] use Figure 3 The structure of the NAND chip CP0 is explained. Figure 3 This is a block diagram of the NAND chip CP0 within the semiconductor storage device 200 included in the memory system 100 of this embodiment. Furthermore, Figure 3 In the diagram, arrows indicate a portion of the connections between blocks, but the connections between blocks are not limited to this. The following description focuses on NAND chip CP0, but NAND chip CP1 has the same configuration.

[0058] The NAND chip CP0 includes an input / output circuit 10, a register 20, a sequencer 30, a voltage generation circuit 40, and memory surfaces PL0 to PL3.

[0059] Input / output circuit 10 receives signals CEn0, SCA0, CLE, ALE, WEn, REn, RE, and WPn from I / F chip 210. Input / output circuit 10 transmits and receives signals DQS, DQSn, and DQ with I / F chip 210. Input / output circuit 10 sends signal RBn0 to I / F chip 210.

[0060] Register 20 includes a status register 21, an address register 22, and an instruction register 23. The status register 21 temporarily stores, for example, status information STS during data write, read, and erase operations. The address register 22 temporarily stores the address ADD received from the I / F chip 210 via the input / output circuit 10. This address ADD includes the row address RA and the column address CA. The instruction register 23 temporarily stores the instruction CMD received from the I / F chip 210 via the input / output circuit 10.

[0061] The sequencer 30 controls the overall operation of the NAND chip CP0. The sequencer 30 receives the instruction CMD from the instruction register 23. Based on the received instruction CMD, the sequencer 30 controls the input / output circuit 10, the status register 21, the voltage generation circuit 40, and the memory surfaces PL0 to PL3 (PL0 to PL3) to perform write, read, and erase operations.

[0062] The voltage generation circuit 40 receives the power supply voltage from the external NAND chip CP0 and generates various voltages from the power supply voltage based on the control of the sequencer 30. The voltage generation circuit 40 applies the generated voltages to memory surfaces PL0 to PL3 (PL0 to PL3).

[0063] Memory planes PL0 to PL3 (PL0 to PL3) are independently controlled by sequencer 30. Memory planes PL0 to PL3 (PL0 to PL3) are units for writing data to and reading data from the memory cell transistors. When writing data, memory planes PL0 to PL3 (PL0 to PL3) receive the written data DAT from the memory controller 300 via input / output circuit 10. Conversely, when reading data, memory planes PL0 to PL3 (PL0 to PL3) send the read data DAT to the I / F chip 210 via input / output circuit 10.

[0064] use Figure 4 The structure of memory plane PL0 will be explained. Figure 4This is a block diagram showing the configuration of the NAND chip CP0 included in the memory system 100 of this embodiment, focusing on the memory plane PL0. Hereinafter, the memory plane PL0 will be described, but the memory planes PL1, PL2, and PL3 also have the same configuration. Furthermore, in Figure 4 In this version, the status register 21, instruction register 23, and memory planes PL1 to PL3 (PL1 to PL3) are omitted.

[0065] The memory plane PL0 includes a memory cell array 51A, a row decoder 52A, a sense amplifier 53A, a data register 54A, and a column decoder 55A.

[0066] The memory cell array 51A has multiple blocks BLK (BLK0 to BLKn, where n is a natural number greater than or equal to 1) containing non-volatile memory cell transistors associated with rows and columns. Furthermore, the number of blocks BLK within the memory cell array 51A is arbitrary. Details regarding the memory cell array 51A will be described below. A voltage is applied to the memory cell array 51A by the voltage generation circuit 40.

[0067] The row decoder 52A is controlled by the sequencer 30. The row decoder 52A receives the row address RA from the address register 22. The row decoder 52A decodes the received row address RA and applies the voltage supplied by the voltage generation circuit 40 to the selected memory cell transistor based on the decoding result.

[0068] The sensing amplifier 53A is controlled by the sequencer 30. A voltage is applied to the sensing amplifier 53A by the voltage generation circuit 40. When reading data, the sensing amplifier 53A senses the data DAT read from the memory cell array 51A. The sensing amplifier 53A then sends the read data DAT to the data register 54A. Additionally, when writing data, the sensing amplifier 53A sends the written data DAT to the memory cell array 51A.

[0069] Data register 54A is controlled by sequencer 30. Voltage is applied to data register 54A by voltage generation circuit 40. Data register 54A includes multiple latching circuits (not shown). The latching circuits store write data and read data DAT. For example, when writing data, data register 54A temporarily stores the write data DAT received from input / output circuit 10 and sends it to sense amplifier 53A. Similarly, when reading data, data register 54A temporarily stores the read data DAT received from sense amplifier 53A and sends it to input / output circuit 10.

[0070] The column decoder 55A is controlled by the sequencer 30. A voltage is applied to the column decoder 55A by the voltage generation circuit 40. The column decoder 55A receives the column address CA from the address register 22. For example, during write, read, and erase operations, the column decoder 55A decodes the column address CA and selects the latch circuit in the data register 54A based on the decoding result.

[0071] (Circuit configuration of memory cell array 51A)

[0072] use Figure 5 The circuit configuration of the memory cell array 51A will be described. Figure 5 This is a circuit diagram of the memory cell array 51A within the memory plane PL0 included in the memory system 100 of this embodiment.

[0073] Figure 5 An example of the circuit configuration of the memory cell array 51A is represented by extracting one block BLK from the multiple block BLKs contained in the memory cell array 51A. All other block BLKs also have... Figure 5 The structure shown.

[0074] A block BLK, for example, contains four string cells SU0 to SU3. Furthermore, the number of string cells SU within a block BLK is arbitrary. Each string cell SU contains multiple NAND strings NS. These multiple NAND strings NS are associated with bit lines BL0 to BLm (where m is a natural number greater than or equal to 1). Each NAND string NS, for example, contains memory cell transistors MC0 to MC7, and select transistors ST1 and ST2. The memory cell transistor MC contains a control gate and a charge accumulation layer, storing data non-volatilely. The select transistors ST1 and ST2 are used to select the string cell SU during various operations.

[0075] In each NAND string NS, the memory cell transistors MC0 to MC7 are connected in series. In the same BLK, the control gates of the memory cell transistors MC0 to MC7 are respectively connected to word lines WL0 to WL7.

[0076] In each NAND string NS, the drain of the select transistor ST1 is connected to the associated bit line BL, and the source of the select transistor ST1 is connected to one end of the series-connected memory cell transistors MC0 to MC7. In the same BLK, the gates of the select transistors ST1 in the string cells SU0 to SU3 are respectively connected to the select gate lines SGD0 to SGD3.

[0077] In each NAND string NS, the drain of the select transistor ST2 is connected to the other end of the series-connected memory cell transistors MC0 to MC7. In the same BLK, the source of the select transistor ST2 is connected to the source line SL, and the gate of the select transistor ST2 is commonly connected to the select gate line SGS.

[0078] In the circuit configuration of the memory cell array 51A described above, the bit line BL is shared among multiple NAND strings NS corresponding to each block BLK. The source line SL is shared among multiple blocks BLK.

[0079] (Reading data using a standard protocol)

[0080] When reading data stored in the NAND chip CP according to the usual protocol, the memory controller 300 performs instruction / address and data transfer via the 8-bit DQ bus. Figure 6 This diagram illustrates the data read method according to a common protocol. The memory controller 300 first issues a read instruction set via the DQ bus. The read instruction set contains information about a specific row address. In this specification, the read instruction set is sometimes simply referred to as read instructions.

[0081] When the NAND chip CP receives a read instruction set issued by the memory controller 300, it performs a read operation on the row address specified by the read instruction set. Figure 6 This example illustrates a read operation performed on a specific row address (shadowed area ha1) of a memory cell array in a specific memory plane, based on a set of read instructions issued by the memory controller 30. During the period tR required for the NAND chip CP to perform the read operation (hereinafter referred to as the read operation period), the NAND chip CP does not occupy the DQ bus, so during this read operation period tR, the memory controller 300 can issue read instructions to other NAND chip CPs.

[0082] When the NAND chip completes the read operation, the memory controller 300 issues a data output instruction set. The data output instruction set contains information about a specific column address within a specific row address. In this specification, the data output instruction set is sometimes simply referred to as the data output instruction.

[0083] When the NAND chip CP receives a data output instruction set issued by the memory controller 300 via the DQ bus, it prepares to output the data at the column address (shadow area ha2) specified by the data output instruction set. When the data output is ready, it outputs the data via the DQ bus.

[0084] During the data output preparation period tWHR2, preparations are made to output data via the DQ bus, and the memory controller 300 cannot issue instructions during this period tWHR2.

[0085] In this case, when the memory controller 300 reads data according to the usual protocol, tWHR2 cannot issue instructions during the data output preparation period, so there is a problem that cannot be improved in terms of latency.

[0086] (SCA Protocol)

[0087] In a typical protocol, the memory controller 300 and the I / F chip 210 transmit instructions / addresses and data via an 8-bit DQ bus, switching between them in a time-division manner. Therefore, during instruction / address transmission, the DQ bus is occupied, preventing data transmission and reducing data transfer efficiency. Against this backdrop, the SCA protocol has been standardized by JEDEC (Joint Electron Device Engineering Councils). This SCA protocol utilizes other buses to transmit instructions / addresses and data without altering the existing NAND chip CP terminal configuration.

[0088] The functions of the signals input to the CLE, ALE, and WE terminals of the NAND chip CP differ between the standard protocol and the SCA protocol. Figure 7A This diagram illustrates the signals CLE or ALE input to the CLE or ALE terminal, the signal WE input to the WE terminal, and the instructions / addresses or data on the DQ bus during the selection of the normal protocol. As shown, at time t2, during the transmission of 8 bits of instructions / addresses or data on the DQ bus (times t1 to t3), the signal WE transitions from low to high. The signal logic of the CLE or ALE signals remains unchanged during times t1 to t3. The DQ bus is latched by the signal WE at time t2 when the signal WE transitions from low to high. In the case of transmitting 8 bits of instructions / addresses, the DQ bus may transmit 8 bits of data.

[0089] Figure 7B This diagram shows the signals CA_CLK, CA[1], and CA[0] input to the WE, CLE, and ALE terminals when selecting the SCA protocol. For instructions / addresses sent using the 8-bit DQ bus in the normal protocol, the SCA protocol uses the CLE and ALE terminals to send them in 2 bits of CA[0:1]. Therefore, in the SCA protocol, CA[0:1] is in packet form. This packet CA[0:1] contains a 4-bit header and an 8-bit body. The header contains 4 bits of information distinguishing between instructions and addresses. The body contains 8 bits of information representing the instruction or address.

[0090] In the standard protocol, an 8-bit instruction / address can be sent in one cycle of the WE signal using an 8-bit wide DQ bus. In contrast, in the SCA protocol, since the instruction / address is sent using a 2-bit wide packet CA[0:1], sending an 8-bit instruction / address requires 4 cycles, and sending the header requires 2 cycles, for a total of 6 cycles. Therefore, CA[0:1] must be acquired not only on the rising edge of the WE signal but also on its falling edge.

[0091] The purpose of the SCA protocol is to maximize the efficiency of the DQ bus, which varies depending on the DQ bus occupancy rate. The DQ bus occupancy rate depends on the time tR for reading data from the NAND chip CP and the transmission period tDout of the read data.

[0092] Figure 8A This is a graph showing the read operation period tR and the data transmission period Dout when one channel is connected to two NAND chip CPs. Figure 8B This is a graph showing the read operation period tR and the data transmission period Dout when one channel is connected to eight NAND chip CPs. Figure 8A and Figure 8B The diagram shows the read operation period tR of the NAND chip CP, the input period of the data output command, and the data transmission period tDout.

[0093] The read operation time required to read data from the NAND chip CP is longer than the data transfer time, so as Figure 8A The NAND chip CPs in each channel are fewer, resulting in longer read latency. Long latency prevents efficient use of the DQ bus, thus diminishing the advantages of the SCA protocol.

[0094] On the other hand, when Figure 8B When there are a large number of NAND chip CPs in each channel, the reading of each NAND chip CP can be performed in parallel, thus shortening the read wait time and increasing the utilization rate of the DQ bus. Therefore, the SCA protocol is effective when there are a large number of NAND chip CPs in each channel.

[0095] Figure 9 This is a block diagram showing the internal structure of the I / F chip 210 in this embodiment. Figure 9 This is an example of forming a semiconductor memory device 200 by housing an I / F chip 210 and multiple NAND chips CP in the same package component.

[0096] like Figure 9As shown, the I / F chip 210 of this embodiment includes a control unit 1. The control unit 1 controls multiple NAND chip CPs. The control unit 1 sends instructions to each NAND chip CP with an independent timing sequence that differs from the input timing sequence of instructions issued by the memory controller 300. Independent timing means that the I / F chip 210 can send instructions other than those issued by the memory controller 300 to the NAND chip CPs. Existing I / F chips 210 have the function of relaying communication between the memory controller 300 and the NAND chip CPs, directly sending instructions issued by the memory controller 300 to the NAND chip CPs. On the other hand, the I / F chip 210 of this embodiment can send instructions issued by the memory controller 300 to the NAND chip CPs. Thus, the I / F chip 210 of this embodiment can not only send instructions issued by the memory controller 300 to the NAND chip CPs, but also send instructions not yet issued by the memory controller 300 to the NAND chip CPs. The control unit 1 is also referred to as a controller. The components within the control unit 1 are implemented, for example, by at least one of registers, memory, adders, multipliers, selectors, and other arithmetic units. Registers are implemented, for example, by sequential circuits such as flip-flops. Memory is implemented, for example, by storage elements such as SRAM or DRAM. Adders, multipliers, selectors, and other arithmetic units are implemented, for example, using combinational logic circuits. The components of the I / F chip 210, excluding the control unit 1, are also implemented, for example, by at least one of registers, memory, adders, multipliers, selectors, and other arithmetic units.

[0097] In a more detailed example, before the memory controller 300 issues an instruction (e.g., a data output instruction), the control unit 1 sends an instruction to the NAND chip CP, temporarily saving the data output from the NAND chip CP in response to the instruction sent to the NAND chip CP. After saving the data, when the memory controller 300 issues an instruction, the saved data is sent back to the memory controller 300. Thus, the I / F chip 210 can pre-read the stored data of the NAND chip CP. Then, when the memory controller 300 issues an instruction, the pre-read data can be quickly fed back to the memory controller 300, thereby reducing latency.

[0098] For example, regardless of whether the memory controller 300 uses the SCA (Separate Command Address) protocol, the control unit 1 can transmit instructions, addresses, and data with the NAND chip CP using the same bus. Alternatively, if the memory controller 300 uses the SCA (Separate Command Address) protocol, the control unit 1 can also transmit instructions and addresses with the NAND chip CP via the first bus and transmit data via a second bus different from the first bus.

[0099] In a more specific example, when the memory controller 300 issues a read instruction, the control unit 1 sends a read instruction to the NAND chip CP, and after the NAND chip CP performs the read operation corresponding to the read instruction and before the memory controller 300 issues a data output instruction, it sends a data output instruction to the NAND chip CP.

[0100] The control unit 1 can also send a data output command to the NAND chip CP after sending a read command to the NAND chip CP and after the maximum allowable time specified in the specification has elapsed until the NAND chip CP finishes the read operation.

[0101] Alternatively, the control unit 1 may send a data output command to the NAND chip CP when a logic change occurs in a specified signal (e.g., ready / busy signal RBn) indicating the operation status sent from the NAND chip CP after a read command is sent to the NAND chip CP.

[0102] The control unit 1 can also use one bus to send read commands and data output commands to the corresponding NAND chip CP and receive data output by the corresponding NAND chip CP for each of the multiple NAND chip CPs when the memory controller 300 adopts the SCA protocol and continuously issues read commands to multiple NAND chip CPs.

[0103] The control unit 1 can also, when the memory controller 300 adopts the SCA protocol and continuously issues read commands to multiple NAND chip CPs, use the first bus for transmitting commands and addresses and the second bus for transmitting data to each of the multiple NAND chip CPs in parallel to receive data output by the corresponding NAND chip CP and send read commands to the corresponding NAND chip CPs.

[0104] The control unit 1 can also adjust the timing of sending read instructions or data output instructions for each of the multiple NAND chip CPs when the memory controller 300 continuously issues read instructions to multiple NAND chip CPs.

[0105] The I / F chip 210 in this embodiment may also have a storage unit 2. The storage unit 2 temporarily stores data output by the NAND chip CP corresponding to the instruction (e.g., a data output instruction) sent to the NAND chip CP. The storage unit 2 is, for example, a high-speed cache memory composed of SRAM (Static Random Access Memory) capable of high-speed read and write. The control unit 1 performs control such that when the storage unit 2 stores data and the memory controller 300 issues a data output instruction, the data stored in the storage unit 2 is quickly sent to the memory controller 300.

[0106] When the memory controller 300 continuously issues read commands to multiple NAND chip CPs, the control unit 1 continuously sends read commands to the multiple NAND chip CPs to perform read operations in parallel using the multiple NAND chip CPs. Alternatively, when the read operation ends and before the memory controller 300 issues data output commands to the multiple NAND chip CPs, the control unit 1 continuously sends data output commands to the multiple NAND chip CPs to temporarily store the multiple data output in parallel by the multiple NAND chip CPs in the storage unit 2.

[0107] The I / F chip 210 in this embodiment may also have a selector 3. The selector 3 selects any one of the multiple data output by the multiple NAND chips CP stored in the storage unit 2 based on the data output instruction issued by the memory controller 300, and sends it to the memory controller 300.

[0108] Figure 10A This is a schematic timing diagram of the memory system 100 of this embodiment. Figure 10A The diagram illustrates the timing of the memory controller 300 sending instructions to the I / F chip 210, and the timing of the I / F chip 210 sending instructions to the NAND chip CP. Instruction A is, for example, a read instruction, and instruction B is, for example, a data output instruction.

[0109] Figure 10A This indicates the timing sequence when the memory controller 300 uses a standard protocol. As described above, in the standard protocol, the memory controller 300 and the I / F chip 210 exchange instructions / addresses and data via the DQ bus. Additionally, the I / F chip 210 and multiple NAND chip CPs exchange instructions / addresses and data via the DQ bus.

[0110] When the I / F chip 210 receives instruction A from the memory controller 300, it sends instruction A to the NAND chip CP. When the NAND chip CP receives instruction A from the I / F chip 210, it performs a read operation according to instruction A. During the read operation tR, the NAND chip CP sets the ready / busy signal RBn to a low level. The ready / busy signal RBn is sent from the NAND chip CP to the I / F chip 210. During the read operation tR, the NAND chip CP transitions the ready / busy signal RBn from a high level to a low level.

[0111] When the ready / busy signal RBn transitions from low to high, the I / F chip 210 sends instruction B to the NAND chip CP before the memory controller 300 issues instruction B. Upon receiving instruction B, the NAND chip CP prepares for data output according to instruction B. When the data output preparation period tWHR2 ends, the NAND chip CP outputs data via the DQ bus. The I / F chip 210 temporarily stores this data in the storage section 2.

[0112] The I / F chip 210 generates a ready / busy signal RBn' suitable for the memory controller 300 based on the ready / busy signal RBn from the NAND chip CP. The ready / busy signal RBn suitable for the memory controller 300 is a signal that changes from high level to low level when the I / F chip 210 receives instruction A from the memory controller 300, and changes from low level to high level when the storage unit 2 finishes saving the data from the NAND chip CP.

[0113] The memory controller 300 issues instruction B when the ready / busy signal RBn from the I / F chip 210 changes from low to high after instruction A is issued. When the I / F chip 210 receives instruction B from the memory controller 300, it sends the data stored in the storage unit 2 to the memory controller 300. Thus, the memory controller 300 can quickly receive the data corresponding to instruction B.

[0114] In this embodiment, when the memory controller 300 continuously sends instruction A (read instruction) to two NAND chip CPs, the I / F chip 210 can send instruction A to the other NAND chip CP while one NAND chip CP is performing a read operation. Therefore, no processing delay caused by the read operation period tR occurs. Furthermore, before the memory controller 300 issues instruction B, the I / F chip 210 sends instruction B to each NAND chip CP to pre-read the data of the NAND chip CP and store it in the storage unit 2. Therefore, when the memory controller 300 subsequently issues instruction B, the stored data in the storage unit 2 can be quickly sent to the memory controller 300. Thus, the data output preparation period tWHR2 of the NAND chip CP is no longer a major factor in reducing latency.

[0115] Figure 10B This is a timing diagram of a comparative memory system. This comparative memory system does not have an I / F chip 210; the memory controller directly sends instructions to the NAND chip CP. When the memory controller issues instruction A, and the NAND chip CP receives instruction A, the NAND chip CP begins a read operation. During the period before the read operation ends, the ready / busy signal RBn is kept low. When the ready / busy signal RBn transitions from low to high, the memory controller issues instruction B. When the NAND chip CP receives instruction B, it begins data output preparation. When data output preparation is complete, it outputs data via the DQ bus.

[0116] In one comparative example, the memory controller was unable to send instructions via the DQ bus during the data output preparation period tWHR2, resulting in increased latency and an inability to improve the read speed of the NAND chip CP.

[0117] The following describes the detailed timing of the memory controller 300 issuing read instructions and data output instructions to the two NAND chips CPA and CPC, and reading the corresponding data from the NAND chips CPA and CPC. In this embodiment, there is not just one method for reading data from the two NAND chips CPA and CPC; several methods can be applied. Hereinafter, several representative methods for reading data from the two NAND chips CPA and CPC will be described as specific examples 1 to 4 in sequence. The read instruction and data output instruction applicable to the NAND chip CPA will be referred to as read instruction A and data output instruction A, respectively, and the read instruction and data output instruction applicable to the NAND chip CPC will be referred to as read instruction C and data output instruction C, respectively.

[0118] (First specific example)

[0119] Figure 11This diagram illustrates the connection relationship between the memory controller 300, the I / F chip 210, and the two NAND chips CPA and CPC in the first embodiment. The two NAND chips CPA and CPC, for example, constitute channel 0 (CH0) and channel 1 (CH1) on the same memory plane. The memory controller 300 in the first embodiment employs the SCA protocol. As described above, in the SCA protocol, the memory controller 300 transmits data and instructions / addresses between itself and the I / F chip 210 using a dedicated data DQ bus and a dedicated instruction / address CA bus. Furthermore, the I / F chip 210 transmits instructions / addresses and data with each NAND chip CP via the DQ bus, respectively.

[0120] Figure 12 This is the timing diagram for the first specific example. Figure 12 The diagram illustrates the DQ bus and CA bus between the memory controller 300 and the I / F chip 210, the DQ(CH0) bus between the I / F chip 210 and the NAND chip CPA, the internal operation of the NAND chip CPA, the DQ(CH0) bus between the I / F chip 210 and the NAND chip CPC, and the internal operation and timing of the NAND chip CPC.

[0121] The following describes an example of how the memory controller 300 issues read instructions and data output instructions to the two NAND chips CPA and CPC.

[0122] First, at time t1, the memory controller 300 sends a read command A to the NAND chip CPA via the DQ bus. After receiving the read command A, the I / F chip 210 sends a read command A to the NAND chip CPA via the DQ(CH0) bus at time t2.

[0123] At time t2, the memory controller 300 sends a read command C to the NAND chip CPC via the DQ bus. After receiving the read command C, the I / F chip 210 sends a read command C to the NAND chip CPC via the DQ(CH1) bus at time t3.

[0124] After receiving read instruction A, the NAND chip CPA begins the read operation at time t3. Time t3 to t5 constitutes the read operation period tR. During the read operation period tR, the NAND chip CPA reads one page of data specified by the row address included in read instruction A. The ready / busy signal RBn sent by the NAND chip CPA to the I / F chip 210 is low during the read operation period tR and becomes high after the read operation period tR ends.

[0125] Next, after receiving the read instruction C, the NAND chip CPC begins the read operation at time t4. Time t4 to t6 constitutes the read operation period tR. During the read operation, the NAND chip CPC reads one page of data as indicated by the row address contained in the read instruction C.

[0126] The I / F chip 210 sends a data output command to the NAND chip CPA at time t5, before the memory controller 300 issues a data output command, at the end of the read operation of the NAND chip CPA. For example, the I / F chip 210 sends the data output command when the ready / busy signal RBn from the NAND chip CPA transitions from low to high. Alternatively, the I / F chip 210 sends the data output command when the elapsed time after sending the read command to the NAND chip CPA exceeds the maximum allowable time for the NAND chip CPA's read operation.

[0127] After receiving the data output command, the NAND chip CPA begins data output preparation at time t6. Time t6 to t8 is the data output preparation period tWHR2. When the data output preparation period tWHR2 ends, the NAND chip CPA sends the read data to the I / F chip 210 via the DQ(CH0) bus from time t8 to t11.

[0128] The I / F chip 210 sends a data output command to the NAND chip CPC at time t6, when the read operation of the NAND chip CPC ends and before the memory controller 300 issues a data output command.

[0129] After receiving the data output command, the NAND chip CPC begins data output preparation at time t7. Time t7 to t9 constitutes the data output preparation period tWHR2. At the end of the data output preparation period tWHR2, the NAND chip CPC sends the read data to the I / F chip 210 via the DQ (CH1) bus between times t9 and t12.

[0130] At time t6, the memory controller 300 sends a new read instruction A to the NAND chip CPA via the DQ bus, and at time t7, it sends a new read instruction C to the NAND chip CPC via the DQ bus.

[0131] In this way, the memory controller 300 can send new read commands A and C to the NAND chips CPA and CPC in parallel during the data output preparation period (times t6 and t7).

[0132] The I / F chip 210 temporarily stores the data sent by the NAND chip CPA to the DQ(CH0) bus in the storage unit 2 between times t8 and t11. Similarly, the NAND chip CPC temporarily stores the data sent by the NAND chip CPC to the DQ(CH1) bus in the storage unit 2 between times t9 and t12.

[0133] Then, in parallel with the NAND chip CPA outputting data to the DQ(CH0) bus, at time t10, the memory controller 300 sends a data output command to the NAND chip CPA via the DQ bus.

[0134] Next, according to the SCA protocol specifications, the memory controller 300 sends an SCE (Select Chip Enable) instruction via the CA bus at time t11, indicating the start of data output from the NAND chip CPA. Upon receiving this instruction, the I / F chip 210 sends the data read from the NAND chip CPA and stored in the memory unit 2 via the DQ bus between times t12 and t15. More specifically, at time t14, the memory controller 300 sends an SCT (Select Chip Terminate) instruction via the DQ bus, indicating the end of data output. Upon receiving this instruction, the I / F chip 210 ends the process of sending the data read from the NAND chip CPA and stored in the memory unit 2 via the DQ bus at time t15.

[0135] At time t11, when the data output period of I / F chip 210 on the DQ(CH0) bus ends, it sends the read instruction A sent by memory controller 300 at time t6 via the DQ(CH0) bus. NAND chip CPA receives read instruction A and performs a read operation to read the data corresponding to the received read instruction A from NAND chip CPA from time t12 to t15.

[0136] At time t12, when the data output period of I / F chip 210 on the DQ(CH1) bus ends, it sends the read instruction C sent by memory controller 300 at time t7 via the DQ(CH1) bus. NAND chip CPC receives read instruction C and performs the operation of reading the data corresponding to the received read instruction C from NAND chip CPC at times t13 to t16.

[0137] At time t15, the memory controller 300 sends an SCE command via the CA bus to indicate the start of data output from the NAND chip CPC. Upon receiving this command, the I / F chip 210 sends the data read from the NAND chip CPC and stored in the memory unit 2 via the DQ bus between times t16 and t20. More specifically, at time t19, the memory controller 300 sends a command to indicate the end of data output via the CA bus. Upon receiving this command, the I / F chip 210 ends the process of sending the data read from the NAND chip CPC and stored in the memory unit 2 via the DQ bus at time t20.

[0138] At time t15, when the read operation of the NAND chip CPA ends, the I / F chip 210 sends a data output command to the NAND chip CPA via the DQ(CH0) bus. The I / F chip 210 and each NAND chip CPA and CPC perform the same operations as those at times t5 to t15 from time t15 to t26.

[0139] During the data output preparation period of the NAND chip CPA and CPC, the memory controller 300 sends new read commands A and C to the I / F chip 210 via the CA bus at times t16 and t17. The memory controller 300 performs the same operations as at times t6 to t16 from times t16 to t27.

[0140] In this first specific example, before the memory controller 300 issues a data output instruction, the I / F chip 210 issues data output instructions to the NAND chips CPA and CPC, sequentially storing the data read from the NAND chips CPA and CPC and transmitted via the DQ(CH0) bus and DQ(CH1) bus in the storage unit 2. Therefore, when the memory controller 300 subsequently issues data output instructions A and C, the data stored in the storage unit 2 can be quickly sent to the memory controller 300. This shortens the data output period to the memory controller 300.

[0141] In addition, when the memory controller 300 adopts the SCA protocol, after the I / F chip 210 saves data in the storage unit 2, the memory controller 300 issues a data output instruction and then issues an SCE instruction whose purpose is to start data output, and then sends the data saved in the storage unit 2 to the memory controller 300. After the memory controller 300 issues an SCT instruction whose purpose is to end data transmission, the data transmission ends.

[0142] (A comparative example)

[0143] Figure 13This diagram illustrates the connection relationship between a comparative memory controller 300 and two NAND chips CPA and CPC. In this comparative example, the memory controller 300 accesses the two NAND chips CPA and CPC without via the I / F chip 210. The memory controller 300 and the two NAND chips CPA and CPC are connected via a DQ bus. This DQ bus transmits instructions / addresses and data.

[0144] Figure 14 This is a timing diagram for a comparative example. Figure 14 The diagram illustrates the timing of the DQ bus, the internal operations of the NAND chip CPA, and the internal operations of the NAND chip CPC.

[0145] The memory controller 300 sends a read instruction A for the NAND chip CPA via the DQ bus at time t1, and sends a read instruction C for the NAND chip CPC via the DQ bus at time t2.

[0146] During the period tR from time t2 to t4, the NAND chip CPA performs the read operation corresponding to read instruction A. During the period tR from time t3 to t5, the NAND chip CPC performs the read operation corresponding to read instruction C.

[0147] At time t4, when the read operation of NAND chip CPA ends, memory controller 300 sends a data output command to NAND chip CPA via the DQ bus. During time t5-t6, NAND chip CPA prepares for data output (tWHR2), and at time t7-t8, sends data indicating the end of data output preparation via the DQ bus. During time t7-t8, memory controller 300 acquires data on the DQ bus, sends a new read command to NAND chip CPA via the DQ bus at time t8, and sends a data output command to NAND chip CPC via the DQ bus at time t9. During time t9-t12, NAND chip CPA performs a read operation (tR). During time t10-t11, NAND chip CPC prepares for data output corresponding to read command C (tWHR2), and at time t12-t13, sends data indicating the end of data output preparation via the DQ bus.

[0148] The memory controller 300 acquires data corresponding to the read instruction C at times t12-t13, sends a new read instruction C to the NAND chip CPC via the DQ bus at time t13, and sends a data output instruction to the NAND chip CPA via the DQ bus at time t14. The NAND chip CPC performs a read operation during the period tR from t14 to t17. The NAND chip CPA prepares for data output during the period tWHR2 from t15 to t16. Then, from t17 to t24, the same operation as from t7 to t14 is performed.

[0149] In a comparative example, for instance, during the data output preparation period of the NAND chip CPA and CPC, the memory controller 300 is unable to issue new instructions, thus increasing latency and failing to improve access speed.

[0150] (Second specific example)

[0151] Figure 15 This diagram illustrates the connection relationships between the memory controller 300, the I / F chip 210, and the two NAND chips CPA and CPC in the second embodiment. The second embodiment shares similarities with the first embodiment in that the memory controller 300 uses the SCA protocol. However, it differs from the first embodiment in that the I / F chip 210 and each NAND chip CP have a dedicated CA bus for instructions / addresses and a dedicated DQ bus for data.

[0152] Figure 16 This is the timing diagram for the second specific example. Figure 16 The diagram illustrates the DQ and CA buses between the memory controller 300 and the I / F chip 210, the DQ(CH0) and CA(CH0) buses between the I / F chip 210 and the NAND chip CPA, the internal operation of the NAND chip CPA, the DQ(CH1) and CA(CH1) buses between the I / F chip 210 and the NAND chip CPC, and the internal operation and timing of the NAND chip CPC. The following is a comparison with... Figure 12 The explanation will focus on the timing differences in the first specific example shown.

[0153] In the second specific example, a DQ(CH0) bus and a CA(CH0) bus are provided between the I / F chip 210 and the NAND chip CPA. Therefore, after the I / F chip 210 sends a data output command to the CA(CH0) bus at time t5, it sends an SCE command, which indicates the start of data output, to the CA(CH0) bus at time t7. Similarly, after the I / F chip 210 sends a data output command to the CA(CH1) bus at time t6, it sends an SCE command, which indicates the start of data output, to the CA(CH1) bus at time t8.

[0154] Additionally, at time t10, while the NAND chip CPA is sending data corresponding to read instruction A via the DQ(CH0) bus, the I / F chip 210 sends a new read instruction A via the CA(CH0) bus. Similarly, at time t11, while the NAND chip CPC is sending data corresponding to read instruction C via the DQ(CH1) bus, the I / F chip 210 sends a new read instruction C via the CA(CH1) bus.

[0155] Therefore, the data output period (times t12 to t31) of the second specific example is shorter than that of the first specific example (times t12 to t31), which can improve the output.

[0156] (Third specific example)

[0157] The memory controller 300, I / F chip 210, and two NAND chips CPA and CPC in the third specific example are equipped with... Figure 15 The connection relationship is the same as that shown in the second specific example. In the third specific example, the start of data output can be indicated when the data stored in the storage unit 2 within the I / F chip 210 is started to be transmitted via the DQ bus, and the end of data output can be indicated when the transmission of the data stored in the storage unit 2 ends. Thus, the instructions indicating the start of data output and the instructions indicating the end of data output are omitted.

[0158] Figure 17 This is the timing diagram for the third specific example. At time t11, and... Figure 16 Similarly, at time t11, the memory controller 300 sends a command indicating the start of data output via the CA bus. Afterwards, the memory controller 300 no longer sends commands indicating the end of data output or the start of data output to the CA bus.

[0159] Therefore, the data output period of the third specific example (times t12 to t27) can be shortened compared to the data output period of the second specific example (times t12 to t31), thereby improving the output.

[0160] In the third embodiment, when the memory controller 300 uses the SCA protocol, the I / F chip 210, after storing data in the storage unit 2, issues a data output instruction from the memory controller 300, specifically an SCE instruction indicating the start of data output. After the memory controller 300 issues the SCE instruction, the I / F chip 210 in the third embodiment sends all the corresponding data stored in the storage unit 2 to the memory controller 300. Then, without waiting for the SCE instruction indicating the start of data output, the I / F chip 210 in the third embodiment sends all the corresponding data stored in the storage unit 2 to the memory controller 300 when the memory controller 300 issues the data output instruction.

[0161] More specifically, in the I / F chip 210 of the third embodiment, the storage unit 2 stores multiple data output from multiple NAND chips CP. Then, after the memory controller 300 initially issues a data output instruction, specifically an SCE instruction indicating the start of data output, the I / F chip 210 of the third embodiment sends the initial data from the multiple data sets to the memory controller 300. Then, when the memory controller 300 issues a data output instruction a second or subsequent time, the I / F chip 210 of the third embodiment does not wait for an SCE instruction indicating the start of data output from the memory controller 300, but instead sends all the corresponding data stored in the storage unit 2 to the memory controller 300.

[0162] (4th specific example)

[0163] In the first to third examples, the memory controller 300 uses the SCA protocol. In contrast, in the fourth example, the memory controller 300 uses a standard protocol.

[0164] Figure 18 This diagram illustrates the connection relationships between the memory controller 300, the I / F chip 210, and the two NAND chips CPA and CPC in the fourth specific example. The memory controller 300 and the I / F chip 210 transmit instructions / addresses and data via the DQ bus. Furthermore, the I / F chip 210 and the NAND chip CPCA transmit instructions / addresses and data via the DQ(CH0) bus, and the I / F chip 210 and the NAND chip CPCB transmit instructions / addresses and data via the DQ(CH1) bus.

[0165] Figure 19 This is the timing diagram for the fourth specific example. Figure 19 The diagram illustrates the DQ bus between the memory controller 300 and the I / F chip 210, the DQ(CH0) bus between the I / F chip 210 and the NAND chip CPA, the internal operation of the NAND chip CPA, the DQ(CH1) bus between the I / F chip 210 and the NAND chip CPB, and the internal operation and timing of the NAND chip CPB. The following is a comparison with... Figure 12 The explanation will focus on the timing differences in the first specific example shown.

[0166] In the fourth specific example, instructions / addresses and data are transferred between the memory controller 300 and the I / F chip 210 via the DQ bus. Therefore, at time t5, the I / F chip 210 sends a data output instruction A via the DQ(CH0) bus. At time t10, after the NAND chip CPA sends the corresponding data to the DQ(CH0) bus, the memory controller 300 sends a new read instruction A via the DQ bus. Then, at time t11, the memory controller 300 sends a new read instruction C via the DQ bus. This is how the timing of the memory controller 300 issuing new read instructions A and C is compared. Figure 12 Significant delay.

[0167] Subsequently, the memory controller 300 sends a data output command A via the DQ bus at time t12. Upon receiving the data output command A, the I / F chip 210 sends the stored data of the storage unit 2 via the DQ bus between times t13 and t15.

[0168] At time t15, the memory controller 300 sends a data output command C via the DQ bus. Upon receiving the data output command C, the I / F chip 210 sends the stored data of the storage unit 2 via the DQ bus from time t16 to t19.

[0169] The I / F chip 210 and the NAND chips CPA and CPC perform the same actions as those at times t2 to t11 during times t11 to t21 and t21 to 30.

[0170] In the fourth example, the memory controller 300 and the I / F chip 210 transmit instructions / addresses and data via the DQ bus. Therefore, in the fourth example, the data output period t13 to t29 is longer compared to the first to third examples. However, in the fourth example, before the memory controller 300 issues a data output instruction, the I / F chip 210 sends the data output instruction to the NAND chips CPA and CPC, pre-reads the stored data of the NAND chips CPA and CPC, and stores it in the storage unit 2. Therefore, in the fourth example, similar to the first to third examples, the stored data in the storage unit 2 can be quickly sent to the memory controller 300 when the memory controller 300 issues a data output instruction, thereby improving the output volume.

[0171] (Installation configuration of semiconductor memory device 200)

[0172] like Figure 9 As shown, the semiconductor memory device 200 of this embodiment, which includes an I / F chip 210 and multiple NAND chip CPs, can be a single integrated chip or a separate chip. Hereinafter, representative mounting configurations of the semiconductor memory device 200 including the I / F chip 210 and multiple NAND chip CPs will be described.

[0173] Figure 20A This diagram illustrates a first mounting example of the semiconductor memory device 200 according to this embodiment. In this first mounting example, the semiconductor memory device 200 has an I / F chip 210 of this embodiment mounted on a support substrate 24, and an integrated chip with multiple NAND chip CPs stacked and packaged on the I / F chip 210. This integrated chip in the first mounting example enables miniaturization of the chip area.

[0174] Figure 20B This diagram illustrates a second mounting example of the semiconductor memory device 200 according to this embodiment. The semiconductor memory device 200 in the second mounting example is an integrated chip obtained by arranging the I / F chip 210 of this embodiment and a plurality of stacked NAND chip CPs adjacently on a support substrate 24 and then packaging them. The integrated chip in the second mounting example has a larger chip area than that in the first mounting example, making wiring between the integrated chip and the NAND chip CPs easier.

[0175] Figure 20C This diagram illustrates a third mounting example of the semiconductor memory device 200 according to this embodiment. The semiconductor memory device 200 in this third mounting example is obtained by arranging the package components of the I / F chip 210 of this embodiment and the package components of the multiple stacked NAND chip CPs adjacently on a PCB (Printed Circuit Board) 25. Because the integrated chip and the NAND chip CPs are packaged separately, noise immunity is improved.

[0176] In this way, the I / F chip 210 of this embodiment has a control unit 1 that can send instructions (e.g., data output instructions) to the memory chip (e.g., NAND chip CP) at an independent timing that is different from the input timing of the instructions (e.g., read instructions) issued by the memory controller 300, so that the output amount of data output to the memory controller 300 can be increased.

[0177] The present invention is not limited to the described embodiments, and includes various variations that can be conceived by those skilled in the art. The effects of the present invention are not limited to the described contents. That is, various additions, modifications, and partial deletions can be made within the scope of the claims and their equivalents, without departing from the concept and spirit of the present invention.

[0178] [Explanation of Symbols]

[0179] 1: Control Department

[0180] 2: Storage Department

[0181] 3: Selector

[0182] 10: Input / output circuit

[0183] 20: Registers

[0184] 21: Status Register

[0185] 22: Address Register

[0186] 23: Instruction Register

[0187] 24: Supporting substrate

[0188] 30: Sequencer

[0189] 40: Voltage generation circuit

[0190] 51A: Memory Cell Array

[0191] 52A: Line Decoder

[0192] 53A: Sensing Amplifier

[0193] 54A: Data Register

[0194] 55A: Column Decoder

[0195] 100: Memory System

[0196] 200: Semiconductor memory devices

[0197] 210: I / F chip

[0198] 300: Memory Controller

[0199] 310: Host Interface Circuit

[0200] 320: Memory interface circuit

[0201] 400: Main unit.

Claims

1. An interface chip, comprising: Signal lines 1, 2, and 3 are used to receive signals from the memory controller. Multiple fourth signal lines are used to send and receive signals with the memory controller, respectively; Multiple fifth signal lines are used to transmit and receive signals with the first memory chip, which contains multiple memory cells; Storage department; and Control Department: When the first signal received from the memory controller by the third signal line is at the first logic level. After receiving a first instruction for a read operation from the memory controller via the first signal line and the second signal line, a second instruction corresponding to the first instruction and for a read operation is sent to the first memory chip via the plurality of fifth signal lines. After the read operation of the first memory chip is completed, and before receiving the third instruction for data output from the memory controller via the first signal line and the second signal line, the fourth instruction for data output is sent to the first memory chip via the plurality of fifth signal lines. Received via the plurality of fifth signal lines: First data output from the first memory chip in response to the fourth instruction sent to the first memory chip. The received first data is saved to the storage unit. After receiving the third instruction, the saved first data is sent to the memory controller via the plurality of fourth signal lines.

2. The interface chip according to claim 1, wherein... The control unit: In the case where the first signal is a second logic level that is different from the first logic level. After receiving the fifth instruction for a read operation from the memory controller via the plurality of fourth signal lines, a sixth instruction corresponding to the fifth instruction and for a read operation is sent to the first memory chip via the plurality of fifth signal lines. After the read operation of the first memory chip is completed, and before receiving the seventh instruction for data output from the memory controller via the plurality of fourth signal lines, the eighth instruction for data output is sent to the first memory chip via the plurality of fifth signal lines. Received via the plurality of fifth signal lines: Second data output from the first memory chip in response to the eighth instruction sent to the first memory chip. Save the received second data. After receiving the 7th instruction, the saved 2nd data is sent to the memory controller via the plurality of 4th signal lines.

3. The interface chip according to claim 1 or 2, further comprising: The sixth signal line is used to receive signals from the memory controller; and Multiple seventh signal lines are used for transmitting and receiving signals with a second memory chip containing multiple memory cells; and The control unit: When the second signal received from the memory controller by the sixth signal line is the first logic level. After receiving the 9th instruction for a read operation from the memory controller via the 1st signal line and the 2nd signal line, the 10th instruction corresponding to the 9th instruction and for a read operation is sent to the 2nd memory chip via the plurality of 7th signal lines. After the read operation of the second memory chip is completed, and before receiving the 11th instruction for data output from the memory controller via the first and second signal lines, the 12th instruction for data output is sent to the second memory chip via the plurality of 7 signal lines. Received via the plurality of seventh signal lines: third data output from the second memory chip in response to the 12th instruction sent to the second memory chip. Save the received third data. After receiving the 11th instruction, the saved 3rd data is sent to the memory controller via the plurality of 4th signal lines.

4. The interface chip according to claim 3, wherein The control unit: When the second signal is at the second logic level, After receiving the 13th instruction for a read operation from the memory controller via the plurality of 4th signal lines, the 14th instruction corresponding to the 13th instruction and for a read operation is sent to the second memory chip via the plurality of 7th signal lines. After the read operation of the second memory chip is completed, and before receiving the 15th instruction for data output from the memory controller via the plurality of 4th signal lines, the 16th instruction for data output is sent to the second memory chip via the plurality of 7th signal lines. Received via the plurality of seventh signal lines: Fourth data output from the second memory chip in response to the 16th instruction sent to the second memory chip. Save the received fourth data. After receiving the 15th instruction, the saved 4th data is sent to the memory controller via the plurality of 4th signal lines.

5. The interface chip according to claim 1, wherein... The first instruction includes a first address, which specifies the first memory cell from the plurality of memory cells of the first memory chip from which the read object is to be retrieved. The second address contained in the second instruction specifies the first storage unit.

6. The interface chip according to claim 5, wherein... The third instruction includes: specifying the third address of the first storage unit. The fourth address contained in the fourth instruction specifies the first storage unit.

7. The interface chip according to claim 1, wherein... The first memory chip includes a latch circuit, and in response to the second instruction, reads the data stored in the first memory cell and saves it to the latch circuit.

8. The interface chip according to claim 7, wherein In response to the fourth instruction, the first memory chip outputs the first data, which includes the data stored in the latch circuit.

9. The interface chip according to claim 2, wherein The sixth instruction is the same as the fifth instruction, and the eighth instruction is the same as the seventh instruction.

10. The interface chip according to claim 2, wherein The first logic level is high, and the second logic level is low.

11. The interface chip according to claim 1, further comprising: The 8th signal line is used to receive signals from the memory controller. When the first signal is at the first logic level, the control unit uses the third signal received on the eighth signal line as a timing signal, and identifies the first instruction based on the fourth signal received via the first signal line and the fifth signal received via the second signal line.

12. The interface chip according to claim 1, wherein... After a predetermined time has elapsed since the control unit sent the second instruction to the first memory chip, it sends the fourth instruction to the first memory chip.

13. The interface chip according to claim 1, wherein... After sending the second instruction to the first memory chip, if there is a logical change in the specified signal indicating the operation state sent from the first memory chip, the control unit will send the fourth instruction to the first memory chip.

14. The interface chip according to claim 13, wherein The specified signal is: ready / busy signal.

15. The interface chip according to claim 1, wherein... The storage unit is SRAM.

16. A semiconductor memory device comprising: The interface chip according to any one of claims 1, 2, and 5 to 15, and The first memory chip.

17. A semiconductor memory device comprising: The interface chip according to claim 3 or 4, The first memory chip, and The second memory chip.

18. A memory system comprising: The semiconductor memory device according to claim 16 or 17, and the memory controller.

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