A row hammer refresh circuit, a row hammer refresh method, and a memory

Abstract

The embodiment of the present disclosure provides a row hammer refresh circuit, a method and a memory. The row hammer refresh circuit comprises: a counting circuit configured to determine an activation number value of a row address; a comparison circuit configured to compare the activation number value of the row address with a preset number threshold; and a write control circuit configured to, when the activation number value of the row address is greater than or equal to the preset number threshold, exist a first operation state. The first operation state is: storing the row address into a row hammer refresh table, and initializing the activation number value of the row address. The row hammer refresh table is configured to store the row address.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a row hammer refresh circuit, a row hammer refresh method, and a memory. Background Technology

[0002] Currently, for memories such as Dynamic Random Access Memory (DRAM), frequent read / write operations on a row in the memory (also known as the attack row) can easily cause frequent voltage jumps on the word line corresponding to that row. These voltage jumps can cause electromagnetic interference to adjacent rows of the memory cell, which can easily affect the accuracy of the data stored in adjacent rows, and thus affect the accuracy of memory read / write operations. This phenomenon is usually called row hammering.

[0003] To mitigate the impact of row hammering on memory, the number of times each row is activated (hereinafter referred to as the activation count value) is recorded. When the activation count value of a row exceeds a preset threshold, that row is designated as the attack row, and row hammering refresh processing is performed on the adjacent rows of the attack row. During the row hammering refresh process, the adjacent rows are refreshed, and the activation count value of the attack row is cleared. In other words, the process of clearing the activation count value of the attack row in the above row hammering refresh process will occupy the row refresh cycle time specified in the protocol, making it difficult to ensure that the refresh processing of adjacent rows is completed within the specified time.

[0004] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0005] This disclosure provides a row hammer refresh circuit, a row hammer refresh method, and a memory.

[0006] In a first aspect, embodiments of this disclosure provide a row hammer refresh circuit, including: The counting circuit is configured to determine the number of times the row address is activated; The comparison circuit is configured to compare the activation count value of the row address with the size of a preset count threshold; The write control circuit is configured to have a first operation state when the activation count value of the row address is greater than or equal to the preset threshold value; the first operation state is: storing the row address in the row hammer refresh table and initializing the activation count value of the row address; The row hammer refresh table is configured to store row addresses.

[0007] In some embodiments, the write control circuit is further configured to have a second operation state when the activation count value of the row address is greater than or equal to the preset count threshold; the second operation state is to update the activation count value of the row address and rewrite the updated activation count value.

[0008] In some embodiments, the counting circuit includes: The first sub-counting circuit is configured to count the number of activations of the row address starting from an initial value to obtain a first count value; The second sub-counting circuit is configured to count based on a preset duration during the period when the row address is activated, and obtain a second count value; An adder circuit is configured to add the first count value and the second count value to obtain the activation count value of the row address.

[0009] In some embodiments, the number of preset number thresholds is N, where N is an integer greater than or equal to 2, wherein the first preset number threshold is the minimum value among the N preset number thresholds, and the Nth preset number threshold is the maximum value among the N preset number thresholds; The row hammer refresh table includes M storage units for storing the row addresses. When M-1 row addresses have been filled into the row hammer refresh table, the activation count value corresponding to the row address filled into the Mth storage unit is greater than or equal to the Nth preset threshold.

[0010] In some embodiments, the N preset number thresholds gradually increase from the first preset number threshold to the Nth preset number threshold, and the N preset number thresholds divide the range greater than the first preset number threshold into N sequentially increasing number intervals; The write control circuit is further configured to, if the activation count value of the row address is in the i-th count interval, store the row address in the row hammer refresh table and set the i-th refresh flag for the row address; Where i is an integer greater than or equal to 1 and less than or equal to N, and the row hammer refresh priority of the row address corresponding to the refresh flag with a larger i value is higher than that of the row address corresponding to the refresh flag with a smaller i value.

[0011] In some embodiments, the row hammer refresh table includes a plurality of storage units for storing the row addresses, wherein a preset number of the storage units are reserved; The write control circuit is further configured to determine whether the number of free storage units in the row hammer refresh table is less than or equal to the preset retention number when the activation count value of the row address is greater than or equal to the preset threshold value. The write control circuit is further configured to maintain the first operation state even when the number of free storage units is greater than the preset retention number. The write control circuit is further configured to, when the number of free storage units is less than or equal to the preset reserved number and greater than 0, maintain the first operation state if the activation count of the row address is greater than or equal to the Nth preset threshold; maintain the second operation state if the activation count of the row address is less than the Nth preset threshold; and / or maintain the second operation state when the number of free storage units is 0 or the activation count of the row address is less than the first preset threshold.

[0012] In some embodiments, the write control circuit is further configured to send an alarm backoff instruction to the host when the number of free storage units is 1 and the activation count of the row address is greater than or equal to the Nth preset threshold, and / or when the number of refresh flags of the Nth refresh flag signal in the row hammer refresh table is greater than a first preset number; so that the host responds to the alarm backoff instruction and issues a preset refresh command.

[0013] In some embodiments, the row hammer refresh table includes a plurality of first storage units and a predetermined number of second storage units. The first storage units are used to store row addresses and activation count values ​​corresponding to the row addresses, and the second storage units are used only to store the row addresses. The write control circuit is further configured to, when the activation count of the row address is greater than or equal to the preset threshold, preferentially store the row address into the first storage unit; when the row hammer refresh table has only the second storage unit available, compare the activation count of the row address with the activation count of the existing row addresses in the row hammer refresh table, and store the row address with the largest activation count into the second storage unit; wherein, the row hammer refresh operation of the row address in the second storage unit is preferentially executed.

[0014] In some embodiments, the write control circuit is further configured to initialize the activation count value of the row address to a random value.

[0015] Secondly, this disclosure provides a row hammer refresh method, the method comprising: determining the activation count value of the row address; Compare the activation count value of the row address with the value of the preset threshold count; When the activation count of the row address is greater than or equal to the preset threshold, a first operation state exists; the first operation state is: storing the row address in the row hammer refresh table and initializing the activation count of the row address.

[0016] In some embodiments, determining the activation count value of the row address includes: Determine a first count value and a second count value corresponding to the row address; wherein, the first count value is the count value obtained by counting the number of times the row address is activated starting from the initial value, and the second count value is the ratio of the activation duration of the row address to a preset duration; The first count value and the second count value are added together to obtain the activation count value of the row address.

[0017] In some embodiments, the number of preset number thresholds is N, where N is an integer greater than or equal to 2. The first preset number threshold is the minimum value among the N preset number thresholds, and the Nth preset number threshold is the maximum value among the N preset number thresholds. The row hammer refresh table includes M row address storage units. When M-1 row addresses have been filled into the row hammer refresh table, the activation count value corresponding to the row address filled into the Mth row address storage unit is greater than or equal to the Nth preset number threshold.

[0018] In some embodiments, the row hammer refresh table includes a plurality of first storage units and a predetermined number of second storage units, wherein the first storage units are used to store row addresses and the activation counts corresponding to the row addresses, and the second storage units are used only to store the row addresses; when the activation count value of the row address is greater than or equal to the preset threshold value, the method further includes: The row address is preferentially stored in the first storage unit. When the row hammer refresh table is empty only in the second storage unit, the activation count value of the row address is compared with the activation count value of the existing row address in the row hammer refresh table, and the row address with the largest activation count value is stored in the second storage unit. Among them, the row hammer refresh operation of the row address in the second storage unit is preferentially executed.

[0019] In some embodiments, the method further includes: when the activation count value of the row address is greater than or equal to the preset count threshold, there is a second operation state; the second operation state is: updating the activation count value of the row address and rewriting the updated activation count value.

[0020] In some embodiments, the N preset number thresholds gradually increase from the first preset number threshold to the Nth preset number threshold, and the N preset number thresholds divide the range greater than the first preset number threshold into N sequentially increasing number intervals; the method further includes: if the activation number value of the row address is in the i-th number interval, storing the row address in the row hammer refresh table, and setting the i-th refresh flag for the row address; wherein i is an integer greater than or equal to 1 and less than or equal to N, and the row hammer refresh priority of the row address corresponding to the refresh flag with a larger i value is higher than that of the row address corresponding to the refresh flag with a smaller i value.

[0021] In some embodiments, the row hammer refresh table includes a plurality of storage units for storing the row addresses, wherein a preset number of the storage units are reserved; The method further includes: when the activation count value of the row address is greater than or equal to the preset count threshold, determining whether the number of free storage units in the row hammer refresh table is less than or equal to the preset reserved number; Even when the number of free storage units is greater than the preset reservation number, the first operating state still exists; When the number of free storage units is less than or equal to the preset reserved number and greater than 0, if the activation count of the row address is greater than or equal to the Nth preset threshold, the first operation state still exists; if the activation count of the row address is less than the Nth preset threshold, the second operation state still exists; and / or, when the number of free storage units is 0, or when the activation count of the row address is less than the first preset threshold, the second operation state still exists.

[0022] In some embodiments, the method further includes: when the number of free storage units is 1 and the activation count of the row address is greater than or equal to the Nth preset threshold, and / or when the number of the Nth refresh flags in the row hammer refresh table is greater than a first preset number, sending an alarm backoff instruction to the host; so that the host responds to the alarm backoff instruction and issues a preset refresh command.

[0023] In some embodiments, initializing the activation count value of the row address includes: initializing the activation count value of the row address to a random value.

[0024] Thirdly, embodiments of this disclosure provide a memory including the row hammer refresh circuit as described in the first aspect.

[0025] This disclosure provides a row hammer refresh circuit, a row hammer refresh method, and a memory. By advancing the initialization step of the activation count value before the row hammer refresh operation, for example, by advancing it to be synchronized with or after the step of writing the row address into the row hammer refresh table, the above initialization step does not need to be executed during the row hammer refresh process. This provides sufficient time for the row hammer refresh process, avoids insufficient time causing the refresh to fail or result in errors, and ensures the data integrity of the memory. Attached Figure Description

[0026] Figure 1 A timing diagram provided for embodiments of this disclosure Figure 1 ; Figure 2 A schematic diagram of a row hammer refresh circuit provided in this embodiment of the present disclosure. Figure 1 ; Figure 3 A timing diagram provided for embodiments of this disclosure Figure 2 ; Figure 4 A timing diagram provided for embodiments of this disclosure Figure 3 ; Figure 5 A schematic diagram of a row hammer refresh circuit provided in this embodiment of the present disclosure. Figure 2 ; Figure 6 A schematic diagram of a row hammer refresh circuit provided in this embodiment of the present disclosure. Figure 3 ; Figure 7 A flowchart illustrating a row hammer refresh method provided in this embodiment of the disclosure. Figure 1 ; Figure 8 A flowchart illustrating a row hammer refresh method provided in this embodiment of the disclosure. Figure 2 ; Figure 9 A flowchart illustrating a row hammer refresh method provided in this embodiment of the disclosure. Figure 3 . Detailed Implementation

[0027] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only for explaining the relevant applications and are not intended to limit the scope of this disclosure. Furthermore, it should be noted that, for ease of description, only the parts relevant to the relevant applications are shown in the accompanying drawings.

[0028] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of this disclosure only and is not intended to be limiting of this disclosure.

[0029] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0030] It should be noted that the terms "first, second, third" used in the embodiments of this disclosure are merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first, second, third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0031] Before providing a further detailed description of the embodiments of this disclosure, the nouns and terms used in the embodiments of this disclosure will be explained. The nouns and terms used in the embodiments of this disclosure shall be interpreted as follows: Per Row Activation Counting (PRAC); Refresh Management (RFM); RowHammer refresh (RHR); Activation Counter (AC) value; Activation Counter Initialization (ACI); RowHammer table; Row Refresh Cycle Time (tRFC); Row Cycle Time (tRC); Activation Counter Update (ACU); Line Activation Time (tRAS); Row Precharge Time (tRP); Repository (Bank); Alert bank off (ABO).

[0032] To avoid memory malfunctions caused by row hammering, a PRAC design records the number of times each word line in the memory is activated (i.e., the activation count value). A row hammering table is used to record the attacking rows (i.e., the rows corresponding to frequently activated word lines) and the activation count value corresponding to each attacking row. The method for determining whether to write the row address and activation count value of the attacking row into the row hammering table is as follows: the activation count value corresponding to the current word line is compared with the activation count value recorded in the row hammering table. If the activation count value corresponding to the current word line is greater than the activation count value of a certain row in the row hammering table, then the row address and activation count value of that row in the row hammering table are replaced with the row address and activation count value of the row corresponding to the current word line. The row address written into the row hammering table can be understood as the row address of the attacking row. Alternatively, the activation count value corresponding to the current word line is compared with a preset threshold. If the activation count value corresponding to the current word line is greater than the preset threshold, the row address and activation count value of the row corresponding to the current word line are written into the row hammer table. The row address written into the row hammer table can be understood as the row address of the attack row.

[0033] It should be noted that after a refresh command is issued, the memory needs to perform a row-by-row refresh process within the time period specified in the protocol. The row-by-row refresh process involves performing a refresh operation on the adjacent rows of the attacking row (denoted as the victim row). The tRFC specified in the protocol defines the minimum number of clock cycles required for a complete refresh operation on a row in the memory. That is, the shortest time that must be waited from the issuance of a refresh command until the row that needs to be refreshed can be reactivated or subjected to other operations (e.g., read / write).

[0034] In one possible implementation, after receiving the refresh command, a hammer refresh process needs to be performed on the victim row, including activation, access (read / write), precharge processing, and initialization of the activation count value of the attacking row, among other steps. Since the refresh process involves multiple steps, and each step consumes a time period specified in tRFC, in practical applications, it may be difficult to ensure that all the above processing steps are completed within the specified time period of tRFC.

[0035] The following is based on Figure 1 Let's take an example to further illustrate this. Figure 1 A timing diagram provided for embodiments of this disclosure Figure 1 ,like Figure 1As shown, taking two adjacent rows of the victim row (including the attacking row) as an example, the attacking row is denoted as WL, and the two adjacent rows are denoted as WL+1 and WL-1, respectively. WL+1 and WL-1 represent the row adjacent to WL in the first direction and the row adjacent to WL in the opposite direction, respectively. Here, tRC can be understood as the shortest time interval from when the activation command for a row is issued to when that row can be reactivated. During row hammer refresh processing, the initialization of the activation count value for row WL and the refresh processing of rows WL+1 and WL-1 need to be completed within the time period corresponding to tRFC. The refresh processing of rows WL+1 and WL-1 may also include ACU processing steps for these two rows. However, in practical applications, it may not be possible to complete all the necessary processing within the tRFC time period. For example, taking a tRFC of 160ns (in practical applications, this time applies to dual-bank memory, i.e., memory operating in dual-bank mode) as an example, the processing time for each of the three rows is approximately 53ns. However, in actual specifications, the row cycle time for a row is 60ns. Therefore, the minimum time requirement for the row cycle time cannot be guaranteed during the row hammer refresh process. Since the row cycle time is usually composed of two parts, tRAS and tRP, the above row hammer refresh process cannot guarantee the complete tRAS and / or tRP time, thus adversely affecting the integrity and accuracy of the data corresponding to the above rows.

[0036] Furthermore, due to the influence of different processes, voltages, and temperatures (PVT), the above-mentioned times will also have actual deviations, making it even more difficult to ensure data integrity.

[0037] Based on this, this disclosure provides a row hammer refresh circuit. By initializing the activation count value corresponding to the row address written to the row hammer refresh table when writing the row address, the initialization of the activation count value does not require occupying the tRFC during refresh processing. This ensures that the refresh processing of the adjacent rows corresponding to the attacked row can be completed within the tRFC time requirement, thereby ensuring data integrity. It should be noted that the following embodiments are applicable to memories exhibiting row hammering phenomena.

[0038] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0039] Figure 2 A schematic diagram of a row hammer refresh circuit provided in this embodiment of the present disclosure. Figure 1 ,like Figure 2 As shown, the row hammer refresh circuit 20 includes: The counting circuit 201 is configured to determine the activation count value of the row address; Comparison circuit 202 is configured to compare the activation count value of the row address with the size of a preset count threshold; The write control circuit 203 is configured to have a first operation state when the activation count value of the row address is greater than or equal to a preset threshold value; the first operation state is: to store the row address in the row hammer refresh table 204 and initialize the activation count value of the row address. Row hammer refresh table 204 is configured to store row addresses.

[0040] It should be noted that the counting circuit 201 is used to count the number of times the row address is activated to obtain the corresponding activation count value. In this embodiment, the structure of the counting circuit 201 is not specifically limited. For example, the counting circuit 201 can be implemented using a counter, which can determine the activation count value of the row address by determining the number of activation commands or precharge commands corresponding to the row address. That is to say, in this embodiment, one counting circuit 201 can correspond to one row address and is used to determine the activation count value corresponding to that row address.

[0041] It should also be noted that the comparison circuit 202 can be connected to the counting circuit 201 to obtain the activation count value determined by the counting circuit 201 and compare the activation count value with a preset threshold. In one possible implementation, the comparison result obtained by the comparison circuit 202 can indicate the likelihood that a row address will affect adjacent row data. For example, if the activation count value of the row address is greater than or equal to the preset threshold, it indicates a high likelihood of affecting adjacent row data. If the activation count value of the row address is less than the preset threshold, it indicates a low likelihood of the current row affecting adjacent row data.

[0042] It should also be noted that this embodiment does not impose specific restrictions on the setting of the preset number of times threshold. In practical applications, one or more preset number of times thresholds can be set. When there are multiple preset number of times thresholds, it can be understood as classifying the degree of possibility of the current row affecting the data of adjacent rows. For example, when there are multiple preset number of times thresholds, if the activation count value of the row address is greater than or equal to any of the preset number of times thresholds, it indicates that the row address meets the entry condition, and the first operation can be executed. For example, the preset number of times threshold can be 1k, 4k, 5k, 8k, 10k, or 15k. In this embodiment, there are no specific restrictions on the value of the preset number of times threshold. In one possible implementation, the value of the preset number of times threshold is related to the process parameters corresponding to the memory and can be determined according to the row hammer intrinsic value of the memory. When the activation count value is greater than the row hammer intrinsic value, it indicates that it will definitely affect the data of adjacent rows. Therefore, in order to avoid the above phenomenon from definitely occurring, a value less than the row hammer intrinsic value can be selected as the preset number of times threshold. It should be noted that, in the embodiments of this disclosure, performing the first operation refers to the specific operation process of performing the first operation state.

[0043] The write control circuit 203 can be connected to the comparison circuit 202 to obtain the comparison result obtained by the comparison circuit 202. If the write control circuit 203 determines that the activation count value corresponding to the row address is greater than or equal to the preset count threshold, it indicates that the row address is likely to have a significant impact on the data stored corresponding to the adjacent row address. In this case, the row address can be written into the row hammer refresh table 204 so that the adjacent rows of the attack row indicated by the row address in the row hammer refresh table 204 can be subjected to row hammer refresh processing in the future.

[0044] It should be noted that, in one possible implementation, if the activation count value corresponding to the row address is greater than or equal to a preset threshold, the data written to the row hammer refresh table 204 can also be indication information used to indicate the row address, and there is no need to further write the activation count value corresponding to the storage row address, thereby reducing the actual storage space occupied by the row hammer refresh table 204. That is to say, the row hammer refresh table 204 can include row address information and the corresponding activation count value, or it can include only row address information.

[0045] In this embodiment, the row hammer refresh table 204 is used to store the row address of the attack row. Subsequently, the row hammer refresh processing can be performed on the adjacent rows based on the row address recorded in the row hammer refresh table 204.

[0046] Furthermore, in this embodiment, the activation count value corresponding to the row address is initialized simultaneously with, after, or before the row address is written to the row hammer refresh table 204. It should be noted that this initialization process sets the activation count value to an initial value. Specifically, the activation count value can be stored in the memory array, and the initialization process can be an operation to initialize the activation count value recorded in the memory array; and / or, the activation count value is output by the counting circuit 201, and the initialization process initializes the output of the counting circuit 201 so that in subsequent operations, the counting circuit 201 restarts counting the activation count value of the row address from the initial value, avoiding errors in the activation count value caused by continuous accumulation of counts. In one possible implementation, the above initialization operation includes steps such as reading the activation count value, rewriting the activation count value, and writing the rewritten activation count value; in another possible implementation, an initialization command can be sent to the counting circuit 201 to initialize its output. The initialization value after this initialization operation is not specifically limited.

[0047] It is understood that in this embodiment, by initializing the activation count value corresponding to the row address when writing the row address into the row hammer refresh table 204, the step of initializing the activation count value is brought forward to when the row address is written into the row hammer refresh table 204. There is no need to wait for the row hammer refresh process to perform the initialization of the activation count value, so that the initialization process of the activation count value does not occupy the processing time of the row hammer refresh process. There is enough time in the row hammer refresh process to perform row hammer refresh processing on the victim row to ensure the data integrity in the memory.

[0048] Furthermore, in this embodiment, the row hammer refresh table 204 can store only the row address. Compared with the storage method of storing both the row address and the activation count value corresponding to the row address in the row hammer refresh table 204, the storage space occupied by the row hammer refresh table 204 can also be reduced.

[0049] Furthermore, compared to the method that requires comparing the activation count of the row address with each activation count stored in the row hammer refresh table 204 to determine whether the row address can be written into the row hammer refresh table 204, in this embodiment, it is only necessary to compare the activation count of the row address with a preset threshold to determine whether to write it into the row hammer refresh table 204, which can improve the comparison efficiency.

[0050] In one possible implementation, the activation count value can be initialized to a preset value during initialization, such as a fixed value of 0 or any other value. In another possible implementation, the activation count value can be initialized to a random value during initialization.

[0051] Understandably, with the activation count initialized to 0, an external attacker could deduce the row order of the row hammer refresh based solely on the activation count. However, initializing the activation count to a random value makes it difficult for an external attacker to deduce the row hammer refresh order from the value alone, thus improving memory security.

[0052] Figure 3 and Figure 4 This is a timing diagram illustrating the row hammer refresh process based on the row hammer refresh circuit 20 provided in the embodiments of this disclosure. Figure 3 The timing diagram shown illustrates that after the row address corresponding to row WL is written into the row hammer refresh table 204, row hammer refresh processing can be performed on rows WL+1 and WL-1 during row hammer refresh processing. Since the activation count value of row WL has been initialized before the row hammer refresh processing, within the time requirement tRFC corresponding to the row hammer refresh, only row WL+1 and WL-1 need to be processed separately, without needing to perform the initialization processing of the activation count value, thus providing ample timing.

[0053] It should be noted that in one possible implementation, during the row hammer refresh process for rows WL+1 and WL-1, the activation count values ​​for these two rows also need to be updated. This is achieved through comparison. Figure 3 and Figure 1 As can be seen, the row hammer refresh circuit 20 provided in this embodiment can ensure that the WL row (i.e., the attack row) does not need to be initialized with the activation count value during the row hammer refresh process, which helps to ensure that the row hammer refresh process of the adjacent rows of the attack row is completed within the tRFC time requirement.

[0054] Figure 4 The timing diagram shown illustrates that after the row address corresponding to row WL is written into the row hammer refresh table 204, further, during the row hammer refresh process, rows WL+1, WL+2, WL-1, and WL-2 can be hammer refreshed. This is equivalent to obtaining two adjacent rows on different sides of the attack row and performing hammer refresh processing. Furthermore, this row hammer refresh process does not require initializing the activation count value of row WL, which helps ensure that adjacent rows corresponding to the attack row can be refreshed within the specified time requirement. Figure 4The refresh management time is used to characterize the data (in one possible implementation, the refresh management time can also be characterized by tRFM). This completes the row hammer refresh process for adjacent rows, further ensuring the data integrity of the memory. Similarly, during the row hammer refresh process for the above four rows, ACU processing is also required for each row separately.

[0055] In some embodiments, the write control circuit 203 is further configured to have a second operation state when the activation count value of the row address is greater than or equal to a preset threshold value; the second operation state is to update the activation count value of the row address and rewrite the updated activation count value.

[0056] For example, in this embodiment, when the write control circuit 203 determines, based on the comparison result of the comparison circuit 202, that the activation count value of the row address is greater than or equal to a preset threshold, it can also update the activation count value corresponding to the row address to ensure that the activation count value corresponding to the row address is the latest value and maintains data accuracy. This value can be temporarily stored by rewriting, and when the conditions for filling the row hammer refresh table 204 are met later, the row address is written into the row hammer refresh table 204 according to the corresponding rules and awaits refresh.

[0057] For example, if the activation count of a row address exceeds a preset threshold, and the row address cannot be written to the current row hammer refresh table 204, the write control circuit 203 can perform a second operation to update the activation count of the row address. It should be noted that the situations where the row address cannot be written to the row hammer refresh table 204 may include: when the row hammer refresh table 204 is full, or when, although there is storage space in the current row hammer refresh table 204, the urgency or priority of the row address requiring hammer refresh does not meet the condition for writing to the remaining storage space. It should be noted that in this embodiment, performing the second operation refers to the specific operational process of performing the second operation state.

[0058] In one example, we will illustrate this by setting two preset threshold counts, with the first threshold being less than the second. Specifically, if the activation count for a row address is greater than the first threshold but less than the second threshold, the urgency of performing a hammer refresh on the adjacent rows of that row address is considered low. Conversely, if the activation count is greater than the second threshold, the urgency of performing a row hammer refresh on the adjacent rows of that row address is considered high.

[0059] In the first case: if the activation count of the row address is greater than or equal to the second preset threshold, but the row hammer refresh table 204 has no space to store the row address, the first operation cannot be performed. However, in order to ensure that the adjacent rows of the row address can still be processed by the row hammer refresh, the activation count corresponding to the row address can be updated to ensure that the activation count of the row address is the latest state.

[0060] The second scenario: If the number of activations of the row address is less than the second preset threshold, and the number of activations of the row address is greater than or equal to the first preset threshold, and if the row hammer refresh table 204 has no space to store the row address, then the write control circuit 203 can also perform the second operation.

[0061] The third scenario: If the number of activations of the row address is less than the second preset threshold, and the number of activations of the row address is greater than or equal to the first preset threshold, and if the row hammer refresh table 204 has space to store the row address, but the urgency of the refresh process represented by the number of activations of the row address is low and cannot be written into the remaining storage space of the row hammer refresh table 204, then the write control circuit 203 can also perform the second operation.

[0062] In another example, taking a preset number of times thresholded to one (i.e., the first preset number of times thresholded to one) as an example, if the write control circuit 203 determines that the activation count of the row address is greater than or equal to the first preset number of times thresholded to one, and there is no remaining storage space in the row hammer refresh table 204, then the write control circuit 203 can perform the second operation. If the write control circuit 203 determines that the activation count of the row address is greater than or equal to the first preset number of times thresholded to one, and there is remaining storage space in the row hammer refresh table 204, then the write control circuit 203 can perform the first operation.

[0063] It should be noted that rewriting the updated activation count value here can mean rewriting the updated activation count value into the storage array used to store the activation count value of the row address, and / or rewriting the activation count value corresponding to the row address into the counting circuit 201 (which can be the counter in the counting circuit 201 in actual applications) corresponding to the row address.

[0064] It should also be noted that, in this embodiment of the present disclosure, the comparison circuit 202 can generate an enabled comparison signal when the activation count value corresponding to the row address is greater than or equal to a preset count threshold, and write the control circuit 203 to perform a first operation or a second operation based on the enabled comparison signal; the comparison circuit 202 can generate a disabled comparison signal when the activation count value corresponding to the row address is less than the preset count threshold, and write the control circuit 203 to perform a second operation based on the disabled comparison signal.

[0065] In some embodiments, Figure 5 This is a schematic diagram of a row hammer refresh circuit provided in an embodiment of this disclosure. Figure 5 As shown, the counting circuit 201 may include: The first sub-counting circuit 2011 is configured to count the number of activations of the row address starting from the initial value to obtain a first count value; The second sub-counting circuit 2012 is configured to count based on a preset duration during the period when the row address is activated, and obtain a second count value; The adder circuit 2013 is configured to add the first count value and the second count value to obtain the activation count value of the row address.

[0066] In this embodiment, the counting circuit 201 is exemplarily composed of a first sub-counting circuit 2011, a second sub-counting circuit 2012, and an adder circuit 2013. The first sub-counting circuit 2011 is used to count the number of activations of a row address based on an initial value. Specifically, each time a row address is activated (e.g., each time an activation command or precharge command for that row address is received), the corresponding activation count is incremented by 1, and the first increment is performed based on the initial value. In practical applications, each row in the memory can be equipped with a separate first sub-counting circuit 2011. Exemplarily, the first sub-counting circuit 2011 can be a counter.

[0067] Furthermore, in practical applications, the longer a row is activated, the greater its impact on the data stored in adjacent rows. Therefore, in this embodiment, when determining the activation count, not only is the number of times a row address is activated considered, but also the activation time of each row address is taken into account. The second sub-counting circuit 2012 counts the activation duration corresponding to the row address using a preset duration as the periodic time base. For example, starting from the activation of the row address, the second count value increments by 1 every preset duration. That is, the second count value can be the integer part of the ratio of the row address's activation duration to the preset duration.

[0068] The adder circuit 2013 can be connected to the first sub-counter circuit 2011 and the second sub-counter circuit 2012 respectively. Specifically, the first input terminal of the adder circuit 2013 is connected to the output terminal of the first sub-counter circuit 2011, and the second input terminal of the adder circuit 2013 is connected to the output terminal of the second sub-counter circuit 2012. It is used to obtain the first count value and the second count value respectively, and to sum the first count value and the second count value, and use the summation result as the activation count value corresponding to the row address.

[0069] It should be noted that in practical applications, when setting up the second sub-counting circuit 2012, one second sub-counting circuit 2012 can be configured for each row.

[0070] Alternatively, since only one row in a Bank can be activated at a time, to save circuit area and reduce circuit complexity, a second sub-counting circuit 2012 can be set up for each Bank in the memory. This second sub-counting circuit 2012 counts the rows contained in the Bank. In this case, the counting circuits 201 corresponding to multiple row addresses in a Bank each have their own first sub-counting circuit 2011 and adder circuit 2013, and share the same second sub-counting circuit 2012. More specifically, the output of the second sub-counting circuit 2012 is connected to the second input of multiple adder circuits 2013. A switch is connected between the output of the second sub-counting circuit 2012 and the second input of the adder circuits 2013. The switch connected to the adder circuit is only turned on when the row address corresponding to the adder circuit 2013 is activated, ensuring that the second count value is correctly added. Here, the row address can be used to generate a corresponding switch signal to control the switch's on or off state.

[0071] In one possible implementation, after the second sub-counting circuit 2012 finishes counting and sends the second count value to the adder circuit 2013, the second count value is also cleared or initialized to avoid counting errors caused by continuous accumulation.

[0072] It should also be noted that, based on Figure 5 When the counting circuit 201 writes the activation count value of the initial row address in the first operation of the control circuit 203, it can initialize both the first count value and the second count value. Specifically, the first count value can be initialized to 0 or a random value, and the second count value can be initialized to 0.

[0073] It should also be noted that, based on Figure 5 When the write control circuit 203 performs the second operation, namely the operation of updating the activation count value of the row address, the counting circuit 201 in this embodiment can write the updated activation count value to the first sub-counting circuit 2011 provided in this embodiment, that is, update the first count value to the calculated activation count value and clear the second count value, so as to realize the update writing of the activation count value.

[0074] It is understood that in this embodiment, the activation count value corresponding to the row address is determined by combining the specific activation count of the row address and the activation duration corresponding to the row address. This helps to improve the accuracy of subsequent determination of whether the row address needs to be refreshed and reduces the possibility of missing or inaccurate data stored in the memory.

[0075] In some embodiments, the preset number of times thresholds and the row hammer refresh table 204 are further designed and processed. In this embodiment, the number of preset number of times thresholds can be set to N, where N is an integer greater than or equal to 2. The first preset number of times threshold is the minimum value among the N preset number of times thresholds, and the Nth preset number of times threshold is the maximum value among the N preset number of times thresholds. The row hammer refresh table 204 includes M storage units for storing row addresses. When M-1 row addresses have been filled into the row hammer refresh table 204, the activation count value corresponding to the row address filled in the Mth storage unit is greater than or equal to the Nth preset number of times threshold.

[0076] For example, in this embodiment, N preset number thresholds can be configured, and among the N preset number thresholds, the larger the value of N, the larger the corresponding preset number threshold value of N. Furthermore, the row hammer refresh table 204 in this embodiment is provided with M storage units, and if only one storage unit remains among the M storage units, the row address can only be written into the aforementioned row hammer refresh table 204 if the activation count value corresponding to the row address is greater than the maximum value among the N preset number thresholds.

[0077] For example, this embodiment will be illustrated using an N value of 3 and an M value of 6. In this example, the row hammer refresh table 204 includes 6 storage units for storing row addresses, and the last storage unit is reserved. When the first 5 storage units all store row addresses, only the row address whose activation count is greater than the maximum preset threshold is stored. The three preset thresholds in this example are: a first preset threshold, a second preset threshold, and a third preset threshold, where the first preset threshold is less than the second preset threshold, and the second preset threshold is less than the third preset threshold. If, at this time, only the last storage unit in the row hammer refresh table 204 remains unoccupied, and the write control circuit 203 determines that the activation count of the row address is greater than or equal to the third preset threshold, then the row address can be written into the reserved bit of the row hammer refresh table 204. If at this time only the last unoccupied storage unit remains in the row hammer refresh table 204, and the write control circuit 203 determines that the activation count of the row address is less than the third preset threshold, then regardless of the relationship between the activation count of the row address and the first and second preset thresholds, the row address cannot be written into the row hammer refresh table 204.

[0078] That is, in this embodiment, the Mth storage unit among the M storage units is used as a preset reserved bit. The Mth storage unit only allows the row address with the row activation count value greater than the maximum preset threshold to be written. The row address with the activation count value greater than the maximum preset threshold can be regarded as the row that most urgently needs to be processed by row hammer refresh, that is, the row with the highest refresh urgency.

[0079] It should be noted that this embodiment only uses the last row address storage unit as a reserved fixed storage unit as an example. In practical applications, other storage units can also be selected.

[0080] It is understandable that this embodiment sets multiple preset threshold levels to achieve a finer-grained range of activation counts, so as to accurately identify rows that urgently need to undergo row hammer refresh processing. Furthermore, through the row address entry setting in this embodiment, when only one row address storage unit remains, the row address of the attacking row that urgently needs row hammer refresh processing can be preferentially written into the row hammer refresh table 204, thereby subsequently prioritizing the hammer refresh processing of the victim row that urgently needs row hammer refresh processing.

[0081] In some embodiments, when the number of preset number thresholds is N, the N preset number thresholds gradually increase from the first preset number threshold to the Nth preset number threshold, and the N preset number thresholds divide the range greater than the first preset number threshold into N sequentially increasing number intervals. The write control circuit 203 is also configured to, if the activation count value of the row address is in the i-th count interval, store the row address in the row hammer refresh table 204 and set the i-th refresh flag for the row address; where i is an integer greater than or equal to 1 and less than or equal to N, and the row hammer refresh priority of the row address corresponding to the refresh flag with a larger i value is higher than that of the row address corresponding to the refresh flag with a smaller i value.

[0082] For example, in this embodiment, N is set to 2. When two preset number of times thresholds are set, the first preset number of times threshold is less than the second preset number of times threshold. Based on the first and second preset number of times thresholds, two sequentially increasing number of times intervals can be obtained. The first number of times interval is the range enclosed by the first and second preset number of times thresholds, and the second number of times interval is the interval containing values ​​greater than or equal to the second preset number of times threshold.

[0083] If the activation count of a row address falls within the first range, a first refresh flag is configured for that row address. If the activation count falls within the second range, a second refresh flag is configured for that row address. A comparison shows that the activation count of the row address corresponding to the second refresh flag is greater than that of the row address corresponding to the first refresh flag. Therefore, the hammer refresh priority for the row corresponding to the second refresh flag can be configured to be higher than that for the row corresponding to the first refresh flag.

[0084] In one possible implementation, when a row hammer refresh operation needs to be performed, if there are multiple row addresses with different refresh flags in the row hammer refresh table 204, the row address to be used for the row hammer refresh operation can be selected from the row hammer refresh table 204 in descending order of row hammer refresh priority, so that the row hammer refresh operation can be performed on the adjacent rows of the row address.

[0085] For example, Table 1 is a schematic diagram of a row hammer refresh table 204 provided in an embodiment of this disclosure.

[0086] Table 1

[0087] The row hammer refresh table 204 shown in Table 1 includes 6 storage units, where each row is one storage unit, and each storage unit can store the row address and the corresponding refresh flag; or, the row address and refresh flag are stored in two storage units respectively, that is, each row has two storage units, then the row hammer refresh table 204 includes 12 storage units, namely 6 storage units for storing row addresses and 6 storage units for storing the refresh flags corresponding to each row address.

[0088] In Table 1, the setting of the last storage unit used to store the row address can be the same as the setting of the last storage unit in the row hammer refresh table 204 in the above embodiment. As a reserved bit, it will not be described again here. The storage unit corresponding to the refresh flag of the last storage unit used to store the row address can be empty, that is, data is not allowed to be written to it. Alternatively, the refresh flag stored in this storage unit can be pre-configured as the Nth refresh flag (that is, the highest priority among the row hammer refresh flags). Or, the refresh flag can be written when the row address is written to the last row. There is no specific limitation on this. The storage unit of the last refresh flag in Table 1 is marked with an X to indicate that data writing is prohibited. This will be used as an example for explanation. That is to say, in the row hammer refresh table 204 provided in Table 1, the row address written to the last row by default is the row address with the highest priority refresh flag.

[0089] It is understood that in this embodiment, by setting a refresh flag for the row address in the row hammer refresh table 204, on the one hand, the row address with the more urgent situation is guaranteed to be entered into the table first, and on the other hand, the row address with the higher refresh flag value can be selected from multiple row addresses for row hammer refresh processing based on the refresh flag, so as to realize the hierarchical processing of row hammer refresh and improve the reliability of the data stored in the memory.

[0090] In some embodiments, the row hammer refresh table 204 includes a plurality of storage units for storing row addresses, including a preset number of storage units to be reserved.

[0091] The write control circuit 203 is also configured to determine whether the number of free storage units in the row hammer refresh table 204 is less than or equal to the preset number of reserved units when the number of activations of the row address is greater than or equal to the preset number of activations threshold. The write control circuit 203 is also configured to perform a first operation when the number of free storage units is greater than a preset reservation number; The write control circuit 203 is also configured to, when the number of free storage units is less than or equal to a preset reserved number and greater than 0, perform a first operation if the activation count of the row address is greater than or equal to the Nth preset threshold; perform a second operation if the activation count of the row address is less than the Nth preset threshold; and / or perform the second operation when the number of free storage units is 0 or the activation count of the row address is less than the first preset threshold.

[0092] It should be noted that executing the first operation refers to the specific operational process of executing the first operation state, and executing the second operation refers to the specific operational process of executing the second operation state.

[0093] For example, in this embodiment, multiple storage units can be set in the row hammer refresh table 204, wherein the storage unit is used to store row addresses. Furthermore, among the multiple storage units, a preset number of storage units are reserved. This preset number of reserved storage units can be understood as reserved storage units. Configuring the preset number of reserved storage units is to ensure that row addresses with larger activation counts are preferentially written into the row hammer refresh table 204.

[0094] It should be noted that in some scenarios, configuring a preset number of storage units is to ensure that the row address with the highest row hammer refresh priority can be written into the row hammer refresh table 204 first. Accordingly, the preset number of units can be regarded as the number of storage locations reserved for the row address with the highest row hammer refresh priority.

[0095] Specifically, when the write control circuit 203 determines that the activation count of the row address is greater than or equal to a preset threshold, it further needs to determine whether there are any remaining storage units in the current row hammer refresh table 204 that have not been written to the row address, in addition to the preset reserved number of storage units. In simpler terms, it needs to determine whether there are any remaining unwritten free storage units in the row hammer refresh table 204, and whether the number of free storage units is greater than the preset reserved number.

[0096] If the write control circuit 203 determines that there are free storage units and the number of free storage units is greater than the preset reserved number, then the first operation can be performed to write the row address and initialize the activation count value corresponding to the row address. In this scenario, after writing the row address to the row activation refresh table, it can still be ensured that there are the preset reserved number of storage units in the row activation refresh table.

[0097] If the write control circuit 203 determines that there are free storage units, but the number of free storage units is less than or equal to the preset reserved number, in this embodiment, it is also necessary to compare the activation count value of the row address with the maximum value among N preset count thresholds (i.e., the Nth preset count threshold), and determine whether the row address can be written into the row hammer refresh table 204 based on the comparison result. Further, if the activation count value of the row address is greater than or equal to the Nth preset count threshold, then the first operation can be performed, and the row address with the highest row hammer refresh priority can be written into the row hammer refresh table 204 through this operation; if the activation count value of the row address is less than the Nth preset count threshold, it indicates that the row hammer refresh priority corresponding to the row address is not the highest priority, therefore, it cannot be written into the free storage unit, but the activation count value corresponding to the row address can be updated by performing the second operation.

[0098] Furthermore, if the write control circuit 203 determines that there is no free storage unit in the current row hammer refresh table 204, regardless of whether the row hammer refresh priority corresponding to the row address is the highest level, it cannot write to the row hammer refresh table 204. Then, the activation count value can be updated by performing the second operation.

[0099] Furthermore, if the write control circuit 203 determines that the activation count value corresponding to the row address is less than the minimum value among N preset count thresholds (i.e., the first preset count threshold), it can indicate that the row address does not need to be entered into the table, or in other words, it indicates that the urgency of the adjacent rows of the row address needing to be processed by row hammer refresh is the lowest. Then, the second operation is used to update the activation count value of the row address, or to initialize the activation count value of the row address.

[0100] For example, suppose there are 6 storage units in row hammer refresh table 204, N preset count thresholds are the first preset count threshold and the second preset count threshold, and the preset retention quantity is 1. Among them, the first preset count threshold is less than the second preset count threshold.

[0101] In this example, assuming there are already 4 written memory cells in the row hammer refresh table 204, if the write control circuit 203 determines that the activation count of the row address is greater than the second preset threshold, since there are 2 free memory cells in the hammer refresh table 204 at this time, and the number of free memory cells (2) is greater than the preset reserved number (1), the row address can be written to the free memory cell in the row hammer refresh table 204. It should be noted that when the position of the preset reserved memory cell in the row hammer refresh table 204 is not fixed, the row address can be written to any free memory cell. When the position of the preset reserved memory cell in the row hammer refresh table 204 is fixed, the row address needs to be written to a free memory cell other than the fixed reserved memory cell mentioned above; that is, the row address is preferentially written to a non-preset reserved memory cell.

[0102] In this example, assuming there are already 5 written memory cells in the row hammer refresh table 204, if the write control circuit 203 determines that the activation count of the row address is greater than the first preset threshold, since there is 1 free memory cell in the hammer refresh table 204, the number of free memory cells is equal to the preset reserved number 1, and the preset reserved memory cell in the row hammer refresh table 204 is used to write the row address with the highest row hammer refresh priority (in this scenario, it can be understood as the row address with an activation count greater than or equal to the second preset threshold). At this time, if the activation count of the row address is less than the second preset threshold, the above row address cannot be written into the row hammer refresh table 204.

[0103] In this example, assuming there are already 5 written memory cells in the row hammer refresh table 204, if the write control circuit 203 determines that the activation count of the row address is greater than the second preset count threshold, and there is 1 free memory cell in the hammer refresh table 204 at this time, the number of free memory cells is equal to the preset reserve number 1, and since the current row address is the row address with the highest row hammer refresh priority, the row address can be written into the free memory cell.

[0104] In this example, if the write control circuit 203 determines that the activation count value corresponding to the row address is less than the first preset threshold, it indicates that the row address is not an attack row, and there is no need to write the row address into the row hammer refresh table 204. Furthermore, a second operation can be performed to update the activation count value of the row address. Alternatively, in one possible implementation, when the activation count value corresponding to the row address is less than the first preset threshold, the activation count value corresponding to the row address can also be initialized. Subsequent accesses to the row address can then restart the activation count from the initial value.

[0105] In this embodiment, there is no specific restriction on the value of the preset retention quantity; it can be one or more.

[0106] In some embodiments, storage units can be reserved not only for the highest priority case, but also for each of the lower priority levels, with one or more storage units reserved. For example, suppose there are four preset count thresholds: a first preset count threshold, a second preset count threshold, a third preset count threshold, and a fourth preset count threshold, with these four preset count thresholds increasing sequentially. Two storage units can be reserved in the row hammer refresh table 204. Row addresses can only be written to the two reserved storage units after row addresses have been written to the remaining storage units in the row hammer refresh table 204 (excluding the two reserved units). Specifically, one reserved storage unit is used only to store row addresses with activation counts greater than or equal to the third preset count threshold and less than the fourth preset count threshold, and the other reserved storage unit is used only to store row addresses with activation counts greater than or equal to the fourth preset count threshold. In other words, the row hammer refresh table 204 can reserve corresponding storage units for each of the higher row hammer refresh priority levels to ensure that row addresses with higher row hammer refresh priority are entered into the table first.

[0107] It is understood that in this embodiment, a predetermined number of storage cells can be reserved in the row hammer refresh table 204. This ensures that row addresses with activation counts greater than or equal to the maximum predetermined threshold are preferentially written into the row hammer refresh table 204, reducing the possibility that row addresses with high urgency for row hammer refresh exist among those not yet in the table. Furthermore, this ensures that the highest priority row addresses are prioritized for row hammer refresh processing. Moreover, by initializing the activation counts of the row addresses written into the row hammer refresh table 204, subsequent processing does not require occupying time slots in the tRFC, avoiding the problem of insufficient row hammer refresh time leading to difficulties in ensuring memory data integrity.

[0108] Based on this, such as Figure 6 As shown, the comparator circuit 202 is specifically configured to compare the activation count value of the row address with the size of a first preset threshold value. When the activation count value of the row address is greater than or equal to the first preset threshold value, it outputs a comparator signal in an enabled state; otherwise, it outputs a comparator signal in an disabled state. The write control circuit 203 may include: The first judgment sub-circuit 2031, connected to the comparison circuit 202, is used to compare the number of free memory cells in the row hammer refresh table 204 with the preset reserve number when it receives the comparison signal of the enable state. When the number of free memory cells in the row hammer refresh table 204 is greater than the preset reserve number, it generates the first control signal of the enable state; when the number of free memory cells is less than or equal to the preset reserve number, it generates the first control signal of the disable state. The first control sub-circuit 2032 is connected to the first judgment sub-circuit 2031. The first control sub-circuit 2032 is used to perform a first operation when it receives a first control signal in an enabled state. The second judgment sub-circuit 2033 is connected to the first judgment sub-circuit 2031. The second judgment sub-circuit 2033 is used to compare the number of free memory cells with the size of 0 when it receives the first control signal of the disabled state; when the number of free memory cells is greater than 0, it generates the second control signal of the enabled state; when the number of free memory cells is 0, it generates the second control signal of the disabled state. The third judgment sub-circuit 2034 is connected to the second judgment sub-circuit 2033. The third judgment sub-circuit 2034 is used to compare the activation count value of the row address with the size of the Nth preset count threshold when it receives the second control signal of the enable state. When the activation count value of the row address is greater than or equal to the Nth preset count threshold, the third control signal of the enable state is generated. When the activation count value of the row address is less than the Nth preset count threshold, the third control signal of the disable state is generated. The first control sub-circuit 2032 is also connected to the third judgment sub-circuit 2034. The first control sub-circuit 2032 is also used to perform the first operation when it receives the third control signal in the enabled state. The second control sub-circuit 2035 is connected to the third judgment sub-circuit 2034. The second control sub-circuit 2035 is used to perform a second operation when it receives a third control signal in a disabled state. The second control sub-circuit 2035 is also connected to the second judgment sub-circuit 2033, and the fourth control sub-circuit 2037 is used to perform the second operation when a second control signal in a disabled state is received. The second control sub-circuit 2035 is also connected to the comparator circuit 202, and the fourth control sub-circuit 2037 is used to perform the second operation when a comparator signal in a disabled state is received.

[0109] For example, the working principle of the row hammer refresh circuit mentioned in this embodiment can be found in the description in the above embodiments, and will not be repeated here.

[0110] In some embodiments, the write control circuit 203 is further configured to send an alarm backoff instruction to the host when the number of free storage units is 1 and the number of activations of the row address is greater than or equal to the Nth preset number threshold, and / or when the number of the Nth refresh flags in the row hammer refresh table 204 is greater than the first preset number; so that the host responds to the alarm backoff instruction and issues a preset refresh command.

[0111] For example, in one scenario of this embodiment, when the write control circuit 203 determines that there is only one free storage unit remaining in the current row hammer refresh table 204, and the activation count value of the row address is greater than or equal to the maximum value among N preset count thresholds, it indicates that the row hammer refresh table 204 will be filled after the row address is written. At this time, the write control circuit 203 can send an alarm avoidance command to the host.

[0112] It should be noted that the host in this embodiment can be a memory controller or a controller specifically used to control the refresh process; no specific limitation is made in this embodiment. Furthermore, the alarm backoff instruction in this embodiment can be used to indicate whether a hammer refresh process is currently needed, or it can be used to indicate the row address of the row that needs to undergo row hammer refresh processing; no specific limitation is made in this embodiment.

[0113] When the host receives the alarm backoff command, the preset refresh command it issues can be understood as an instruction to clear a second preset number of row addresses in the row hammer refresh table 204. The value of the second preset number is not specifically limited in this embodiment and can be any value from 1 to the total number of storage units in the row hammer refresh table 204. For example, the row hammer refresh table 204 includes 6 storage units for storing row addresses. The first preset number can be 3, and the second preset number can be 4. When the number of Nth refresh flags in the row hammer refresh table 204 is greater than 3, when the host receives the alarm backoff command, it will prioritize performing row-to-row hammer refresh processing on the adjacent rows of the 4 row addresses with the highest refresh flag values ​​in the row hammer refresh table 204. In another scenario, the alarm backoff command can be used to indicate the row address of the attacking row and the row addresses of the adjacent rows affected by the attacking row that currently needs row hammer refresh processing. After performing row hammer refresh processing on the row addresses of the adjacent rows indicated by the alarm backoff command, the row addresses in the row hammer refresh table 204 (i.e., the attacking rows corresponding to the adjacent rows that have already undergone row hammer refresh processing) can be cleared. This clearing process can be performed by the write control circuit 203 or by the host; no specific limitation is made in this embodiment. In one possible implementation, the preset refresh command can also be called a refresh management (RFM) command.

[0114] In another scenario of this embodiment, when the write control circuit 203 detects that the number of the Nth refresh flags in the current row hammer refresh table 204 is greater than the first preset number, that is, the number of row addresses in the row hammer refresh table 204 with an activation count value greater than the Nth preset number threshold is greater than the first preset number, then an alarm backoff command can be sent to the host so that the adjacent rows of the row address corresponding to the Nth refresh flag in the row hammer refresh table 204 can be prioritized for row hammer refresh.

[0115] It should be noted that the meaning of the Nth refresh flag in this embodiment is the same as that of the Nth refresh flag, and the determination method can refer to the determination method of the i-th refresh flag mentioned in the above embodiments of this disclosure, which will not be repeated here. Furthermore, this embodiment does not impose specific restrictions on the value of the first preset quantity.

[0116] It is understood that in this embodiment, a preset refresh instruction can be triggered by sending an alarm backoff instruction to the host, thereby performing row hammer refresh processing on the memory and ensuring the integrity of the memory data. Furthermore, in this embodiment, the scenario for triggering the sending of the alarm backoff instruction can be one or more of the following: determining that the current row hammer refresh table 204 will be full, or the number of row addresses with the highest row hammer priority in the row hammer refresh table 204 is greater than a first preset number. Further, the alarm backoff instruction triggering conditions in this embodiment are set so that row addresses in the row hammer refresh table 204 can be cleared in a timely manner, and when the number of row addresses requiring priority processing in the row hammer refresh table 204 is large, row hammer refresh processing can also be triggered in a timely manner, improving the integrity of the memory data.

[0117] In one possible implementation, the row hammer refresh table 204 includes multiple first storage units and a predetermined number of second storage units. The first storage units are used to store the row address and the activation count value corresponding to the row address, and the second storage units are used only to store the row address.

[0118] The write control circuit 203 is also configured to, when the activation count of the row address is greater than or equal to a preset threshold, preferentially store the row address into the first storage unit; when the row hammer refresh table 204 has only the second storage unit free, compare the activation count of the row address with the activation count of the row address already in the row hammer refresh table 204, and store the row address with the largest activation count into the second storage unit; wherein, the row hammer refresh operation of the row address in the second storage unit is performed preferentially.

[0119] For example, in this embodiment, the storage units in the row hammer refresh table 204 have two different storage methods. One method stores the row address and the corresponding activation count value, and the other method stores only the row address. When the write control circuit 203 determines that the activation count value of the row address is greater than or equal to a preset threshold, it indicates that the current row address can be added to the table. Furthermore, when determining which storage method to use for the row address, it is also necessary to consider the data already stored in the row hammer refresh table 204.

[0120] When the activation count of a row address is greater than or equal to a preset threshold, in one scenario, if there are remaining unoccupied first storage units in the current row hammer refresh table 204, the row address and its activation count can be written into the unoccupied first storage unit. In another scenario, if there are no unoccupied first storage units in the current row hammer refresh table 204, the activation count of the row address needs to be compared with the activation counts stored in each first storage unit, and the row address corresponding to the maximum activation count is written into the second storage unit. Specifically, if the activation count of the row address is not the maximum value, the row address in the first storage unit used to store the maximum activation count can be written into the second storage unit, and the first storage unit is cleared before writing the row address and its corresponding activation count into it. If the activation count of the row address is the maximum value, the row address can be written into the second storage unit.

[0121] It should be noted that in this embodiment, the second storage unit is only used to store row addresses. After the row address is written into the second storage unit, the activation count value corresponding to the row address also needs to be initialized.

[0122] Furthermore, in this embodiment, there is a distinction in row hammer refresh priority between the first storage unit and the second storage unit. Specifically, the row hammer refresh priority corresponding to the second storage unit is higher than the row hammer refresh priority corresponding to any of the first storage units.

[0123] It should be noted that the row hammer refresh priority corresponding to each first storage unit can be the same, or the priority corresponding to each first storage unit can be determined according to the activation count value of its corresponding storage. The larger the activation count value, the higher the row hammer refresh priority corresponding to the first storage unit.

[0124] For example, Table 2 is a schematic diagram of another row hammer refresh table 204 provided in an embodiment of this disclosure.

[0125] Table 2

[0126] As shown in Table 2, the first column of the row hammer refresh table 204 contains 6 storage units for storing row addresses, while the first 5 storage units of the second column contain the activation count values ​​corresponding to each row address. When the 10 storage units of the first 5 rows are full, if there are still row addresses that need to be written to the row hammer refresh table 204, the activation count value of the row address to be written can be compared with the activation count values ​​in the row hammer refresh table 204. The row address corresponding to the maximum activation count value is then written to the last storage unit of the first column, and the activation count value of that row address is initialized. If the row address to be written is the row address corresponding to the maximum activation count value, no modification to the written data is required. If the row address to be written is not the row address corresponding to the maximum activation count value, the storage units originally used to store the maximum activation count value and the storage units storing the row address corresponding to the maximum activation count value need to be cleared, and the row address to be written and its corresponding activation count value are written to the cleared storage space.

[0127] For example, suppose the row addresses stored in the row hammer refresh table 204 are 1, 3, 4, 8, and 10, and the activation count values ​​corresponding to each row address are 150, 500, 450, 300, and 200, respectively. If the activation count value of row 12 is 180, and 180 exceeds the preset threshold, but since 180 is not the maximum value of the activation count value stored in the row hammer refresh table 204, and the maximum value is 500, then the row address 3 corresponding to 500 can be written into the last row of the first column of the row hammer refresh table 204, and the content of the second row of the row hammer refresh table 204 (that is, the original storage is row address 3 and activation count value 500) can be modified, that is, 3 is written at the row address of the second row, and 180 is written at the activation count value.

[0128] It is understandable that, compared to storing multiple row addresses and the activation count value of each row address in the row hammer refresh table 204, in this embodiment, the row hammer refresh table 204 only needs to store multiple row addresses and the activation count values ​​corresponding to some of the row addresses, which can effectively reduce the storage space occupied by the row hammer refresh table 204. Furthermore, in this embodiment, the first storage unit is written first, and when the first storage unit is full, the row address with the highest activation count value is written to the second storage unit, so as to achieve the effect of prioritizing row hammer refresh processing on the row addresses in the second storage unit. In addition, by initializing the activation count value corresponding to the row address written to the second storage unit, when performing row hammer refresh on adjacent rows of the row address in the second storage unit, there is no need to introduce the initialization step for the activation count value of the attack row, reducing the time consumption of tRFC and ensuring that adjacent rows of the attack row have sufficient tRAS for hammer refresh processing.

[0129] In another embodiment of this disclosure, see Figure 7 This is a flowchart illustrating a row hammer refresh method provided in an embodiment of this disclosure. Figure 1 ,like Figure 7 As shown, the row hammer refresh method provided in this embodiment includes the following steps: S901. Determine the activation count value for the row address.

[0130] S902. Compare the activation count value of the row address with the value of the preset count threshold.

[0131] S903. When the activation count of the row address is greater than or equal to a preset threshold, a first operation state exists; the first operation state is: store the row address in the row hammer refresh table and initialize the activation count of the row address. It should be noted that... Figure 7 In step S903, the existence of a first operation state is represented by performing a first operation.

[0132] In some embodiments, step S901 includes: Determine the first count value and the second count value corresponding to the row address; wherein, the first count value is the count value obtained by counting the number of times the row address is activated starting from the initial value, and the second count value is the ratio of the activation duration of the row address to the preset duration; add the first count value and the second count value to obtain the activation count value of the row address.

[0133] In some embodiments, the number of preset number thresholds is N, where N is an integer greater than or equal to 2. The first preset number threshold is the minimum value among the N preset number thresholds, and the Nth preset number threshold is the maximum value among the N preset number thresholds. The row hammer refresh table includes M row address storage units. When M-1 row addresses have been filled into the row hammer refresh table, the activation count value corresponding to the row address filled in the Mth row address storage unit is greater than or equal to the Nth preset number threshold.

[0134] In some embodiments, the row hammer refresh table includes a plurality of first storage units and a predetermined number of second storage units. The first storage units are used to store row addresses and the activation counts corresponding to the row addresses, and the second storage units are used only to store row addresses. When the activation count value of a row address is greater than or equal to a preset threshold, the row hammer refresh method further includes: preferentially storing the row address in the first storage unit; when the row hammer refresh table has only empty second storage units, comparing the activation count value of the row address with the activation count values ​​of existing row addresses in the row hammer refresh table, and storing the row address with the largest activation count value in the second storage unit; wherein, the row hammer refresh operation of the row address in the second storage unit is performed preferentially.

[0135] In some embodiments, the row hammer refresh method further includes: when the activation count value of the row address is greater than or equal to a preset count threshold, there is a second operation state; the second operation state is: updating the activation count value of the row address and rewriting the updated activation count value.

[0136] In some embodiments, N preset number thresholds gradually increase from the first preset number threshold to the Nth preset number threshold, and the N preset number thresholds divide the range greater than the first preset number threshold into N sequentially increasing number intervals; the method further includes: if the activation number value of the row address is in the i-th number interval, storing the row address in the row hammer refresh table, and setting the i-th refresh flag for the row address; wherein, i is an integer greater than or equal to 1 and less than or equal to N, and the row hammer refresh priority of the row address corresponding to the refresh flag with a larger i value is higher than that of the row address corresponding to the refresh flag with a smaller i value.

[0137] In some embodiments, the row hammer refresh table includes a plurality of storage units for storing row addresses, including a preset number of storage units to be reserved; The row hammer refresh method also includes: when the number of activations of the row address is greater than or equal to a preset threshold, determining whether the number of free storage units in the row hammer refresh table is less than or equal to a preset reserved number; Even when the number of free storage units exceeds the preset reservation limit, the first operation state still exists; If the number of free storage units is less than or equal to the preset reserved number and greater than 0, and the activation count of the row address is greater than or equal to the Nth preset threshold, a first operation state still exists; if the activation count of the row address is less than the Nth preset threshold, a second operation state still exists; and / or, if the number of free storage units is 0, or the activation count of the row address is less than the first preset threshold, a second operation state still exists.

[0138] In some embodiments, the row hammer refresh method further includes: when the number of free storage units is 1 and the number of activations of the row address is greater than or equal to the Nth preset number threshold, and / or when the number of the Nth refresh flags in the row hammer refresh table is greater than a first preset number, sending an alarm backoff instruction to the host; so that the host responds to the alarm backoff instruction and issues a preset refresh command.

[0139] In some embodiments, initializing the activation count value of the row address includes: initializing the activation count value of the row address to a random value.

[0140] It is understood that the principle of the row hammer refresh method mentioned in this embodiment is similar to that in the above embodiments, and will not be repeated here.

[0141] Figure 8A flowchart illustrating a row hammer refresh method provided in this embodiment of the disclosure. Figure 2 ,like Figure 8 As shown, in this example, a first preset threshold THRD1 and a second preset threshold THRD2, which are less than the row hammer intrinsic value of the memory process, are set, and THRD2 > THRD1. A reserved memory cell is then set for the second refresh flag (Flag2 flag). This process includes the following brief description: After row j completes the activation-precharge process, the first count value is read out and added to the second count value to calculate the new activation count value AC corresponding to row j.

[0142] Determine whether the obtained activation count value AC is greater than the second preset number threshold THRD2.

[0143] If the activation count AC is greater than the second preset threshold THRD2, then it is further determined whether the current row's hammer refresh table is already full. If the activation count AC is not greater than the second preset threshold THRD2, then it is further determined whether the activation count AC is greater than the first preset threshold THRD1.

[0144] If it is determined that the row hammer refresh table is not full, the row address of row j is written into the row hammer refresh table, and the refresh flag corresponding to row j is set to the second refresh flag Flag2 (i.e., Flag2 flag) in the row hammer refresh table. After writing, the activation count value corresponding to row j is initialized, i.e., ACI is executed. Furthermore, if the activation count value of row j is greater than the second preset threshold THRD2, and the row hammer refresh table is not full, it is necessary to further determine whether only one storage unit remains in the row hammer refresh table. If only one storage unit remains, it indicates that the row hammer refresh table will be filled, and an alarm backoff needs to be triggered to clear the contents stored in the row hammer refresh table. If the row hammer refresh table does not have only one storage unit remaining, the process ends.

[0145] If the activation count value is greater than the second preset threshold, and the row hammer refresh table is already full, then it is necessary to further update the activation count value corresponding to the row to the new activation count value obtained above and store it, that is, to execute ACU.

[0146] Furthermore, if the newly obtained activation count value AC is less than or equal to the second preset number threshold THRD2 and greater than the first preset number threshold THRD1, it is further determined whether only one storage unit remains in the row hammer refresh table. If only one storage unit remains in the row hammer refresh table, the above ACU steps are executed. If the newly obtained activation count value is less than or equal to the second preset number threshold and less than or equal to the first preset number threshold THRD1, the above ACU steps are also executed.

[0147] If the newly obtained activation count value AC is less than or equal to the second preset count threshold THRD2 and greater than the first preset count threshold THRD1, and there are multiple remaining storage units in the row hammer refresh table, then the row address corresponding to row j can be written into the row hammer refresh table, and the refresh flag corresponding to row j can be set to the first refresh flag (i.e., Flag1 flag) in the row hammer refresh table. After writing to the table, ACI processing is performed.

[0148] It should be noted that in this embodiment, the second preset number threshold is greater than the first preset number threshold, and the last storage unit in the row hammer refresh table is a preset reserved bit, allowing only the row address corresponding to the activation number value greater than the second preset number threshold to be written. Furthermore, in this embodiment, the Flag can be used to indicate the urgency or priority of the row hammer refresh process, wherein the urgency of Flag2 is higher than that of Flag1, or the row hammer refresh priority of Flag2 is higher than that of Flag1.

[0149] Figure 9 A flowchart illustrating a hammer-based refresh method provided in this embodiment of the present disclosure. Figure 3 In this embodiment, after the device is initialized and powered on, the system can check the row hammer refresh table to see if there is a Flag2 flag (i.e., ...). Figure 9 If the second refresh flag (in the table) exists, the row address corresponding to the Flag2 flag is determined first, and row hammer refresh processing is performed on the adjacent row corresponding to that row address first. After the row hammer refresh processing is completed, the process returns to the step of searching for Flag2 in the row hammer refresh table in this embodiment. Further, if the Flag2 flag does not exist in the row hammer refresh table, but the Flag1 flag (i.e., ...) exists... Figure 9 If the row hammer refresh table does not contain either Flag2 or Flag1, the process returns to the step of determining whether Flag2 exists. In this embodiment, the row adjacent to the row corresponding to Flag2 is selected for RHR, and the adjacent rows are then processed.

[0150] It should be noted that the selection method for adjacent rows is not limited in this embodiment. The row before and the row after the current row can be selected as adjacent rows, or the row before or the row after the current row can be selected as adjacent rows. Furthermore, the device mentioned in this embodiment can be the write control circuit 203 mentioned in this disclosure, or the memory corresponding to the write control circuit 203; no specific limitations are imposed in this embodiment.

[0151] Furthermore, this disclosure also provides a memory that includes the row hammer refresh circuit provided in any of the above embodiments.

[0152] For details not disclosed in the embodiments of this disclosure, please refer to the description of the foregoing embodiments for understanding.

[0153] The above description is merely a preferred embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure.

[0154] It should be noted that, in this disclosure, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0155] The sequence numbers of the embodiments disclosed above are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0156] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0157] The features disclosed in the several product embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new product embodiments.

[0158] The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0159] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A row hammer refresh circuit, characterized in that, include: The counting circuit is configured to determine the number of times the row address is activated; The comparison circuit is configured to compare the activation count value of the row address with the size of a preset count threshold; The write control circuit is configured to have a first operation state when the activation count value of the row address is greater than or equal to the preset count threshold. The first operation state is: storing the row address into the row hammer refresh table and initializing the activation count value of the row address; The row hammer refresh table is configured to store row addresses.

2. The row hammer refresh circuit according to claim 1, characterized in that, The write control circuit is further configured to have a second operation state when the activation count value of the row address is greater than or equal to the preset count threshold; the second operation state is to update the activation count value of the row address and rewrite the updated activation count value.

3. The row hammer refresh circuit according to claim 1, characterized in that, The counting circuit includes: The first sub-counting circuit is configured to count the number of activations of the row address starting from an initial value to obtain a first count value; The second sub-counting circuit is configured to count based on a preset duration during the period when the row address is activated, and obtain a second count value; An adder circuit is configured to add the first count value and the second count value to obtain the activation count value of the row address.

4. The row hammer refresh circuit according to claim 2, characterized in that, The number of preset number thresholds is N, where N is an integer greater than or equal to 2, wherein the first preset number threshold is the minimum value among the N preset number thresholds, and the Nth preset number threshold is the maximum value among the N preset number thresholds; The row hammer refresh table includes M storage units for storing the row addresses. When M-1 row addresses have been filled into the row hammer refresh table, the activation count value corresponding to the row address filled into the Mth storage unit is greater than or equal to the Nth preset threshold.

5. The row hammer refresh circuit according to claim 4, characterized in that, The N preset number thresholds gradually increase from the first preset number threshold to the Nth preset number threshold, and the N preset number thresholds divide the range greater than the first preset number threshold into N sequentially increasing number intervals; The write control circuit is further configured to, if the activation count value of the row address is in the i-th count interval, store the row address in the row hammer refresh table and set the i-th refresh flag for the row address; Where i is an integer greater than or equal to 1 and less than or equal to N, and the row hammer refresh priority of the row address corresponding to the refresh flag with a larger i value is higher than that of the row address corresponding to the refresh flag with a smaller i value.

6. The row hammer refresh circuit according to claim 4, characterized in that, The row hammer refresh table includes multiple storage units for storing the row addresses, including a preset number of the storage units; The write control circuit is further configured to determine whether the number of free storage units in the row hammer refresh table is less than or equal to the preset retention number when the activation count value of the row address is greater than or equal to the preset threshold value. The write control circuit is further configured to maintain the first operation state even when the number of free storage units is greater than the preset retention number. The write control circuit is further configured to, when the number of free storage units is less than or equal to the preset reserved number and greater than 0, maintain the first operation state if the activation count of the row address is greater than or equal to the Nth preset threshold; maintain the second operation state if the activation count of the row address is less than the Nth preset threshold; and / or maintain the second operation state when the number of free storage units is 0 or the activation count of the row address is less than the first preset threshold.

7. The row hammer refresh circuit according to claim 6, characterized in that, The write control circuit is further configured to send an alarm backoff command to the host when the number of free storage units is 1 and the activation count of the row address is greater than or equal to the Nth preset threshold, and / or when the number of the Nth refresh flag in the row hammer refresh table is greater than a first preset number; so that the host responds to the alarm backoff command and issues a preset refresh command.

8. The row hammer refresh circuit according to claim 1, characterized in that, The row hammer refresh table includes multiple first storage units and a predetermined number of second storage units. The first storage units are used to store the row address and the activation count value corresponding to the row address, and the second storage units are only used to store the row address. The write control circuit is further configured to, when the activation count of the row address is greater than or equal to the preset threshold, preferentially store the row address into the first storage unit; when the row hammer refresh table has only the second storage unit available, compare the activation count of the row address with the activation count of the existing row addresses in the row hammer refresh table, and store the row address with the largest activation count into the second storage unit; wherein, the row hammer refresh operation of the row address in the second storage unit is preferentially executed.

9. The row hammer refresh circuit according to any one of claims 1-8, characterized in that, The write control circuit is also used to initialize the activation count value of the row address to a random value.

10. A method for refreshing by hammering, characterized in that, include: Determine the activation count for the row address; Compare the activation count value of the row address with the value of the preset threshold count; When the activation count of the row address is greater than or equal to the preset threshold, a first operation state exists; the first operation state is: storing the row address in the row hammer refresh table and initializing the activation count of the row address.

11. The method according to claim 10, characterized in that, Determine the activation count value for the row address, including: Determine a first count value and a second count value corresponding to the row address; wherein, the first count value is the count value obtained by counting the number of times the row address is activated starting from the initial value, and the second count value is the ratio of the activation duration of the row address to a preset duration; The first count value and the second count value are added together to obtain the activation count value of the row address.

12. The method according to claim 10, characterized in that, The number of preset number thresholds is N, where N is an integer greater than or equal to 2, wherein the first preset number threshold is the minimum value among the N preset number thresholds, and the Nth preset number threshold is the maximum value among the N preset number thresholds; The row hammer refresh table includes M row address storage units. When M-1 row addresses have been filled into the row hammer refresh table, the activation count value corresponding to the row address filled into the Mth row address storage unit is greater than or equal to the Nth preset count threshold.

13. The method according to claim 10, characterized in that, The row hammer refresh table includes multiple first storage units and a predetermined number of second storage units. The first storage units are used to store row addresses and the number of activations corresponding to the row addresses, and the second storage units are only used to store the row addresses. When the activation count value of the row address is greater than or equal to the preset threshold, the method further includes: The row address is preferentially stored in the first storage unit. When the row hammer refresh table is only empty in the second storage unit, the activation count value of the row address is compared with the activation count value of the existing row address in the row hammer refresh table, and the row address with the largest activation count value is stored in the second storage unit. Among them, the row hammer refresh operation of the row address in the second storage unit is preferentially executed.

14. A memory, characterized in that, Includes the row hammer refresh circuit as described in any one of claims 1-9.

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