A memristor reading and writing test circuit and method with high-speed hard-off current limiting and closed-loop precise resistance adjusting functions

Abstract

The present application relates to a kind of high-speed hard-off current limiting and closed-loop precision resistance regulating function's memristor reading and writing test circuit and method, the circuit includes pulse generation circuit, two-stage current limiting passage selection switch, high-speed hard-off current limiting passage, closed-loop precision current limiting passage, polarity switching circuit, the memristor to be measured and current-voltage conversion reading circuit.High-speed hard-off current limiting passage according to the comparison result of sampling voltage and set threshold controls MOS fast-off, to cut off overcurrent write path;Closed-loop precision current limiting passage is adjusted power regulating tube by operational amplifier negative feedback, and is realized multi-grade current limiting with switchable current limiting resistance.Two current limiting passages share polarity switching circuit and current-voltage conversion reading circuit, and FPGA calculates the resistance of memristor according to sampling result, realizes target resistance closed-loop modulation.The present application considers the fast protection of narrow pulse write-in and the precision control of target resistance programming.

Description

Technical Field

[0001] This invention relates to the field of memristor testing and driving technology, and in particular to a memristor read / write test circuit and method that combines high-speed hard-shutdown current limiting and closed-loop precision resistance adjustment. It is especially suitable for automated testing of memristors in narrow pulse writing, bipolar switching, current limiting protection, target resistance modulation, and current reading processes. Background Technology

[0002] A memristor is a two-terminal device with non-volatile resistance modulation characteristics, whose resistance state can reversibly change under the action of an applied voltage or current pulse. Due to its low power consumption, high integration, synaptic plasticity, and in-memory computing potential, memristors have broad application prospects in fields such as novel non-volatile memories, neuromorphic computing, reconfigurable circuits, and brain-like intelligent hardware.

[0003] In the fabrication, screening, and application research of memristors, read / write tests are typically required. These tests generally include steps such as pulse writing, resistance reading, status determination, polarity switching, current limiting protection, and multiple closed-loop modulation. Due to the small size of memristor devices and the highly nonlinear formation and breakage of their conductive filaments, excessive current during writing can easily lead to irreversible breakdown or overwriting. Therefore, current limiting protection is a crucial element in memristor testing circuits.

[0004] Existing memristor testing methods typically employ a test platform comprised of a source meter, pulse generator, oscilloscope, relay matrix, and external acquisition equipment. While this approach can perform basic read and write operations, the system is complex, bulky, and lacks automation, and struggles to achieve rapid overcurrent shutdown under narrow pulse conditions. Furthermore, when precise modulation of the memristor to a target resistance value is required, a single current-limiting method cannot simultaneously guarantee fast response and high-precision control.

[0005] Specifically, in narrow-pulse writing scenarios, the write pulse duration is short, requiring the overcurrent protection circuit to have a fast response speed to promptly cut off the write path when the current exceeds the threshold. In target resistance modulation scenarios, however, the focus is more on precise control of the write current and read feedback, necessitating a closed-loop approach to gradually adjust the write conditions and stabilize the memristor resistance within a preset range. Existing test circuits typically struggle to simultaneously meet both of these requirements on a single platform.

[0006] Therefore, it is necessary to provide a memristor read / write test circuit that simultaneously possesses high-speed hard-shutdown current limiting and closed-loop precision impedance adjustment capabilities within the same test platform, and can be combined with polarity switching, current reading, and automatic control to achieve safety, accuracy, and automation in the memristor read / write test process. Summary of the Invention

[0007] The purpose of this invention is to provide a memristor read / write test circuit and method that combines high-speed hard-shutdown current limiting and closed-loop precision resistance adjustment, in order to solve the problem that existing memristor test circuits cannot simultaneously meet the requirements of narrow-pulse fast overcurrent protection and precise modulation of target resistance value.

[0008] To achieve the above objectives, the present invention provides the following solution: A memristor read / write test circuit that combines high-speed hard-shutdown current limiting with closed-loop precision impedance adjustment includes: Pulse generation circuit, used to output test pulses; The current limiting circuit selection switch is used to control the test pulse to enter the high-speed hard shutdown current limiting circuit or the closed-loop precision current limiting circuit, and to control the connection between the high-speed hard shutdown current limiting circuit or the closed-loop precision current limiting circuit and the polarity switching circuit. A high-speed hard-shutdown current-limiting path is used to generate a shutdown signal based on threshold comparison and cut off the write current path during pulse writing. A closed-loop precision current limiting circuit is used to adjust the conduction level of the power regulation transistor through the negative feedback of the operational amplifier, so that the feedback node voltage follows the reference voltage. The input terminal of the polarity switching circuit is connected to the high-speed hard-shutdown limiting circuit or the closed-loop precision limiting circuit, and the output terminal is connected to the memristor under test, which is used to switch the connection polarity of the two ends of the memristor under test. A current-to-voltage reading circuit is used to perform closed-loop adjustment of the target resistance value of the memristor under test based on the reference voltage.

[0009] Optionally, the high-speed hard shutdown current limiting path includes a high-speed current limiting range selection circuit, a voltage comparator, a logic control unit, and a MOS fast shutdown unit. The high-speed current limiting range selection circuit is used to select different sampling resistors and generate a sampling voltage corresponding to the write current. The voltage comparator is used to compare the sampled voltage corresponding to the write current with the set threshold of the high-speed digital-to-analog converter (DAC). The logic control unit is used to generate a MOS transistor control signal based on the pulse synchronization signal and the voltage comparator output signal. The MOS fast turn-off unit is used to turn on or cut off the write current path according to the MOS control signal. The MOS fast turn-off unit is connected in series in the main transmission path of the test pulse. One main current terminal of the MOS fast turn-off unit is used to receive the test pulse selected by the first current limiting path selection switch, and the other main current terminal is connected to the high-speed current limiting range selection circuit.

[0010] Optionally, the logic control unit includes NOT gates, D flip-flops, and AND gates; The pulse synchronization signal is input to the NOT gate, and the output of the NOT gate is connected to the asynchronous set terminal of the D flip-flop. The data input terminal of the D flip-flop is connected to a low level; The output of the voltage comparator is connected to the clock input of the D flip-flop; The output of the D flip-flop and the pulse synchronization signal are respectively input to the logic AND gate; The output of the AND gate is connected to the control terminal of the MOS fast shutdown unit.

[0011] Optionally, the closed-loop precision current limiting circuit includes a precision current limiting range selection circuit, an operational amplifier, and a power regulating transistor; The precision current limiting range selection circuit includes a single-pole multi-throw analog switch and multiple current limiting resistors with different resistance values, used to select current limiting resistors with different resistance values. One input terminal of the operational amplifier is used to receive the reference voltage output by the DAC, and the other input terminal is used to receive the feedback node voltage. The output terminal of the operational amplifier is connected to the control terminal of the power regulating transistor. The operational amplifier is used to adjust the conduction level of the power regulating transistor through negative feedback, so that the feedback node voltage follows the reference voltage output by the DAC. The power regulating transistor is connected in series in the main transmission path of the test pulse. One main current terminal of the power regulating transistor is used to receive the test pulse selected by the first current limiting path selection switch, and the other main current terminal is connected to the precision current limiting range selection circuit.

[0012] Optionally, the current-to-voltage reading circuit includes a transimpedance amplifier, a transimpedance resistor, an analog-to-digital converter (ADC), and an FPGA control and processing unit; The transimpedance amplifier is used to convert the current flowing through the memristor under test into a voltage signal; The analog-to-digital converter (ADC) is used to acquire the voltage signal; The FPGA control processing unit is used to calculate the resistance value of the memristor under test based on the voltage signal acquired by the analog-to-digital converter (ADC), the reference voltage, and the currently connected current-limiting resistor, and adjust the reference voltage, test pulse parameters, current-limiting level, or polarity switching state according to the calculation results, so as to perform closed-loop modulation of the target resistance value of the memristor under test.

[0013] This invention also discloses a memristor read / write test method based on a memristor read / write test circuit, comprising: Test pulses are generated using a pulse generation circuit; According to the test task, the test pulse is selected to be input into the high-speed hard shutdown limiting circuit or the closed-loop precision limiting circuit. The high-speed hard shutdown limiting circuit generates a shutdown signal and cuts off the write current path, while the closed-loop precision limiting circuit makes the feedback node voltage follow the reference voltage. The polarity of the connection between the two ends of the memristor under test is switched by a polarity switching circuit. The test pulse is applied to the memristor under test via a selected current-limiting path and polarity-switching circuit. The voltage of the memristor under test is acquired by a current-to-voltage reading circuit, and the resistance value of the memristor under test is calculated based on the reference voltage. Determine whether to continue writing, switch the current limiting level, switch the writing polarity, or end the test based on the resistance value of the memristor under test.

[0014] Optionally, the high-speed hard-shutdown current-limiting path generating a shutdown signal and trunculating the write current path includes: When the pulse synchronization signal is low, the D flip-flop is in an asynchronous set state and the AND gate outputs a low level, turning off the MOS fast shutdown unit. When the pulse synchronization signal is high and the sampled voltage does not exceed the set threshold voltage, the AND gate outputs a high level, turning on the MOS fast shutdown unit. When the sampled voltage exceeds the set threshold voltage, the voltage comparator output flips and triggers the D flip-flop to output a low level, causing the AND gate to output a low level, thereby turning off the MOS fast shutdown unit.

[0015] Optionally, calculating the resistance value of the memristor under test includes: The voltage of the memristor under test (MTBT) is acquired through a transimpedance amplifier and an analog-to-digital converter (ADC). The MTBT current is calculated based on the voltage signal and the transimpedance resistance. The resistance of the MTBT is then calculated based on the MTBT current, the DAC output reference voltage, and the currently connected current-limiting resistor. Optionally, the resistance of the MTBT is calculated. The method is as follows: ; in, For current limiting resistor, The magnitude of the current flowing through the memristor under test is obtained by collecting the voltage and the transresistance. To set the voltage.

[0016] Optionally, determining whether to continue writing, switch the current limiting level, switch the writing polarity, or end the test based on the resistance value of the memristor under test includes: When the calculated resistance value of the memristor under test does not fall within the target resistance range, adjust the DAC output voltage, pulse width, pulse count, current limiting level, or polarity switching state, and continue writing and reading; when the calculated resistance value of the memristor under test falls within the target resistance range, stop writing and save the test results.

[0017] The beneficial effects of the present invention are as follows: First, the present invention sets up a high-speed hard-shutdown current limiting circuit and a closed-loop precision current limiting circuit in the same memristor read / write test circuit, and different current limiting methods can be selected according to the test task, thereby taking into account both the fast protection requirements in the narrow pulse writing process and the precision control requirements in the target resistance modulation process.

[0018] Secondly, the high-speed hard shutdown limiting circuit of the present invention uses a voltage comparator, a D flip-flop, a logic gate and a MOSFET to form a hardware-level fast shutdown path. When the write current exceeds the set threshold, the MOSFET can be quickly turned off and the write current can be cut off, reducing the risk of memristor breakdown due to transient overcurrent.

[0019] Third, the closed-loop precision current limiting circuit of the present invention uses operational amplifier negative feedback to control the conduction degree of the power regulating tube, and combines transimpedance amplifier and ADC to read the memristor current in real time, thereby calculating the current resistance value of the memristor and performing closed-loop adjustment according to the target resistance value, thus improving the accuracy of resistance value programming.

[0020] Fourth, the present invention sets up current limiting range selection circuits in both the high-speed hard-shutdown current limiting circuit and the closed-loop precision current limiting circuit, and uses a single-pole multi-throw analog switch and multiple sampling resistors to realize the selection of multiple current limiting ranges, so that the test circuit can be adapted to memristor devices with different resistance ranges, different write voltages and different withstand currents.

[0021] Fifth, the present invention uses a polarity switching circuit to reverse the connection relationship between the two ends of the memristor under test, so that the test system can easily realize forward and reverse writing without an additional negative voltage source, thus improving the flexibility of SET and RESET operations.

[0022] Sixth, this invention uses FPGA to uniformly coordinate pulse generation, current limiting level selection, path switching, polarity switching, ADC sampling, and closed-loop judgment, which facilitates automated testing of memristors and improves testing efficiency and consistency. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 This is an overall structural block diagram of the memristor read / write test circuit according to an embodiment of the present invention; Figure 2 This is a schematic diagram of the high-speed hard-shutdown limiting flow path according to an embodiment of the present invention; Figure 3 This is a schematic diagram of the closed-loop precision flow-limiting path structure according to an embodiment of the present invention; Figure 4 This is a schematic diagram of the current limiting gear selection circuit according to an embodiment of the present invention; Figure 5 This is a schematic diagram of the polarity switching circuit according to an embodiment of the present invention; Figure 6 This is a schematic diagram of the current-to-voltage reading circuit structure according to an embodiment of the present invention; Figure 7 This is a flowchart of a memristor read / write test method according to an embodiment of the present invention. Detailed Implementation

[0025] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0026] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0027] This embodiment proposes a memristor read / write test circuit that combines high-speed hard-shutdown current limiting with closed-loop precision impedance adjustment, including: Pulse generation circuit, used to output test pulses; The current limiting circuit selection switch is used to control the test pulse to enter the high-speed hard shutdown current limiting circuit or the closed-loop precision current limiting circuit, and to control the connection between the high-speed hard shutdown current limiting circuit or the closed-loop precision current limiting circuit and the polarity switching circuit. A high-speed hard-shutdown current-limiting path is used to generate a shutdown signal based on threshold comparison and cut off the write current path during pulse writing. A closed-loop precision current limiting circuit is used to adjust the conduction level of the power regulation transistor through the negative feedback of the operational amplifier, so that the feedback node voltage follows the reference voltage. The input terminal of the polarity switching circuit is connected to the high-speed hard-shutdown limiting circuit or the closed-loop precision limiting circuit, and the output terminal is connected to the memristor under test, which is used to switch the connection polarity of the two ends of the memristor under test. A current-to-voltage reading circuit is used to perform closed-loop adjustment of the target resistance value of the memristor under test based on the reference voltage.

[0028] Furthermore, the pulse generation circuit includes an FPGA and a high-speed digital-to-analog converter (DAC). The FPGA is used to generate digital pulse data, pulse synchronization signals, current limiting path selection signals, current limiting gear selection signals, polarity switching control signals, and sampling control signals. The high-speed digital-to-analog converter (DAC) is used to convert the digital pulse data into analog test pulses.

[0029] Furthermore, the high-speed hard shutdown current limiting path includes a high-speed current limiting range selection circuit, a voltage comparator, a logic control unit, and a MOS fast shutdown unit. The high-speed current limiting range selection circuit is used to select different sampling resistors and generate a sampling voltage corresponding to the write current. The voltage comparator is used to compare the sampled voltage corresponding to the write current with the set threshold of the high-speed digital-to-analog converter (DAC). The logic control unit is used to generate a MOS transistor control signal based on the pulse synchronization signal and the voltage comparator output signal. The MOS fast turn-off unit is used to turn on or cut off the write current path according to the MOS control signal. The MOS fast turn-off unit is connected in series in the main transmission path of the test pulse. One main current terminal of the MOS fast turn-off unit is used to receive the test pulse selected by the first current limiting path selection switch, and the other main current terminal is connected to the high-speed current limiting range selection circuit.

[0030] Furthermore, the logic control unit includes NOT gates, D flip-flops, and AND gates; The pulse synchronization signal is input to the NOT gate, and the output of the NOT gate is connected to the asynchronous set terminal of the D flip-flop. The data input terminal of the D flip-flop is connected to a low level; The output of the voltage comparator is connected to the clock input of the D flip-flop; The output of the D flip-flop and the pulse synchronization signal are respectively input to the logic AND gate; The output of the AND gate is connected to the control terminal of the MOS fast shutdown unit.

[0031] Furthermore, the high-speed current limiting level selection circuit includes a single-pole multi-throw analog switch and multiple sampling resistors with different resistance values. The single-pole multi-throw analog switch is used to select one of the sampling resistors to be connected to the high-speed hard-shutdown current limiting path to configure different overcurrent detection levels.

[0032] Furthermore, the closed-loop precision current limiting circuit includes a precision current limiting range selection circuit, an operational amplifier, and a power regulating transistor; The precision current limiting range selection circuit includes a single-pole multi-throw analog switch and multiple current limiting resistors with different resistance values, used to select current limiting resistors with different resistance values. One input terminal of the operational amplifier is used to receive the reference voltage output by the DAC, and the other input terminal is used to receive the feedback node voltage. The output terminal of the operational amplifier is connected to the control terminal of the power regulating transistor. The operational amplifier is used to adjust the conduction level of the power regulation transistor through negative feedback, so that the feedback node voltage follows the reference voltage output by the DAC; The power regulating transistor is connected in series in the main transmission path of the test pulse. One main current terminal of the power regulating transistor is used to receive the test pulse selected by the first current limiting path selection switch, and the other main current terminal is connected to the precision current limiting range selection circuit.

[0033] Furthermore, the precision current limiting level selection circuit includes a single-pole multi-throw analog switch and multiple current limiting resistors with different resistance values. The single-pole multi-throw analog switch is used to select one of the current limiting resistors to be connected to the closed-loop precision current limiting circuit to configure different precision current limiting levels.

[0034] Among the multiple sampling resistors or current-limiting resistors with different resistance values, the larger the resistance value, the smaller the corresponding allowable current-limiting level; the smaller the resistance value, the larger the corresponding allowable current-limiting level.

[0035] Furthermore, the current-to-voltage reading circuit includes a transimpedance amplifier, a transimpedance resistor, an analog-to-digital converter (ADC), and an FPGA control and processing unit; The transimpedance amplifier is used to convert the current flowing through the memristor under test into a voltage signal; The analog-to-digital converter (ADC) is used to acquire the voltage signal; The FPGA control processing unit is used to calculate the resistance value of the memristor under test based on the voltage signal acquired by the analog-to-digital converter (ADC), the reference voltage, and the currently connected current-limiting resistor, and adjust the reference voltage, test pulse parameters, current-limiting level, or polarity switching state according to the calculation results, so as to perform closed-loop modulation of the target resistance value of the memristor under test.

[0036] Specifically, let the resistance of the transresistor be... The voltage acquired by the ADC is The current of the memristor under test satisfy: ; Alternatively, based on the polarity relationship of the transimpedance amplifier: .

[0037] In the closed-loop precision current-limiting circuit, let the connected current-limiting resistor be... The resistance of the memristor to be tested is (From the perspective of circuit accuracy, if we ignore the switch on-resistance, wiring resistance, and contact resistance, or if we pre-calibrate and compensate for the above parasitic resistances, the feedback node voltage is approximately equal to the current-limiting resistor.) With the memristor under test (Total voltage across both ends), DAC output reference voltage is The FPGA control processing unit then calculates the resistance value of the memristor under test according to the following formula: .

[0038] The system then determines whether to continue the write operation based on the calculated resistance value of the memristor under test.

[0039] Furthermore, the polarity switching circuit is a double-pole double-throw switch circuit, an H-bridge switch circuit, or an equivalent switch array, used to exchange the connection relationship between the two ends of the memristor under test and the output terminal of the previous stage, so as to realize forward writing and reverse writing of the memristor under test.

[0040] Furthermore, the first current limiting path selection switch and the second current limiting path selection switch are one or more of analog switches, relays, solid-state switches, and MOS switch arrays, or are equivalently implemented by a multi-pole multi-throw switch network.

[0041] The sources of the three DACs—the high-speed DAC that generates the test pulse, the threshold reference voltage of the high-speed path comparator, and the reference voltage in the precision path—can be generated by independent DACs or by different output channels of the same multi-channel DAC; each DAC or DAC channel is controlled by an FPGA.

[0042] The memristor read / write test circuit in this embodiment will be further described below with reference to the accompanying drawings: like Figure 1 As shown, this embodiment provides a memristor read / write test circuit, including a pulse generation circuit, a first current limiting path selection switch, a high-speed hard shutdown current limiting path, a closed-loop precision current limiting path, a second current limiting path selection switch, a polarity switching circuit, the memristor under test, and a current-to-voltage reading circuit.

[0043] The pulse generation circuit consists of an FPGA and a high-speed DAC. The FPGA generates digital pulse data, pulse synchronization signals, current limiting mode selection signals, current limiting range selection signals, polarity switching control signals, and sampling control signals. The high-speed DAC generates analog test pulses based on the digital pulse data output from the FPGA. These analog test pulses can be used for memristor read, write, SET, and RESET operations.

[0044] The first current limiting path selection switch is located after the pulse generation circuit and is used to select whether the test pulse enters the high-speed hard-shutdown current limiting path or the closed-loop precision current limiting path. The second current limiting path selection switch is located after both current limiting paths and is used to connect the output of the selected current limiting path to the polarity switching circuit. The first and second current limiting path selection switches can be implemented by analog switches, relays, solid-state switches, or MOS switch arrays, respectively, or they can be integrated into a multi-pole multi-throw switch network.

[0045] Therefore, when selecting the high-speed hard-shutdown limiting circuit, the test pulse is applied to the memristor under test via the high-speed hard-shutdown limiting circuit, the second limiting circuit selection switch, and the polarity switching circuit, and the current is read by the current-to-voltage reading circuit; when selecting the closed-loop precision limiting circuit, the test pulse is applied to the memristor under test via the closed-loop precision limiting circuit, the second limiting circuit selection switch, and the polarity switching circuit, and the current is read by the current-to-voltage reading circuit.

[0046] like Figure 2 As shown, the high-speed hard shutdown current limiting circuit includes a high-speed current limiting range selection circuit, a voltage comparator, a logic control unit, and a MOS fast shutdown unit.

[0047] A high-speed hard-turn-off current-limiting path is set in the main transmission path of the test pulse. The analog test pulse output by the pulse generation circuit is input to the main current terminal of the MOS fast turn-off unit after passing through the first current-limiting path selection switch. The other main current terminal of the MOS fast turn-off unit is connected to the high-speed current-limiting range selection circuit and output to the polarity switching circuit through the second current-limiting path selection switch. Therefore, the MOS fast turn-off unit is not only used as a logic control device, but is connected in series in the write current path of the test pulse to the memristor under test, used to control whether the test pulse can continue to be transmitted to the memristor under test.

[0048] The high-speed current limiting range selection circuit includes a single-pole multi-throw analog switch and multiple sampling resistors with different resistance values. By selecting different sampling resistors, the relationship between the sampling voltage and the write current can be changed, thereby configuring different overcurrent detection threshold ranges. The larger the sampling resistor value, the larger the sampling voltage generated under the same current conditions, and therefore the smaller the corresponding allowable current limiting range; the smaller the sampling resistor value, the larger the corresponding allowable current limiting range.

[0049] One input of the voltage comparator receives a sampled voltage generated by a high-speed current limiting range selection circuit, and the other input receives a threshold voltage provided by a DAC or a reference voltage source. When the sampled voltage does not exceed the threshold voltage, the voltage comparator outputs a low level; when the sampled voltage exceeds the threshold voltage, the voltage comparator outputs a high level.

[0050] The logic control unit includes a NOT gate, a D flip-flop, and an AND gate. One pulse synchronization signal is input to the NOT gate, and the output of the NOT gate is connected to the asynchronous set terminal of the D flip-flop. The data input of the D flip-flop is connected to a low level. The output of the voltage comparator is connected to the clock input of the D flip-flop. The output of the D flip-flop and the pulse synchronization signal are both input to the AND gate. The output of the AND gate is connected to the control terminal of the MOS fast shutdown unit.

[0051] The working process of high-speed hard-closing and traffic restriction is as follows.

[0052] When no pulse is input, the pulse synchronization signal is low, and after passing through the NOT gate, it becomes high, putting the D flip-flop in an asynchronous set state, and the D flip-flop outputs a high level. Since the pulse synchronization signal is low at this time, the AND gate outputs a low level, the MOS fast turn-off unit is in the off state, and the main current path between the pulse generation circuit output and the high-speed current limiting range selection circuit is broken. Therefore, the test pulse cannot be transmitted to the subsequent polarity switching circuit and the memristor under test.

[0053] When a pulse is input, the pulse synchronization signal is high, the NOT gate outputs a low level, the D flip-flop is de-asynchronously set and maintains a high output level. At this time, the high output level of the D flip-flop and the pulse synchronization signal are input to the AND gate, causing the AND gate to output a high level. The MOS fast turn-off unit is turned on. At this time, the analog test pulse output by the pulse generation circuit is applied to the memristor under test through the main current channel of the MOS fast turn-off unit, the high-speed current limiting range selection circuit, the second current limiting path selection switch, and the polarity switching circuit, thus forming a write current path.

[0054] When the write current of the memristor under test increases, and the sampling voltage generated by the high-speed current limiting range selection circuit exceeds the DAC's set threshold, the voltage comparator output flips from low to high, generating a rising edge at the clock input of the D flip-flop. Since the data input of the D flip-flop is connected to a low level, the output of the D flip-flop flips from high to low under the action of this rising edge. At this time, the output of the AND gate changes from high to low, and the MOS fast turn-off unit quickly turns off, thereby cutting off the write current path and disconnecting the main transmission path of the test pulse. Even if the pulse generation circuit is still in the current pulse output period, the test pulse is blocked by the MOS fast turn-off unit and cannot be applied to the memristor under test, thus achieving fast current limiting protection under narrow pulse conditions.

[0055] like Figure 3 As shown, the closed-loop precision current limiting circuit includes a precision current limiting range selection circuit, an operational amplifier, and a power regulating transistor. The closed-loop precision current limiting circuit is located between the first current limiting circuit selection switch and the second current limiting circuit selection switch. Its input terminal receives the test pulse selected by the first current limiting circuit selection switch, and its output terminal outputs the controlled test pulse to the second current limiting circuit selection switch.

[0056] A power regulator transistor is connected in series in the main transmission path of the test pulse. Specifically, one main current terminal of the power regulator transistor serves as the pulse input terminal of the closed-loop precision current limiting circuit, used to receive the test pulse output from the pulse generation circuit and selected by the first current limiting circuit selection switch; the other main current terminal of the power regulator transistor is connected to the precision current limiting range selection circuit. The output terminal of the precision current limiting range selection circuit serves as the pulse output terminal of the closed-loop precision current limiting circuit, and is connected to the subsequent polarity switching circuit via the second current limiting circuit selection switch. Therefore, the test pulse is not directly applied to the memristor under test, but first passes through the power regulator transistor and the precision current limiting range selection circuit, and then is applied to the memristor under test by the subsequent polarity switching circuit.

[0057] The precision current limiting range selection circuit includes a single-pole multi-throw (SPMD) analog switch and multiple current-limiting resistors with different resistance values. These resistors provide different precision current limiting ranges. The SPMD analog switch is used to select one of the current-limiting resistors. Connect to the main transmission path of the test pulse to adapt to different current limiting levels. Current limiting resistor. The larger the resistance value, the smaller the write current allowed under the same control conditions; current-limiting resistor The smaller the resistance value, the greater the write current allowed to pass under the same control conditions.

[0058] The non-inverting input of the operational amplifier receives the reference voltage from the DAC output. The inverting input is connected to the feedback node, and the output is connected to the control terminal of the power regulator. Power regulator and current-limiting resistor are also included. and the memristor under test This forms a series write path. The operational amplifier adjusts the conduction level of the power regulation transistor through negative feedback, making the feedback node voltage similar to the DAC output reference voltage. To maintain consistency, the power regulator transistor is not simply fully turned on during the test pulse input period, but rather in a controlled on state under the control of the operational amplifier, thereby regulating the flow of the test pulse through the power regulator transistor and the current-limiting resistor. The magnitude of the current transmitted to the subsequent circuit.

[0059] Memristor under test The circuit is connected to a current-to-voltage reading circuit via a polarity switching circuit. Under different polarity switching states, the corresponding terminal of the memristor under test is connected to the current-to-voltage reading circuit. The current-to-voltage reading circuit includes a transimpedance amplifier, a transimpedance resistor, an ADC, and an FPGA control processing unit. The non-inverting input of the transimpedance amplifier is grounded, and the inverting input is connected to the memristor under test. One end of the resistor is connected between the output and inverting input of the transimpedance amplifier. Since the transimpedance amplifier forms a virtual ground input structure, current flows through the memristor under test. The current is converted into a voltage output and acquired by the ADC.

[0060] When the test pulse is within the valid input period, the closed-loop precision current limiting circuit provides a controlled write current path through the power regulator. The test pulse sequentially passes through the power regulator, the precision current limiting range selection circuit, the second current limiting circuit selection switch, the polarity switching circuit, and the memristor under test, and finally enters the current-to-voltage readout circuit. The current-to-voltage readout circuit converts the current flowing through the memristor under test into a voltage signal, which is then acquired by the ADC and sent to the FPGA for processing.

[0061] Let the resistance of the transresistor be... The voltage acquired by the ADC is Then the memristor under test current Based on the polarity of the transimpedance amplifier, it can be expressed as: ; When only the current amplitude is considered, it can also be expressed as: ; Due to the current-limiting resistor With the memristor under test When connected in series, the same current flows through both. When the operational amplifier, under negative feedback, makes the feedback node voltage equal to the DAC output voltage... At that time, the current limiting resistor and the memristor under test The series resistance satisfies: ; Therefore, the memristor under test The resistance value can be calculated as follows: ; like Figure 6 As shown, the current-to-voltage readout circuit includes a transimpedance amplifier, a transimpedance resistor, an ADC, and an FPGA control processing unit. Based on the ADC sampling voltage... Transresistance Current limiting resistor and DAC setting voltage Calculate the memristor under test The FPGA calculates the current resistance value and compares it with the target resistance range. When the calculated memristor resistance value is lower or higher than the target range, the FPGA adjusts the DAC output voltage, write pulse width, write pulse count, polarity switching state, or current limiting level, and then performs write and read operations again. When the calculated memristor resistance value falls within the target range, the FPGA stops the write process, completing closed-loop precision resistance adjustment.

[0062] When the test pulse ends, the pulse input of the closed-loop precision current limiting circuit disappears, and the write current flowing through the power regulator, precision current limiting range selection circuit, memristor under test, and current-to-voltage readout circuit is correspondingly cut off. Thus, the test pulse provides the time window and drive energy required for memristor writing; the operational amplifier and power regulator limit the write current within this time window; the precision current limiting range selection circuit configures different current limiting ranges; and the current-to-voltage readout circuit provides the current feedback information required for closed-loop impedance adjustment.

[0063] like Figure 4 As shown, the current limiting range selection circuit in this embodiment includes a single-pole multi-throw (SPMD) analog switch and multiple sampling resistors or current-limiting resistors with different resistance values. For example, the multiple resistors may include 100Ω, 10kΩ, and 1MΩ. The common terminal of the SPMD analog switch is connected to the current limiting path, and its multiple selection terminals are respectively connected to resistors with different resistance values. The FPGA outputs a range selection signal to control the SPMD analog switch to select one of the resistors, so that the corresponding resistor is connected to the current limiting path. The specific resistance value and number of sampling resistors or current-limiting resistors can be expanded according to the current range, resistance range, and test accuracy requirements of the memristor under test.

[0064] like Figure 5 As shown, the polarity switching circuit employs a double-pole double-throw switch or an equivalent H-bridge switch array. By switching the state of the double-pole double-throw switch, the connection direction between the two ends of the memristor under test and the output terminal of the preceding stage can be exchanged. Thus, without changing the output polarity of the preceding stage pulse generator circuit, a positive or negative pulse can be applied to the two ends of the memristor under test, realizing SET and RESET operations.

[0065] The aforementioned MOS fast turn-off unit can be implemented using NMOS transistors, PMOS transistors, complementary MOS switches, or solid-state switches; the single-pole multi-throw analog switch can be implemented using an analog multiplexer, a relay array, or a semiconductor switch array; the polarity switching circuit can be implemented using a double-pole double-throw relay, an analog switch matrix, or an H-bridge circuit; the FPGA can also be replaced with a microcontroller, a programmable logic device, or other digital control unit.

[0066] This embodiment also provides a memristor read / write test method based on the aforementioned memristor read / write test circuit, including: Test pulses are generated using a pulse generation circuit; According to the test task, the test pulse is selected to be input into the high-speed hard shutdown limiting circuit or the closed-loop precision limiting circuit. The high-speed hard shutdown limiting circuit generates a shutdown signal and cuts off the write current path, while the closed-loop precision limiting circuit makes the feedback node voltage follow the reference voltage. The polarity of the connection between the two ends of the memristor under test is switched by a polarity switching circuit. The test pulse is applied to the memristor under test via a selected current-limiting path and polarity-switching circuit. The voltage of the memristor under test is acquired by a current-to-voltage reading circuit, and the resistance value of the memristor under test is calculated based on the reference voltage. Determine whether to continue writing, switch the current limiting level, switch the writing polarity, or end the test based on the resistance value of the memristor under test.

[0067] Furthermore, the high-speed hard-shutdown current-limiting path for generating a shutdown signal and trunculating the write current path includes: When the pulse synchronization signal is low, the D flip-flop is in an asynchronous set state and the AND gate outputs a low level, turning off the MOS fast shutdown unit. When the pulse synchronization signal is high and the sampled voltage does not exceed the set threshold voltage, the AND gate outputs a high level, turning on the MOS fast shutdown unit. When the sampled voltage exceeds the set threshold voltage, the voltage comparator output flips and triggers the D flip-flop to output a low level, causing the AND gate to output a low level, thereby turning off the MOS fast shutdown unit.

[0068] Further, calculating the resistance value of the memristor under test includes: The voltage of the memristor under test is acquired by a transimpedance amplifier and an analog-to-digital converter (ADC). The current of the memristor under test is calculated based on the voltage signal and the transimpedance resistance. The resistance value of the memristor under test is calculated based on the current of the memristor under test, the DAC output reference voltage, and the currently connected current-limiting resistor.

[0069] Furthermore, the resistance value of the memristor under test is calculated. The method is as follows: ; in, For current limiting resistor, The current flowing through the memristor under test is calculated by collecting the voltage and the transresistance. To set the voltage.

[0070] Furthermore, determining whether to continue writing, switch the current limiting level, switch the writing polarity, or end the test based on the resistance value of the memristor under test includes: When the calculated resistance value of the memristor under test does not fall within the target resistance range, adjust the DAC output voltage, pulse width, pulse count, current limiting level, or polarity switching state, and continue writing and reading; when the calculated resistance value of the memristor under test falls within the target resistance range, stop writing and save the test results. The following is in conjunction with the appendix Figure 7 The memristor read / write test method of this embodiment is further described, including the following steps.

[0071] Step S1: The FPGA configures pulse parameters according to the test task. The pulse parameters include pulse amplitude, pulse width, pulse period, number of pulses, and pulse polarity.

[0072] In step S2, the FPGA controls the first current limiting path selection switch and the second current limiting path selection switch to select either the high-speed hard shutdown current limiting path or the closed-loop precision current limiting path.

[0073] In step S3, the FPGA controls the single-pole multi-throw analog switch to select the appropriate sampling resistor or current-limiting resistor based on the allowable current range of the memristor under test and the target test conditions, so as to set the current-limiting level.

[0074] In step S4, the FPGA controls the polarity switching circuit to determine the connection direction of the two ends of the memristor under test in order to perform a SET operation or a RESET operation.

[0075] Step S5: The pulse generation circuit outputs a test pulse, which is applied to the memristor under test via the selected current-limiting path and polarity switching circuit. When the high-speed hard-shutdown current-limiting path is selected, proceed to step S6; when the closed-loop precision current-limiting path is selected, proceed to step S7.

[0076] Step S6: In the high-speed hard shutdown current limiting mode, when the sampling voltage exceeds the DAC set threshold, the voltage comparator triggers the D flip-flop to flip, causing the MOS fast shutdown unit to turn off and cut off the write current.

[0077] In step S7, under closed-loop precision current limiting mode, the operational amplifier adjusts the power regulation tube through negative feedback so that the feedback node voltage follows the DAC set voltage; at the same time, the transimpedance amplifier and ADC acquire the current information of the memristor under test.

[0078] In step S8, the FPGA calculates the current resistance value of the memristor under test based on the ADC sampling results and determines whether it falls within the target resistance value range.

[0079] Step S9: If the memristor under test does not enter the target resistance range, the FPGA adjusts the DAC output voltage, pulse width, pulse count, current limiting level, or polarity switching state, and repeats steps S5 to S8; if the memristor under test enters the target resistance range, the writing stops and the test results are saved.

[0080] The embodiments described above are merely preferred embodiments of the present invention and are not intended to limit the scope of the present invention. Various modifications and improvements made to the technical solutions of the present invention by those skilled in the art without departing from the spirit of the present invention should fall within the protection scope defined by the claims of the present invention.

Claims

1. A memristor read / write test circuit that combines high-speed hard-shutdown current limiting with closed-loop precision impedance adjustment, characterized in that, include: Pulse generation circuit, used to output test pulses; The current limiting circuit selection switch is used to control the test pulse to enter the high-speed hard shutdown current limiting circuit or the closed-loop precision current limiting circuit, and to control the connection between the high-speed hard shutdown current limiting circuit or the closed-loop precision current limiting circuit and the polarity switching circuit. A high-speed hard-shutdown current-limiting path is used to generate a shutdown signal based on threshold comparison and cut off the write current path during pulse writing. A closed-loop precision current limiting circuit is used to adjust the conduction level of the power regulation transistor through the negative feedback of the operational amplifier, so that the feedback node voltage follows the reference voltage. The input terminal of the polarity switching circuit is connected to the high-speed hard-shutdown limiting circuit or the closed-loop precision limiting circuit, and the output terminal is connected to the memristor under test, which is used to switch the connection polarity of the two ends of the memristor under test. A current-to-voltage reading circuit is used to perform closed-loop adjustment of the target resistance value of the memristor under test based on the reference voltage.

2. The memristor read / write test circuit according to claim 1, characterized in that, The high-speed hard shutdown current limiting circuit includes a high-speed current limiting range selection circuit, a voltage comparator, a logic control unit, and a MOS fast shutdown unit. The high-speed current limiting range selection circuit is used to select different sampling resistors and generate a sampling voltage corresponding to the write current. The voltage comparator is used to compare the sampled voltage corresponding to the write current with the set threshold of the high-speed digital-to-analog converter (DAC). The logic control unit is used to generate a MOS transistor control signal based on the pulse synchronization signal and the voltage comparator output signal. The MOS fast turn-off unit is used to turn on or cut off the write current path according to the MOS control signal. The MOS fast turn-off unit is connected in series in the main transmission path of the test pulse. One main current terminal of the MOS fast turn-off unit is used to receive the test pulse selected by the first current limiting path selection switch, and the other main current terminal is connected to the high-speed current limiting range selection circuit.

3. The memristor read / write test circuit according to claim 2, characterized in that, The logic control unit includes NOT gates, D flip-flops, and AND gates; The pulse synchronization signal is input to the NOT gate, and the output of the NOT gate is connected to the asynchronous set terminal of the D flip-flop. The data input terminal of the D flip-flop is connected to a low level; The output of the voltage comparator is connected to the clock input of the D flip-flop; The output of the D flip-flop and the pulse synchronization signal are respectively input to the logic AND gate; The output of the AND gate is connected to the control terminal of the MOS fast shutdown unit.

4. The memristor read / write test circuit according to claim 1, characterized in that, The closed-loop precision current limiting circuit includes a precision current limiting range selection circuit, an operational amplifier, and a power regulating transistor; The precision current limiting range selection circuit includes a single-pole multi-throw analog switch and multiple current limiting resistors with different resistance values, used to select current limiting resistors with different resistance values. One input terminal of the operational amplifier is used to receive the reference voltage output by the DAC, and the other input terminal is used to receive the feedback node voltage. The output terminal of the operational amplifier is connected to the control terminal of the power regulating transistor. The operational amplifier is used to adjust the conduction level of the power regulating transistor through negative feedback, so that the feedback node voltage follows the reference voltage output by the DAC. The power regulating transistor is connected in series in the main transmission path of the test pulse. One main current terminal of the power regulating transistor is used to receive the test pulse selected by the first current limiting path selection switch, and the other main current terminal is connected to the precision current limiting range selection circuit.

5. The memristor read / write test circuit according to claim 1, characterized in that, The current-to-voltage reading circuit includes a transimpedance amplifier, a transimpedance resistor, an analog-to-digital converter (ADC), and an FPGA control and processing unit. The transimpedance amplifier is used to convert the current flowing through the memristor under test into a voltage signal; The analog-to-digital converter (ADC) is used to acquire the voltage signal; The FPGA control processing unit is used to calculate the resistance value of the memristor under test based on the voltage signal acquired by the analog-to-digital converter (ADC), the reference voltage, and the currently connected current-limiting resistor, and adjust the reference voltage, test pulse parameters, current-limiting level, or polarity switching state according to the calculation results, so as to perform closed-loop modulation of the target resistance value of the memristor under test.

6. A memristor read / write test method based on the memristor read / write test circuit according to any one of claims 1 to 5, characterized in that, include: Test pulses are generated using a pulse generation circuit; According to the test task, the test pulse is selected to be input into the high-speed hard shutdown limiting circuit or the closed-loop precision limiting circuit. The high-speed hard shutdown limiting circuit generates a shutdown signal and cuts off the write current path, while the closed-loop precision limiting circuit makes the feedback node voltage follow the reference voltage. The polarity of the connection between the two ends of the memristor under test is switched by a polarity switching circuit. The test pulse is applied to the memristor under test via a selected current-limiting path and polarity-switching circuit. The voltage of the memristor under test is acquired by a current-to-voltage reading circuit, and the resistance value of the memristor under test is calculated based on the reference voltage. Determine whether to continue writing, switch the current limiting level, switch the writing polarity, or end the test based on the resistance value of the memristor under test.

7. The memristor read / write test method according to claim 6, characterized in that, The high-speed hard shutdown current-limiting path generates a shutdown signal and cuts off the write current path, including: When the pulse synchronization signal is low, the D flip-flop is in an asynchronous set state and the AND gate outputs a low level, turning off the MOS fast shutdown unit. When the pulse synchronization signal is high and the sampled voltage does not exceed the set threshold voltage, the AND gate outputs a high level, turning on the MOS fast shutdown unit. When the sampled voltage exceeds the set threshold voltage, the voltage comparator output flips and triggers the D flip-flop to output a low level, causing the AND gate to output a low level, thereby turning off the MOS fast shutdown unit.

8. The memristor read / write test method according to claim 6, characterized in that, Calculating the resistance value of the memristor under test includes: The voltage of the memristor under test is acquired by a transimpedance amplifier and an analog-to-digital converter (ADC). The current of the memristor under test is calculated based on the voltage signal and the transimpedance resistance. The resistance value of the memristor under test is calculated based on the current of the memristor under test, the DAC output reference voltage, and the currently connected current-limiting resistor.

9. The memristor read / write test method according to claim 8, characterized in that, Calculate the resistance value of the memristor under test The method is as follows: ； in, For current limiting resistor, The magnitude of the current flowing through the memristor under test is obtained by collecting the voltage and the transresistance. To set the voltage.

10. The memristor read / write test method according to claim 6, characterized in that, Determining whether to continue writing, switch the current limiting level, switch the writing polarity, or end the test based on the resistance value of the memristor under test includes: When the calculated resistance value of the memristor under test does not fall within the target resistance range, adjust the DAC output voltage, pulse width, pulse count, current limiting level, or polarity switching state, and continue writing and reading; when the calculated resistance value of the memristor under test falls within the target resistance range, stop writing and save the test results.

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