A chromatographic diagnosis method and system based on multi-source analyzer time series data

Abstract

The present application relates to the technical field of computer system fault diagnosis, and discloses a chromatographic diagnosis method and system based on multi-source analyzer time sequence data, which synchronously collects an application layer chromatographic original sampling sequence of a target chromatographic analyzer and a bottom layer clock synchronization deviation sequence of a field bus node; a macroscopic offset difference value of a key component is obtained through peak value detection, and discrete integral accumulation is performed on a bottom layer transient time deviation to generate a cumulative clock drift value; a dynamic time warping with a strip time window constraint is used to establish a time sequence mapping relationship between the two types of characteristic sequences, and a phase locking correlation coefficient is calculated. The system combines the phase locking correlation coefficient and the bottom layer clock cumulative drift extreme value to judge bottom layer software and hardware abnormalities, and when an abnormality is confirmed, the original time stamp is reversely compensated according to a distortion path matrix and a segmented linear interpolation result, and a reconstructed chromatographic data message is output.

Description

Technical Field

[0001] This invention relates to the field of computer system fault diagnosis technology, specifically to a chromatographic diagnostic method and system based on time-series data from a multi-source analyzer. Background Technology

[0002] Chromatography analyzers are widely used in industrial process monitoring, gas component analysis, and online quality control. As industrial field control systems evolve towards networking, distributed computing, and edge computing, the sampling, data reporting, and status diagnostic processes of chromatography analyzers typically rely on fieldbus, industrial Ethernet, time-sensitive networks, or distributed clock synchronization mechanisms. For chromatographic analysis processes that depend on periodic sampling and retention time determination, the stability of the sampling timing directly affects the chromatographic peak position, retention time calculation, and subsequent component identification results.

[0003] Current diagnostic methods for chromatographic analyzers typically rely primarily on application-layer chromatographic data. For example, they assess instrument or process status based on peak shape, peak area, retention time shift, baseline noise, or changes in component concentration. While these methods can reflect physicochemical factors such as column aging, carrier gas flow fluctuations, temperature control anomalies, and sample component changes, their diagnostic focus is mainly on the instrument itself or the process flow. When the timing shift in chromatographic data originates from fieldbus clock synchronization errors, synchronization message jitter, network congestion, or real-time operating system task scheduling blockages or interruption response delays, relying solely on application-layer chromatographic data is insufficient to determine whether the anomaly is caused by instability in the underlying computer hardware and software timing base.

[0004] In industrial settings, the application-layer sampling data of a target chromatograph and the underlying synchronization status data of the fieldbus node often have different data sources, sampling periods, and physical dimensions. Application-layer chromatographic signals typically exhibit macroscopic, slowly varying time-series data with periods in the order of seconds or longer, while underlying clock synchronization deviations, phase compensation amounts, and interruption delays manifest as transient fluctuations with periods in the order of microseconds or even shorter. Directly comparing these two types of data can easily lead to matching errors due to inconsistent sampling frequencies, misaligned time windows, and inconsistent dimensions. This can result in misjudging actual process anomalies as underlying system anomalies, or misjudging underlying hardware and software time base anomalies as fluctuations in chromatographic operating conditions.

[0005] Existing computer system fault diagnosis or industrial network diagnostic methods typically focus on communication packet loss, link delay, synchronization errors, or node status itself. While they can detect underlying communication or scheduling anomalies, they usually cannot further determine whether such anomalies have propagated to the chromatographic application layer data, nor can they compensate for the timestamps of already generated application layer chromatographic data based on underlying clock drift. For chromatographic sampling sequences that already carry distorted timestamps, without a temporal mapping relationship between application layer features and underlying clock deviations, even if underlying clock anomalies can be detected, it is difficult to determine the compensation amount corresponding to each sampling point.

[0006] Therefore, a chromatographic diagnostic solution for fault diagnosis and fault tolerance in computer systems is needed. This solution should be able to simultaneously utilize application-layer chromatographic time-series data and underlying clock synchronization status data to establish a correlation between the two types of heterogeneous data on a unified physical time scale. This solution should distinguish between external physicochemical process anomalies and underlying hardware / software time base anomalies, and compensate for the original timestamps of the application-layer chromatographic data when underlying hardware / software anomalies are confirmed, thereby improving the availability of chromatographic data under abnormal network conditions in industrial settings. Summary of the Invention

[0007] To address the shortcomings of existing technologies, this invention provides a chromatographic diagnostic method and system based on time-series data from a multi-source analyzer. This solves the problem that existing chromatographic analyzers struggle to distinguish between retention time shifts caused by chromatographic process factors and underlying hardware / software time base anomalies caused by fieldbus clock synchronization errors, network congestion, or real-time operating system interruptions. Furthermore, they are unable to effectively compensate for the distortion of the original timestamp caused by underlying time base anomalies.

[0008] To achieve the above objectives, the present invention provides the following technical solution:

[0009] The first aspect of this invention provides a chromatographic diagnostic method based on time-series data from a multi-source analyzer, comprising the following steps:

[0010] The application layer chromatography raw sampling sequence of the target chromatographic analyzer and the underlying clock synchronization deviation sequence of the fieldbus node corresponding to the target chromatographic analyzer are collected synchronously.

[0011] Cross-layer feature extraction is performed on the original chromatographic sampling sequence of the application layer and the clock synchronization deviation sequence of the bottom layer to generate application layer feature sequences and bottom system feature sequences aligned with physical time scales, respectively.

[0012] Dynamic time warping calculation with striped time window constraints is performed on the application layer feature sequence and the underlying system feature sequence to generate a twisted path matrix that records the temporal mapping relationship. The phase-locked correlation coefficient between the application layer feature sequence and the underlying system feature sequence is calculated based on the twisted path matrix. The width of the striped time window is 5% to 10% of the total length of the application layer feature sequence.

[0013] By combining the phase-locked correlation coefficient, the preset judgment threshold, and whether the extreme value of the cumulative clock drift value exceeds the hardware natural temperature drift dead zone, it is determined whether the target chromatograph has experienced a low-level hardware or software abnormality. The judgment threshold of the phase-locked correlation coefficient is 0.75 to 0.85, and the natural temperature drift dead zone is the maximum time offset interval corresponding to the normal temperature drift of the hardware clock device of the chromatograph.

[0014] When an underlying hardware or software anomaly is detected, the distorted original timestamps in the original sampling sequence of the application layer chromatography are compensated in reverse order based on the time-series mapping relationship recorded in the distorted path matrix.

[0015] Preferably, the step of synchronously acquiring the application layer chromatography raw sampling sequence of the target chromatograph and the underlying clock synchronization deviation sequence of the fieldbus node corresponding to the target chromatograph specifically includes:

[0016] The hard real-time interrupt signal generated by the distributed clock synchronization protocol based on the fieldbus drives the analog-to-digital converter of the target chromatograph to perform discrete sampling and binds to generate the application layer chromatographic raw sampling sequence with the original timestamp; synchronously reads the synchronization control register of the fieldbus node to obtain the micro phase compensation value and the real-time operating system interrupt delay time, and after normalizing the micro phase compensation value and the real-time operating system interrupt delay time to the unit and sign, synthesizes the transient time deviation within the current diagnostic cycle to form the underlying clock synchronization deviation sequence.

[0017] Preferably, the step of generating application-layer feature sequences and underlying system feature sequences aligned to physical time scales specifically includes:

[0018] Peak detection is performed on the original sampled sequence of the applied layer chromatography, the actual retention time of key components in the original sampled sequence of the applied layer chromatography is extracted, and the macroscopic offset difference between the actual retention time and the reference retention time is calculated. The applied layer feature sequence is composed of each macroscopic offset difference.

[0019] Within a set time window, the underlying clock synchronization deviation sequence is discretely integrated and accumulated to convert the incremental transient time deviation into the accumulated clock drift value, thus forming the underlying system characteristic sequence.

[0020] Preferably, the step of generating a twisted path matrix for recording time-series mapping relationships, and calculating the phase-locked correlation coefficient between the application layer feature sequence and the underlying system feature sequence based on the twisted path matrix, specifically includes:

[0021] Within a band-shaped time window constraint with a width of 5% to 10% of the total length of the application layer feature sequence, calculate the cumulative distance matrix between the application layer feature sequence and the underlying system feature sequence;

[0022] By backtracking and optimizing the cumulative distance matrix, the twisted path matrix is ​​generated. The path coordinates of the twisted path matrix record the alignment relationship in time phase between the macroscopic offset difference value in the application layer feature sequence and the cumulative clock drift value in the underlying system feature sequence.

[0023] By consulting the twisted path matrix, two synchronous alignment sequences of equal length and physically aligned are generated, and the ratio of the product of their covariance and their respective standard deviations is calculated. This ratio is then used as the phase-locked correlation coefficient.

[0024] Preferably, the step of determining whether the target chromatograph has experienced a low-level hardware or software malfunction by combining the phase-locked correlation coefficient, the preset judgment threshold, and whether the extreme value of the accumulated clock drift exceeds the hardware natural temperature drift dead zone specifically includes:

[0025] The phase-locked correlation coefficient is compared with a preset judgment threshold, and the extreme value of the cumulative clock drift value in the current observation window is monitored to see if it exceeds the natural temperature drift dead zone. The judgment threshold is 0.75 to 0.85, and the natural temperature drift dead zone is the maximum time offset interval corresponding to the normal temperature drift of the hardware clock device of the chromatograph.

[0026] If the phase-locked correlation coefficient is greater than or equal to the judgment threshold, and the extreme value of the accumulated clock drift exceeds the natural temperature drift dead zone, then the target chromatograph is judged to have a low-level hardware or software abnormality.

[0027] When diagnosing underlying hardware and software anomalies, the discrete mapping relationship between key feature points and underlying cumulative clock drift values ​​is determined based on the twisted path matrix. A piecewise linear interpolation algorithm is then used to extend this discrete mapping relationship to all original sampling points of the application layer chromatography original sampling sequence.

[0028] Subtract the corresponding target cumulative clock drift value from the original timestamp of each original sampling point to obtain the physical reference timestamp after reverse compensation.

[0029] A second aspect of the present invention provides a chromatographic diagnostic system based on multi-source analyzer time-series data, for performing the above-described chromatographic diagnostic method based on multi-source analyzer time-series data, the system comprising:

[0030] The multi-source data acquisition module is used to synchronously acquire the application layer chromatography raw sampling sequence of the target chromatograph and the underlying clock synchronization deviation sequence of the fieldbus node corresponding to the target chromatograph.

[0031] The cross-layer feature extraction module is used to perform cross-layer feature extraction on the application layer chromatographic raw sampling sequence and the bottom layer clock synchronization deviation sequence, respectively generating application layer feature sequences and bottom layer system feature sequences aligned with physical time scales.

[0032] The timing phase-locked analysis module is used to perform dynamic time warping calculations with striped time window constraints on the application layer feature sequence and the underlying system feature sequence, generate a twisted path matrix that records the timing mapping relationship, and calculate the phase-locked correlation coefficient between the application layer feature sequence and the underlying system feature sequence based on the twisted path matrix, wherein the width of the striped time window is 5% to 10% of the total length of the application layer feature sequence;

[0033] The diagnosis and compensation module is used to determine whether the target chromatograph has experienced a low-level hardware or software malfunction by combining the phase-locked correlation coefficient, a preset judgment threshold, and whether the extreme value of the accumulated clock drift exceeds the hardware natural temperature drift dead zone. When the low-level hardware or software malfunction is determined to have occurred, the module performs reverse timestamp compensation on the distorted original timestamps in the original sampling sequence of the application layer chromatography based on the time-series mapping relationship recorded in the distorted path matrix. The judgment threshold for the phase-locked correlation coefficient is set to 0.75 to 0.85, and the natural temperature drift dead zone is the maximum time offset interval corresponding to the normal temperature drift of the chromatograph's hardware clock device.

[0034] Preferably, the system is deployed in an edge computing gateway;

[0035] The multi-source data acquisition module is equipped with a hardware interrupt monitoring unit. The hardware interrupt monitoring unit is used to capture the hard real-time interrupt signal generated when the distributed clock of the fieldbus triggers the analog-to-digital converter, and bind it to generate the application layer chromatography raw sampling sequence carrying the original timestamp.

[0036] Preferably, the cross-layer feature extraction module allocates independent buffer spaces in the memory of the edge computing gateway for the application layer chromatographic raw sampling sequence and the bottom layer clock synchronization deviation sequence, and the cross-layer feature extraction module is internally equipped with a discrete integral accumulator;

[0037] The discrete integral accumulator is used to convert the incremental transient time deviation in the underlying clock synchronization deviation sequence into a cumulative clock drift value, thereby achieving consistent alignment between the absolute physical time dimension of the underlying system feature sequence in the memory space and the macroscopic offset difference value of the application layer feature sequence.

[0038] Preferably, the diagnosis and compensation module is configured with a dual-dimensional fault isolation logic based on a judgment threshold and a natural temperature drift dead zone, wherein the judgment threshold is 0.75 to 0.85, and the natural temperature drift dead zone is the maximum time offset interval corresponding to the normal temperature drift of the chromatograph hardware clock device;

[0039] When the phase-locked correlation coefficient is less than the judgment threshold, the abnormality is judged to originate from an external physicochemical process, and a process deviation alarm is sent to the upper-level business system.

[0040] When the phase-locked correlation coefficient is greater than or equal to the judgment threshold and the extreme value of the cumulative drift of the underlying clock does not exceed the natural temperature drift dead zone, the timestamp reverse compensation mechanism is not triggered.

[0041] When the phase-locked correlation coefficient is greater than or equal to the judgment threshold and the extreme value of the cumulative drift of the underlying clock exceeds the natural temperature drift dead zone, an underlying hardware or software anomaly is determined to have occurred, and timestamp reverse compensation is triggered.

[0042] Preferably, the diagnosis and compensation module interfaces with the uplink output of the edge computing gateway communication protocol stack;

[0043] Within the output buffer of the edge computing gateway, the original timestamp of the application layer chromatography data packet is replaced with the physical reference timestamp obtained by subtracting the target cumulative clock drift value from the original timestamp; the target cumulative clock drift value is obtained by mapping the twisted path matrix and combining it with piecewise linear interpolation;

[0044] The message with the replaced timestamp is repackaged into a chromatography data message that eliminates timing jitter errors and output to the upper-level monitoring system.

[0045] This invention provides a chromatographic diagnostic method and system based on time-series data from a multi-source analyzer. It offers the following advantages:

[0046] 1. This invention integrates the chromatographic retention time offset and the underlying clock synchronization deviation sequence of the fieldbus node into the same diagnostic process by synchronously acquiring the original chromatographic sampling sequence of the application layer and the underlying clock synchronization state. The application layer data is used to obtain the macroscopic offset difference value through peak detection, and the underlying data is used to obtain the cumulative clock drift value through unit normalization, sign normalization and discrete integral accumulation. This allows the two to be compared on a unified physical time scale, thereby improving the ability to identify underlying hardware and software time base anomalies.

[0047] 2. This invention employs dynamic time warping calculation with a striped time window constraint to generate a distorted path matrix that records the temporal mapping relationship between the application layer feature sequence and the underlying system feature sequence. Based on the aligned synchronous comparison sequence, the phase-locked correlation coefficient is calculated. This processing method can adapt to situations where the application layer chromatographic sampling and the underlying diagnostic polling frequency are inconsistent, reducing matching deviations caused by direct comparison of heterogeneous data at different frequencies, and providing a data foundation for subsequent fault isolation.

[0048] 3. This invention combines phase-locked correlation coefficient and the extreme value of cumulative drift of the underlying clock during anomaly detection, and introduces a natural temperature drift dead zone for dual-dimensional judgment. When the anomaly is confirmed to originate from the underlying hardware and software, the system performs reverse compensation on the original timestamp in the original sampling sequence of the applied layer chromatography based on the distorted path matrix and piecewise linear interpolation results. This method can correct the time axis offset without changing the amplitude of the original chromatographic signal, reducing the probability of confusing process anomalies with underlying time base anomalies. Attached Figure Description

[0049] Figure 1 This is a schematic diagram of the system deployment structure provided in an embodiment of the present invention;

[0050] Figure 2 A flowchart of the diagnostic method provided in an embodiment of the present invention;

[0051] Figure 3 This diagram illustrates the verification of chromatographic time-domain distortion and reverse compensation fault tolerance mechanism caused by underlying network congestion in an embodiment of the present invention. Detailed Implementation

[0052] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0053] See attached document Figure 1 In one embodiment of the present invention, a chromatography diagnostic system based on time-series data from a multi-source analyzer is deployed within an edge computing gateway in an industrial fieldbus network. The underlying hardware of the edge computing gateway is an industrial control computer running a real-time operating system, internally equipped with a media access control network card supporting time-sensitive networking or industrial Ethernet protocols.

[0054] To eliminate time base drift errors caused by ambient temperature fluctuations in naturally running local clocks, industrial fieldbus networks employ a time-triggered architecture. Field nodes do not use freely running local independent clocks as the final sampling time base. Instead, while retaining the local hardware oscillation source, the fieldbus's distributed clock synchronization protocol performs phase calibration and frequency discipline on the local clock, thereby establishing a globally unified physical time base.

[0055] Specifically, the target chromatograph, fieldbus nodes, and edge computing gateway are all located within the same distributed clock synchronization domain. The local high-precision clock of the edge computing gateway participates in synchronization as either the master clock or slave clock within this domain. Therefore, the global receive timestamp generated by the edge computing gateway, the sampling trigger timestamp generated by the field nodes, and the underlying synchronization status timestamp can all be mapped to the same physical time coordinate system.

[0056] For information on the underlying message interaction, phase alignment mechanism, and master-slave clock synchronization mechanism of the fieldbus distributed clock protocol, those skilled in the art can refer to the IEEE 1588 protocol, the EtherCAT distributed clock standard, or relevant time-sensitive network specifications.

[0057] Based on the aforementioned hardware operating environment, the system in this embodiment divides the memory and processor architecture of the edge computing gateway into four main execution modules. The multi-source data acquisition module is directly mounted on the lower layer of the edge computing gateway's communication protocol stack, responsible for reading the message payload and register status of the field nodes. The cross-layer feature extraction module is connected to the data acquisition module, allocating an independent buffer space in memory to perform dimensionality alignment and dimensionality reduction operations on heterogeneous data.

[0058] The timing phase-locked loop (PLL) analysis module, as the core computing engine, performs dynamic time warping and correlation calculations. The diagnostic and compensation module connects to the output of the communication protocol stack. When a low-level computer hardware or software anomaly is diagnosed, it does not write back or tamper with the original communication messages in the fieldbus link. Instead, it reconstructs the timestamps of the application-layer chromatography data messages to be sent to the upper-level monitoring system within the output buffer of the edge computing gateway.

[0059] The diagnostic and compensation module replaces the distorted timestamp in the output data structure with the compensated physical reference timestamp, thereby achieving system-level error shielding and fault-tolerant recovery without changing the original fieldbus communication process or interfering with the hardware operation of the target chromatograph.

[0060] See attached document Figure 2 After the edge computing gateway is powered on and completes system initialization, it repeatedly executes the following steps to complete the fault diagnosis of the computer's underlying layer and the fault-tolerant reconstruction of time-series data.

[0061] S101 synchronously acquires the application layer chromatography raw sampling sequence of the target chromatograph and the underlying clock synchronization deviation sequence of the fieldbus node corresponding to the target chromatograph.

[0062] The analog-to-digital converter of the target chromatograph relies on a hard real-time interrupt generated by a distributed clock to trigger discrete sampling, and generates an application-layer data message with the original absolute timestamp at the sampling trigger moment or the sampling drive execution moment.

[0063] Under normal synchronization, the original absolute timestamp characterizes the occurrence time of the sampling event relative to the global physical time base. However, when network congestion, synchronization message jitter, or real-time operating system task scheduling blockage occurs in the fieldbus synchronization link, the distributed clock phase calibration process or hard real-time interrupt response process shifts, causing the sampling trigger time of the analog-to-digital converter to distort relative to the ideal physical time base. This distortion further manifests as a time base offset in the original timestamp of the application-layer chromatography data message.

[0064] While acquiring application layer messages, the multi-source data acquisition module reads the underlying synchronization status data of the fieldbus node corresponding to the target chromatograph through the bus diagnostic service, and extracts the micro-phase compensation value reflecting the underlying jitter status of the system and the interrupt delay time of the real-time operating system.

[0065] Considering that there is often a physical difference between the reporting cycle of application layer messages and the refresh frequency of the underlying control registers, the multi-source data acquisition module uses the local high-precision clock system of the edge computing gateway to stamp the data with a global receiving timestamp when acquiring these two types of data.

[0066] Among them, the local high-precision clock system of the edge computing gateway is synchronized with the fieldbus distributed clock synchronization domain where the target chromatograph is located, so that the global receiving timestamp can be under the same physical time base as the sampling timestamp and the synchronization control register status timestamp of the field node.

[0067] This global receiving timestamp serves as the absolute coordinate reference for subsequently dividing the synchronous observation time window, ensuring that heterogeneous data with different sampling rates can achieve coarse alignment within the same observation period, thus avoiding misdiagnosis caused by data sliding window misalignment.

[0068] S102, perform cross-layer feature extraction on the original sampling sequence of the application layer chromatography and the bottom layer clock synchronization deviation sequence to generate application layer feature sequences and bottom layer system feature sequences aligned with physical time scales, respectively.

[0069] The chromatographic application layer data represents a macroscopic, slowly varying signal, while the underlying clock network state represents a microscopic, transient signal. The cross-layer feature extraction module uses a peak detection algorithm to extract the actual retention time of key components in the application layer data and calculates the macroscopic offset difference between the actual retention time and the ideal reference retention time.

[0070] Considering that microsecond-level transient network jitter cannot be directly equivalent to second-level chromatographic peak position shift, the cross-layer feature extraction module performs discrete integral accumulation on the bottom transient clock deviation data within the set observation time window, converting the high-frequency network jitter variable into the cumulative absolute value of clock drift.

[0071] This operation makes the temporal physical dimensions of the feature sequences of the underlying system and the macroscopic offset difference values ​​of the feature sequences of the application layer directly comparable in the same coordinate system, forming the basis for subsequent comparison calculations.

[0072] S103 performs dynamic time warping calculation with striped time window constraints on the application layer feature sequence and the underlying system feature sequence to generate a twisted path matrix that records the time-series mapping relationship, and calculates the phase-locked correlation coefficient between the application layer feature sequence and the underlying system feature sequence based on the twisted path matrix.

[0073] During the spatial optimization process, the timing phase-locked loop (PLL) analysis module records the path coordinates of two sets of feature sequences when they reach the minimum cumulative distance in multidimensional space, thereby generating a distorted path matrix. The node data in this matrix objectively reflects the topological mapping relationship between the application layer feature points where macroscopic chemical timing distortion occurs and the underlying cumulative clock drift data points that cause this distortion.

[0074] After aligning the two sequences based on this topological relationship, the system calculates the ratio of the product of their covariance and their respective standard deviations, using the result as the phase-locked correlation coefficient characterizing the degree of coupling between cross-layer physical quantities. To prevent processor arithmetic overflow errors caused by the denominator approaching zero due to the feature sequences being perfectly stationary (i.e., with zero standard deviation) during correlation coefficient division, the system hard-codes a small anti-zero constant into the denominator term. This fault-tolerant design ensures that the algorithm logic can still flow smoothly without causing system crashes when both the network and chemical conditions are in an extremely stable state.

[0075] S104, based on the phase-locked correlation coefficient and the cumulative clock drift value in the system characteristic sequence, determine whether the target chromatograph has experienced a low-level hardware or software anomaly. In practical industrial applications, the system can perform specific anomaly assessments by extracting mathematical characteristics such as the extreme values, average values, or root mean square values ​​of the cumulative clock drift value within the observation time window.

[0076] The diagnosis and compensation module incorporates dual-dimensional isolation logic based on correlation thresholds and physical temperature drift dead zones. In a preferred embodiment, the system compares the real-time calculated phase-locked correlation coefficient with a calibrated decision threshold (typically 0.75–0.85), extracts the extreme value of the accumulated clock drift within the current observation window (i.e., the maximum time base offset), and simultaneously monitors whether this extreme value of the underlying clock accumulated drift exceeds the hardware natural temperature drift dead zone.

[0077] When the correlation coefficient is greater than or equal to the threshold and the drift extreme value exceeds the limit, the system diagnoses that a low-level computer hardware or software abnormality has occurred (such as network congestion or task scheduling blockage).

[0078] Conversely, if the abnormality is not found, it is determined to be a process abnormality caused by fluctuations in the external physicochemical environment.

[0079] S105, when a low-level hardware or software anomaly is detected, the distorted original timestamps in the original sampling sequence of the application layer chromatography are compensated in reverse order based on the time-series mapping relationship recorded in the distorted path matrix.

[0080] The diagnostics and compensation module intercepts application layer data packets within the communication protocol stack. It uses a distorted path matrix to perform data indexing and accurately extracts the specific cumulative clock drift value that causes time-domain distortion at the current sampling point. The module then calls the processor's arithmetic logic unit to perform reverse timestamp compensation calculations, using the following formula:

[0081] ;

[0082] in, This represents the physical reference timestamp output after the system's underlying fault-tolerant reconstruction. This indicates the distorted original timestamp carried in the original sampling sequence of the applied layer chromatography; This represents the target cumulative clock drift value corresponding to the original sampling point, found through mapping and interpolation using the twisted path matrix.

[0083] This subtraction compensation operation is used to remove the equivalent time base offset component introduced by distributed clock synchronization error, network congestion, and real-time operating system interruption blocking from the application layer message time axis, thereby reconstructing the sampling timestamp relative to the ideal physical time base.

[0084] After the edge computing gateway completes the calculation according to the above formula, it uses the physical reference timestamp to overwrite the distorted timestamp in the original message data structure in the memory buffer. Without changing the operating conditions of the on-site physical pipelines and sensors, the system outputs the repackaged chromatographic data message, which eliminates network jitter errors, to the upper-level monitoring system, thus completing the low-level data reconstruction and system fault tolerance under abnormal computer network conditions.

[0085] In the field of fault tolerance for low-level computer systems, accurate error detection relies on the seamless interception of the system's underlying hardware state. In this embodiment, the multi-source data acquisition module within the edge computing gateway, as a core component directly interacting with the fieldbus communication protocol stack, is responsible for continuously monitoring the system's underlying execution state. This monitoring mechanism is not limited to simple data reception but constructs a heterogeneous data source at the underlying level to characterize the health status of the computer system through cross-layer data interception.

[0086] To ensure the absolute time accuracy of on-site chromatographic data sampling, the multi-source data acquisition module performs synchronous acquisition tasks within the gateway for both application layer messages and underlying link status. This includes the following detailed steps:

[0087] S201, based on the hardware interrupt listening unit, binds and generates the application layer chromatography raw sampling sequence.

[0088] As a preferred approach, the multi-source data acquisition module of the edge computing gateway is equipped with a hardware interrupt monitoring unit. Under normal operating conditions, the analog-to-digital converter of the target chromatograph generates a hard real-time interrupt signal to drive sampling, relying on the distributed clock protocol of the fieldbus, rather than relying on a freely running local crystal oscillator.

[0089] The hardware interrupt monitoring unit continuously captures the rising edge of the hard real-time interrupt signal to trigger an action. When the analog-to-digital converter completes the discrete sampling conversion of the chemical component analog signal, the system's underlying logic immediately extracts the current absolute network time from the local high-precision clock register and binds it to the newly acquired chromatographic voltage amplitude in a data structure.

[0090] After the above hardware-level binding operations, the system generates the application layer chromatography raw sampling sequence carrying the original timestamp, and its mathematical expression is as follows:

[0091] ;

[0092] in, This indicates the original sampling sequence obtained from the applied layer chromatography. This represents the global physical index number of the original high-frequency sampling point, and its value range is... ~ ; Indicates the first The amplitude of the chromatographic signal obtained after analog-to-digital conversion of each sampling point; This represents the original timestamp automatically assigned by the underlying hardware when the analog-to-digital converter of the target chromatograph triggers sampling due to a hard real-time interrupt; This represents the total number of application layer sampling points within a single observation time window set by the system.

[0093] The above sequence construction process converts the simulated chemical concentration into a strict time-series message with a time dimension attribute in the computer architecture, providing an application-layer data foundation for subsequent time-domain distortion analysis.

[0094] S202, synchronously extract the media access control layer register status to form the underlying clock synchronization deviation sequence. While capturing application layer data, the multi-source data acquisition module, in the background scheduling of the edge computing gateway, sends underlying status diagnostic service messages to the fieldbus node corresponding to the target chromatograph according to the set diagnostic polling cycle. This service message bypasses the chromatograph application layer business data channel and directly accesses the underlying synchronization status interface exposed by the target node's communication controller, media access control layer driver, or distributed clock synchronization unit.

[0095] The underlying synchronization status interface can be a synchronization control register, a driver layer diagnostic object, a synchronization message timestamp buffer, or an equivalent diagnostic variable provided by the fieldbus protocol stack. It is used to characterize at least one or more of the following: master-slave clock phase deviation, synchronization message propagation delay, servo compensation amount, synchronization packet loss status, or node clock calibration status.

[0096] When the specific fieldbus chip does not directly provide an independent synchronization control register field, the system can also obtain an equivalent micro phase compensation value by the driver layer based on the sending timestamp, receiving timestamp, and round-trip delay measurement results of the synchronization message.

[0097] This embodiment selects the micro-phase compensation value and the real-time operating system interrupt latency as input parameters for anomaly monitoring based on their clear physical causal relationship. The micro-phase compensation value directly reflects the network propagation delay jitter between the field device and the master clock at the Ethernet physical layer; while the real-time operating system interrupt latency quantifies the software response lag caused by high-priority task blocking when the microcontroller performs multi-task scheduling.

[0098] These two micro-deviations in the underlying hardware and software will ultimately disrupt the isochronism of the analog-to-digital converter interrupt sampling in the form of physical clock jitter. Therefore, extracting these two parameters can most objectively define the health status of the system's underlying hardware and software.

[0099] The system obtains the micro-phase compensation value of the target node in the current synchronization cycle and the real-time operating system interrupt delay time by parsing the returned register data frame.

[0100] Before performing combined calculations, the system first performs unit normalization and sign normalization on the two parameters mentioned above. Unit normalization refers to converting the microscopic phase compensation value and the real-time operating system interrupt delay time into nanoseconds, microseconds, or other equivalent time units.

[0101] Sign normalization refers to converting two parameters into an equivalent time offset with a unified physical direction according to the rule that the actual sampling time is positive when it lags behind the ideal sampling time and negative when it is ahead.

[0102] After completing unit normalization and sign normalization, the system synthesizes the two equivalent time offsets to obtain the transient time deviation within the current diagnostic cycle. This transient time deviation characterizes the incremental time base offset of the target node within the current synchronization cycle due to network propagation jitter, synchronization phase calibration errors, or lag in real-time operating system interrupt response. For the specific addressing addresses and message frame structures of the synchronization control registers in the standard industrial fieldbus specification, those skilled in the art can consult the corresponding bus communication control standard documents.

[0103] The multi-source data acquisition module serializes and reassembles the transient time deviations and their corresponding reading times obtained through continuous polling to generate a low-level clock synchronization deviation sequence for recording the underlying communication health status of computer nodes. Its structure is as follows:

[0104] ;

[0105] in, This represents the underlying clock synchronization deviation sequence; This represents the global index number of the underlying diagnostic data acquisition, and its value range is... ~ ; Indicates at index The newly added equivalent transient time deviation within the diagnostic polling period is used to characterize the newly added time base offset component of the target node relative to the ideal sampling time base within the diagnostic period. This indicates that the edge computing gateway is performing the first... The global receive absolute timestamp when reading the underlying synchronization status parameters during the next polling; This indicates the total number of low-level diagnostic reads within the same set observation time window.

[0106] in, It is calculated from the synchronization control state parameters and the real-time operating system interrupt response state. In the calculation... Previously, the system first converted the micro-phase compensation value and the real-time operating system interrupt delay time to the same time unit, and then normalized the sign according to the rule that lag of the actual sampling time relative to the ideal sampling time is positive and advance is negative; then, the normalized underlying time deviation parameters were synthesized into .

[0107] It should be noted that, This represents the newly added time base offset component within the current diagnostic period, not the cumulative total drift up to the current moment; up to The cumulative clock drift at each moment is determined by express.

[0108] Considering the link transmission delay between the edge computing gateway initiating a polling request and receiving a response message, the system records the global absolute timestamp of reception. At that time, compensation and deduction are performed based on the round-trip time (RTT) ranging protocol of the fieldbus to ensure that the timestamp strictly corresponds to the actual physical time when the field register value is generated, thereby ensuring strict timing alignment with the application layer timestamp on a macroscopic operating scale.

[0109] Based on the execution characteristics of the physical hardware, the sampling frequency of the application-layer analog-to-digital converter and the polling frequency of the underlying diagnostic messages can be set independently. This physical mechanism directly results in the total lengths of the two sets of sequences being typically unequal, i.e. .

[0110] After acquiring the heterogeneous sequence data at different frequencies, the multi-source data acquisition module distributes and pushes it to an independent buffer space allocated in the memory of the edge computing gateway. When writing to the buffer space, the system simultaneously saves the global timestamp, data source identifier, and observation window number corresponding to each data point, so that the subsequent cross-layer feature extraction module can perform windowing processing on data with different sampling frequencies based on the same physical time base.

[0111] Through the above methods, the system completes the closed-loop acquisition of the front-end data source for computer low-level fault detection.

[0112] After obtaining the aforementioned two sets of heterogeneous pre-monitoring data, the application layer chromatographic messages have the characteristics of large data volume and reflect macroscopic slow-changing physical and chemical processes, while the underlying diagnostic status presents microscopic digital attributes of high-frequency transient fluctuations. If these two types of raw data are directly compared mathematically, the diagnostic logic will fail due to the serious misalignment between the spatiotemporal scale and the data dimension.

[0113] Based on the aforementioned engineering pain points, the cross-layer feature extraction module in this embodiment allocates independent buffer spaces for the two types of sequences in the memory of the edge computing gateway, and performs the following feature dimensionality reduction and scale alignment steps:

[0114] S301 performs application layer feature dimensionality reduction and macroscopic offset difference calculation.

[0115] The core mechanism of chromatographic analysis lies in qualitative analysis through the retention times of different components. Any distortion of the system's time base will ultimately be directly projected as a shift of that retention time on the time axis. Based on this physical correspondence, the cross-layer feature extraction module reads the previously generated application layer chromatographic raw sampling sequence from the memory buffer space.

[0116] In order to extract key temporal distortion features from massive background data, the internal logic unit of the system performs threshold determination and peak finding operation based on baseline noise amplitude on the original sequence, accurately locates the chromatographic peaks of key chemical components, and extracts their corresponding actual retention times.

[0117] The specific judgment threshold is not fixed, but dynamically determined during the system initialization phase by multiplying the noise standard deviation (usually 3 to 5 times) by acquiring a pure carrier gas baseline. This ensures that trace components are not missed, while filtering out high-frequency spikes caused by electrical interference. For algorithms on first-derivative peak finding and baseline smoothing and noise reduction of chromatographic signals, those skilled in the art can refer to relevant chromatographic data processing manuals.

[0118] After obtaining the actual retention time, the system performs a difference operation between it and the baseline retention time pre-loaded in the gateway memory. When no valid chromatographic peak is detected within the current observation time window, the signal-to-noise ratio of the chromatographic peak is lower than the preset threshold, or the key component peaks overlap severely and the actual retention time cannot be reliably extracted, the cross-layer feature extraction module does not perform subsequent dynamic time warping and correlation calculations for that observation window.

[0119] In this case, the system marks the current observation time window as an invalid diagnostic window and uses the diagnostic results of the previous valid observation window according to the preset strategy, or outputs a diagnostic prompt that the feature data is insufficient to the upper-level business system.

[0120] When the number of key components that can be extracted within a single observation time window is less than the preset minimum number, the system can stitch together the effective feature points from multiple consecutive observation time windows to form an extended application layer feature sequence before participating in subsequent phase-locked analysis, so as to ensure that the correlation calculation has a sufficient number of statistical samples.

[0121] As a preferred method, the baseline retention time is not a hard-coded arbitrary constant, but rather a physical baseline parameter determined offline by averaging multiple repeated samples under ideal operating conditions: standard calibration gas calibration and a stable network connection. The mathematical expression for the difference calculation is as follows:

[0122] ;

[0123] in, Indicates the extracted first The macroscopic offset difference values ​​of each key chemical component are arranged sequentially to form the application layer feature sequence. The index number representing the key chemical component extracted, with a value ranging from 1 to... , The total number of target components calibrated within a single analysis cycle; This indicates the peak-finding algorithm used to extract the first peak from the original sampled sequence of layer chromatography. The actual retention timestamps of each component; This indicates the timestamp of the calibration reference retained for this component.

[0124] The aforementioned dimensionality reduction operation removes non-featured baseline background sampling points, reduces the computing power overhead of the edge computing gateway processor, and quantifies the degree of macroscopic distortion of the chemical component's peak time deviating from the absolute time base coordinates.

[0125] S302 performs underlying transient deviation transformation and absolute dimension alignment based on a discrete integral accumulator.

[0126] Compared to the macroscopic differential features at the application layer (scaled in seconds), the transient deviation data recorded in the underlying clock synchronization deviation sequence is typically at the microsecond level. This high-frequency oscillation instantaneous state cannot directly reflect the long-term evolution trend of the system's time base. To eliminate the difference between these two at the physical time scale, the cross-layer feature extraction module incorporates a discrete integral accumulator.

[0127] Before performing the specific discrete integral calculation, considering that extreme congestion in industrial field networks can lead to out-of-order message arrivals and logical inversion of adjacent received timestamps, the system incorporates time monotonicity verification logic before integration accumulation. The integrator only performs the accumulation operation when the current timestamp is greater than the previous timestamp, thereby ensuring the physical continuity and correctness of the accumulated clock drift.

[0128] After monotonicity verification, the discrete integral accumulator performs iterative summation of discrete incremental transient time deviations within a set continuous observation time window, converting them into a cumulative amount characterizing the overall time base drift.

[0129] To avoid repeatedly accumulating absolute phase deviations, the system determines the physical meaning of the underlying synchronization state parameters before performing accumulation. When the underlying synchronization state parameters represent absolute phase deviations, the system first performs differential processing on the absolute phase deviations of adjacent cycles to obtain the new transient deviation increment for the current cycle; when the underlying synchronization state parameters represent periodic compensation increments, the system directly incorporates the compensation increment into the discrete integral accumulator.

[0130] With this processing method, each cumulative clock drift value in the underlying system feature sequence represents the equivalent time base offset that has been accumulated from the start time of the current observation window to the corresponding diagnostic reading time, rather than a repeated superposition of the same absolute deviation.

[0131] The specific data transformation iterative equation is as follows:

[0132] ;

[0133] in, This indicates that the aforementioned index is The target cumulative clock drift value is calculated based on the reading time of the underlying diagnostics. The cumulative values ​​at each reading time are combined in sequence to form the underlying system characteristic sequence. Indicates the previous time (i.e., index is 1) The historical cumulative clock drift value is calculated using the time; in the initial scan period of each observation window, the boundary conditions are strictly set to... .

[0134] This accumulation operation step addresses the engineering characteristics of discrete sampling in industrial settings by superimposing the underlying hardware and software scheduling delays and network jitter deviations on the time axis. Through this operation, the stateless transient phase difference data is reconstructed into a cumulative clock drift value with absolute physical time dimensions.

[0135] After the above processing steps, the macroscopic offset difference values ​​of the underlying system features and the application layer features are aligned in terms of physical dimensions in the memory space. The two feature sequences, which originally exhibited heterogeneous characteristics at different frequencies, are mapped to a unified absolute time coordinate system, thus laying an equivalent mathematical foundation for the subsequent execution of spatial topology optimization and correlation phase-locked analysis by the system kernel.

[0136] After completing the dimensional alignment of the aforementioned cross-layer features, the system retrieves the application layer feature sequence and the underlying system feature sequence in memory. Since these two sets of sequences originate from the chemical analysis cycle and the underlying network polling, respectively, there are objective differences in their array lengths due to physical mechanisms.

[0137] To establish accurate spatiotemporal topological mappings between feature sequences of unequal length, this embodiment employs the Dynamic Time Warping (DTW) algorithm to measure and eliminate temporal misalignments caused by different sampling rates. The timing phase-locked loop analysis module, as the core computational engine, performs the following spatial optimization and correlation calculation steps:

[0138] S401 constructs the cumulative distance matrix using a dynamic time warping algorithm based on a striped time window constraint. The time-series phase-locked loop analysis module allocates a two-dimensional matrix space in memory to record the Euclidean distance and cumulative optimization path between each element point of the two sequences.

[0139] After completing the dimensional alignment of the aforementioned cross-layer features, the system retrieves application-layer feature sequences and underlying system feature sequences, both with lengths greater than zero, in memory. In conventional unconstrained dynamic time warping algorithms, in order to minimize the global distance, the algorithm often incorrectly maps the retained time offset data at the beginning of the application-layer sequence to the clock drift state at the end of the underlying feature sequence. This non-causal cross-cycle mapping, which does not conform to the unidirectional nature of physical time, directly violates the objective law of delay propagation in industrial field networks.

[0140] Based on the aforementioned physical constraints, this embodiment introduces a striped time window constraint mechanism during the two-dimensional matrix optimization process. To prevent addressing overflow or singularity errors at matrix boundaries, this embodiment forcibly sets the cumulative distance of the initial starting point of the matrix to 0 before the spatial state transition, and initializes other out-of-bounds index boundary values ​​to positive infinity. After completing the boundary initialization, the system performs iterative calculations in multidimensional space according to the spatial state transition equation. The specific constraint distance calculation formula is as follows:

[0141] ;

[0142] in, Represents the first feature sequence of the application layer The element and the first element of the underlying system feature sequence elements (i.e., the aforementioned index is ) The cumulative clock drift value calculated at time The shortest cumulative distance required for matching; The absolute Euclidean distance between the two independent elements is expressed by the equation: The calculation process must strictly satisfy the striped time window constraint. This time window constraint can be determined based on the actual retained timestamps corresponding to the application layer feature points, the global received absolute timestamps corresponding to the underlying system feature points, and the time difference between the two under the same physical time base.

[0143] In one implementation, the system can map the application layer feature sequence and the underlying system feature sequence to normalized index coordinates respectively, and then use... Quickly constrain in the form of;

[0144] In another implementation, the system makes a judgment directly based on the physical time difference constraint, that is, it only allows application layer feature points to be matched with underlying system feature points within its physical causal propagation time range.

[0145] This represents the upper limit of the physical time optimization window width set by the system, or the upper limit of the index window width converted from the physical time window. Through this constraint, the system avoids incorrectly mapping the retention time offset of the application layer sequence header to the clock drift state of the lower-level feature sequence tail, thereby preventing non-causal cross-cycle matching that does not conform to the unidirectionality of physical time.

[0146] As a preferred method, window parameters The value is not arbitrarily set, but is dynamically determined based on the physical ratio of the maximum tolerable transmission delay period of the industrial Ethernet to the single sampling period of the chromatography. It is usually taken as the total length of the application layer feature sequence. 5% to 10% (rounded down).

[0147] By introducing this constraint parameter By limiting the search space for time-series alignment to a reasonable physical causal time difference, not only are meaningless cross-cycle mismatches avoided, but the space complexity and cyclic computation load of the edge computing gateway processor are also reduced.

[0148] When the constrained dynamic time warping calculation cannot generate an effective path from the start point to the end point of the matrix under the current window parameters, the system can gradually widen the window parameters according to the preset step size until the maximum physical optimization window allowed by the system is reached.

[0149] If a valid twisted path cannot be generated within the maximum physical optimization window, the system determines that the application layer feature sequence and the underlying system feature sequence within the current observation time window do not meet the conditions for cross-layer phase-locked analysis. In this case, the system does not trigger the timestamp reverse compensation mechanism, but instead outputs a status flag indicating feature matching failure or insufficient diagnostic confidence to avoid performing erroneous compensation when the mapping relationship is unreliable.

[0150] S402, generates a twisted path matrix by backtracking based on the cumulative distance matrix.

[0151] When the state transition equation is iterated to the end coordinates of the matrix, the timing phase-locked loop analysis module triggers the reverse backtracking logic. Starting from the end coordinates of the matrix, the system gradually searches for the predecessor node in the direction of minimum cumulative distance gradient until it has completely backtracked to the starting coordinates of the matrix.

[0152] Throughout the backtracking optimization process, the system sequentially extracts all selected 2D matrix coordinate points and stores them in an independent matrix structure to generate a twisted path matrix. The data structure of this twisted path matrix is ​​characterized by a continuous and monotonic linked list of indexed maps. The core physical significance of generating this matrix lies in its objective recording in computer memory of the spatiotemporal topological mapping relationship between application-layer data points experiencing macroscopic chemical timing distortions and the underlying cumulative clock drift data points that directly caused these distortions. This provides a precise data index association table for subsequent underlying reverse fault-tolerant compensation.

[0153] S403, sequence alignment is performed based on the twisted path matrix, and the phase-locked correlation coefficient is calculated. By referring to the aforementioned generated twisted path matrix, the timing phase-locked analysis module performs element copying, compression, or stretching resampling on the application layer feature sequences and the underlying system feature sequences of unequal lengths, generating two synchronously aligned sequences of completely equal length, which are physically phase aligned. These are denoted here as sequences S403 and S404 respectively. and sequence .

[0154] After completing the sequence synchronization alignment, in order to accurately quantify the linear coupling degree between cross-layer physical quantities, the system calls the floating-point arithmetic unit of the edge computing gateway processor to calculate the coupling degree of these two synchronized alignment sequences in the time domain based on the mathematical statistics principle of Pearson correlation coefficient.

[0155] Before performing correlation calculations, the system first determines whether the total number of mapping nodes given by the twisted path matrix is ​​greater than the preset minimum sample size. If the number of mapping nodes is too small, causing the correlation calculation to lack stable statistical significance, the system pauses the correlation determination for the current observation time window and marks the current window as a window with insufficient sample size.

[0156] In a preferred embodiment, the system can stitch together the distortion path results of multiple consecutive effective observation windows to form a synchronous alignment sequence that meets the minimum sample number requirement, and then perform phase-locked correlation coefficient calculation.

[0157] The specific formula for calculating the phase-locked correlation coefficient is as follows:

[0158] ;

[0159] in, This represents the calculated phase-locked correlation coefficient, whose output value range is strictly distributed within a closed interval of −1 to 1; This represents the total number of mapped nodes given by the twisted path matrix, which is the total length of the sequence after resampling and alignment. and These represent the first and second digits of the aligned synchronous alignment sequence, respectively. The numerical value of each sequence element; and These represent the arithmetic mean of the two synchronized alignment sequences within the current full observation window; This represents a small, zero-preventing positive real constant hard-coded into the denominator term; in this embodiment, its typical value is 10. -6 .

[0160] In this correlation calculation, the numerator uses a covariance model to quantify the co-variance trend between chemical time-series shift and underlying network jitter; the denominator normalizes the co-variance result by calculating the product of the standard deviations of the two.

[0161] In real-world industrial environments, when both the system communication network and chemical analysis conditions are in a stable and healthy state, all elements of both characteristic sequences tend to have a constant mean without fluctuations. In this case, the calculated standard deviation will approach zero. Staticly setting a zero-prevention constant in the formula's denominator effectively prevents the processor from performing illegal division-by-zero operations under stable conditions. This ensures that the control gateway does not trigger arithmetic overflows or kernel interrupts under any stable input conditions, thus effectively guaranteeing the system robustness of the computer's underlying monitoring and fault-tolerance mechanisms.

[0162] After obtaining the phase-locked correlation coefficient calculated above, the system enters the core stage of low-level fault tolerance and anomaly handling. Typically, chromatographic retention time shifts in industrial settings originate from two distinct physical mechanisms:

[0163] One type is the change in pure chemical process, such as column aging and carrier gas flow rate fluctuations;

[0164] Another type is computer system clock distortion caused by underlying network congestion or real-time operating system scheduling lag. This embodiment achieves precise isolation of these two types of faults through the following steps, and performs low-level seamless fault tolerance for computer system-level time base faults.

[0165] S501 performs hardware and software fault isolation determination based on a correlation threshold. The system has a preset fault isolation determination threshold. .

[0166] As a preferred approach, the threshold value is typically set between 0.75 and 0.85. This threshold is not a fixed constant set subjectively, but rather is generated offline by injecting known high-frequency delay jitter faults into the communication network before the system leaves the factory, recording the correlation coefficient values ​​output by the analyzer multiple times under fault conditions, and calibrating based on the lower limit confidence interval of its statistical distribution.

[0167] In the complex electromagnetic environment of industrial sites, sudden interference can easily lead to outliers in single mathematical feature extractions. To avoid biased judgments due to relying solely on a single statistical indicator, this embodiment introduces a two-dimensional verification logic that incorporates physical dead zones when performing anomaly detection. The system not only calculates the outliers in real time... With preset In addition to comparative logical operations, the maximum fluctuation of the cumulative clock drift value is extracted from the aforementioned generated underlying system characteristic sequence as an extreme value. It is then monitored whether this extreme value of the cumulative clock drift within the current observation window exceeds the natural temperature drift dead zone allowed by the hardware crystal oscillator. This natural temperature drift dead zone is the theoretical maximum drift time constant calculated by multiplying the PPM temperature drift error limit specified in the datasheet of the target chromatograph's local hardware oscillation source or distributed clock synchronization unit by the total duration of the current observation window.

[0168] It should be noted that although the target chromatograph establishes a unified physical time base through a fieldbus distributed clock protocol, its underlying hardware still relies on a local oscillator to generate the basic clock signal. Therefore, the local hardware oscillator is allowed to have device-level natural temperature drift within the distributed clock calibration range. The system uses the theoretical maximum drift corresponding to this natural temperature drift as a physical dead zone to distinguish between normal device-level clock fluctuations and system-level time base distortion caused by abnormal network synchronization failures or task scheduling blockages.

[0169] When the judgment result is Furthermore, when the cumulative drift extreme value of the underlying clock within the current observation window exceeds the natural temperature drift dead zone, it signifies a highly coordinated change between the macroscopic timing offset of the application layer and the underlying network communication jitter or operating system scheduling blockage, and this underlying drift has exceeded the range that normal hardware temperature drift can explain. Based on this, the system confirms that the current occurrence is a computer system-level fault caused by underlying hardware and software time base disorder, and subsequently triggers a timestamp reverse compensation fault tolerance mechanism.

[0170] when If this occurs, it indicates that there is no sufficiently strong lock-on relationship between the macroscopic retention time offset of the application layer and the underlying clock drift. The system tends to determine that the anomaly originates from column aging, changes in carrier gas flow rate, temperature control fluctuations, or other external physicochemical process factors.

[0171] when However, when the cumulative drift extreme value of the underlying clock does not break through the natural temperature drift dead zone, the system believes that although there is a certain synchronous change trend between the two types of features, the underlying drift amplitude is still within the normal fluctuation range of the hardware, and the timestamp reverse compensation mechanism is not triggered.

[0172] Therefore, the system only determines that the underlying computer hardware and software is abnormal when both the correlation condition and the physical drift amplitude condition are met; otherwise, the edge computing gateway only sends process deviation alarms or clock fluctuation prompts to the upper-layer business system without interfering with the time base of the original sampled data.

[0173] S502 performs reverse timestamp compensation based on the twisted path matrix and linear interpolation algorithm.

[0174] After confirming the fault tolerance mechanism is triggered, the system kernel needs to process the raw chromatographic sampling sequence of the application layer. Each original timestamp in the system undergoes error stripping. Based on the principle of spatial mapping, the system consults the previously generated distorted path matrix to obtain the discrete mapping relationship between the underlying clock's accumulated drift value and the application layer's macroscopic time axis.

[0175] The twisted path matrix mainly records the mapping relationship between key feature points in the application layer and feature points in the underlying system, and therefore corresponds to a finite number of discrete feature points. In order to apply this discrete mapping relationship to all high-frequency sampling points in the original chromatographic sampling sequence of the application layer, the system further constructs a continuous or piecewise continuous compensation function based on the actual retention timestamps corresponding to each key feature point and the underlying cumulative clock drift value obtained by mapping them.

[0176] This compensation function characterizes the equivalent time base offset that should be subtracted at any original sampling time. In this way, the system achieves an expanded mapping of compensation amounts from a small number of key chromatographic peak feature points to the full spectrum of original sampling points.

[0177] Considering that the number of original full-spectrum sampling points is much larger than the number of feature points extracted by peak finding, if step-type discrete compensation values ​​are directly used to crudely subtract sampling points in adjacent intervals, it will severely disrupt the continuity of the chromatographic simulation signal in the time domain, resulting in a large number of unnatural singularities in the first derivative of the reconstructed signal waveform.

[0178] Based on the technical consideration of ensuring the integrity of the physical form of the data, this embodiment adopts a piecewise linear interpolation algorithm before compensation calculation to smoothly map the discrete cumulative drift values ​​at a finite number of feature points to each high-frequency original sampling time.

[0179] For the original sampling points located before the first mapped feature point, the system can use the compensation amount corresponding to the first mapped feature point to maintain the endpoints, or it can perform finite extrapolation based on the first linear slope. For the original sampling points located after the last mapped feature point, the system can use the compensation amount corresponding to the last mapped feature point to maintain the endpoints, or it can perform finite extrapolation based on the last linear slope.

[0180] After completing point-by-point compensation, the system further performs timestamp monotonicity verification. If adjacent compensated timestamps are inverted or the interval is less than the minimum sampling interval allowed by the hardware, the system performs monotonicity correction on subsequent compensated timestamps according to the minimum sampling interval constraint to ensure that the output fault-tolerant application layer sampling sequence still meets the time axis continuity and monotonicity required for chromatographic data processing.

[0181] For specific function expansion forms of piecewise linear interpolation algorithms, endpoint preservation, and finite extrapolation, those skilled in the art can consult numerical analysis manuals.

[0182] After the above interpolation mapping process, the system calls the arithmetic logic unit to traverse the original sequence and perform point-by-point reverse compensation operations. The core calculation formula is as follows:

[0183] ;

[0184] in, The aforementioned first The actual physical timestamps obtained from each sampling point after undergoing underlying fault tolerance compensation; This indicates that, based on the twisted path matrix and after piecewise linear interpolation, it is precisely aligned to the aforementioned global index. The transient clock drift compensation component of the original sampling point.

[0185] This step uses mathematical inverse operations to eliminate spurious system delays added to application layer messages due to Ethernet transmission latency and microcontroller interruption blocking.

[0186] S503, assemble fault-tolerant chromatographic sequences and restore high-level operations.

[0187] After point-by-point reverse compensation calculation, the multi-source data acquisition module of the edge computing gateway re-binds the cleaned newly generated timestamp with the original voltage amplitude cached in memory to generate a fault-tolerant application layer sampling sequence, the mathematical expression of which is as follows:

[0188] ;

[0189] in, This indicates a pure fault-tolerant chromatographic sequence after the underlying clock synchronization error has been processed.

[0190] The reconstruction process, without altering the internal hardware circuitry of the target chromatograph or discarding historically collected data, relied on the software reverse compensation logic on the edge computing gateway side to repair the system-level data error caused by the failure of distributed clock synchronization.

[0191] Through the above mechanism, the system shields upper-layer business applications from the transient failure states of the underlying hardware and software, thus achieving the data fault tolerance goal of the industrial control system.

[0192] It should be noted that the timestamp reverse compensation mechanism in this embodiment is mainly used to correct application-layer chromatographic data time axis errors caused by distributed clock synchronization errors, network congestion, synchronization message jitter, or real-time operating system interruptions. This mechanism does not change the chromatographic signal amplitude of the original sampling point, nor is it used to correct amplitude distortion caused by sensor failure, simulation front-end failure, column damage, abnormal carrier gas components, or abnormal chemical reaction processes.

[0193] When the system determines that the anomaly originates from an external physical or chemical process rather than an underlying hardware or software time base anomaly, the edge computing gateway only outputs a process anomaly alarm or diagnostic prompt, without performing timestamp reverse compensation. This avoids misinterpreting actual process changes as underlying computer clock failures, thereby improving the reliability of system fault isolation.

[0194] Specific application example: Online chromatographic diagnostics and fault compensation for natural gas in a petrochemical plant.

[0195] Application scenario background:

[0196] A high-precision gas chromatograph was deployed at a natural gas pipeline monitoring node in a large petrochemical plant to detect the concentrations of methane (critical component 1) and ethane (critical component 2) in the pipeline in real time. The analyzer is connected to a fieldbus (TSN network) based on the IEEE 1588 protocol and is in the same distributed clock synchronization domain as the edge computing gateway. Under normal operating conditions, the reference retention time for standard calibration gas calibration is: methane... ethane The natural temperature drift dead zone calibration of the hardware oscillator is as follows: .

[0197] Abnormal operating condition triggering and data acquisition (S101, S201-S202):

[0198] During a certain observation window, a sudden large-scale video surveillance data stream occurred at the industrial site, causing severe congestion on the Ethernet link. This congestion triggered high-frequency jitter in the distributed clock synchronization messages, and simultaneously caused high-priority task scheduling blockage in the underlying real-time operating system (RTOS) of the target chromatography analyzer.

[0199] Application Layer Data Acquisition: The edge computing gateway captured raw application layer chromatographic sampling sequences with distorted timestamps based on hardware interrupts. Due to the delayed interrupt response, the sampling that should have been triggered at 60.00s was delayed and timestamped.

[0200] Low-level state acquisition: The diagnostic service synchronously extracted the low-level clock synchronization deviation sequence by polling at a frequency of 10Hz. .

[0201] Cross-layer feature extraction and dimensional alignment (S102, S301-S302):

[0202] Application-layer feature dimensionality reduction (S301): System pair The peak search was performed, and the actual peak timestamp of methane was found. ethane .

[0203] Calculate the macroscopic offset difference: The chromatographic peaks appear to drift to the right as a whole.

[0204] Underlying absolute dimension alignment (S302): After the discrete integral accumulator performs monotonicity verification, it aligns the microsecond-level increments. Execute iterative equations .

[0205] Calculation results show that as network congestion intensifies, cumulative clock drift increases. It climbs rapidly between 40 and 100 seconds, reaching its maximum cumulative drift extreme value. (i.e., 800ms).

[0206] Dynamic time warping and correlation analysis (S103, S401-S403):

[0207] The system uses window constraints (Set to 5% of the chromatographic cycle) Execute the DTW algorithm to generate a twisted path matrix.

[0208] After resampling and alignment, the system calculates the phase-locked correlation coefficient between the macroscopic offset difference sequence (sequence A') and the cumulative clock drift sequence (sequence B'). :

[0209] ;

[0210] Calculation .

[0211] Fault isolation determination (S104, S501):

[0212] The system retrieves the preset isolation threshold. .

[0213] Decision logic: Current They exhibit a high positive correlation; and the bottom-level drift extreme values (Breaking through the dead zone of natural temperature drift in hardware).

[0214] Diagnostic conclusion: The current retention time drift is not caused by column aging or carrier gas fluctuations (abnormal physicochemical process), but is clearly a timing distortion caused by network congestion at the underlying computer system level.

[0215] Timestamp Reverse Compensation and Service Recovery (S105, S502-S503):

[0216] The system triggers a fault-tolerance mechanism, consults the distorted path matrix, and uses piecewise linear interpolation to discretely transform the path. Mapped to the compensation components corresponding to high-frequency sampling points .

[0217] Perform the inverse arithmetic operation: For example, at the moment of ethane elution, the timestamp is distorted. The table lookup and interpolation yielded the accumulated latency of the underlying system at that moment, which was exactly [value missing]. After compensation, the timestamp was reconstructed. .

[0218] Finally, a pure, fault-tolerant chromatographic sequence was generated. Then, upload it to the higher-level monitoring system.

[0219] Experimental verification and effect comparison:

[0220] To verify the effectiveness and data security of the algorithm in an industrial environment, we compared the chromatogram parsing results of three sets of conditions: ideal no-jitter operation, severe network congestion operation (without compensation), and fault-tolerant reconstruction operation in this embodiment.

[0221] methane retention time 60.00s 60.55s (Seriously out of tolerance) 60.01s (recovery time, relative error 0.01%) Ethane retention time 120.00s 120.78s (Severely out of tolerance) 120.02s (recovery, relative error 0.01%) Chromatographic peak voltage amplitude 0.850V 0.850V 0.850V Peak area integral value 3.421 V·s 3.421 V·s 3.421 V·s System alarm status normal False alarm: Abnormal process composition Normally, underlying IT faults are shielded, and the upper layers are unaware of them.

[0222] Conclusion:

[0223] Observation Appendix Figure 3 (a) with appendix Figure 3 (b) shows the temporal mapping relationship, and the appendix... Figure 3 (a) The discrete integral accumulator at the bottom layer objectively and continuously records the clock accumulation drift phenomenon caused by network congestion (showing a clear linear rise in the 40s to 100s interval of the physical reference axis). This microscopic bottom-layer communication delay directly leads to a macroscopic pseudo-drift of the applied layer chromatographic peak in Figure (b) (as shown by the curve, the methane peak shows a small pseudo-drift). The ethane peak, being in the later stage of the delay accumulation, exhibited a more pronounced pseudo-drift. The highly coordinated evolutionary trend exhibited by both at the time axis and at the distortion level directly confirms the effectiveness of this invention in utilizing dynamic time warping and correlation analysis (calculating phase-locked correlation coefficients). It can accurately identify and isolate anomalies in the underlying IT network and fluctuations in external physical and chemical processes.

[0224] Comparison Appendix Figure 3 (b) and appendix Figure 3 (c) It is evident that the distorted timestamp sequence without system fault tolerance processing exhibits severe retention time errors. If directly uploaded, it can easily trigger process alarms in the monitoring system or even lead to sample rejection. However, when the core reconstruction calculation of this invention is applied... After that, the system outputs the fault-tolerant sequence. (Appendix) Figure 3 (c) Perfect regression in the time domain coordinates, and retention time with the ideal baseline (see appendix). Figure 3 (c) A seamless overlap was achieved. This indicates that the system's piecewise linear interpolation compensation strategy, based on the twisted path matrix generation, successfully and accurately removed the spurious network jitter attached to the original message timeline.

[0225] Observation Appendix Figure 3 (b) and appendix Figure 3As can be seen from the ordinate of (c), regardless of the distortion and reconstruction in the time domain, the voltage amplitude characteristics (peak height, peak width, and peak area) of the chromatographic signal remain consistent. This strongly demonstrates that the fault-tolerance mechanism of this invention only performs mathematical inverse mapping and correction on the horizontal axis timestamp in the message structure, without filtering, masking, or tampering with the amplitude of the analog signal representing the actual chemical component concentration throughout the entire process. This characteristic ensures the physical legitimacy of industrial field metrological-level test data, achieving a system-level high-reliability fault-tolerance goal of shielding computer time base faults at the lower level and ensuring that upper-level business operations are completely unaware of them, without interfering with the operation of any chromatographic sensor hardware.

Claims

1. A method for chromatographic diagnostics based on multi-source analyzer time series data, characterized by, The method includes the following steps: The application layer chromatography raw sampling sequence of the target chromatographic analyzer and the underlying clock synchronization deviation sequence of the fieldbus node corresponding to the target chromatographic analyzer are collected synchronously. Cross-layer feature extraction is performed on the original chromatographic sampling sequence of the application layer and the clock synchronization deviation sequence of the bottom layer to generate application layer feature sequences and bottom system feature sequences aligned with physical time scales, respectively. Dynamic time warping calculation with striped time window constraints is performed on the application layer feature sequence and the underlying system feature sequence to generate a twisted path matrix that records the temporal mapping relationship. The phase-locked correlation coefficient between the application layer feature sequence and the underlying system feature sequence is calculated based on the twisted path matrix. The width of the striped time window is 5% to 10% of the total length of the application layer feature sequence. By combining the phase-locked correlation coefficient, the preset judgment threshold, and whether the extreme value of the cumulative clock drift value exceeds the hardware natural temperature drift dead zone, it is determined whether the target chromatograph has experienced a low-level hardware or software abnormality. The judgment threshold of the phase-locked correlation coefficient is 0.75 to 0.85, and the natural temperature drift dead zone is the maximum time offset interval corresponding to the normal temperature drift of the hardware clock device of the chromatograph. When an underlying hardware or software anomaly is detected, the distorted original timestamps in the original sampling sequence of the application layer chromatography are compensated in reverse order based on the time-series mapping relationship recorded in the distorted path matrix.

2. The method of claim 1, wherein, The steps of synchronously acquiring the application layer chromatography raw sampling sequence of the target chromatographic analyzer and the underlying clock synchronization deviation sequence of the fieldbus node corresponding to the target chromatographic analyzer specifically include: The hard real-time interrupt signal generated by the distributed clock synchronization protocol based on the fieldbus drives the analog-to-digital converter of the target chromatograph to perform discrete sampling and binds to generate the application layer chromatographic raw sampling sequence with the original timestamp; synchronously reads the synchronization control register of the fieldbus node to obtain the micro phase compensation value and the real-time operating system interrupt delay time, and after normalizing the micro phase compensation value and the real-time operating system interrupt delay time to the unit and sign, synthesizes the transient time deviation within the current diagnostic cycle to form the underlying clock synchronization deviation sequence.

3. The method of claim 1, wherein the method further comprises: The steps of generating application-layer feature sequences and underlying system feature sequences aligned to physical time scales specifically include: Peak detection is performed on the original sampled sequence of the applied layer chromatography, the actual retention time of key components in the original sampled sequence of the applied layer chromatography is extracted, and the macroscopic offset difference between the actual retention time and the reference retention time is calculated. The applied layer feature sequence is composed of each macroscopic offset difference. Within a set time window, the underlying clock synchronization deviation sequence is discretely integrated and accumulated to convert the incremental transient time deviation into the accumulated clock drift value, thus forming the underlying system characteristic sequence.

4. The method of claim 3, wherein the method further comprises: The step of generating a twisted path matrix for recording time-series mapping relationships, and calculating the phase-locked correlation coefficient between the application layer feature sequence and the underlying system feature sequence based on the twisted path matrix, specifically includes: Within a band-shaped time window constraint with a width of 5% to 10% of the total length of the application layer feature sequence, calculate the cumulative distance matrix between the application layer feature sequence and the underlying system feature sequence; By backtracking and optimizing the cumulative distance matrix, the twisted path matrix is ​​generated. The path coordinates of the twisted path matrix record the alignment relationship in time phase between the macroscopic offset difference value in the application layer feature sequence and the cumulative clock drift value in the underlying system feature sequence. By consulting the twisted path matrix, two synchronous alignment sequences of equal length and physically aligned are generated, and the ratio of the product of their covariance and their respective standard deviations is calculated. This ratio is then used as the phase-locked correlation coefficient.

5. The chromatographic diagnostic method based on time-series data from a multi-source analyzer according to claim 4, characterized in that, The step of determining whether the target chromatograph has experienced a low-level hardware or software malfunction, based on the phase-locked correlation coefficient, the preset judgment threshold, and whether the extreme value of the accumulated clock drift exceeds the hardware's natural temperature drift dead zone, specifically includes: The phase-locked correlation coefficient is compared with a preset judgment threshold, and the extreme value of the cumulative clock drift value in the current observation window is monitored to see if it exceeds the natural temperature drift dead zone. The judgment threshold is 0.75 to 0.85, and the natural temperature drift dead zone is the maximum time offset interval corresponding to the normal temperature drift of the hardware clock device of the chromatograph. If the phase-locked correlation coefficient is greater than or equal to the judgment threshold, and the extreme value of the accumulated clock drift exceeds the natural temperature drift dead zone, then the target chromatograph is judged to have a low-level hardware or software abnormality. When diagnosing underlying hardware and software anomalies, the discrete mapping relationship between key feature points and underlying cumulative clock drift values ​​is determined based on the twisted path matrix. A piecewise linear interpolation algorithm is then used to extend this discrete mapping relationship to all original sampling points of the application layer chromatography original sampling sequence. Subtract the corresponding target cumulative clock drift value from the original timestamp of each original sampling point to obtain the physical reference timestamp after reverse compensation.

6. A chromatographic diagnostic system based on time-series data from a multi-source analyzer, characterized in that, The system is used to perform a chromatographic diagnostic method based on multi-source analyzer time-series data as described in any one of claims 1-5, the system comprising: The multi-source data acquisition module is used to synchronously acquire the application layer chromatography raw sampling sequence of the target chromatograph and the underlying clock synchronization deviation sequence of the fieldbus node corresponding to the target chromatograph. The cross-layer feature extraction module is used to perform cross-layer feature extraction on the application layer chromatographic raw sampling sequence and the bottom layer clock synchronization deviation sequence, respectively generating application layer feature sequences and bottom layer system feature sequences aligned with physical time scales. The timing phase-locked analysis module is used to perform dynamic time warping calculations with striped time window constraints on the application layer feature sequence and the underlying system feature sequence, generate a twisted path matrix that records the timing mapping relationship, and calculate the phase-locked correlation coefficient between the application layer feature sequence and the underlying system feature sequence based on the twisted path matrix, wherein the width of the striped time window is 5% to 10% of the total length of the application layer feature sequence; The diagnosis and compensation module is used to determine whether the target chromatograph has experienced a low-level hardware or software malfunction by combining the phase-locked correlation coefficient, a preset judgment threshold, and whether the extreme value of the accumulated clock drift exceeds the hardware natural temperature drift dead zone. When the low-level hardware or software malfunction is determined to have occurred, the module performs reverse timestamp compensation on the distorted original timestamps in the original sampling sequence of the application layer chromatography based on the time-series mapping relationship recorded in the distorted path matrix. The judgment threshold for the phase-locked correlation coefficient is set to 0.75 to 0.85, and the natural temperature drift dead zone is the maximum time offset interval corresponding to the normal temperature drift of the chromatograph's hardware clock device.

7. A chromatographic diagnostic system based on time-series data from a multi-source analyzer according to claim 6, characterized in that, The system is deployed on an edge computing gateway; The multi-source data acquisition module is equipped with a hardware interrupt monitoring unit. The hardware interrupt monitoring unit is used to capture the hard real-time interrupt signal generated when the distributed clock of the fieldbus triggers the analog-to-digital converter, and bind it to generate the application layer chromatography raw sampling sequence carrying the original timestamp.

8. A chromatographic diagnostic system based on time-series data from a multi-source analyzer according to claim 7, characterized in that, The cross-layer feature extraction module allocates independent buffer space in the memory of the edge computing gateway for the application layer chromatographic raw sampling sequence and the bottom layer clock synchronization deviation sequence. The cross-layer feature extraction module is equipped with a discrete integral accumulator. The discrete integral accumulator is used to convert the incremental transient time deviation in the underlying clock synchronization deviation sequence into a cumulative clock drift value, thereby achieving consistent alignment between the absolute physical time dimension of the underlying system feature sequence in the memory space and the macroscopic offset difference value of the application layer feature sequence.

9. A chromatographic diagnostic system based on time-series data from a multi-source analyzer according to claim 6, characterized in that, The diagnosis and compensation module is configured with a two-dimensional fault isolation logic based on a judgment threshold and a natural temperature drift dead zone. The judgment threshold is 0.75 to 0.85, and the natural temperature drift dead zone is the maximum time offset interval corresponding to the normal temperature drift of the hardware clock device of the chromatograph. When the phase-locked correlation coefficient is less than the judgment threshold, the abnormality is judged to originate from an external physicochemical process, and a process deviation alarm is sent to the upper-level business system. When the phase-locked correlation coefficient is greater than or equal to the judgment threshold and the extreme value of the cumulative drift of the underlying clock does not exceed the natural temperature drift dead zone, the timestamp reverse compensation mechanism is not triggered. When the phase-locked correlation coefficient is greater than or equal to the judgment threshold and the extreme value of the cumulative drift of the underlying clock exceeds the natural temperature drift dead zone, an underlying hardware or software anomaly is determined to have occurred, and timestamp reverse compensation is triggered.

10. A chromatographic diagnostic system based on time-series data from a multi-source analyzer according to claim 7, characterized in that, The diagnosis and compensation module interfaces with the output terminal of the edge computing gateway communication protocol stack; Within the output buffer of the edge computing gateway, the original timestamp of the application layer chromatography data packet is replaced with the physical reference timestamp obtained by subtracting the target cumulative clock drift value from the original timestamp. The target cumulative clock drift value is obtained by mapping the twisted path matrix and combining it with piecewise linear interpolation; The message with the replaced timestamp is repackaged into a chromatography data message that eliminates timing jitter errors and output to the upper-level monitoring system.

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