Thin film resistor and method of manufacturing the same

Abstract

The present application provides a thin film resistor and a manufacturing method thereof. The method includes forming an insulating oxide film on the upper surface of a substrate; forming a first inner electrode pair on both ends of the insulating oxide film; performing a direct current multi-target mixed sputtering operation to deposit a resistance layer on part of the insulating oxide film and part of the first inner electrode pair; performing a radio frequency-direct current mixed sputtering operation to deposit a doped layer on the resistance layer; performing an annealing operation to make the doped layer form an oxidized doped thin film; and forming a passivation layer on the oxidized doped thin film. Thus, the resistance value and resistivity of the thin film resistor can be controlled.

Description

Technical Field

[0001] This invention relates to a thin-film resistor and a method for manufacturing the same, and more particularly to a thin-film resistor and a method for manufacturing the same by forming a resistive layer using a DC multi-target hybrid sputtering operation. Background Technology

[0002] In existing thin-film resistors, the resistive layer is formed by sputtering a single alloy target. Therefore, the material composition of the target determines most of the resistance characteristics. The temperature-dependent resistivity of the sputtered resistive layer can be adjusted using high-temperature annealing. However, the resistivity of the resistive layer is limited by the target material. Therefore, to increase the resistance value, the only option is to adjust the thin film pattern. The pattern adjustment is limited by the adjustable area. Thus, to achieve a higher resistance value in existing thin-film resistors, the target material must be changed. If the target material does not have a higher resistivity, the thin-film resistor cannot achieve a higher resistance value.

[0003] In view of this, there is an urgent need to provide a thin-film resistor and its manufacturing method to adjust the resistance value of the thin-film resistor. Summary of the Invention

[0004] One aspect of the present invention is to provide a method for manufacturing a thin-film resistor, which involves using a DC multi-target hybrid sputtering operation to deposit a resistive layer containing different metals, thereby achieving the effect of controlling the resistance value of the thin-film resistor.

[0005] Another aspect of the present invention is to provide a thin-film resistor, which is prepared using the above-described method.

[0006] According to one aspect of the present invention, a method for manufacturing a thin-film resistor is provided. This method includes forming an insulating oxide film on the upper surface of a substrate; forming a first internal electrode pair on both ends of the insulating oxide film; performing a DC multi-target hybrid sputtering operation to deposit a resistive layer on portions of the insulating oxide film and the first internal electrode pair, wherein the DC multi-target hybrid sputtering operation includes sputtering a nickel-chromium alloy, tantalum metal, and molybdenum metal; performing a radio frequency-DC hybrid sputtering operation to deposit a doped layer on the resistive layer, wherein the radio frequency-DC hybrid sputtering operation includes radio frequency sputtering of silicon and DC sputtering of aluminum; performing an annealing operation to form an oxide-doped thin film; and forming a passivation layer on the oxide-doped thin film.

[0007] According to an embodiment of the present invention, the above-described operation of forming an insulating oxide film includes: forming a sputtered layer on a substrate, wherein the sputtered layer comprises tantalum or silicon; and sintering the sputtered layer to form an insulating oxide film, wherein the insulating oxide film comprises tantalum oxide or silicon oxide.

[0008] According to one embodiment of the present invention, in the above-mentioned DC multi-target hybrid sputtering operation, the sputtering power of tantalum metal is 60% to 100% of the sputtering power of nickel-chromium alloy, and the sputtering power of molybdenum metal is 5% to 30% of the sputtering power of nickel-chromium alloy.

[0009] According to one embodiment of the present invention, in the above-described RF-DC hybrid sputtering operation, the sputtering power of aluminum is 20% to 50% of the sputtering power of silicon.

[0010] According to one embodiment of the present invention, based on a resistive layer weight of 100wt%, the resistive layer comprises 45wt% to 75wt% nickel-chromium alloy; 20wt% to 40wt% tantalum; and 5wt% to 15wt% molybdenum.

[0011] According to one embodiment of the present invention, the weight ratio of aluminum to silicon in the doped layer is 1:1 to 1:5.

[0012] According to an embodiment of the present invention, the method further includes forming a first insulating protective layer on a passivation layer; and forming a second inner electrode pair on both ends of an insulating oxide film, covering portions of the first inner electrode pair and the first insulating protective layer.

[0013] According to an embodiment of the present invention, the method further includes forming a second insulating protective layer on the exposed portion of the first insulating protective layer and the portion of the second inner electrode pair.

[0014] According to an embodiment of the present invention, the method further includes forming a back electrode pair at both ends of the lower surface of the substrate; and forming an outer electrode pair extending from the second insulating protective layer along both sides of the substrate to connect the back electrode pair.

[0015] According to another aspect of the present invention, a thin-film resistor is provided, which is prepared by the above-described method.

[0016] The thin-film resistor and its manufacturing method of the present invention deposit a resistor layer containing different metals by means of DC multi-target hybrid sputtering operation, and deposit a doped layer on the resistor layer by means of radio frequency-DC hybrid sputtering operation, so as to achieve the effect of controlling the resistance value and resistivity of the thin-film resistor. Attached Figure Description

[0017] A better understanding of the present invention will be obtained by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, as is standard practice in the industry, many features are not drawn to scale. In fact, for clarity of discussion, the dimensions of many features may be arbitrarily scaled.

[0018] Figure 1 A cross-sectional view is provided to illustrate a thin-film resistor according to some embodiments of the present invention.

[0019] Figures 2A to 2I A top view illustrating an intermediate stage of the manufacturing process of a thin-film resistor according to some embodiments of the present invention.

[0020] Figure 3 This is a graph showing the relationship between the temperature resistivity of a thin-film resistor and the annealing temperature according to some embodiments of the present invention. Detailed Implementation

[0021] The following disclosure provides numerous different embodiments or illustrations to implement various features of the invention. The specific examples of components and configurations described below are for the purpose of simplifying the invention. These are, of course, merely illustrative and are not intended to be limiting. For example, a description of a first feature formed on or above a second feature includes embodiments where the first and second features are in direct contact, as well as embodiments where other features are formed between the first and second features such that the first and second features are not in direct contact. Furthermore, the invention repeats element symbols and / or letters in various specific examples. This repetition is for the purpose of simplifying and clarifying the description and does not imply a relationship between the various discussed embodiments and / or configurations.

[0022] Furthermore, spatially relative terms, such as "below," "below," "lower," "above," and "upper," are used to facilitate the description of the relationship between a part or feature depicted in the accompanying drawings and other parts or features. In addition to the directions depicted in the drawings, spatially relative terms also include different orientations of the elements during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptions used in this invention can also be interpreted in this way.

[0023] The manufacture and use of embodiments of the present invention are discussed in detail below. However, it will be understood that the embodiments provide many applicable inventive concepts that can be implemented in a wide variety of specific contexts. The specific embodiments discussed are for illustrative purposes only and are not intended to limit the scope of the invention.

[0024] As used in this invention, “around,” “about,” “approximately,” or “substantially” generally mean within 20 percent, 10 percent, or 5 percent of the stated value or range.

[0025] As described above, the present invention provides a thin film resistor and its manufacturing method, which involves depositing a resistor layer containing different metals using a DC multi-target hybrid sputtering operation, and depositing a doped layer on the resistor layer using a radio frequency-DC hybrid sputtering operation, so as to achieve the effect of controlling the resistance value and resistivity of the thin film resistor.

[0026] Please see Figure 1 This is a cross-sectional view illustrating a thin-film resistor 100 according to some embodiments of the present invention. The thin-film resistor 100 includes a substrate 105. In some embodiments, the material of the substrate 105 may include ceramic materials such as alumina (Al2O3), aluminum nitride (AlN), beryllium oxide (BeO), magnesium oxide (MgO), and alumina-doped zirconium (ZTA), or combinations thereof.

[0027] The thin-film resistor 100 includes an insulating oxide film 110 disposed on the upper surface 105A of the substrate 105. In some specific examples, the insulating oxide film 110 comprises tantalum oxide (Ta2O5) or silicon oxide (SiO2). The insulating oxide film 110 completely covers the upper surface 105A of the substrate 105 to reduce the surface roughness of the substrate 105, thereby increasing the adhesion to the resistor layer 130.

[0028] The thin-film resistor 100 includes a first inner electrode pair 120, a resistive layer 130, an oxide-doped thin film 135, a passivation layer 140, a first insulating protective layer 150, a second inner electrode pair 160, and a second insulating protective layer 170 disposed on an insulating oxide film 110. The first inner electrode pair 120 is disposed at both ends of the insulating oxide film 110. In some embodiments, the material of the first inner electrode pair 120 includes glass, silver, or an electrode paste of silver and palladium, or a combination thereof.

[0029] A resistive layer 130 is disposed on the portion of the insulating oxide film 110 not covered by the first inner electrode pair 120 and on the portion of the first inner electrode pair 120. In some embodiments, based on a resistive layer 130 of 100 wt%, the resistive layer 130 comprises approximately 45 wt% to approximately 75 wt% of a nickel-chromium alloy, approximately 20 wt% to approximately 40 wt% of tantalum, and approximately 5 wt% to approximately 15 wt% of molybdenum. The nickel-chromium alloy is the main component of the resistive layer 130; therefore, the nickel-chromium alloy content within the aforementioned range allows the resistive layer 130 to have a suitable resistance value; the inclusion of tantalum within the aforementioned range allows the resistive layer 130 to have water-resistant properties; and the inclusion of molybdenum within the aforementioned range allows the resistance value of the resistive layer 130 to be adjusted. In some embodiments, the thickness of the resistive layer 130 is approximately 0.02 μm to approximately 0.5 μm. This thickness range allows the resistive layer 130 to have a suitable resistivity.

[0030] An oxide-doped thin film 135 is disposed on the resistive layer 130. In some embodiments, the oxide-doped thin film 135 comprises silicon oxide and aluminum oxide. The silicon oxide and aluminum oxide in the oxide-doped thin film 135 also partially diffuse into the resistive layer 130, thereby adjusting the temperature coefficient of resistance (TCR) and resistivity of the resistive layer 130.

[0031] The passivation layer 140 is configured to completely cover the resistive layer 130. In some embodiments, the passivation layer 140 comprises an insulating material, such as silicon oxide, tantalum oxide, silicon nitride, or a combination thereof.

[0032] A first insulating protective layer 150 is disposed on the passivation layer 140 and on a portion of the first inner electrode pair 120. In some embodiments, the material of the first insulating protective layer 150 comprises resin, epoxy resin, epoxy resin containing inorganic fillers, or a combination thereof.

[0033] The second inner electrode pair 160 is disposed at both ends of the insulating oxide film 110 and covers a portion of the first inner electrode pair 120 and the first insulating protective layer 150. The second inner electrode pair 160 protects the first inner electrode pair 120 from the intrusion of sulfur-containing gases. In some embodiments, the material of the second inner electrode pair 160 comprises epoxy resin and silver.

[0034] The second insulating protective layer 170 is disposed on the portion of the first insulating protective layer 150 not covered by the second inner electrode pair 160 and on the portion of the second inner electrode pair 160. In some embodiments, the material of the second insulating protective layer 170 includes resin, epoxy resin, epoxy resin containing inorganic fillers, or a combination thereof.

[0035] The thin-film resistor 100 further includes a back electrode pair 180 disposed on the lower surface 105B of the substrate 105. In some embodiments, the back electrode pair 180 is disposed at both ends of the lower surface 105B of the substrate 105. In some embodiments, the material of the back electrode pair 180 comprises epoxy resin and silver.

[0036] The thin-film resistor 100 further includes a bonding layer 185 and an external electrode pair 190. The bonding layer 185 is disposed on a side 105C of the substrate 105, and the external electrode pair 190 extends from the second insulating protective layer 170 along the bonding layer 185 to cover the back electrode pair 180. In some embodiments, the bonding layer 185 is made of a nickel-chromium alloy (NiCr). The external electrode pair 190 includes a nickel layer 190A and a tin layer 190B.

[0037] Figures 2A to 2I To illustrate a top view of an intermediate stage of the process of a thin-film resistor 100 according to some embodiments of the present invention, wherein Figures 2A to 2H For the upper surface 105A of the substrate 105 (refer to) Figure 1 A top-down view, and Figure 2I This is a top view taken from the lower surface 105B of the substrate 105. The following utilizes... Figures 2A to 2I Explain the manufacturing process of thin-film resistor 100.

[0038] First, please also refer to Figure 1 and Figure 2A An insulating oxide film 110 is formed on the substrate 105. In some embodiments, the step of forming the insulating oxide film 110 includes first forming a sputtered layer on the substrate 105, and then sintering the sputtered layer to form the insulating oxide film 110. In the foregoing embodiments, the thickness of the sputtered layer is about 0.02 μm to about 0.1 μm, which ensures complete oxidation after sintering. In some specific examples, the sputtered layer contains tantalum (Ta) or silicon (Si), so the insulating oxide film 110 contains tantalum oxide (Ta2O5) or silicon oxide (SiO2). Tantalum oxide and silicon oxide have good affinity for the subsequently formed resistive layer 130.

[0039] Next, first internal electrodes 120A and 120B (collectively referred to as the first internal electrode pair 120) are formed on both ends of the insulating oxide film 110. In some embodiments, the first internal electrode pair 120 is formed by printing and sintering. The substrate 105 has a length L along its long side in the X direction and a width W along its short side in the Y direction, wherein the first internal electrode pair 120 is disposed on both ends of the long side of the substrate 105. The first internal electrodes 120B and 120A each have a length CL along the X direction and a width CW along the Y direction. In some embodiments, the length CL is about 1 / 5 to about 1 / 3 of the length L, and the width CW is about 4 / 5 to about 1 times the width W.

[0040] Please see Figure 2B A masking layer 210A is formed on the periphery of the insulating oxide film 110 and a portion of the first inner electrode pair 120, exposing the area to be plated 210B. In some embodiments, the masking layer 210A is a removable glass ink, and the masking layer 210A can be formed by means of, for example, printing, coating, or lamination. In some embodiments, the length RL of the area to be plated 210B in the X direction is about 1 / 4 to about 3 / 4 times the length L, and the width RW in the Y direction is about 2 / 5 to about 4 / 5 times the width W.

[0041] Next, regarding Figure 2B The surface shown is subjected to a DC multi-target hybrid sputtering operation to deposit a resistive layer 130. In some embodiments, the DC multi-target hybrid sputtering operation includes sputtering a nickel-chromium alloy (NiCr). 44 The gas used in the DC multi-target hybrid sputtering operation is argon, and the pressure in the sputtering chamber is approximately 5 × 10⁻⁶. -3 torr to approximately 8×10 -2In some embodiments, the sputtering power of tantalum metal is about 60% to about 100% of the sputtering power of nickel-chromium alloy, and the sputtering power of molybdenum metal is about 5% to about 30% of the sputtering power of nickel-chromium alloy. With the aforementioned sputtering power, the resulting resistive layer 130 can contain about 45 wt% to about 75 wt% of nickel-chromium alloy, about 20 wt% to about 40 wt% of tantalum, and about 5 wt% to about 15 wt% of molybdenum. As described above, this specific content range allows the resistive layer 130 to have suitable resistivity and water resistance properties.

[0042] In some specific examples, the sputtering power of the nickel-chromium alloy is 0.6 kW, the sputtering power of the tantalum metal is 0.6 kW, and the sputtering power of the molybdenum metal is 0.15 kW; thus, the resulting resistive layer 130 comprises approximately 55 wt% nickel-chromium alloy, 37 wt% tantalum, and 8 wt% molybdenum.

[0043] Then, a radio frequency (RF)-direct current (DC) hybrid sputtering operation is performed to deposit a doped layer on the resistive layer 130. The RF-DC hybrid sputtering operation requires first heating the substrate 105 in a cavity to approximately 150°C to approximately 250°C, a temperature lower than the curing temperature of the glass ink in the mask layer 210A. Next, the RF target and DC target are turned on for sputtering. In some embodiments, the RF-DC hybrid sputtering operation includes RF sputtering of a silicon target and DC sputtering of an aluminum target, wherein the power of the aluminum target is approximately 20% to approximately 50% of the power of the silicon target. In this embodiment, the weight ratio of aluminum to silicon in the doped layer is approximately 1:1 to approximately 1:5. The aforementioned power range and weight ratio of aluminum and silicon contribute to the formation of a doped film with a suitable thickness. In some embodiments, the average thickness of the doped film is approximately 0.005 μm to approximately 0.05 μm, which provides a better doping effect.

[0044] After the doped layer is formed, the masking layer 210A is removed using a chemical solvent or deionized water to expose a portion of the first internal electrode pair 120.

[0045] Please see Figure 2C The doped layer is annealed in an atmospheric high-temperature furnace at a temperature of approximately 300°C to approximately 600°C for approximately 2 to approximately 6 hours. This annealing process allows some of the silicon and aluminum in the doped layer to diffuse into the resistive layer 130, forming silicon oxide (SiO2) and aluminum oxide (Al2O3), and also forming an oxide-doped thin film 135 on the resistive layer 130. Forming the oxide-doped thin film 135 through annealing helps to adjust the temperature resistivity and resistivity of the thin film resistor 100. Figure 3As shown in Figure 300, different annealing temperatures yield different temperature resistivity coefficients. In some specific examples, when the annealing temperature is 450°C and the holding time is 3 hours, the temperature resistivity of the thin film resistor 100 is less than 50 ppm, and the resistivity is 1383 μΩ-cm.

[0046] Next, a resistance adjustment step is performed on the resistive layer 130 and the oxide-doped thin film 135 above it, which can be done using laser or physical processing to adjust the resistance value. After the resistance adjustment step, atmospheric pressure low-temperature heat treatment can be performed to eliminate the thermal effects of physical processing and micro-oxidation at the cross-section of the resistor processing. In some embodiments, the atmospheric pressure low-temperature heat treatment is performed at a temperature of about 200°C to about 350°C and held at that temperature for about 0.5 hours to about 3 hours. In one specific example, after the resistance adjustment step is performed using laser, a heat treatment is performed at a temperature of 270°C for 1.5 hours.

[0047] Please see Figure 2D A mask layer 220A is formed on the periphery of the insulating oxide film 110 and a portion of the first inner electrode pair 120, exposing the passivation region 220B. In some embodiments, the mask layer 220A is a removable ink or photoresist, which can be formed by means of, for example, printing, coating, or lamination. The size of the passivation region 220B must be such that the subsequently formed passivation layer 140 completely covers the resistive layer 130 (and the oxide-doped thin film 135). In some embodiments, the length PL of the passivation region 220B in the X direction is about 3 / 4 to about 4 / 5 times the length L, and the width PW in the Y direction is about 4 / 5 to about 1 times the width W.

[0048] Next, a passivation layer 140 is formed on the oxide-doped thin film 135 and the mask layer 220A. In some embodiments, the passivation layer 140 may be formed by sputtering or chemical vapor deposition. Then, the mask layer 220A is removed using a chemical solvent or deionized water, so that the passivation layer 140 is formed on a portion of the oxide-doped thin film 135 and the first internal electrode pair 120, such as... Figure 2E As shown.

[0049] Please see Figure 2F A first insulating protective layer 150 is formed to cover the passivation layer 140. The first insulating protective layer 150 is used to protect the passivation layer 140 and the first internal electrode pair 120. In some embodiments, the first insulating protective layer 150 is formed by printing or photolithography. In some embodiments, the length G1L of the first insulating protective layer 150 in the X direction is (length L-250) μm to (length L-100) μm, and the width G1W in the Y direction is about 4 / 5 to about 1 times the width W.

[0050] Please see Figure 2G A second inner electrode 160A and a second inner electrode 160B (collectively referred to as the second inner electrode pair 160) are formed on both ends of the insulating oxide film 110, covering portions of the first inner electrode pair 120 and the first insulating protective layer 150. In some embodiments, the second inner electrode pair 160 may be formed by printing. The second inner electrode 160A and the second inner electrode 160B each have a length C2L along the X direction and a width C2W along the Y direction. In some embodiments, the length C2L is about 1 / 4 to about 1 / 3 of the length L, and the width C2W is about 4 / 5 to about 1 times the width W.

[0051] Please see Figure 2H A second insulating protective layer 170 is formed on the first insulating protective layer 150 and the second inner electrode pair 160. The second insulating protective layer 170 is used to protect portions of the first insulating protective layer 150 and the second inner electrode pair 160. In some embodiments, the second insulating protective layer 170 is formed by printing or photolithography. In some embodiments, the length G2L of the second insulating protective layer 170 in the X direction is about 1 / 3 to about 2 / 3 times the length L, and the width G2W in the Y direction is about 4 / 5 to about 1 times the width W.

[0052] Please see Figure 2I Back electrodes 180A and 180B (collectively referred to as back electrode pair 180) are formed on both ends of the lower surface 105B of the substrate 105. In some embodiments, back electrodes 180A and 180B are formed by printing. Back electrodes 180A and 180B each have a length BCL along the X direction and a width BCW along the Y direction. In some embodiments, the length BCL is about 1 / 4 to about 1 / 3 of the length L, and the width BCW is about 4 / 5 to about 1 times the width W.

[0053] Please refer to the previous document. Figure 1 ,exist Figure 2H and Figure 2I After the process is completed, an interconnect layer 185 is formed on the side 105C of the substrate 105. In some embodiments, the interconnect layer 185 is formed by sputtering. Next, a nickel layer 190A and a tin layer 190B (i.e., the external electrode pair 190) are sequentially formed from the second insulating protective layer 170 along the interconnect layer 185 to cover the back electrode pair 180. In some embodiments, the external electrode pair 190 is formed by electroplating.

[0054] Based on the above, the present invention provides a thin film resistor and a method for manufacturing the same, which involves depositing a resistor layer containing different metals using a DC multi-target hybrid sputtering operation, and depositing a doped layer on the resistor layer using a radio frequency-DC hybrid sputtering operation, so as to achieve the effect of controlling the resistance value and resistivity of the thin film resistor.

[0055] Although the present invention has been disclosed above with reference to several embodiments, it is not intended to limit the present invention. Those skilled in the art to which this invention pertains can make various modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

[0056] [Symbol Explanation]

[0057] 100: Thin film resistor

[0058] 105:Substrate

[0059] 105A: Top surface

[0060] 105B: Lower surface

[0061] 105C: Side

[0062] 110: Insulating oxide film

[0063] 120: First internal electrode pair

[0064] 120A, 120B: First internal electrode

[0065] 130: Resistive layer

[0066] 135: Oxide-doped thin films

[0067] 140: Passivation layer

[0068] 150: First insulating protective layer

[0069] 160: Second internal electrode pair

[0070] 160A, 160B: Second internal electrode

[0071] 170: Second insulating protective layer

[0072] 180: Back electrode pair

[0073] 180A, 180B: Back electrode

[0074] 185: Connector Layer

[0075] 190: External electrode pair

[0076] 190A: Nickel layer

[0077] 190B: Tin layer

[0078] 210A: Masking layer

[0079] 210B: Area to be plated

[0080] 220A: Cover Layer

[0081] 220B: Area to be passivated

[0082] 300: Relationship Diagram

[0083] L,CL,RL,PL,G1L,C2L,G2L,BCL: Length

[0084] W, CW, RW, PW, G1W, C2W, G2W, BCW: Width

[0085] X, Y: Direction.

Claims

1. A method of manufacturing a thin film resistor, characterized by, Include: An insulating oxide film is formed on the upper surface of the substrate; The first internal electrode pair is formed at both ends of the insulating oxide film; A DC multi-target hybrid sputtering operation is performed to deposit a resistive layer on a portion of the insulating oxide film and a portion of the first internal electrode pair, wherein the DC multi-target hybrid sputtering operation includes sputtering a nickel-chromium alloy, tantalum metal, and molybdenum metal; A radio frequency-DC hybrid sputtering operation is performed to deposit a doped layer on the resistor layer, wherein the radio frequency-DC hybrid sputtering operation includes radio frequency sputtering of silicon and DC sputtering of aluminum; An annealing process is performed to form an oxide-doped thin film on the doped layer. as well as A passivation layer is formed on the oxide-doped thin film.

2. The method of claim 1, wherein The process of forming the insulating oxide film includes: A sputtered layer is formed on the substrate, wherein the sputtered layer comprises tantalum or silicon; and The sputtered layer is sintered to form the insulating oxide film, wherein the insulating oxide film comprises tantalum oxide or silicon oxide.

3. The method of claim 1, wherein the method further comprises: In this DC multi-target hybrid sputtering operation, the sputtering power of the tantalum metal is 60% to 100% of the sputtering power of the nickel-chromium alloy, and the sputtering power of the molybdenum metal is 5% to 30% of the sputtering power of the nickel-chromium alloy.

4. The method for manufacturing a thin-film resistor according to claim 1, characterized in that, In this RF-DC hybrid sputtering operation, the sputtering power of the aluminum is 20% to 50% of the sputtering power of the silicon.

5. The method for manufacturing a thin-film resistor according to claim 1, characterized in that, Based on a weight of 100 wt%, the resistive layer comprises: 45wt% to 75wt% nickel-chromium alloy; 20wt% to 40wt% tantalum; and 5 wt% to 15 wt% molybdenum.

6. The method for manufacturing a thin-film resistor according to claim 1, characterized in that, The weight ratio of aluminum to silicon in this doped layer is 1:1 to 1:

5.

7. The method for manufacturing a thin-film resistor according to claim 1, characterized in that, Also includes: A first insulating protective layer is formed on the passivation layer; and The second inner electrode pair is formed on both ends of the insulating oxide film and covers a portion of the first inner electrode pair and the first insulating protective layer.

8. The method for manufacturing a thin-film resistor according to claim 7, characterized in that, Also includes: A second insulating protective layer is formed on the exposed portion of the first insulating protective layer and on the portion of the second inner electrode pair.

9. The method for manufacturing a thin-film resistor according to claim 8, characterized in that, Also includes: Forming back electrode pairs at both ends of the lower surface of the substrate; and An external electrode pair is formed that extends from the second insulating protective layer along both sides of the substrate to connect to the back electrode pair.

10. A thin-film resistor, characterized in that, Prepared by the method according to any one of claims 1 to 9.

Images