An integrated anti-reflective protection and clamping adjustable high-voltage ESD protection structure

Abstract

The application relates to the technical field of semiconductor integrated circuit design, and particularly relates to a high-voltage ESD protection structure with integrated anti-reverse protection and adjustable clamping, which is composed of three units of a PDEMOS_ESD tube P1, an HVDIO_ESD diode D1 and X-stage serially connected NMOS_ISO_ESD tubes N1-NX, and all the devices are monolithically integrated on the same silicon chip; each stage of the NMOS_ISO_ESD tubes adopts a gate coupling GCN topology structure, and the overall trigger and clamping voltage can be linearly adjusted by adjusting the stacking stage number X; the application can simultaneously realize electrostatic discharge and power reverse connection protection, and the clamping voltage is flexibly optional to be compatible with multiple voltage domains; the trigger voltage of the full-link GCN architecture is reduced by 30%-50%, the ESD effective discharge window is greatly widened, the multi-stage serially connected voltage divider improves the overall voltage resistance of the device, the single device is compatible with multiple voltage domains, the application can be mass-produced by using a conventional high-voltage process, the static leakage current is low, and the high-low temperature reliability is strong.

Description

Technical Field

[0001] This invention relates to the field of semiconductor integrated circuit design technology, specifically a high-voltage ESD protection structure that integrates anti-reverse protection and adjustable clamping. Background Technology

[0002] With the large-scale application of high-voltage integrated circuits in automotive electronics, industrial power supplies, and fast charging drives, high-voltage ports frequently encounter severe conditions such as electrostatic discharge (ESD) shocks and reverse connection errors in actual use. The ESD reliability and reverse connection protection of high-voltage interfaces have become key challenges in chip design. There is an urgent need for an ESD protection solution for high-voltage interfaces that can simultaneously achieve ESD discharge, reverse connection protection, and compatibility with multiple rated voltage levels.

[0003] Current high-voltage electrostatic discharge (ESD) protection devices generally have several shortcomings. Conventional gate-grounded NMOS and gate-coupled NMOS structures rely on the drain-source PN junction for small-amplitude negative voltage discharge, which cannot withstand full-amplitude reverse connection of the power supply. When the positive and negative terminals of the input power supply are reversed, the parasitic PN junction of the device conducts in the forward direction, and a large reverse current flows back into the internal circuit, which may cause abnormalities such as gate oxide breakdown of the internal MOS and chip latch-up damage. Traditional high-voltage thyristor structures have extremely low reverse withstand voltage, and a small reverse negative voltage can sustain conduction and short circuit, which may cause device damage. The industry's conventional solution is to connect an external anti-reverse Schottky diode in series with the chip, but external devices occupy PCB space and introduce forward conduction voltage drop losses, which is not conducive to improving power efficiency.

[0004] Furthermore, the trigger voltage and holding clamp voltage of existing high-voltage electrostatic discharge (ESD) devices are uniquely determined by the manufacturing process and device layout dimensions. These parameters cannot be changed after fabrication. If a single chip platform needs to be compatible with products across multiple voltage domains, the aspect ratio of the ESD device must be repeatedly modified, requiring re-fabrication and iteration. This results in long development cycles and high customization costs. Moreover, a fixed clamp voltage is difficult to match the different operating margin requirements of the chip. Excessive clamping can easily damage the gate oxide of the back-end core, while insufficient clamping leads to excessive static leakage current and degraded overall power consumption. On the other hand, conventional ESD devices have a small effective discharge space, relying solely on the gate RC coupling capacitor to pre-raise the gate voltage and lower the trigger voltage, while the DC breakdown voltage remains essentially unchanged. Unidirectionally widening the effective discharge window has limited improvement in discharge margin. Therefore, given these shortcomings, there is an urgent need to develop a high-voltage ESD protection structure that integrates reverse protection and adjustable clamping to overcome the deficiencies in current practical applications. Summary of the Invention

[0005] The purpose of this invention is to provide a high-voltage ESD protection structure that integrates anti-reverse protection and adjustable clamping, so as to solve the problems mentioned in the background art.

[0006] To achieve the above objectives, the present invention provides the following technical solution: A high-voltage ESD protection structure integrating anti-reverse protection and adjustable clamping is provided. The high-voltage ESD protection structure is used for electrostatic protection of high-voltage I / O ports. The entire structure only has two external ports: high-voltage I / O ports and chip common ground GND. It is monolithically integrated on the same silicon chip by a PDEMOS_ESD transistor, an HVDIO_ESD diode, and an X-level series NMOS_ISO_ESD transistor, where X is the number of stacking levels. The drain of the PDEMOS_ESD transistor is connected to the high-voltage I / O port, its source and substrate are connected to the intermediate node NET1, and its gate is connected to the intermediate node NET1 through the first resistor R0, forming a gate coupling structure by relying on its own gate-drain parasitic capacitance. The cathode of the HVDIO_ESD diode is connected to the intermediate node NET1, and the anode is connected to the chip common ground; The drain and source of the X-stage NMOS_ISO_ESD transistor are connected in series, with the drain of the first stage connected to the intermediate node NET1 and the source of the last stage connected to the chip's common ground. Each NMOS_ISO_ESD transistor uses a gate-coupled topology, with its gate connected to its own drain via a coupling capacitor and simultaneously connected to its own source via a pull-down resistor of the same stage.

[0007] As a further aspect of the present invention, the stacking level X ranges from 2 to 8.

[0008] As a further aspect of the present invention: each NMOS_ISO_ESD transistor adopts deep N-well isolation, independent substrate bias, drain connected to its own ISO potential, and source short-circuited to its own substrate. The source of the previous NMOS_ISO_ESD transistor is connected to the drain of the next NMOS_ISO_ESD transistor, and so on in series until the source of the last stage is connected to the common ground. All NMOS_ISO_ESD transistors have identical gate width, gate length, coupling capacitance, and pull-down resistor parameters.

[0009] As a further aspect of the present invention: the drain terminal of the PDEMOS_ESD transistor adopts a lightly doped drain structure or a field plate structure.

[0010] As a further aspect of the present invention: the NMOS_ISO_ESD transistor adopts a deep N-well isolation structure or a LOCOS local oxidation isolation structure.

[0011] As a further aspect of the present invention: the HVDIO_ESD diode is a high-voltage PN junction diode, employing an N-well / P+ injection or P-well / N+ injection structure; The reverse breakdown voltage of the HVDIO_ESD diode is greater than the sum of the DC breakdown voltages of a single stage of the X-level NMOS_ISO_ESD diode.

[0012] As a further aspect of the present invention, the time constant of the single-stage NMOS_ISO_ESD gate-coupled RC circuit is in the range of 5 to 200 ns.

[0013] As a further aspect of the present invention: the ESD trigger voltage of the high-voltage ESD protection structure satisfies: Forward ESD trigger voltage: Vtr+=VPN(P1)+X×Vt(NMOS_ISO_ESD); Reverse ESD trigger voltage: Vtr-=VPN(D1)+Vt(PDEMOS_ESD); Where VPN(P1) is the forward voltage drop of the PN junction between the drain of PDEMOS_ESD transistor P1 and the substrate, Vt(NMOS_ISO_ESD) is the trigger voltage of a single-stage NMOS_ISO_ESD transistor, and X is the number of stacking stages. VPN(D1) is the forward voltage drop of HVDIO_ESD, and Vt(PDEMOS_ESD) is the trigger voltage of PDEMOS_ESD transistor P1.

[0014] As a further aspect of the present invention: the high-voltage ESD protection structure includes two independent discharge paths: Forward ESD discharge path: High voltage I / O port → PDEMOS_ESD transistor → intermediate node NET1 → X-stage series NMOS_ISO_ESD transistor → chip common ground; Reverse negative voltage discharge path: chip common ground → HVDIO_ESD diode → intermediate node NET1 → PDEMOS_ESD tube → high voltage I / O port.

[0015] As a further aspect of the present invention: the coupling capacitance of each NMOS_ISO_ESD transistor ranges from 0.3pF to 12pF; The resistance value of the first resistor and the pull-down resistor of each NMOS_ISO_ESD transistor ranges from 5kΩ to 200kΩ.

[0016] Compared with the prior art, the beneficial effects of the present invention are: First, it achieves integrated anti-reverse protection by integrating a high-voltage PDEMOS_ESD transistor on-chip to achieve full-range reverse isolation, abandoning the traditional discrete solution of "ESD device + PCB external Schottky anti-reverse protection", saving PCB board area and improving overall efficiency. Secondly, the clamping voltage is flexibly selectable. By stacking PDEMOS_ESD transistors in series with multiple NMOS_ISO_ESD transistors, the overall withstand voltage of the device is increased from a single transistor to multiple levels, which can adapt to the high voltage application requirements of different potentials. Furthermore, compared to conventional GGNMOS electrostatic protection structures, the full-link GCN gate coupling architecture of this invention can reduce the device trigger voltage by 30% to 50%, while keeping the DC breakdown voltage essentially unchanged, significantly widening the ESD discharge window and increasing the high-voltage ultra-thin gate oxide protection margin. In addition, the system has higher reliability. The parasitic parameters of the monolithic integrated structure are much smaller than those of the discrete "ESD + external anti-reverse diode" solution. A single device can withstand the dual severe stresses of forward ESD and reverse power connection at the same time, and the protection stability is stronger under high and low temperature and process deviation. Finally, series stacking improves withstand voltage and has good process versatility. The PDEMOS_ESD tube and multiple NMOS_ISO_ESD tubes are connected in series to divide the voltage. The withstand voltage can be several times that of a single tube using conventional and mature high voltage technology. No special process needs to be customized, which is convenient for mass production. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the high-voltage ESD protection structure circuit in an embodiment of the present invention. Detailed Implementation

[0018] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0019] The specific implementation of the present invention will be described in detail below with reference to specific embodiments.

[0020] Please see Figure 1 This invention provides a high-voltage ESD (electrostatic discharge) protection structure with integrated reverse polarity protection and adjustable clamping. It is suitable for electrostatic discharge protection of high-voltage I / O ports in automotive power chips and industrial high-voltage drive chips, simultaneously achieving electrostatic discharge and reverse polarity protection, and is compatible with high-voltage interface applications with multiple rated voltage levels. The high-voltage ESD protection structure only exposes two external ports: the HVI / O port (high-voltage input / output port) and the chip common ground GND (chip common ground terminal). The entire structure consists of three main units: a PDEMOS_ESD transistor (high-voltage P-type diffused metal-oxide-semiconductor electrostatic discharge protection transistor) P1, an HVDIO_ESD diode (high-voltage diode electrostatic discharge protection transistor) D1, and X series-connected NMOS_ISO_ESD transistors (isolated N-channel metal-oxide-semiconductor electrostatic discharge protection transistors) N1 to NX. All components are monolithically integrated on a single silicon wafer. Here, X is a configurable stacking level (positive integer), typically ranging from 2 to 8 levels, which can be flexibly configured according to the voltage withstand requirements of the actual application.

[0021] The drain of the PDEMOS_ESD transistor P1 is connected to the HVI / O port, and the source of the PDEMOS_ESD transistor P1 is connected to the intermediate node NET1 along with the substrate. The gate of the PDEMOS_ESD transistor P1 is connected to the intermediate node NET1 via a first resistor R0. The gate-drain parasitic capacitance Cgd(P1) of the PDEMOS_ESD transistor P1 and the first resistor R0 form an RC coupling circuit with a time constant of: τ(P1)=R0×Cgd(P1); The ESD triggering speed of the PDEMOS_ESD transistor P1 is controlled by the time constant τ(P1). Through the RC coupling circuit formed by the gate-drain parasitic capacitance Cgd(P1) of the PDEMOS_ESD transistor P1 and the first resistor R0, the gate potential can be quickly coupled and adjusted when the ESD pulse arrives, allowing the PDEMOS_ESD transistor P1 to enter the conduction state earlier, thereby reducing the trigger voltage and widening the effective ESD discharge window. The PDEMOS_ESD transistor P1 is a high-voltage P-type diffused MOS transistor, and its drain terminal can adopt a lightly doped drain (LDD) structure or a field plate structure to improve the withstand voltage.

[0022] The cathode of the HVDIO_ESD diode D1 is connected to the intermediate node NET1, and the anode of the HVDIO_ESD diode D1 is connected to the chip's common ground GND. The HVDIO_ESD diode D1 is mainly used for reverse ESD negative voltage discharge. By setting the HVDIO_ESD diode D1, a discharge path can be provided when reverse ESD negative voltage occurs at the HVI / O port, quickly guiding the reverse ESD energy to ground and protecting the internal circuit from reverse ESD impact. At the same time, under the reverse power connection condition, the HVDIO_ESD diode D1 is forward-biased, which can clamp the potential of the intermediate node NET1 near the diode's forward conduction voltage, preventing the negative voltage from being further transmitted to the internal circuit. The HVDIO_ESD diode D1 is a high-voltage PN junction diode, implemented using an N-well / P+ injection or P-well / N+ injection structure, and the HVDIO_ESD reverse withstand voltage is greater than the sum of the withstand voltages of X levels of NMOS_ISO_ESD.

[0023] The drains and sources of the X-stage NMOS_ISO_ESD transistors N1 to NX are connected in series. The drain of the first-stage NMOS_ISO_ESD transistor N1 is connected to the intermediate node NET1, and the source of the last-stage NMOS_ISO_ESD transistor NX is connected to the chip's common ground GND. The drain of each stage is connected to its own ISO potential (using deep N-well isolation and independent substrate bias), and the source is connected to its own substrate. The source of the previous stage is connected to the drain of the next stage, and the series connections end in series until the last stage is connected to the common ground. The gate width and gate length, as well as the parameters C and R, are completely identical for each stage of the NMOS_ISO_ESD transistor (ensuring that τ is completely equal for each stage).

[0024] The single-stage NMOS_ISO_ESD transistor adopts a standard GCN topology: the gate of the NMOS_ISO_ESD transistor is connected to its own drain via a coupling capacitor, and the gate of the NMOS_ISO_ESD transistor is simultaneously connected to its own source via a pull-down resistor; the single-stage RC time constant τ = R × C takes a value of 5 to 200 ns, matching the HBM 150 ns electrostatic pulse timing. Specifically, for the Xth stage NMOS_ISO_ESD transistor NX (X = 1, 2, ..., X), one end of the Xth stage coupling capacitor CX is connected to the drain of the Xth stage NMOS_ISO_ESD transistor NX, and the other end is connected to the gate of the Xth stage NMOS_ISO_ESD transistor NX; one end of the Xth stage resistor RX is connected to the gate of the Xth stage NMOS_ISO_ESD transistor NX, and the other end is connected to the source of the Xth stage NMOS_ISO_ESD transistor NX. By using a multi-stage series GCN structure, the overall withstand voltage can be increased to X times that of a single transistor, achieving high-voltage ESD protection. At the same time, each stage adopts a gate coupling structure, which can pre-raise the gate potential through capacitive coupling when an ESD pulse arrives, allowing the NMOS transistor channel to turn on in advance. Compared with traditional GGNMOS, the trigger voltage Vt1 is reduced by 30% to 50%, while the DC breakdown voltage DCBV remains basically unchanged. This significantly widens the discharge margin between Vt1 and DCBV, increases the effective ESD discharge window, and improves the safety margin for high-voltage ultra-thin gate oxide protection.

[0025] In the NMOS_ISO_ESD transistor, "ISO" represents the isolation structure, specifically a deep N-well isolation or local oxidation isolation (LOCOS) structure, to improve the device's withstand voltage and latch-up resistance.

[0026] The typical capacitance range of each coupling capacitor C1 to CX is 0.3pF to 12pF, and the typical resistance range of each resistor R1 to RX is 5kΩ to 200kΩ. The specific parameters are adjusted according to the required RC time constant.

[0027] The principle of adjustable clamping voltage in this invention is as follows: the number of stacking stages X is a variable parameter, which can be adjusted by increasing or decreasing the number of NMOS_ISO_ESD transistors N1 to NX to adjust the trigger voltage of forward ESD.

[0028] By changing the stacking level X, the trigger voltage and clamping voltage of the overall structure can be linearly adjusted to adapt to the application requirements of different voltage platforms. Using this adjustable clamping structure, the same chip platform can be configured with different stacking levels X to be compatible with multi-voltage domain products, eliminating the need for repeated modifications to the aspect ratio of ESD devices and re-fabrication iterations, significantly shortening the R&D cycle and reducing customization costs. Simultaneously, the clamping voltage can be flexibly adjusted according to the different operating margin requirements of the chip, avoiding excessive clamping leading to gate oxide breakdown in the back-end core, or insufficient clamping leading to excessive static leakage current and degraded overall power consumption.

[0029] The ESD discharge path of this invention is divided into two paths: a positive ESD path and a reverse negative pressure path.

[0030] The forward ESD path is as follows: HVI / O port → PDEMOS_ESD transistor P1 (drain → source / substrate) → intermediate node NET1 → first-stage NMOS_ISO_ESD transistor N1 → second-stage NMOS_ISO_ESD transistor N2 → ... → Xth-stage NMOS_ISO_ESD transistor NX → chip common ground GND; The reverse negative voltage path is: chip common ground GND → HVDIO_ESD diode D1 (anode → cathode) → intermediate node NET1 → PDEMOS_ESD transistor P1 (source / substrate → drain) → HVI / O port.

[0031] The working principle of this embodiment will be explained in detail below with reference to various working conditions: Operating Condition 1: Chip powered on by normal DC (HVI / O with rated positive DC voltage applied) Under normal DC operating conditions, a rated positive DC voltage is applied to the HVI / O port. At this time, the drain of PDEMOS_ESD transistor P1 is higher than the substrate potential, and the PN junction is forward biased. For each NMOS_ISO_ESD transistor N1 to NX, due to the DC blocking characteristics of the gate coupling capacitors at each stage, the DC voltage cannot raise the gate potential of the NMOS_ISO_ESD transistor through capacitive coupling. Simultaneously, the gate of each NMOS_ISO_ESD transistor is clamped to its own source potential by the pull-down resistor of that stage, resulting in a gate-source voltage Vgs = 0. Therefore, all NMOS_ISO_ESD transistors connected in series are in the off state. The cathode potential (NET1 node potential) of HVDIO_ESD diode D1 is higher than the anode potential (GND potential), and the PN junction is in the reverse bias off state. The reverse withstand voltage of HVDIO_ESD is greater than the sum of the withstand voltages of the X NMOS_ISO_ESD transistors.

[0032] Forward clamping voltage: Vclamp+=VPN(P1)+X×DCBV(NMOS_ISO_ESD); Where VPN(P1) is the forward voltage drop of the PN junction between the drain of PDEMOS_ESD transistor P1 and its substrate, DCBV(NMOS_ISO_ESD) is the DC withstand voltage of a single-stage NMOS_ISO_ESD transistor, and X is the number of stacking stages.

[0033] In summary, under normal DC operating conditions, the high-voltage ESD protection structure is in a cut-off state, the leakage current of the device is maintained at the nA level, there is no additional static power consumption, and it does not affect the normal electrical parameters of the HVI / O port.

[0034] Operating Condition 2: HVI / O forward ESD impact (HBM / MMns level forward high voltage spike) When the HVI / O port is subjected to a forward ESD impact, a high-frequency transient high-voltage pulse on the order of nanoseconds will appear. At this time, the drain of the PDEMOS_ESD transistor P1 is forward biased to the PN junction of the substrate (equal to the NET1 potential). Simultaneously, the ESD pulse raises the gate potential of each transistor from N1 to NX through the coupling of each stage of the capacitor, causing the channel of each NMOS_ISO_ESD transistor to turn on in advance; after the device turns on, the internal parasitic lateral BJT avalanche is triggered, and the ESD energy is rapidly discharged to ground along the forward discharge path.

[0035] Based on the total clamping voltage set by the stacking level X, the instantaneous high voltage at the port can be limited to the core's safe withstand voltage range, achieving forward electrostatic clamping protection. This structure adopts a GCN architecture throughout the entire link. By pre-raising the gate voltage through gate coupling to reduce the trigger voltage Vt1, while the DC breakdown voltage DCBV remains basically unchanged, the voltage difference between DCBV and Vt1 is significantly widened, resulting in a larger effective ESD discharge window.

[0036] Forward ESD trigger voltage: Vtr+=VPN(P1)+X×Vt(NMOS_ISO_ESD); Where VPN(P1) is the forward voltage drop of the PN junction between the drain of PDEMOS_ESD transistor P1 and its substrate, Vt(NMOS_ISO_ESD) is the trigger voltage of a single-stage NMOS_ISO_ESD transistor, and X is the number of stacked stages.

[0037] Operating Condition 3: DC power supply reverse connection (HVI / O negative voltage < 0V, reverse protection condition) When the power supply is reversed, the HVI / O port potential is lower than the GND potential (i.e., HVI / O is negative). At this time, the cathode of the HVDIO_ESD diode D1 is negative and the anode is 0V, and the PN junction is forward-biased, clamping the potential of the intermediate node NET1 near the diode's forward conduction voltage. Simultaneously, the drains of each stage from N1 to NX are successively negative, and the substrate of the NMOS_ISO_ESD transistor in the entire series link is forward-biased to the drain PN junction. The parasitic PN junctions of N1 to NX are connected in series to the NET1 node and in parallel with the PN junction of D1.

[0038] For PDEMOS_ESD transistor P1, its source / substrate (NET1 node) potential is higher. R0 connects the gate potential to the substrate potential, and PDEMOS_ESD transistor P1 is in the off state, which eliminates the chip latch-up and gate oxide breakdown caused by negative voltage backflow from the root, achieving the effect of on-chip integrated anti-reverse.

[0039] Reverse clamping voltage: Vclamp-=VPN(D1)+DCBV(PDEMOS_ESD); Where VPN(D1) is the forward voltage drop of HVDIO_ESD, and DCBV(PDEMOS_ESD) is the DC withstand voltage of PDEMOS_ESD transistor P1.

[0040] Operating Condition 4: HVI / O Reverse ESD Impact (HBM / MMns Level Negative Pressure Peak) When an HVI / O port is subjected to a reverse ESD shock, a high-frequency transient high-voltage pulse in the nanosecond range will appear.

[0041] At this time, the cathode of HVDIO_ESD diode D1 is at negative voltage, the anode is at 0V, and the PN junction is forward biased, clamping the potential of the intermediate node NET1 near the diode's forward bias voltage. Simultaneously, the drains of each stage from N1 to NX are sequentially at negative voltage. The substrate of the fully cascaded NMOS_ISO_ESD diode is forward biased to the PN junction at the drain end. The parasitic PN junctions from N1 to NX are connected in series to the NET1 node and simultaneously in parallel with the PN junction of D1.

[0042] For PDEMOS_ESD transistor P1, its source / substrate (NET1 node) potential is higher. The gate-drain parasitic capacitance Cgd(P1) of PDEMOS_ESD transistor P1 forms an RC coupling circuit with R0. The time constant is: τ(P1)=R0×Cgd(P1); The ESD triggering speed of the PDEMOS_ESD transistor P1 is controlled by the time constant τ(P1). Through the RC coupling circuit formed by the gate-drain parasitic capacitance Cgd(P1) of the PDEMOS_ESD transistor P1 and the first resistor R0, the gate potential can be quickly coupled and adjusted when the ESD pulse arrives, so that the PDEMOS_ESD transistor P1 enters the conduction state in advance, thereby reducing the trigger voltage and widening the effective ESD discharge window.

[0043] Reverse ESD trigger voltage: Vtr-=VPN(D1)+Vt(PDEMOS_ESD); Where VPN(D1) is the forward voltage drop of the HVDIO_ESD transistor, and Vt(PDEMOS_ESD) is the trigger voltage of the PDEMOS_ESD transistor.

[0044] It should be noted that, in this invention, although the specification describes the embodiments, not every embodiment contains only one independent technical solution. This way of describing the specification is only for clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A high-voltage ESD protection structure integrating reverse protection and adjustable clamping, used for electrostatic protection of high-voltage I / O ports, characterized in that: The entire device has only two external ports: a high-voltage I / O port and a chip common ground GND. It is monolithically integrated on the same silicon chip by a PDEMOS_ESD transistor, an HVDIO_ESD diode, and an X-level series NMOS_ISO_ESD transistor, where X is the number of stacking levels. The drain of the PDEMOS_ESD transistor is connected to the high-voltage I / O port, its source and substrate are connected to the intermediate node NET1, and its gate is connected to the intermediate node NET1 through the first resistor R0, forming a gate coupling structure by relying on its own gate-drain parasitic capacitance. The cathode of the HVDIO_ESD diode is connected to the intermediate node NET1, and the anode is connected to the chip common ground; The drain and source of the X-stage NMOS_ISO_ESD transistor are connected in series, with the drain of the first stage connected to the intermediate node NET1 and the source of the last stage connected to the chip's common ground. Each NMOS_ISO_ESD transistor uses a gate-coupled topology, with its gate connected to its own drain via a coupling capacitor and simultaneously connected to its own source via a pull-down resistor of the same stage.

2. The high-voltage ESD protection structure with integrated anti-reverse protection and adjustable clamping as described in claim 1, characterized in that, The stacking level X is a positive integer from 2 to 8.

3. The integrated anti-Clamp and clamp adjustable high voltage ESD protection structure according to claim 1, wherein, Each NMOS_ISO_ESD transistor uses deep N-well isolation, independent substrate bias, drain connected to its own ISO potential, and source shorted to its own substrate. The source of the previous NMOS_ISO_ESD transistor is connected to the drain of the next NMOS_ISO_ESD transistor, and so on in series until the source of the last stage is connected to the common ground. All NMOS_ISO_ESD transistors have identical gate width, gate length, coupling capacitance, and pull-down resistor parameters.

4. The integrated anti-Clamp and clamp adjustable high voltage ESD protection structure of claim 1, wherein, The drain of the PDEMOS_ESD transistor adopts a lightly doped drain structure or a field plate structure.

5. The integrated anti-Clamp and clamp adjustable high voltage ESD protection structure according to claim 1, wherein, The NMOS_ISO_ESD transistor adopts a deep N-well isolation structure or a LOCOS local oxidation isolation structure.

6. The integrated antireflection protection and clamped adjustable high-voltage ESD protection structure of claim 1, wherein, The HVDIO_ESD diode is a high-voltage PN junction diode, employing an N-well / P+ injection or P-well / N+ injection structure. The reverse breakdown voltage of the HVDIO_ESD diode is greater than the sum of the DC breakdown voltages of a single stage of the X-level NMOS_ISO_ESD diode.

7. The integrated anti-Clamp and clamp adjustable high voltage ESD protection structure according to claim 1, wherein, The time constant of a single-stage NMOS_ISO_ESD gate-coupled RC circuit ranges from 5 to 200 ns.

8. The integrated anti-Clamp and clamp adjustable high voltage ESD protection structure of claim 1, wherein, The ESD trigger voltage of the high-voltage ESD protection structure satisfies: Forward ESD trigger voltage: Vtr+=VPN(P1)+X×Vt(NMOS_ISO_ESD); Reverse ESD trigger voltage: Vtr-=VPN(D1)+Vt(PDEMOS_ESD); Where VPN(P1) is the forward voltage drop of the PN junction between the drain of PDEMOS_ESD transistor P1 and the substrate, Vt(NMOS_ISO_ESD) is the trigger voltage of a single-stage NMOS_ISO_ESD transistor, and X is the number of stacking stages. VPN(D1) is the forward voltage drop of HVDIO_ESD, and Vt(PDEMOS_ESD) is the trigger voltage of PDEMOS_ESD transistor P1.

9. The integrated anti-Clamp and clamp adjustable high voltage ESD protection structure of claim 1, wherein, The high-voltage ESD protection structure includes two independent discharge paths: Forward ESD discharge path: High voltage I / O port → PDEMOS_ESD transistor → intermediate node NET1 → X-stage series NMOS_ISO_ESD transistor → chip common ground; Reverse negative voltage discharge path: chip common ground → HVDIO_ESD diode → intermediate node NET1 → PDEMOS_ESD tube → high voltage I / O port.

10. The high-voltage ESD protection structure with integrated anti-reverse protection and adjustable clamping as described in claim 1, characterized in that, The coupling capacitance of a single-stage NMOS ISO-ESD transistor ranges from 0.3pF to 12pF. The first resistor R0 and the pull-down resistors of each NMOS stage have a resistance range of 5kΩ to 200kΩ.

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