A net-following and network-constructing dual-mode control method based on current instruction switching

Abstract

The application relates to the technical field of follow-network and network-constructing dual-mode control, and discloses a follow-network and network-constructing dual-mode control method based on current instruction switching, which comprises the following steps: synchronously sampling d / q-axis currents, d / q-axis voltages and phase-locked loop phases and angular frequencies of a PCC point, and performing mode switching judgment to generate a switching trigger signal; forcibly injecting the d / q-axis currents, the d / q-axis voltages and the phase-locked loop phases and angular frequencies into all integrator initial values of corresponding modes to complete state tracking pre-synchronization; respectively calculating a first d-axis current instruction and a first q-axis current instruction of the follow-network mode and converging the first d-axis current instruction and the first q-axis current instruction with a second d-axis current instruction and a second q-axis current instruction of the network-constructing mode into the same current inner loop entrance to obtain a unified d-axis current instruction and a unified q-axis current instruction and input the unified d-axis current instruction and the unified q-axis current instruction into corresponding current inner loops for differential operation, and outputting gate driving signals, so that the follow-network and network-constructing dual-mode switching control is ensured to be continuous and without step jumps at the switching moment.

Description

Technical Field

[0001] This invention relates to the field of grid-connected dual-mode control technology, and in particular to a grid-connected dual-mode control method based on current command switching. Background Technology

[0002] Existing converter control methods are divided into two categories: grid-following control (GFL) and grid-connected control (GFM). Grid-following control relies on phase-locked loops to track the grid voltage phase and operates in grid-connected mode as a current source, which has good power regulation performance under strong grid conditions. Grid-connected control autonomously establishes voltage and frequency references through algorithms such as virtual synchronous generators, which has stronger stability support capabilities under weak grid or islanded conditions.

[0003] However, existing dual-mode switching schemes employ two independent control structures. During switching, the mode conversion occurs directly at the control structure layer. The inner current loop integrator in grid-connected mode and the outer voltage loop integrator in grid-connected mode operate independently, resulting in numerical differences in the integrator state variables between the two structures during switching. This structural independence causes the integrator in the mode to be activated to start from a mismatched initial value at the time of switching. This leads to a step jump between the output current command and the actual current value before switching. This jump is directly injected into the inner current loop, triggering a transient inrush current, causing system power and voltage frequency oscillations, and in severe cases, triggering overcurrent protection. Summary of the Invention

[0004] This invention provides a grid-based dual-mode control method based on current command switching, thereby solving the current command step problem caused by the discontinuity of integrator state variables. It can ensure continuous and stepless current command switching control in grid-based dual-mode switching at the switching moment.

[0005] The first aspect of this invention provides a grid-connected dual-mode control method based on current command switching, the grid-connected dual-mode control method based on current command switching comprising: Simultaneously sample the d / q axis current, d / q axis voltage, and phase-locked loop phase and angular frequency at the PCC point, and perform mode switching judgment to generate a switching trigger signal; Based on the switching trigger signal, the d / q axis current, the d / q axis voltage, the phase-locked loop phase, and the angular frequency are forcibly injected into the initial values ​​of all integrators in the corresponding mode to complete the state tracking pre-synchronization; The first d-axis current command and the first q-axis current command in the grid-following mode are calculated separately and then converged with the second d-axis current command and the second q-axis current command in the grid-forming mode to the same current inner loop entrance to obtain a unified d-axis current command and a unified q-axis current command. The unified d-axis current command and the unified q-axis current command are input into the corresponding current inner loop for differential operation, and the gate drive signal is output.

[0006] In conjunction with the first aspect, in a first implementation of the first aspect of the present invention, the step of synchronously sampling the d / q axis current, d / q axis voltage, and phase-locked loop phase and angular frequency at the PCC point and performing mode switching judgment to generate a switching trigger signal includes: Simultaneously sample the d / q axis current, d / q axis voltage, and phase-locked loop phase and angular frequency at the PCC point; The mode switching is determined based on the d / q axis voltage and the phase-locked loop phase, and a switching trigger signal is generated.

[0007] In conjunction with the first aspect, in a second implementation of the first aspect of the present invention, the step of determining the mode switching based on the d / q axis voltage and the phase-locked loop phase, and generating a switching trigger signal, includes: The effective voltage value of the PCC point is calculated based on the d / q axis voltage; the phase-locked loop phase error is obtained by subtracting the phase of the phase-locked loop from the actual phase of the power grid. The effective voltage value is compared with the voltage drop threshold. When the effective voltage value is lower than the voltage drop threshold and the duration exceeds the first holding period, a switching trigger signal for grid-to-grid conversion is generated. The phase error of the phase-locked loop is compared with the phase error threshold. When the phase error of the phase-locked loop exceeds the phase error threshold and the duration exceeds the first holding period, a switching trigger signal for the grid-to-grid conversion is generated. The effective voltage value is compared with the voltage recovery threshold, and the phase-locked loop phase error is compared with the phase error recovery threshold. When the effective voltage value is higher than the voltage recovery threshold and the phase-locked loop phase error is lower than the phase error recovery threshold, and the conditions are met simultaneously and the duration exceeds the second holding period, a switching trigger signal for network construction to network following is generated.

[0008] In conjunction with the first aspect, in a third implementation of the first aspect of the present invention, the step of forcibly injecting the d / q axis current, the d / q axis voltage, and the phase-locked loop phase and the angular frequency into the initial values ​​of all integrators of the corresponding mode based on the switching trigger signal to complete the state tracking pre-synchronization includes: When the switching trigger signal for the grid-to-network conversion is received, the d / q axis current, the d / q axis voltage, the phase-locked loop phase, and the angular frequency are forcibly injected into the initial values ​​of all integrators in the grid-to-network conversion mode to complete the state tracking pre-synchronization of the grid-to-network conversion direction. Upon receiving the switching trigger signal from mesh formation to mesh following, the d / q axis current and the angular frequency are forcibly injected into the initial values ​​of all integrators in the mesh following mode to complete the state tracking pre-synchronization of the mesh formation to mesh following direction.

[0009] In conjunction with the first aspect, in the fourth implementation of the first aspect of the present invention, the step of forcibly injecting the d / q axis current, the d / q axis voltage, and the phase-locked loop phase and the angular frequency into the initial values ​​of all integrators in the network construction mode upon receiving the switching trigger signal for the network-to-network conversion, to complete the state tracking pre-synchronization of the network-to-network conversion direction, includes: When a switching trigger signal for grid-to-grid conversion is received, the phase-locked loop phase is forcibly injected into the initial value of the phase integrator of the virtual synchronous generator in grid-connection mode, and the angular frequency is forcibly injected into the initial value of the angular frequency integrator of the virtual synchronous generator in grid-connection mode. The initial value of the voltage outer loop d-axis integrator in the network construction mode is calculated based on the d-axis current and d-axis voltage, the d-axis voltage reference value, and the voltage outer loop scaling factor. At the same time, the initial value of the voltage outer loop q-axis integrator in the network construction mode is calculated based on the q-axis current and q-axis voltage, the q-axis voltage reference value, and the voltage outer loop scaling factor. These values ​​are then forcibly injected into the voltage outer loop d / q-axis integrators in the network construction mode to complete the state tracking pre-synchronization in the direction of network transition from following the grid to network construction.

[0010] In conjunction with the first aspect, in the fifth implementation of the first aspect of the present invention, the step of forcibly injecting the d / q axis current and the angular frequency into the initial values ​​of all integrators in the following mode when receiving the switching trigger signal for the mesh-to-following transition, thereby completing the state tracking pre-synchronization in the mesh-to-following direction, includes: Force the d-axis current to be injected into the initial value of the d-axis current command feedforward in the meshing mode, and force the q-axis current to be injected into the initial value of the q-axis current command feedforward in the meshing mode. The current output phase and current output angular frequency of the virtual synchronous generator corresponding to the network configuration mode are read. The current output phase is forcibly injected into the initial value of the phase-locked loop phase integrator, and the current output angular frequency is forcibly injected into the initial value of the phase-locked loop angular frequency integrator, thus completing the state tracking pre-synchronization of the network configuration to the grid following direction.

[0011] In conjunction with the first aspect, in the sixth implementation of the first aspect of the present invention, the step of separately calculating the first d-axis current command and the first q-axis current command in the meshing mode and converging them with the second d-axis current command and the second q-axis current command in the meshing mode to the same current inner loop entrance to obtain a unified d-axis current command and a unified q-axis current command includes: The first d-axis current command in grid-connected mode is calculated based on the active power command and d-axis voltage, and the first q-axis current command in grid-connected mode is calculated based on the reactive power command and d-axis voltage. The second d-axis current command of the network configuration mode is calculated based on the initial value of the d-axis integrator of the outer voltage loop, the d-axis voltage error, and the voltage outer loop scaling factor; and the second q-axis current command of the network configuration mode is calculated based on the initial value of the q-axis integrator of the outer voltage loop, the q-axis voltage error, and the voltage outer loop scaling factor. Based on the mode flag, the first d-axis current command and the second d-axis current command are sent to the same d-axis input of the current inner loop for selection, and the first q-axis current command and the second q-axis current command are sent to the same q-axis input of the current inner loop for selection, so as to obtain a unified d-axis current command and a unified q-axis current command.

[0012] In conjunction with the first aspect, in the seventh implementation of the first aspect of the present invention, the step of selecting the first d-axis current command and the second d-axis current command by sending them to the same d-axis input of the current inner loop based on the mode flag bit, and selecting the first q-axis current command and the second q-axis current command by sending them to the same q-axis input of the current inner loop to obtain a unified d / q-axis current command, includes: When the mode flag is set to the net flag value, the first d-axis current command is selected to the d-axis input of the current inner loop, and the first q-axis current command is selected to the q-axis input of the current inner loop, so as to obtain a unified d-axis current command and a unified q-axis current command. When the mode flag is set to the network flag value, the second d-axis current command is selected to the d-axis input of the inner current loop, and the second q-axis current command is selected to the q-axis input of the inner current loop, resulting in a unified d-axis current command and a unified q-axis current command.

[0013] In conjunction with the first aspect, in the eighth implementation of the first aspect of the present invention, the step of inputting the unified d-axis current command and the unified q-axis current command into the corresponding current inner loop for differential operation and outputting the gate drive signal includes: The unified d-axis current command and the unified q-axis current command are input into the inner current loop for differential operation to obtain the d-axis modulation voltage reference value and the q-axis modulation voltage reference value; The d-axis modulation voltage reference value and the q-axis modulation voltage reference value are input into the SVPWM modulation module for space vector pulse width modulation, and the gate drive signal is output.

[0014] In conjunction with the first aspect, in the ninth implementation of the first aspect of the present invention, the step of performing differential operation on the input current inner loop of the unified d-axis current command and the unified q-axis current command to obtain the d-axis modulation voltage reference value and the q-axis modulation voltage reference value includes: The d-axis current error is obtained by subtracting the unified d-axis current command from the measured d-axis current value at the PCC point, and the q-axis current error is obtained by subtracting the unified q-axis current command from the measured q-axis current value at the PCC point. The d-axis current error is multiplied by the proportional coefficient of the inner current loop and then added to the state quantity of the d-axis integrator of the inner current loop to obtain the d-axis proportional integral output of the inner current loop; the q-axis current error is multiplied by the proportional coefficient of the inner current loop and then added to the state quantity of the q-axis integrator of the inner current loop to obtain the q-axis proportional integral output of the inner current loop. The d-axis proportional-integral output is added to the d-axis decoupled feedforward voltage to obtain the d-axis modulation voltage reference value; the q-axis proportional-integral output is added to the q-axis decoupled feedforward voltage to obtain the q-axis modulation voltage reference value.

[0015] Compared with existing technologies, this invention uses a continuous sampling mechanism to trigger a switching signal based on the effective voltage value and the phase-locked loop (PLL) phase error. It also introduces a hysteresis holding period mechanism to distinguish between the grid-following to grid-building and grid-building to grid-following directions, avoiding erroneous and repeated switching problems caused by brief fluctuations in grid voltage. For the grid-following to grid-building direction, this invention precisely injects the PLL phase and angular frequency into the initial value of the virtual synchronous generator integrator, and through compensation calculations, maps the d / q-axis current and voltage to the initial value of the voltage outer loop integrator, ensuring that the current command output at the switching moment in grid-building mode is completely consistent with the current actual value. For the grid-building to grid-following direction, it injects the current phase and angular frequency of the virtual synchronous generator into the initial value of the PLL integrator, ensuring that the PLL starts from the aligned state and eliminating the transition time required for re-locking. The above pre-synchronization assignment is completed within the same sampling period. After the assignment is completed, the two current commands are converged to the same current inner loop entrance by flipping the mode flag bit. Since the two current commands have the same value at the switching time, the unified d / q axis current command remains continuous without step before and after the switching. The integrator state of the shared current inner loop does not need to be reset. The SVPWM modulation wave transitions smoothly. No transient impact current is generated during the switching process. This invention does not require retuning any control parameters after the switching, and realizes fast, smooth and disturbance-free bidirectional switching between the following mode and the network construction mode. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] The structures, proportions, sizes, etc., shown in the accompanying drawings of this specification are only for the purpose of assisting those skilled in the art in understanding and reading the content disclosed in the specification, and are not intended to limit the conditions under which the present invention can be implemented. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in the proportions, or adjustments to the size, without affecting the effects and objectives that the present invention can produce, should still fall within the scope of the technical content disclosed in the present invention.

[0018] Figure 1 This is a flowchart illustrating the dual-mode control method for grid-connected networks based on current command switching provided in an embodiment of the present invention. Figure 2 This is a schematic diagram of the mode switching judgment process in an embodiment of the present invention; Figure 3 This is a schematic diagram of the state tracking pre-synchronization process in an embodiment of the present invention; Figure 4 This is a flowchart illustrating the generation of unified d-axis current commands and unified q-axis current commands in an embodiment of the present invention. Figure 5 This is a schematic diagram of the output gate drive signal in an embodiment of the present invention. Detailed Implementation

[0019] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0020] The flowchart shown in the attached diagram is for illustrative purposes only and does not necessarily include all content and operations / steps, nor does it necessarily have to be performed in the order described. For example, some operations / steps can be broken down, combined, or partially merged, so the actual execution order may change depending on the actual situation.

[0021] It should also be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.

[0022] It should also be further understood that the term "and / or" as used in this specification and the appended claims refers to any combination of one or more of the associated listed items, and all possible combinations, and includes such combinations. See also Figure 1One embodiment of the dual-mode control method for grid-connected networks based on current command switching in this invention includes: Step S100: Synchronously sample the d / q axis current, d / q axis voltage, and phase-locked loop phase and angular frequency at the PCC point and perform mode switching judgment to generate a switching trigger signal; Step S200: Based on the switching trigger signal, the d / q axis current, d / q axis voltage, and phase-locked loop phase and angular frequency are forcibly injected into the initial values ​​of all integrators in the corresponding mode to complete the state tracking pre-synchronization. Step S300: Calculate the first d-axis current command and the first q-axis current command in the meshing mode respectively, and converge them with the second d-axis current command and the second q-axis current command in the meshing mode to the same current inner loop entrance to obtain a unified d-axis current command and a unified q-axis current command. Step S400: Input the unified d-axis current command and the unified q-axis current command into the corresponding current inner loop for differential operation, and output the gate drive signal.

[0023] This invention employs a continuous sampling mechanism, triggering a switching signal based on the effective voltage value and the phase error of the phase-locked loop (PLL). It also introduces a hysteresis holding period mechanism to distinguish between the grid-following to grid-building and grid-building to grid-following directions, avoiding erroneous and repeated switching problems caused by brief fluctuations in grid voltage. For the grid-following to grid-building direction, the invention precisely injects the PLL phase and angular frequency into the initial value of the virtual synchronous generator integrator, and through compensation calculations, maps the d / q-axis current and voltage to the initial value of the voltage outer loop integrator, ensuring that the current command output at the switching moment in grid-building mode is completely consistent with the current actual value. For the grid-building to grid-following direction, the invention injects the current phase and angular frequency of the virtual synchronous generator into the initial value of the PLL integrator, ensuring that the PLL starts from the aligned state and eliminating the transition time required for re-locking. The above pre-synchronization assignment is completed within the same sampling period. After the assignment is completed, the two current commands are converged to the same current inner loop entrance by flipping the mode flag bit. Since the two current commands have the same value at the switching time, the unified d / q axis current command remains continuous without step before and after the switching. The integrator state of the shared current inner loop does not need to be reset. The SVPWM modulation wave transitions smoothly. No transient impact current is generated during the switching process. This invention does not require retuning any control parameters after the switching, and realizes fast, smooth and disturbance-free bidirectional switching between the following mode and the network construction mode.

[0024] In one specific embodiment, such as Figure 2 The process of executing step S100 may specifically include the following steps: S101. Synchronously sample the d / q axis current, d / q axis voltage, and phase-locked loop phase and angular frequency at the PCC point; S102. Based on the d / q axis voltage and the phase-locked loop phase, determine the mode switching and generate a switching trigger signal.

[0025] Specifically, the controller synchronously acquires the three-phase voltage, three-phase current, and phase-locked loop (PLL) output status at the PCC point within the same control cycle. After sampling, it obtains the d-axis current, q-axis current, d-axis voltage, and q-axis voltage at the PCC point through coordinate transformation. Simultaneously, it reads the phase and angular frequency output by the PLL at the same sampling moment, ensuring that the current, voltage, and PLL status all correspond to the same instantaneous electrical state. To avoid time deviations between different sampling channels, the voltage and current sampling channels can use the same sampling trigger source. The analog-to-digital conversion is uniformly triggered by a timer or PWM interrupt within a fixed sampling period, and the sampled values ​​are latched in the interrupt at the end of the conversion, so that the d / q-axis voltage and PLL phase are not affected by asynchronous refresh. For example, the sampling period can be set to 100μs, which corresponds to a 10kHz control frequency and can match the current inner loop control cycle of common grid-connected converters. In products with different power device switching frequencies, sampling chip conversion times, or controller operational margins, the sampling period is synchronously adjusted according to the actual control frequency of the current inner loop and is not used as a fixed limiting condition. After the sampled data enters the controller, it first undergoes zero-bias correction, proportional conversion, and amplitude limiting protection. Then, according to the phase-locked loop (PLL) output phase, it completes the conversion from three-phase stationary coordinates to d / q synchronous rotating coordinates to obtain the real-time state variables used for dual-mode control. In each sampling cycle, the controller writes the d-axis current, q-axis current, d-axis voltage, q-axis voltage, PLL phase, and PLL angular frequency into the state buffer. The state buffer only retains a valid state snapshot of the current control cycle to avoid historical averages weakening the transient characteristics of faults.

[0026] The controller determines the mode switching based on the latched d / q axis voltages and phase-locked loop (PLL) phase. The decision logic primarily revolves around whether the PCC point voltage amplitude has dropped and whether the PLL phase has deviated from the stable tracking range. For the grid-to-network transition, the voltage drop threshold can be set to 0.9 times the rated voltage, the phase error threshold to 5°, and the first hold period to 2 sampling periods. The 0.9 times rated voltage indicates that the PCC point voltage has entered a significant disturbance range; the 5° threshold indicates that the PLL phase tracking deviation is no longer suitable for maintaining stability with grid-to-network control; and the 2 sampling periods suppress false triggering caused by single-point sampling glitches while maintaining a relatively fast response speed. The controller generates a grid-to-network transition trigger signal when it detects that the voltage amplitude is below the voltage drop threshold and continues to meet the hold period requirement, or when it detects that the PLL phase error exceeds the phase error threshold and continues to meet the hold period requirement. For the transition from grid connection to grid following mode, the judgment process adopts a recovery confirmation approach. After the voltage at the PCC point recovers to above the voltage recovery threshold and the phase-locked loop phase error falls back to within the phase error recovery threshold, continuous confirmation is required before allowing the transition back to grid following mode. The voltage recovery threshold is higher than the voltage drop threshold, and the phase error recovery threshold is lower than the phase error threshold, providing a hysteresis range for mode switching judgment. The recovery confirmation time can be set to 200ms, which covers the short-term oscillation process after grid disturbances, reducing the possibility of repeated mode reversals near the critical state. After the switching trigger signal is generated, the controller limits the trigger signal to a pulse with a single control cycle width and synchronously latches the current, voltage, phase, and angular frequency states at the trigger moment.

[0027] In one specific embodiment, the process of performing step S102 may specifically include the following steps: Calculate the effective voltage value at the PCC point based on the d / q axis voltage; calculate the phase error of the phase-locked loop by subtracting the phase of the phase-locked loop from the actual phase of the power grid. The effective voltage value is compared with the voltage drop threshold. When the effective voltage value is lower than the voltage drop threshold and the duration exceeds the first holding cycle, a switching trigger signal for grid-to-grid conversion is generated. The phase error of the phase-locked loop is compared with the phase error threshold. When the phase error of the phase-locked loop exceeds the phase error threshold and the duration exceeds the first holding cycle, a switching trigger signal for the grid-to-grid conversion is generated. The effective voltage value is compared with the voltage recovery threshold, and the phase-locked loop phase error is compared with the phase error recovery threshold. When the effective voltage value is higher than the voltage recovery threshold and the phase-locked loop phase error is lower than the phase error recovery threshold, and the conditions are met and the duration exceeds the second holding period, a switching trigger signal for grid construction to grid connection is generated.

[0028] Specifically, the effective value of the PCC point voltage is calculated based on the d / q axis voltage. The controller reads the latched d-axis and q-axis voltages within the same sampling period and calculates them according to the modulus. The current voltage amplitude at point PCC is obtained, where Indicates the first The effective value of the PCC point voltage in each sampling period, in V. Indicates the first The d-axis voltage for each sampling period, in V. Indicates the first The q-axis voltage for each sampling period, in V; simultaneously, the controller subtracts the phase-locked loop output phase from the actual grid phase obtained through independent zero-crossing detection or grid phase observation module to obtain the phase-locked loop phase error, which can be expressed as: ,in This indicates the phase error, expressed in rad or °. This indicates the output phase of the phase-locked loop. This indicates the actual phase of the power grid.

[0029] The controller compares the effective value of the voltage at point PCC with the voltage sag threshold, which can be set to... ,in The voltage threshold, representing the rated voltage, is used to identify when the PCC point voltage has entered a significant drop range. When the effective value of the PCC point voltage is below this threshold, the voltage drop counter increments in each sampling cycle. When the effective value of the PCC point voltage recovers above the threshold, the voltage drop counter is reset to zero. When the accumulated voltage drop counter exceeds the first hold period, the controller generates a switching trigger signal for grid-to-grid conversion. The first hold period can be set to 2 sampling cycles to filter out single-sampling glitches and maintain a fast switching response. Simultaneously, the controller compares the absolute value of the phase-locked loop (PLL) phase error with a phase error threshold, which can be set to 5°, to identify when the PLL has deviated from the stable tracking range. When the phase error exceeds the phase error threshold, the phase error counter increments. When the phase error falls back below the phase error threshold, the phase error counter is reset to zero. When the accumulated phase error counter exceeds the first hold period, a switching trigger signal for grid-to-grid conversion is also generated.

[0030] For the grid transition from grid connection to grid connection, a second hold counter is activated when the effective value of the voltage at the PCC point is higher than the voltage recovery threshold and the phase-locked loop (PLL) phase error is lower than the phase error recovery threshold. After the above recovery conditions persist for more than the second hold period, a grid connection to grid connection switching trigger signal is generated. The second hold period can be converted into the corresponding sampling period based on a 200ms recovery confirmation time, allowing the controller to obtain a longer status confirmation window before mode revert, reducing repeated switching caused by short-term swirl during grid disturbance recovery. After the switching trigger signal is generated, the controller shapes the signal into a pulse with a width of one sampling period and latches the d / q axis current, d / q axis voltage, PLL phase, and angular frequency at the trigger moment.

[0031] In one specific embodiment, such as Figure 3 The process of executing step S200 can specifically include the following steps: S201. Upon receiving the switching trigger signal for the grid-to-grid conversion, the d / q axis current, d / q axis voltage, and phase-locked loop phase and angular frequency are forcibly injected into the initial values ​​of all integrators in the grid-to-grid conversion mode to complete the state tracking pre-synchronization of the grid-to-grid conversion direction. S202. Upon receiving the switching trigger signal for the transition from network configuration to network tracking, the d / q axis current and angular frequency are forcibly injected into the initial values ​​of all integrators in the network tracking mode to complete the state tracking pre-synchronization of the network configuration to network tracking direction.

[0032] Specifically, after entering the state tracking pre-synchronization process, the controller first freezes the mode flag bit toggling action and latches the d-axis current, q-axis current, d-axis voltage, q-axis voltage, phase-locked loop phase, and phase-locked loop angular frequency of the PCC point that have been synchronously sampled at the trigger time. This ensures that the integrator initialization process of the control mode to be activated uses the electrical state at the same time, avoiding inconsistent states formed by the current channel, voltage channel, and phase channel due to different refresh timing. Upon receiving the grid-connected to grid-connected mode switching trigger signal, the controller maintains the closed-loop operation of the grid-connected mode's inner current loop. Simultaneously, it enables the grid-connected mode integrator, writing the phase-locked loop (PLL) phase and angular frequency into the phase integrator and angular frequency integrator of the virtual synchronous generator in grid-connected mode. This ensures that the internal voltage phase reference of the grid-connected mode remains consistent with the grid phase tracked by the grid-connected mode before the switch. Simultaneously, the controller compensates the d / q-axis integrator of the grid-connected mode's outer voltage loop based on the d / q-axis current and voltage states at the trigger moment. This ensures that the outer voltage loop output of the grid-connected mode, after activation, can connect to the current actual current state, rather than starting with historical residual integral values ​​or default zero initial values. After the above writing process is completed, the controller performs a validity check on the writing results of each integrator in the network construction mode. For example, it checks whether the written value exceeds the controller's allowed range, whether the limiting flag is triggered, and whether it is consistent with the current voltage outer loop reference direction. After the check is passed, the allowed mode flag bit is flipped from the following flag value to the network construction flag value, thereby ensuring that the network construction current command received by the unified current inner loop inlet is smoothly connected with the current state before the switch.

[0033] Upon receiving the switching trigger signal from grid-to-grid transition, the controller employs the same state latching and write arbitration mechanism to maintain the grid-to-grid mode's continued output within the pre-synchronization period. Simultaneously, it writes the d-axis and q-axis currents at the trigger moment into the initial values ​​of the d-axis and q-axis current command feedforwards for the grid-to-grid mode, ensuring that the grid-to-grid mode does not start participating in the current inner loop from old or uninitialized commands from the previous shutdown period when it resumes operation. Furthermore, the controller reads the current output phase and angular frequency of the virtual synchronous generator in the grid-to-grid mode and writes these values ​​into the initial values ​​of the corresponding integrator in the grid-to-grid mode's phase-locked loop (PLL), allowing the PLL to re-enter the tracking process from its position of continuous connection with the grid's internal voltage reference. After completing the pre-synchronization of the grid-to-grid transition direction, the controller releases the mode flag toggling lock and sends the grid-to-grid mode current command into the unified current inner loop input, ensuring continuous operation of the current inner loop, decoupling feedforward, and SVPWM modulation module before and after the switch. The entire pre-synchronization process can be completed within one sampling period. During the integrator writing process, the shared current inner loop integration state is not reset, nor are the current loop proportional coefficient, integral coefficient, and modulation module parameters changed. Therefore, the switching action mainly occurs at the state initialization level of the mode to be activated. The underlying current closed loop continues to recursively advance, thereby reducing the risk of current command step jump, modulation voltage sudden change, and power oscillation at the moment of mode switching.

[0034] In one specific embodiment, the process of performing step S201 may specifically include the following steps: When the switching trigger signal for grid-to-grid conversion is received, the phase of the phase-locked loop is forcibly injected into the initial value of the phase integrator of the virtual synchronous generator in grid-connected mode, and the angular frequency is forcibly injected into the initial value of the angular frequency integrator of the virtual synchronous generator in grid-connected mode. The initial value of the voltage outer loop d-axis integrator in the network construction mode is calculated based on the d-axis current and d-axis voltage, the d-axis voltage reference value, and the voltage outer loop scaling factor. At the same time, the initial value of the voltage outer loop q-axis integrator in the network construction mode is calculated based on the q-axis current and q-axis voltage, the q-axis voltage reference value, and the voltage outer loop scaling factor. These values ​​are then forcibly injected into the voltage outer loop d / q-axis integrators in the network construction mode to complete the state tracking pre-synchronization in the direction of network transition from following the grid to network construction.

[0035] Specifically, upon receiving the grid-connected to grid-connected mode switching trigger signal, the controller latches a snapshot of the state at the trigger moment within the sampling period of the rising edge of the trigger signal, and immediately toggles the pause mode flag. It then adjusts the control structure of the grid-connected mode to be activated to an initial state consistent with the current grid-connected operating state. The controller writes the phase-locked loop phase at the trigger moment into the initial value of the phase integrator of the virtual synchronous generator in the grid-connected mode, and writes the phase-locked loop angular frequency at the trigger moment into the initial value of the angular frequency integrator of the virtual synchronous generator in the grid-connected mode, which can be expressed as: ; ; in, This represents the initial value of the virtual synchronous generator angular frequency integrator, in rad / s. This represents the initial value of the virtual synchronous generator phase integrator, in rad. This indicates the switching trigger sampling time; the above assignment causes the internal phase and frequency reference of the grid construction mode to start from the grid phase and angular frequency that have been locked in the grid-following mode, reducing the active power fluctuation caused by phase misleading.

[0036] The controller initializes the outer voltage loop integrator with compensation values ​​based on the d-axis current, q-axis current, d-axis voltage, q-axis voltage, and the grid-mode voltage reference value at the trigger moment. This ensures that the current command output by the grid-mode outer voltage loop at activation closely matches the actual current state at the trigger moment. The corresponding assignment relationship is as follows: ; ; in, This represents the initial value of the d-axis integrator in the outer voltage loop, in A. This represents the initial value of the voltage outer loop q-axis integrator, in A. and The currents at the trigger moment are represented by the d-axis and q-axis currents, in amperes (A). and The reference values ​​for the d-axis and q-axis voltages at the trigger moment are represented in V. This represents the voltage outer loop proportional coefficient, in A / V. Through the aforementioned compensation relationship, the deviation between the voltage reference value and the measured voltage at the PCC point is factored into the integrator's initial value. When the grid-connected voltage outer loop takes over control, it will not start from a zero integral state or a historical residual state, but rather from an integral state that can offset the voltage deviation. After writing the phase integrator, angular frequency integrator, and voltage outer loop d / q-axis integrator, the controller performs amplitude limiting verification and sets the validity flag on the written values. After confirming that the initial values ​​of each integrator have been written, it releases the mode flag bit flip lock, allowing the grid-connected current command to enter the unified current inner loop entry. Because the pre-synchronization assignment is completed within one sampling period, and the shared current inner loop integrator is not cleared, the state tracking pre-synchronization of the grid-to-grid-connection direction can complete the current command continuity constraint before the control structure switch, thereby reducing the risk of modulation voltage mutation and inrush current at the moment of switching.

[0037] In one specific embodiment, the process of performing step S202 may specifically include the following steps: Force the d-axis current to be injected into the initial value of the d-axis current command feedforward in the meshing mode, and force the q-axis current to be injected into the initial value of the q-axis current command feedforward in the meshing mode. The current output phase and current output angular frequency of the virtual synchronous generator corresponding to the network configuration mode are read. The current output phase is forcibly injected into the initial value of the phase-locked loop phase integrator, and the current output angular frequency is forcibly injected into the initial value of the phase-locked loop angular frequency integrator, thus completing the state tracking pre-synchronization of the network configuration to the grid following direction.

[0038] Specifically, upon receiving the grid-to-grid switching trigger signal, the controller latches the electrical state of the grid-connected mode during the same sampling period when the trigger signal is valid, and temporarily delays the mode flag flipping, ensuring that the grid-connected mode maintains the voltage and frequency support output of the current period. Simultaneously, it enables the pre-synchronization write permission for the grid-connected mode control channel. At this time, the controller writes the d-axis current at the trigger moment into the d-axis current command feedforward initial value of the grid-connected mode, and also writes the q-axis current at the trigger moment into the q-axis current command feedforward initial value of the grid-connected mode. This ensures that when the grid-connected mode resumes taking over the unified current inner loop entry, the current command starting point directly matches the current actual current state, preventing residual power command conversion results or default initial values ​​from the grid-connected mode shutdown period from entering the current inner loop. The corresponding assignment relationship can be expressed as: ; ; After the initial value of the current command feedforward is written, the controller continues to read the current output phase and current output angular frequency from the virtual synchronous generator operating register corresponding to the grid mode, and writes the current output phase into the initial value of the phase-locked loop (PLL) phase integrator, and the current output angular frequency into the initial value of the PLL angular frequency integrator, so that the PLL enters the tracking process from the phase and frequency state already established in the grid mode. The corresponding assignment relationship can be expressed as: ; ; After the above assignment is completed, the controller sets the pre-synchronization completion flag for the current feedforward channel and the phase-locked loop integrator channel in grid-following mode, and verifies the phase continuity, angular frequency range, and current command limiting status after writing. After the verification is passed, the controller releases the mode flip lock, switches the mode flag to the grid-following flag value, and allows the d / q axis current command generated in grid-following mode to enter the unified current inner loop entry. Since the initial value of the current command feedforward is directly derived from the actual current at the trigger moment, and the initial value of the phase-locked loop integrator is directly derived from the current state of the virtual synchronous generator in grid-building mode, the grid-following mode does not need to undergo a long transient process of re-phase-locking when taking over, and the integrator state of the shared current inner loop does not need to be cleared or reset. Therefore, the state tracking pre-synchronization in the grid-to-grid-following direction can complete the control mode handover under the condition of continuous operation of the underlying modulation link, and reduce the risk of current surge, phase change, and modulation reference voltage jump at the moment of switching.

[0039] In one specific embodiment, such as Figure 4 The process of executing step S300 can specifically include the following steps: S301, calculate the first d-axis current command in grid-connected mode based on active power command and d-axis voltage, and calculate the first q-axis current command in grid-connected mode based on reactive power command and d-axis voltage; S302. Calculate the second d-axis current command of the network configuration mode based on the initial value of the d-axis integrator of the outer voltage loop, the d-axis voltage error, and the proportional coefficient of the outer voltage loop; and calculate the second q-axis current command of the network configuration mode based on the initial value of the q-axis integrator of the outer voltage loop, the q-axis voltage error, and the proportional coefficient of the outer voltage loop. S303. Based on the mode flag, the first d-axis current command and the second d-axis current command are sent to the same d-axis input of the current inner loop for selection, and the first q-axis current command and the second q-axis current command are sent to the same q-axis input of the current inner loop for selection, so as to obtain a unified d-axis current command and a unified q-axis current command.

[0040] Specifically, the controller reads the active power command, reactive power command, and d-axis voltage at the PCC point in each sampling cycle, and converts the power regulation target into the first d-axis current command and the first q-axis current command in grid-connected mode under grid orientation conditions. Since the grid-connected mode operates in grid-connected form as a current source, the current command generation path does not require an additional integration stage. Instead, it generates the current setpoint in real time based on the algebraic relationship between the power command and the d-axis voltage, which can be expressed as: ; ; in, Indicates the first The sampling period is the first d-axis current command of the grid mode, in A. Indicates the first The sampling period is the first q-axis current command of the grid mode, in A. This command represents active power, in watts (W). This represents the reactive power command, measured in var. To prevent the current command from being abnormally amplified due to the d-axis voltage at the PCC point being too low under voltage dips or sampling disturbances, the controller sets an effective calculation lower limit for the d-axis voltage before power conversion. For example, the effective calculation lower limit is set to 0.2 times the rated d-axis voltage. This value is mainly used to prevent excessive current commands when the denominator is close to zero, and forms a protection hierarchy with the aforementioned voltage dip threshold. In the event of significant grid anomalies, the switching judgment prioritizes guiding the system into the grid support process.

[0041] The controller invokes the initial values ​​of the voltage outer loop d-axis integrator and voltage outer loop q-axis integrator, which were written during the state tracking pre-synchronization phase, and combines them with the d-axis voltage error, q-axis voltage error, and voltage outer loop scaling factor of the current sampling period to generate the second d-axis current command and the second q-axis current command for the network configuration mode. The corresponding calculation relationship can be expressed as: ; The q-axis is controlled by the same mechanism. , and The second q-axis current command is calculated, where, The second d-axis current command, in amperes (A), indicates the meshing mode. This represents the state quantity of the d-axis integrator in the outer voltage loop, in A. This represents the state quantity of the voltage outer loop q-axis integrator, in A. This represents the voltage outer loop proportionality coefficient, with units of A / V; and These represent the d-axis and q-axis voltage reference values ​​in the network configuration mode, respectively, in V. The voltage outer loop proportional coefficient can be tuned according to the bandwidth separation principle, so that the response speed of the voltage outer loop is lower than that of the current inner loop. For example, the cutoff angular frequency of the voltage outer loop can be taken as one-tenth of the cutoff angular frequency of the current inner loop. This value is beneficial to maintain a clear distinction between the dynamic levels of the inner and outer loops and reduce the high-frequency disturbances caused to the current inner loop during the network voltage regulation process.

[0042] After calculating the two types of current commands, the current inner loop structure remains unchanged. Instead, based on the mode flag, the first d-axis current command and the first q-axis current command output in the grid-following mode, or the second d-axis current command and the second q-axis current command output in the network-forming mode, are sent to the same d-axis and q-axis inputs of the current inner loop. The same current inner loop continues to perform error adjustment, decoupling compensation, and modulation reference generation. Since the current commands in the grid-following and network-forming modes can be calculated synchronously in each sampling period, when the mode flag flips, only the source of the current command entering the unified input is changed. The current inner loop recursion process is not interrupted, nor is the underlying modulation link reset. Therefore, the unified d-axis current command and the unified q-axis current command can smoothly enter the subsequent control stage under pre-synchronization constraints.

[0043] In one specific embodiment, the process of executing step S303 may specifically include the following steps: When the mode flag is set to the grid flag value, the first d-axis current command is selected to the d-axis input of the current inner loop, and the first q-axis current command is selected to the q-axis input of the current inner loop, so as to obtain a unified d-axis current command and a unified q-axis current command. When the mode flag is set to the network flag value, the second d-axis current command is selected to the d-axis input of the inner current loop, and the second q-axis current command is selected to the q-axis input of the inner current loop, resulting in a unified d-axis current command and a unified q-axis current command.

[0044] Specifically, before the mode flag bit participates in the current command selection, the controller can set the grid flag value to 0 and the network flag value to 1, and simultaneously retain the latest calculation results of the first d-axis current command, the first q-axis current command, the second d-axis current command, and the second q-axis current command in each sampling period, so that when the mode flag bit is flipped, only the data source of the current inner loop entrance is changed, without changing the operation structure of the current inner loop itself.

[0045] When the mode flag is set to the grid-following flag value, the d-axis input selector connects the first d-axis current command to the d-axis input of the current inner loop, and the q-axis input selector connects the first q-axis current command to the q-axis input of the current inner loop. At this time, the unified d-axis current command and the unified q-axis current command are equal to the current commands converted from active power commands and reactive power commands in the grid-following mode, respectively. The subsequent current inner loop continues to perform closed-loop regulation according to the grid-following power regulation target. When the mode flag is set to the grid-building flag value, the d-axis input selector connects the second d-axis current command to the same d-axis input of the current inner loop, and the q-axis input selector connects the second q-axis current command to the same q-axis input of the current inner loop. At this time, the unified d-axis current command and the unified q-axis current command are equal to the current commands output by the voltage outer loop in the grid-building mode, respectively. The subsequent current inner loop continues to serve the grid-building voltage support target. The above selection process can be implemented using a two-to-one multiplexer or by using integer flag branching in the control program. For ease of software and hardware description unification, the selection relationship can be expressed as: ; ; in, Indicates the first The mode flag bit for each sampling period, a value of 0 indicates the following mode, and a value of 1 indicates the construct mode; This indicates a unified d-axis current command. This represents a unified q-axis current command, with units of A. Since the mode flag can only be 0 or 1, the gating calculation is equivalent to a hard-switching selection relationship in actual execution, without generating an interpolated transition current command. To ensure no input jitter occurs during gating, the controller can limit the mode flag flipping to the next sampling boundary after the state tracking neck synchronously completes the flag setting, and synchronously update the d-axis and q-axis input selectors within the same sampling period, ensuring consistent current command sources for both axes. After gating, the unified d-axis and q-axis current commands are directly written to the shared current inner loop input register. The current inner loop integrator, decoupling feedforward channel, and SVPWM modulation channel all maintain continuous recursion. Therefore, the switching between grid-following mode and grid-building mode is limited to the current command input level, reducing the risk of modulation voltage abrupt changes caused by overall control structure switching.

[0046] In one specific embodiment, such as Figure 5 The process of executing step S400 can specifically include the following steps: S401. Input the unified d-axis current command and the unified q-axis current command into the inner current loop and perform differential operation to obtain the d-axis modulation voltage reference value and the q-axis modulation voltage reference value. S402. Input the d-axis modulation voltage reference value and the q-axis modulation voltage reference value into the SVPWM modulation module for space vector pulse width modulation, and output the gate drive signal.

[0047] Specifically, after the unified d-axis current command and the unified q-axis current command have been written through the same current inner loop entry, the controller reads the measured values ​​of the d-axis current and the q-axis current at the PCC point according to a fixed sampling period. It then performs differential calculations between the unified d-axis current command and the measured d-axis current value, and between the unified q-axis current command and the measured q-axis current value, thereby forming the two-axis current deviation. Subsequently, the shared current inner loop performs proportional regulation, integral state recursion, and decoupling feedforward superposition based on the two-axis current deviation to obtain the d-axis modulation voltage reference value and the q-axis modulation voltage reference value. Since both grid-connected and grid-connected modes access the same inner current loop, the inner current loop does not need to re-establish an independent control link before and after mode switching, nor does it need to clear the integrator status of the inner current loop. The proportional regulation channel, integral recursion channel, cross-coupling compensation channel, and voltage feedforward channel all operate continuously according to the original control cycle. When the grid-connected flag value is valid, the inner current loop receives the unified current command converted from the power command. When the grid-connected flag value is valid, the inner current loop receives the unified current command generated by the voltage outer loop. Although the two sources correspond to different control objectives, the differential operation structure after entering the underlying current closed loop remains consistent. In implementation, the controller can fix the operation sequence of the inner current loop as follows: sample value reading, command value latching, current deviation calculation, proportional-integral regulation, decoupling feedforward compensation, modulation voltage limiting, and reference value output. The current deviation calculation result can also be judged by overcurrent limiting before entering the regulator. When the unified current command exceeds the allowable current boundary of the converter, the controller prioritizes the amplitude constraint of the unified current command to ensure that the modulation voltage reference value is within the range that the power devices and DC bus voltage can withstand.

[0048] The controller sends the d-axis and q-axis modulation voltage reference values ​​to the SVPWM modulation module and performs an inverse transformation based on the phase of the current synchronous rotating coordinate system. This converts the two-axis modulation voltage reference values ​​into spatial voltage vector references in a stationary coordinate system. The SVPWM modulation module then calculates the adjacent effective vector duration and zero vector duration based on the sector where the spatial voltage vector is located, and converts the duration into a three-phase bridge arm PWM comparison value. Finally, the PWM generator outputs the gate drive signal for the corresponding power switching device. Since the modulation voltage reference value comes from a continuously recursively shared current inner loop, the SVPWM modulation module does not need to switch independent modulators or reallocate PWM carrier counters and dead-time configurations during mode switching. The gate drive signal only changes naturally with the unified current command and the current inner loop adjustment result. The SVPWM modulation module can update the three-phase duty cycle in each carrier cycle and load the comparison register uniformly at the PWM counter reload boundary to avoid abnormal bridge arm drive pulse width caused by the modulation reference value being updated in the middle of the carrier. At the same time, the bus voltage normalization limit can be set before the modulation voltage reference value enters the SVPWM modulation module to prevent overmodulation distortion caused by the reference vector exceeding the linear modulation range.

[0049] In one specific embodiment, the process of executing step S401 may specifically include the following steps: The d-axis current error is obtained by subtracting the unified d-axis current command from the measured d-axis current value at the PCC point, and the q-axis current error is obtained by subtracting the unified q-axis current command from the measured q-axis current value at the PCC point. Multiply the d-axis current error by the proportional coefficient of the inner current loop and add the result to the state quantity of the d-axis integrator of the inner current loop to obtain the d-axis proportional-integral output of the inner current loop; multiply the q-axis current error by the proportional coefficient of the inner current loop and add the result to the state quantity of the q-axis integrator of the inner current loop to obtain the q-axis proportional-integral output of the inner current loop. The d-axis proportional-integral output is added to the d-axis decoupled feedforward voltage to obtain the d-axis modulation voltage reference value. The q-axis proportional-integral output is added to the q-axis decoupled feedforward voltage to obtain the q-axis modulation voltage reference value.

[0050] Specifically, after inputting the unified d-axis current command and unified q-axis current command into the current inner loop, the controller reads the measured d-axis current and q-axis current values ​​at the PCC point within the same sampling period. It then performs differential calculations using the unified current command as the target quantity and the measured current as the feedback quantity, thus generating the d-axis current error and q-axis current error. The current inner loop no longer distinguishes between the current command originating from the grid-following mode and the grid-building mode, but processes the two-axis current errors according to the same proportional-integral (PI) control structure, ensuring the continuity of the underlying closed-loop recursion before and after mode switching. The d-axis current error is first multiplied by the proportional coefficient of the current inner loop to obtain the d-axis proportional control component, and then superimposed on the d-axis integrator state quantity of the current inner loop to form the d-axis PI output. The q-axis current error is multiplied by the proportional coefficient of the current inner loop according to the same control cycle, and then superimposed on the q-axis integrator state quantity of the current inner loop to form the q-axis PI output. The corresponding current inner loop modulation voltage calculation relationship can be expressed as: ; ; in, and These represent the d-axis modulation voltage reference value and the q-axis modulation voltage reference value, respectively, in V; This represents the proportional coefficient of the inner current loop, with units of V / A; and These represent the state variables of the d-axis integrator and the q-axis integrator in the inner current loop, respectively, in units of V; Indicates the first The synchronous rotational angular frequency of each sampling period, in units of ; This represents the output filter inductance of the converter, in H (wattage). and These represent the d-axis voltage feedforward and q-axis voltage feedforward, respectively, in volts (V). In the above calculations, the proportional-integral (PI) output is used to quickly correct the deviation between the unified current command and the measured current; the cross-coupling compensation term is used to offset the coupling effect between the d-axis and q-axis in the synchronous rotating coordinate system; and the voltage feedforward is used to compensate for the influence of the PCC point voltage or the inverter output-side reference voltage on the modulation reference. After completing the PI output, the controller adds the d-axis PI output to the d-axis decoupling feedforward voltage to obtain the d-axis modulation voltage reference value; simultaneously, it adds the q-axis PI output to the q-axis decoupling feedforward voltage to obtain the q-axis modulation voltage reference value.

[0051] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0052] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause an electronic device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0053] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A dual-mode control method for grid-connected systems based on current command switching, characterized in that, include: Simultaneously sample the d / q axis current, d / q axis voltage, and phase-locked loop phase and angular frequency at the PCC point, and perform mode switching judgment to generate a switching trigger signal; Based on the switching trigger signal, the d / q axis current, the d / q axis voltage, the phase-locked loop phase, and the angular frequency are forcibly injected into the initial values ​​of all integrators in the corresponding mode to complete the state tracking pre-synchronization; The first d-axis current command and the first q-axis current command in the grid-following mode are calculated separately and then converged with the second d-axis current command and the second q-axis current command in the grid-forming mode to the same current inner loop entrance to obtain a unified d-axis current command and a unified q-axis current command. The unified d-axis current command and the unified q-axis current command are input into the corresponding current inner loop for differential operation, and the gate drive signal is output.

2. The dual-mode control method for grid-connected networks based on current command switching according to claim 1, characterized in that, The synchronous sampling of the d / q axis current, d / q axis voltage, and phase-locked loop phase and angular frequency at the PCC point is used to determine mode switching and generate a switching trigger signal, including: Simultaneously sample the d / q axis current, d / q axis voltage, and phase-locked loop phase and angular frequency at the PCC point; The mode switching is determined based on the d / q axis voltage and the phase-locked loop phase, and a switching trigger signal is generated.

3. The dual-mode control method for grid-connected networks based on current command switching according to claim 2, characterized in that, The step of determining the mode switching based on the d / q axis voltage and the phase-locked loop phase, and generating a switching trigger signal, includes: The effective voltage value of the PCC point is calculated based on the d / q axis voltage; the phase-locked loop phase error is obtained by subtracting the phase of the phase-locked loop from the actual phase of the power grid. The effective voltage value is compared with the voltage drop threshold. When the effective voltage value is lower than the voltage drop threshold and the duration exceeds the first holding period, a switching trigger signal for grid-to-grid conversion is generated. The phase error of the phase-locked loop is compared with the phase error threshold. When the phase error of the phase-locked loop exceeds the phase error threshold and the duration exceeds the first holding period, a switching trigger signal for the grid-to-grid conversion is generated. The effective voltage value is compared with the voltage recovery threshold, and the phase-locked loop phase error is compared with the phase error recovery threshold. When the effective voltage value is higher than the voltage recovery threshold and the phase-locked loop phase error is lower than the phase error recovery threshold, and the conditions are met simultaneously and the duration exceeds the second holding period, a switching trigger signal for network construction to network following is generated.

4. The dual-mode control method for grid-connected networks based on current command switching according to claim 3, characterized in that, The process of forcibly injecting the d / q axis current, d / q axis voltage, and phase-locked loop phase and angular frequency into the initial values ​​of all integrators in the corresponding mode based on the switching trigger signal to complete state tracking pre-synchronization includes: When the switching trigger signal for the grid-to-network conversion is received, the d / q axis current, the d / q axis voltage, the phase-locked loop phase, and the angular frequency are forcibly injected into the initial values ​​of all integrators in the grid-to-network conversion mode to complete the state tracking pre-synchronization of the grid-to-network conversion direction. Upon receiving the switching trigger signal from mesh formation to mesh following, the d / q axis current and the angular frequency are forcibly injected into the initial values ​​of all integrators in the mesh following mode to complete the state tracking pre-synchronization of the mesh formation to mesh following direction.

5. The dual-mode control method for grid-connected networks based on current command switching according to claim 4, characterized in that, Upon receiving the switching trigger signal for the grid-to-network conversion, the initial values ​​of all integrators in the grid-building mode are forcibly injected with the d / q axis current, d / q axis voltage, phase-locked loop phase, and angular frequency to complete the state tracking pre-synchronization in the grid-to-network conversion direction, including: When a switching trigger signal for grid-to-grid conversion is received, the phase-locked loop phase is forcibly injected into the initial value of the phase integrator of the virtual synchronous generator in grid-connection mode, and the angular frequency is forcibly injected into the initial value of the angular frequency integrator of the virtual synchronous generator in grid-connection mode. The initial value of the voltage outer loop d-axis integrator in the network construction mode is calculated based on the d-axis current and d-axis voltage, the d-axis voltage reference value, and the voltage outer loop scaling factor. At the same time, the initial value of the voltage outer loop q-axis integrator in the network construction mode is calculated based on the q-axis current and q-axis voltage, the q-axis voltage reference value, and the voltage outer loop scaling factor. These values ​​are then forcibly injected into the voltage outer loop d / q-axis integrators in the network construction mode to complete the state tracking pre-synchronization in the direction of network transition from following the grid to network construction.

6. The dual-mode control method for grid-connected networks based on current command switching according to claim 5, characterized in that, Upon receiving the switching trigger signal from mesh formation to mesh following, the d / q axis current and the angular frequency are forcibly injected into the initial values ​​of all integrators in the mesh following mode to complete the state tracking pre-synchronization in the mesh formation to mesh following direction, including: Force the d-axis current to be injected into the initial value of the d-axis current command feedforward in the meshing mode, and force the q-axis current to be injected into the initial value of the q-axis current command feedforward in the meshing mode. The current output phase and current output angular frequency of the virtual synchronous generator corresponding to the network configuration mode are read. The current output phase is forcibly injected into the initial value of the phase-locked loop phase integrator, and the current output angular frequency is forcibly injected into the initial value of the phase-locked loop angular frequency integrator, thus completing the state tracking pre-synchronization of the network configuration to the grid following direction.

7. The dual-mode control method for grid-connected networks based on current command switching according to claim 6, characterized in that, The process of separately calculating the first d-axis current command and the first q-axis current command in the grid-following mode and converging them with the second d-axis current command and the second q-axis current command in the network-forming mode to the same current inner loop inlet, thereby obtaining a unified d-axis current command and a unified q-axis current command, includes: The first d-axis current command in grid-connected mode is calculated based on the active power command and d-axis voltage, and the first q-axis current command in grid-connected mode is calculated based on the reactive power command and d-axis voltage. The second d-axis current command of the network configuration mode is calculated based on the initial value of the d-axis integrator of the outer voltage loop, the d-axis voltage error, and the voltage outer loop scaling factor; and the second q-axis current command of the network configuration mode is calculated based on the initial value of the q-axis integrator of the outer voltage loop, the q-axis voltage error, and the voltage outer loop scaling factor. Based on the mode flag, the first d-axis current command and the second d-axis current command are sent to the same d-axis input of the current inner loop for selection, and the first q-axis current command and the second q-axis current command are sent to the same q-axis input of the current inner loop for selection, so as to obtain a unified d-axis current command and a unified q-axis current command.

8. The dual-mode control method for grid-connected networks based on current command switching according to claim 7, characterized in that, The step of selecting the first d-axis current command and the second d-axis current command by sending them to the same d-axis input of the current inner loop, and selecting the first q-axis current command and the second q-axis current command to the same q-axis input of the current inner loop, based on the mode flag bit, to obtain a unified d / q-axis current command, includes: When the mode flag is set to the net flag value, the first d-axis current command is selected to the d-axis input of the current inner loop, and the first q-axis current command is selected to the q-axis input of the current inner loop, so as to obtain a unified d-axis current command and a unified q-axis current command. When the mode flag is set to the network flag value, the second d-axis current command is selected to the d-axis input of the inner current loop, and the second q-axis current command is selected to the q-axis input of the inner current loop, resulting in a unified d-axis current command and a unified q-axis current command.

9. The dual-mode control method for grid-connected networks based on current command switching according to claim 8, characterized in that, The step of inputting the unified d-axis current command and the unified q-axis current command into the corresponding current inner loop for differential operation and outputting a gate drive signal includes: The unified d-axis current command and the unified q-axis current command are input into the inner current loop and differentially calculated to obtain the d-axis modulation voltage reference value and the q-axis modulation voltage reference value. The d-axis modulation voltage reference value and the q-axis modulation voltage reference value are input into the SVPWM modulation module for space vector pulse width modulation, and the gate drive signal is output.

10. The dual-mode control method for grid-connected networks based on current command switching according to claim 9, characterized in that, The step of performing differential operations on the input current inner loop of the unified d-axis current command and the unified q-axis current command to obtain the d-axis modulation voltage reference value and the q-axis modulation voltage reference value includes: The d-axis current error is obtained by subtracting the unified d-axis current command from the measured d-axis current value at the PCC point, and the q-axis current error is obtained by subtracting the unified q-axis current command from the measured q-axis current value at the PCC point. The d-axis current error is multiplied by the proportional coefficient of the inner current loop and then added to the state quantity of the d-axis integrator of the inner current loop to obtain the d-axis proportional integral output of the inner current loop; the q-axis current error is multiplied by the proportional coefficient of the inner current loop and then added to the state quantity of the q-axis integrator of the inner current loop to obtain the q-axis proportional integral output of the inner current loop. The d-axis proportional-integral output is added to the d-axis decoupled feedforward voltage to obtain the d-axis modulation voltage reference value; the q-axis proportional-integral output is added to the q-axis decoupled feedforward voltage to obtain the q-axis modulation voltage reference value.

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