Electronic device and power supply method

Abstract

The embodiment of the application discloses electronic equipment and a power supply method, and relates to the field of integrated circuits. The electronic equipment comprises a controller, a switching circuit and a chip. The chip comprises a service monitoring unit and a service processing unit. The service monitoring unit is used for monitoring service data, and in the case that a data flow change of the service data is detected, a target signal indicating the data flow change is generated, and the target signal is provided to the controller. The controller is used for generating a current parameter corresponding to the target signal based on the target signal, and controlling the switching circuit to output a power supply voltage to the chip according to the current parameter. The service processing unit is used for processing the service data based on the power supply voltage. The electronic equipment and the power supply method provided by the embodiment of the application can quickly adjust the power supply voltage output to the chip, and improve the performance of the chip.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and more particularly to an electronic device and a power supply method. Background Technology

[0002] In existing electronic devices, a power controller is usually provided. Various chips in the electronic device (such as communication chips, artificial intelligence chips, etc.) are connected to the power controller. The power controller provides voltage to each chip based on the power consumption of each chip.

[0003] Typically, the operating current of a chip changes dynamically. For example, an increase in chip workload can cause a sudden increase in chip current, or a sudden decrease in chip current due to internal operating conditions. These changes in chip current lead to changes in the chip's input voltage. In existing technologies, power controllers usually acquire the chip's input voltage and adjust the chip's supply voltage accordingly. However, power controllers cannot respond to changes in chip current in a timely manner, resulting in a drop in the chip's input voltage during scenarios with sudden increases in chip current. When the input voltage drop is too large, causing the chip's input voltage to fall below its minimum operating voltage, the chip cannot function properly. Therefore, improving the power controller's response speed to changes in chip current to improve chip performance becomes a problem that needs to be solved. Summary of the Invention

[0004] The electronic device and power supply method provided in this application can quickly adjust the power supply voltage output to the chip, thereby improving the chip's performance. To achieve the above objectives, the embodiments of this application adopt the following technical solutions:

[0005] In a first aspect, embodiments of this application provide an electronic device, which includes a controller, a switching circuit, and a chip; the chip includes a service monitoring unit and a service processing unit; the service monitoring unit is used to monitor service data, and when a change in the data flow of the service data is detected, to generate a target signal indicating the change in data flow, and to provide the target signal to the controller; the controller is used to generate a current parameter corresponding to the target signal based on the target signal, and to control the switching circuit to output a power supply voltage to the chip according to the current parameter; the service processing unit is used to process the service data based on the power supply voltage.

[0006] The electronic device provided in this application embodiment has a service monitoring unit in the chip that sends a target signal indicating changes in data flow to the controller. Based on the current parameters corresponding to the target signal, the unit can control the voltage output by the switching circuit. Since there is a time delay between the chip receiving service data and starting to process the service data, the chip directly sends the target signal to the controller based on the changes in data flow. The controller directly controls the voltage output by the switching circuit based on the target signal. Thus, the controller can respond quickly to the chip within the time delay and provide the required current to the chip within the time delay. Therefore, compared with the prior art, the power supply voltage output by the switching circuit to the chip can be quickly adjusted, which is beneficial to improving the stability and reliability of the chip operation.

[0007] In one possible implementation, the chip is specifically used to: encode the changed data flow and generate a target signal based on the encoding result. In other words, the target signal is obtained by encoding the changed data flow. By encoding the changed data flow, the magnitude of the data flow can be clearly indicated, allowing the power management unit to more accurately determine the chip's current requirements and thus more accurately adjust the supply voltage output to the chip.

[0008] In one possible implementation, the controller is specifically used to: obtain the current parameter corresponding to the target signal from a preset mapping relationship between signal and current parameters, and generate a control signal using the current parameter; and a switching circuit, based on the control signal, outputs a power supply voltage to the chip.

[0009] In one possible implementation, the current parameters include the current magnitude and at least one of the following: the rate of change of current and the delay time; wherein the delay time is the time from when the controller receives the target signal to when the current in the chip begins to rise; the rate of change of current is the ratio of the amount of change of current to the time of change of current, and the time of change of current is the time from when the current in the chip begins to change until it reaches its maximum value.

[0010] Typically, due to the time delay of current surges in a chip, if the power management unit (PMU) immediately provides all the current required by the chip in response to the target signal, the input voltage to the chip may surge before the aforementioned time delay has elapsed, potentially damaging the chip or reducing its lifespan. Therefore, the PMU also generates a control signal based on at least one of the delay time and the rate of current change, thereby gradually providing the chip with the required current within the delay time, thus improving chip lifespan.

[0011] In one possible implementation, the chip includes a first interface, the controller includes a second interface, and the service monitoring unit is specifically used to send target signals to the controller through the first interface and the second interface; wherein the first interface and the second interface each include one of the following: an adaptive voltage regulation interface or a power management bus interface.

[0012] In one possible implementation, the chip includes at least one of the following: a communication chip, an optical switching chip, a central processing unit chip, a graphics processing unit chip, a neural network processor chip, an image signal processor chip, or a digital signal processor chip.

[0013] Secondly, embodiments of this application provide a power management unit, which includes a controller and a switching circuit; the controller is used to receive a target signal from a chip, generate current parameters based on the target signal, and control the switching circuit using the current parameters; wherein the target signal is used to indicate changes in the data flow of service data in the chip; the switching circuit is used to output a power supply voltage to the chip based on the control of the controller.

[0014] In the power management unit provided in this application embodiment, the controller in the power management unit receives a target signal indicating a change in data flow from the chip, and can then control the voltage output by the switching circuit based on the current parameters corresponding to the target signal. Since there is a time delay between the chip receiving service data and starting to process the service data, the chip directly sends the target signal to the power management unit based on the data flow, and the power management unit directly controls the voltage output by the switching circuit based on the target signal. Thus, the power management unit can respond quickly to the chip within the aforementioned time delay to provide the required current to the chip within the aforementioned time delay. Therefore, compared with the prior art, the response delay of the power management unit can be greatly reduced, which is beneficial to improving the stability and reliability of chip operation.

[0015] In one possible implementation, the controller is specifically used to: obtain the current parameter corresponding to the target signal from a preset mapping relationship between signal and current parameters, and generate a control signal using the current parameter; and a switching circuit, based on the control signal, outputs a power supply voltage to the chip.

[0016] By pre-setting the mapping relationship, the current parameters can be obtained from the preset mapping relationship between signal and current parameters. The controller can quickly obtain the current parameters, which can further improve the response speed to changes in chip current.

[0017] In one possible implementation, the current parameters include the current magnitude and at least one of the following: the rate of change of current and the delay time; wherein the delay time is the time from when the controller receives the target signal to when the current in the chip begins to rise; the rate of change of current is the ratio of the amount of change of current to the time of change of current, and the time of change of current is the time from when the current in the chip begins to change until it reaches its maximum value.

[0018] Typically, due to the time delay of current surges in a chip, if the power management unit (PMU) immediately provides all the current required by the chip in response to the target signal, the input voltage to the chip may surge before the aforementioned time delay has elapsed, potentially damaging the chip or reducing its lifespan. Therefore, the PMU also generates a control signal based on at least one of the delay time and the rate of current change, thereby gradually providing the chip with the required current within the delay time, thus improving chip lifespan.

[0019] In one possible implementation, the power management unit includes an interface through which the controller can specifically receive target signals. The interface may include an adaptive voltage regulation interface or a power management bus interface.

[0020] In one possible implementation, the controller includes a voltage loop and a control unit; the voltage loop is used to: read the supply voltage output by the switching circuit, and generate control parameters based on the difference between the supply voltage and a preset reference voltage, the control parameters including at least one of the duty cycle and conduction time of the switching element in the switching circuit; the controller is used to: receive a target signal from the chip, obtain current parameters from the mapping relationship, and generate a control signal using the control parameters and the current parameters.

[0021] In one possible implementation, the control unit can compare the magnitude of the current generated based on the target signal with the current magnitude. If the current level does not change, the control signal and control parameters are the same, that is, the control unit directly provides the control parameters to the switching circuit. If the current level changes, the control unit can generate a control signal based on the current parameters (for example, a mapping relationship between control signals and current parameters is preset, and the control signal corresponding to the current parameters is read).

[0022] By setting up a voltage loop and a control unit in the controller, the structure of the existing power management unit can be slightly modified. This allows the voltage loop to add a control unit module without being aware of the control unit. The control unit module can then receive target signals and generate control signals, thereby reducing the cost of the power management unit.

[0023] In one possible implementation, the controller includes a voltage loop, a control unit, and a current loop. The voltage loop is used to: read the supply voltage output by the switching circuit and generate a first reference current signal based on the difference between the supply voltage and a preset reference voltage. The control unit is used to: receive a target signal from the chip, obtain current parameters from the mapping relationship, generate a second reference current signal using the control parameters, and generate a third reference current signal based on the first and second reference current signals, which is then provided to the current loop. The current loop is used to: collect feedback current from the switching circuit and generate a control signal based on the feedback current and the third reference current signal.

[0024] In one possible implementation, the control unit can compare the current magnitude generated based on the target signal with the current magnitude. If the current level has not changed, the first reference current signal and the third reference current signal are the same, and the control unit directly provides the first reference current signal to the current loop. If the current level changes, the control unit can generate a second reference current signal based on the current parameters (for example, a mapping relationship between the second reference current signal and the current parameters is preset, and the second reference current signal corresponding to the current parameters is read), and then provide the second reference current signal to the current loop.

[0025] By setting up voltage loops, control units, and current loops in the controller, the structure of existing power management units can be slightly modified. This allows the voltage and current loops to add control unit modules without being aware of the control unit. The control unit modules can then receive target signals and generate reference current signals for the current loop, thereby reducing the cost of the power management unit.

[0026] In one possible implementation, the chip includes at least one of the following: a communication chip, an optical switching chip, a central processing unit chip, a graphics processing unit chip, a neural network processor chip, an image signal processor chip, or a digital signal processor chip.

[0027] Thirdly, embodiments of this application provide a chip, which includes a service monitoring unit and a service processing unit; the service monitoring unit is used to monitor service data, and when a change in the data traffic of the service data is detected, to generate a target signal indicating the change in data traffic, and to provide the target signal to a power management unit; the service processing unit is used to process the service data based on the power supply voltage provided by the power management unit.

[0028] Typically, there is a time delay between the receipt of service data by the controller and the commencement of processing by the service processing unit. After receiving the service data, the chip generates a target signal corresponding to the data flow within a preset time period (e.g., one clock cycle or one counter cycle) and provides it to the power management unit. The power management unit can then respond quickly to the chip within the aforementioned time delay based on the current parameters corresponding to the target signal, thereby providing the required current to the chip within that time delay. Compared to existing technologies, this significantly reduces the response latency of the power management unit, improving the stability and reliability of the chip's operation.

[0029] In one possible implementation, the service processing unit includes multiple units; the service monitoring unit is also used to: select a target service processing unit among the multiple service processing units; the target service processing unit is used to process service data based on the power supply voltage.

[0030] In one possible implementation, the chip also includes a cache; the controller is further configured to store business data in the cache; and the target business unit is specifically configured to read business data from the cache and process the business data.

[0031] In one possible implementation, the chip includes an interface through which the service monitoring unit can send target signals. The interface may include an adaptive voltage regulation interface or a power management bus interface.

[0032] In one possible implementation, the chip includes at least one of the following: a communication chip, an optical switching chip, a central processing unit chip, a graphics processing unit chip, a neural network processor chip, an image signal processor chip, or a digital signal processor chip.

[0033] Fourthly, embodiments of this application provide a power supply method, which includes: a service monitoring unit in a chip monitoring service data; generating a target signal indicating the change in data traffic when a change in the data traffic of the service data is detected; and providing the target signal to a controller; the controller generating a current parameter corresponding to the target signal based on the target signal; and controlling a switching circuit to output a power supply voltage to the chip according to the current parameter; and a service processing unit in the chip processing the service data based on the power supply voltage.

[0034] In one possible implementation, generating a target signal indicating changes in data traffic includes: encoding the changed data traffic and generating the target signal based on the encoding result.

[0035] In one possible implementation, the controller generates current parameters corresponding to the target signal based on the target signal, and controls the switching circuit in the power management unit according to the current parameters, including: the controller obtains the current parameters corresponding to the target signal from a preset mapping relationship between signals and current parameters, generates a control signal using the current parameters, and provides the switching circuit to the switching circuit.

[0036] In one possible implementation, the current parameters include the current magnitude and at least one of the following: the rate of change of current and the delay time; wherein the delay time is the time from when the controller receives the target signal to when the current in the chip begins to rise; the rate of change of current is the ratio of the amount of change of current to the time of change of current, and the time of change of current is the time from when the current in the chip begins to change until it reaches its maximum value.

[0037] Fifthly, embodiments of this application provide a power supply method applied to a power management unit. The power supply method includes: receiving a target signal from a chip by a controller, generating current parameters based on the target signal, and controlling a switching circuit using the current parameters; wherein the target signal is used to indicate changes in the data flow of service data in the chip; and the switching circuit outputs a power supply voltage to the chip based on the control of the controller.

[0038] In one possible implementation, the current parameters include the current magnitude and at least one of the following: the rate of change of current and the delay time; wherein the delay time is the time from when the processor receives the target signal to when the current in the chip begins to rise; the rate of change of current is the ratio of the amount of change of current to the time of change of current, and the time of change of current is the time from when the current in the chip begins to change until it reaches its maximum value.

[0039] In one possible implementation, the controller receives a target signal from the chip, generates current parameters based on the target signal, and controls the switching circuit using the current parameters. This includes: the controller obtaining the current parameters corresponding to the target signal from a preset mapping relationship between signals and current parameters, generating a control signal using the current parameters, and providing the switching circuit to the switching circuit.

[0040] In one possible implementation, generating a control signal using current parameters includes: reading the supply voltage output by the switching circuit; generating control parameters based on the difference between the supply voltage and a preset reference voltage; the control parameters including at least one of the duty cycle and conduction time of the switching element in the switching circuit; receiving a target signal from the chip; obtaining current parameters from the mapping relationship; and generating a control signal using the control parameters and the current parameters.

[0041] In one possible implementation, generating a control signal using current parameters includes: reading the supply voltage output by the switching circuit, generating a first reference current signal based on the difference between the supply voltage and a preset reference voltage; generating a second reference current signal using control parameters, generating a third reference current signal based on the first and second reference current signals and providing it to the current loop; acquiring feedback current from the switching circuit, and generating a control signal based on the feedback current and the third reference current signal.

[0042] Sixthly, embodiments of this application provide a power supply method applied to a chip. The power supply method includes: a service monitoring unit monitoring service data, and generating a target signal indicating the change in data traffic when a change in the data traffic of the service data is detected, and providing the target signal to a power management unit; and a service processing unit processing the service data based on the power supply voltage provided by the power management unit.

[0043] In one possible implementation, the power supply method further includes: the service monitoring unit selecting a target service processing unit from among multiple service processing units; and the target service processing unit processing the service data.

[0044] In a seventh aspect, embodiments of this application also provide a computer-readable storage medium for storing a computer program, which, when executed by an electronic device, is used to implement the methods described in the fourth to sixth aspects or any possible implementation thereof.

[0045] Eighthly, embodiments of this application also provide a computer program product, which, when executed by an electronic device, is used to implement the methods described in the fourth to sixth aspects or any possible implementation thereof.

[0046] It should be understood that aspects four through eight of this application are consistent with the technical solutions of aspects one through three of this application, and the beneficial effects achieved by each aspect and the corresponding feasible implementation are similar, and will not be repeated here. Attached Figure Description

[0047] Figure 1A This is a schematic diagram of a power management unit in the related technology provided in the embodiments of this application;

[0048] Figure 1B The embodiments provided in this application are as follows Figure 1A The waveform diagrams shown are of the chip current, the output current of the power management unit, and the output voltage.

[0049] Figure 2 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application;

[0050] Figure 3 This is a schematic diagram illustrating the mapping relationship between data traffic and target signals provided in an embodiment of this application;

[0051] Figure 4 This is a schematic diagram illustrating the mapping relationship between the target signal and the current provided in the embodiments of this application;

[0052] Figure 5 This is a flowchart illustrating the interaction between various components in the electronic device provided in the embodiments of this application;

[0053] Figure 6 This is a schematic diagram illustrating the mapping relationship between the control signal and the current change, delay time, and current change rate provided in the embodiments of this application;

[0054] Figure 7 This is a schematic diagram of the structure of a chip provided in an embodiment of this application;

[0055] Figure 8 This is a schematic diagram of a power management unit provided in an embodiment of this application;

[0056] Figure 9 This is yet another structural schematic diagram of the power management unit provided in the embodiments of this application;

[0057] Figure 10 This is a flowchart of a power supply method provided in an embodiment of this application. Detailed Implementation

[0058] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the embodiments of this application.

[0059] The terms "first" and "second," etc., in the specification and drawings of the embodiments of this application are used to distinguish different objects or to distinguish different treatments of the same object, rather than to describe a specific order of objects.

[0060] Furthermore, the terms "comprising" and "having," and any variations thereof, used in the description of the embodiments of this application are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the steps or units listed, but may optionally include other steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or devices.

[0061] It should be noted that in the description of the embodiments of this application, the words "exemplarily" or "for example" are used to indicate examples, illustrations, or explanations. Any embodiment or design scheme described as "exemplarily" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design schemes. Specifically, the use of the words "exemplarily" or "for example" is intended to present the relevant concepts in a specific manner.

[0062] In the description of the embodiments of this application, unless otherwise stated, "a plurality of" means two or more.

[0063] In existing technologies, the operating current of a chip changes dynamically. For example, an increase in chip workload can cause a sudden increase in chip current; conversely, a sudden decrease in chip current may occur due to internal operating conditions. These changes in chip current lead to changes in the chip's input voltage. Existing technologies typically employ various methods to adjust the chip's input voltage in response to these current variations. Please refer to [reference needed]. Figure 1A , Figure 1A This is a schematic diagram of a power management unit in the related technology provided in the embodiments of this application. For example... Figure 1A As shown, the power management unit includes a voltage loop and a power circuit. The voltage loop is used to input a reference voltage and a feedback voltage, which is the voltage output from the power management unit's output terminal vo, and also the voltage input to the chip's power supply terminal. The voltage loop compares the reference voltage and the feedback voltage, and adjusts the switching elements in the power circuit based on the comparison result to regulate the chip's input voltage.

[0064] When the chip current suddenly increases, there is usually a delay between the change in chip current and the voltage loop detecting the voltage drop. Furthermore, the voltage loop typically adjusts the voltage slowly. When the difference between the chip's reference voltage and the feedback voltage is large, the voltage loop cannot immediately adjust the voltage output by the power management unit to the target value (i.e., the reference voltage), requiring a certain amount of time to slowly adjust to the target value, thus incurring a delay. These various delays cause the power management unit to be unable to respond to sudden changes in chip current, resulting in a significant drop in the chip's input voltage, potentially falling below the chip's minimum supply voltage. Figure 1B As shown, Figure 1B The diagram schematically illustrates the current demand waveform of the chip, the current waveform output by the power management unit 01 to the chip, and the voltage waveform supplied by the power management unit 01 to the chip. Figure 1BAs can be seen, during time period t1, the chip current suddenly increases; the current supplied by the power management unit 01 to the chip does not change during time period t1, meaning there is a delay of time period t1. After a delay of time period t2 following the increase in chip current, the current supply capability of the power management unit 01 to the chip begins to change, and it is not until time period t3 that the chip's current requirement is met. Therefore, during the period from time period t1 to time period t3, the voltage supplied by the power management unit 01 to the chip drops. When the voltage drops below the minimum supply voltage, the chip cannot function normally. Therefore, improving the response speed of the power management unit to changes in chip current, thereby improving chip performance, becomes a problem that needs to be solved.

[0065] In the electronic device provided in this application embodiment, the load generates a target signal based on the data flow of service data and provides it to the power management unit. The processor in the power management unit can then generate a control signal based on the current corresponding to the target signal to control the voltage output by the switching circuit. Since there is a time delay between the load chip receiving the service data and starting to process the service data, the load chip directly sends the target signal to the power management unit based on the data flow, and the power management unit directly controls the voltage output by the switching circuit based on the target signal. Thus, the power management unit can quickly respond to the load chip within the aforementioned time delay to provide the required current to the load chip within the aforementioned time delay. Therefore, compared with the prior art, the response delay of the power management unit can be greatly reduced, which is beneficial to improving the stability and reliability of the load chip's operation.

[0066] The electronic devices provided in this application embodiment may include, but are not limited to: digital communication devices, optical communication devices, intelligent computing devices (e.g., including but not limited to: artificial intelligence devices or general-purpose processor devices), server devices, or terminal devices. Terminal devices may include, but are not limited to: mobile phones, tablet computers, personal computers, handheld computers, mobile internet devices (MID), cameras, wearable devices (e.g., smartwatches, smart bracelets, pedometers, etc.), audio equipment, audio / video players, set-top boxes, game consoles, printers, mice, keyboards, in-vehicle equipment (e.g., devices on vehicles such as cars, airplanes, ships, trains, and high-speed trains), virtual reality (VR) devices, augmented reality (AR) devices, wireless terminals in industrial control, smart home devices (e.g., refrigerators, televisions, air conditioners, electricity meters, etc.), intelligent robots, workshop equipment, wireless terminals in self-driving, wireless terminals in remote medical surgery, wireless terminals in smart grids, wireless terminals in transportation safety, and smart city technologies. Wireless terminals in a city, or wireless terminals in a smart home, flying equipment (e.g., intelligent robots, hot air balloons, drones), etc.

[0067] Please refer to Figure 2 , Figure 2 This is a schematic diagram of the structure of the electronic device 100 provided in an embodiment of this application. For example... Figure 2 The illustrated electronic device 100 includes a power management unit (PMU) 10 and a load. The power management unit 10 can be any type of electronic component; for example, the PMU 10 can be a chip or chipset, or a circuit board with a chipset mounted on it, etc., and this embodiment is not limited in this respect. Optionally, the components included in the PMU 10 shown in this embodiment can be integrated into one or more chips, and these one or more chips can be placed in a chipset. Optionally, the components included in the PMU 10 (e.g.) Figure 2The controller 11 and switching circuit 12 shown can be integrated into the same chip, which can be called a power management chip. The load can include various types of components, such as, but not limited to, communication components, optical switching components, or intelligent computing components. In one possible implementation, each of the above-mentioned load components can be one or more chips, such as a communication chip, an optical switching chip, a central processing unit (CPU) chip, a graphics processing unit (GPU) chip, a neural network processing unit (NPU) chip, an image signal processor (ISP) chip, or a digital signal processor (DSP). The PMU 10 can supply power to the various types of loads described above. It should be noted that, in the embodiments of this application, the PMU 10 supplying power to the load can be understood as the PMU 10 outputting a power supply voltage to the load. Figure 2 In the electronic device 100 shown, the case where the load is a chip 20 is schematically illustrated. In the embodiments of this application, the following description takes a chip as the load, but it is not intended to limit the solution.

[0068] like Figure 2As shown, PMU10 includes a voltage output terminal vo and a signal receiving terminal v11; chip 20 includes a power supply input terminal vd and a signal output terminal v21. The voltage output terminal vo of PMU10 is connected to the power supply input terminal vd of chip 20 through electronic circuit S1. PMU10 outputs a power supply voltage to chip 20 through the voltage output terminal vo and electronic circuit S1. The signal receiving terminal v11 of PMU10 is connected to the signal output terminal v21 of chip 20 through electronic circuit S2. Chip 20 sends a target signal to PMU10 through the signal output terminal v21 and electronic circuit S2. The aforementioned electronic circuit S1 and electronic circuit S2 can be, for example, patterned conductive lines. Optionally, the patterned conductive lines can be, for example, metal lines formed by etching metal (e.g., copper). It should be noted that in this embodiment, the signal receiving terminal v11 may include one or more ports, and similarly, the signal output terminal v21 of chip 20 may also include one or more ports. When the signal receiver v11 includes multiple ports, the number of ports in the signal output terminal v21 is the same as the number of ports in the signal receiver v11, and they are connected one-to-one. Furthermore, the number of ports in both the signal receiver v11 and the signal output terminal v21 can be set based on the number of bits in the target signal. The figure schematically shows that both the signal receiver v11 and the signal output terminal v21 have two ports, meaning the target signal can include two bits, but this is not intended to limit the scheme. Further, the signal receiver v11 and the signal output terminal v21 can be analog circuit ports, so that each port in the signal output terminal v21 can send an analog signal to the corresponding port in the signal receiver v11. The analog circuit port can be, for example, an analog voltage port or an analog current port. When the signal receiving end v11 and the signal output end v21 are analog voltage ports, the signal transmitted from the signal output end v21 to the signal receiving end v11 through the electronic circuit S2 can be a voltage signal, such as a high-level signal (equivalent to "1") or a low-level signal (equivalent to "0"). When the signal receiving end v11 and the signal output end v21 are analog current ports, the signal transmitted from the signal output end v21 to the signal receiving end v11 through the electronic circuit S2 can be a current signal, such as a current signal (equivalent to "1") or a no-current signal (equivalent to "0").

[0069] Figure 2In the illustrated embodiment, PMU10 schematically receives a target signal from chip 20 via electronic circuit S2. In this embodiment, chip 20 can also send the target signal to PMU10 in many other possible ways. In one possible implementation, electronic device 100 may also include a bus, and both PMU10 and chip 20 can be connected to the bus. Thus, chip 20 can send the target signal to PMU10 via the bus. In this possible implementation, the bus can replace the aforementioned electronic circuit S2 as the signal transmission path, and the signal can be a digital signal (also called a software instruction signal), which may be, for example, multiple bits. When chip 20 sends the target signal to PMU10 via the bus, the interface between the signal output terminal v21 of chip 20 and the signal receiving terminal v11 of PMU10 may include, but is not limited to, an adaptive voltage scaling (AVS) interface or a power management bus (PMBus) interface. In addition, in other possible implementations, chip 20 can also send signals to PMU10 via wireless communication (such as WIFI, Bluetooth, and other short-range communication methods), and the signal can also be a digital signal including multiple bits. Furthermore, in this embodiment, the target signal can also include more bits, such as 3 bits or 8 bits. This embodiment describes an example where chip 20 sends a target signal to PMU10 through signal output terminal v21 and electronic circuit S2, and the target signal is 2 bits, but this is not intended to limit the solution.

[0070] In this embodiment, chip 20 may include a service monitoring unit 21 and a service processing unit 22. The service monitoring unit 21 may be connected to the signal output terminal v21 of chip 20. Furthermore, chip 20 may include more ports, at least some of which may be used to receive service data from external sources (e.g., coupled upstream chips or components). The figure schematically shows chip 20 further including ports v22 and v23, and these two ports are used to receive service data from external sources. It is understood that chip 20 may also include more types of ports, and the number of ports used to receive service data may be more or less; this embodiment does not specifically limit this. The service monitoring unit 21 may also be connected to ports v22 and v23, thereby enabling real-time or periodic monitoring of the data flow of service data received by ports v22 and v23. When a change in the data flow of service data is detected, a target signal is generated, and then the target signal is sent to PMU10 via electronic circuit S2. The service processing unit 22 is used to process the services input to chip 20. In one possible implementation, the service monitoring unit 21 can also send a start signal to the service processing unit 21 to instruct the service processing unit to process the service data. A more detailed structural reference for chip 20 is provided below. Figure 7 The example shown.

[0071] The service monitoring unit 21 can encode data traffic into one or more bits based on the size of the data traffic. For example, the data traffic can be divided into four levels, and thus the four levels of data traffic can be encoded into two bits; or, for another example, the data traffic can be divided into 16 levels, and thus the sixteen levels of data traffic can be encoded into four bits. It is understood that the size of the data traffic can also be divided into more or fewer levels, resulting in a corresponding target signal comprising more or fewer bits. In one possible implementation, the service monitoring unit 21 can pre-set a mapping relationship 1 between data traffic and the target signal. Therefore, after obtaining the size of the data traffic, the service monitoring unit 21 can query this mapping relationship 1 to obtain the bits corresponding to the data traffic, i.e., the target signal. This embodiment of the application takes dividing the data traffic into four levels as an example, through... Figure 3 The specific example shown describes mapping relationship 1. For example... Figure 3 As shown, in mapping relationship 1, the horizontal axis represents data flow and the vertical axis represents the target signal. From Figure 3As can be seen, the data traffic is divided into four levels. The first level has a data traffic of less than 25%, and the target signal corresponding to this level is "00". The second level has a data traffic of greater than or equal to 25% and less than 50%, and the target signal corresponding to this level is "01". The third level has a data traffic of greater than or equal to 50% and less than 75%, and the target signal corresponding to this level is "10". The fourth level has a data traffic of greater than or equal to 75%, and the target signal corresponding to this level is "11". Assuming that the service monitoring unit 21 detects that the data traffic received by ports v22 and v23 is in the second level, it can obtain the target signal "01" and then send the target signal "01" to PMU10. In one possible implementation of this application embodiment, the service monitoring unit 21 can periodically acquire the data traffic and then periodically send the target signal to PMU10.

[0072] PMU10 may include a controller 11 and a switching circuit 12. The controller 11 may be a hardware circuit, such as, but not limited to, an application-specific integrated circuit (ASIC), discrete gates, transistor logic devices, or discrete hardware components. In another possible implementation, the controller 11 may also be a software-driven processor, such as, but not limited to, a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSPs), field-programmable gate arrays (FPGAs), or other types of programmable logic devices. The general-purpose processor may be a microprocessor or any conventional processor. The controller 11 may include multiple connection terminals, among which may be terminals connected to the switching circuit 12. In one possible implementation, when the electronic device 100 is as follows... Figure 2 In the structure shown, the controller 11 may include a terminal connected to port v11 of the PMU 10. Figure 3The diagram schematically illustrates controller 11 including three connection terminals p0 to p2. Connection terminals p0 and p1 can be connected to port v11 of PMU 10 to receive target signals from chip 20 through port v11 of PMU 10. Connection terminal p2 of controller 11 is connected to switching circuit 12. Switching circuit 12 can include various types of circuits, such as, but not limited to, buck circuits, boost circuits, or buck-boost circuits. Furthermore, switching circuit 12 can also be a multi-phase circuit, such as a three-phase buck circuit. It is understood that switching circuit 12 can include multiple switching elements, as well as necessary components such as capacitors and inductors; the aforementioned switching elements can be, for example, transistors. The connection between controller 11 and switching circuit 12 can be that controller 11 is connected to the control terminals of the switching elements in switching circuit 12.

[0073] The controller 11 can receive the target signal from the service monitoring unit 21 through port v11 of the PMU 10, and then control the voltage signal output by the switching circuit 12 based on the target signal. Specifically, in one possible implementation, the PMU 10 may also include a memory, which may include, but is not limited to, registers, caches, or RAM. The memory of the PMU 10 may pre-store a mapping relationship 2 between the target signal and the current magnitude. Based on the target signal, the controller 11 can query the current corresponding to the target signal in the mapping relationship 2, and generate a control signal based on the queried current to control at least one of the voltage and current output by the switching circuit 12 by controlling the parameters of the switching circuit 12, thereby providing the corresponding current to the chip 20. The parameters of the switching circuit 12 may include, but are not limited to, the duty cycle of each transistor in the switching circuit 12, or the on-time of each transistor in the switching circuit 12. When the switching circuit 12 is a multi-phase circuit, the controller 11 can also adjust the number of phases that are turned on in the switching circuit 12; for example, when the switching circuit 12 is a three-phase BUCK circuit, it can control each phase of the BUCK circuit to be turned on, or control some of the BUCK circuits to be turned on. This application embodiment takes a signal including two bits as an example, through... Figure 4 The specific example shown describes mapping relationship 2. From Figure 4As can be seen, when the target signal includes two bits, the current corresponding to the target signal can be divided into four levels. Specifically, a target signal of "00" corresponds to current I0, a target signal of "01" corresponds to current I1, a target signal of "10" corresponds to current I2, and a target signal of "11" corresponds to current I3. The magnitude of current I0 is lower than that of current I1, the magnitude of current I1 is lower than that of current I2, and the magnitude of current I2 is lower than that of current I3. This mapping relationship 2 can be obtained in advance using methods such as testing and simulation and then set in PMU10. From mapping relationships 1 and 2, it can be seen that there is a mapping relationship between the data flow in chip 20 and the current required by controller 11.

[0074] based on Figure 2 The electronic device 100 shown is for reference. Figure 5 , Figure 5 This is a schematic diagram of the interaction process 500 between PMU10 and chip 20 provided in an embodiment of this application. The interaction process 500 includes the following steps.

[0075] Step 501: The service monitoring unit 21 in chip 20 detects the data traffic received by port v22 and port v23, generates a target signal indicating the change in data traffic when the data traffic changes, and provides the target signal to PMU10.

[0076] Step 502: The controller 11 in PMU10 obtains the current corresponding to the target signal based on the target signal and the pre-set mapping relationship 2 between the target signal and the current. Step 503: Based on the obtained current, a control signal is generated and provided to the switching circuit 12.

[0077] In step 503, the switching circuit 12 in PMU10 outputs a power supply voltage to chip 20 through the voltage output terminal vo of controller 11 based on the control signal.

[0078] Step 504: The service processing unit 21 in chip 20 processes the service data received by chip 20 based on the power supply voltage.

[0079] For the specific implementation of steps 501 to 503, please refer to... Figure 2 The descriptions of the relevant components in the electronic device 100 shown will not be repeated.

[0080] Depend on Figure 2 The electronic device 100 shown and Figure 5As shown in the interaction flow 500, chip 20 generates a target signal based on the data flow of the service and provides it to PMU10. Thus, controller 11 in PMU10 can generate a control signal based on the current corresponding to the target signal to control the voltage output by switching circuit 12. Since there is a time delay between chip 20 receiving service data and starting to process service data, chip 20 directly sends the target signal to PMU10 based on the service data flow, and PMU10 directly controls the voltage output by switching circuit based on the target signal. Therefore, compared with the existing technology where PMU10 needs to collect the feedback voltage at the output end in real time and generate the control signal of switching circuit based on the feedback voltage using a voltage loop, the response delay of PMU10 can be greatly reduced, which is beneficial to improving the stability and reliability of chip 20.

[0081] above Figure 2 In the illustrated electronic device 100, a controller 11 determines the current magnitude corresponding to the target signal based on the mapping relationship 2 between the target signal and the current, and adjusts the voltage output of the switching circuit 12 based on the current magnitude. In an optional implementation of this application embodiment, in addition to generating the control signal for the switching circuit 12 based on the current magnitude, the controller 11 can also generate the control signal for the switching circuit 12 based on more current parameters. These more current parameters include not only the current level change (i.e., the current magnitude), but also the current change rate and delay time; wherein, the delay time is the time from when the controller 11 receives the target signal to when the current in the chip begins to rise; the current change rate is the ratio of the current change amount to the current change time; the current change time can be the time required for the current in the chip 20 to change from one current level (denoted as current Ii) to another current level (denoted as current Ij) (i.e., the time required for the current in the chip to change to reach its maximum value). The current change amount is the difference between current Ij and current Ii. The current level can be, for example, as shown in the example... Figure 4 As shown, Figure 4 The diagram schematically illustrates four current levels, from I0 to I3. The difference between current Ij and current Ii is determined by the difference between the data flow rate of the previous cycle and the data flow rate of the current cycle of chip 20.

[0082] The controller 11 can obtain parameters such as the rate of change of current and delay time of the chip 20 in various ways. In one possible implementation, the rate of change of current and delay time can be obtained in advance using methods such as testing and simulation, and then embedded in the controller 11. In another possible implementation, when the chip 20 sends a target signal to the controller 11, it can also send the delay time and the rate of change of current to the controller 11. This delay time and the rate of change of current can be recorded by the chip 20 during multiple operations. In a specific implementation, among the additional ports included in the chip 20 and PMU 10, there can also be ports for transmitting the delay time and the rate of change of current. The chip 20 can send the delay time and the rate of change of current simultaneously when sending the target signal to the controller 11 through these ports. The port types and specific implementations of the ports for transmitting the delay time and the ports for transmitting the rate of change of current in the chip 20 and PMU 10 can be similar to those of the ports for transmitting the target signal in the chip 20 and PMU 10, as described in the relevant description. Furthermore, the delay time and current change rate can also be encoded into multiple bits, with the specific implementation similar to the target signal, and will not be described in detail here. By using chip 20 to send the delay time and current change rate to controller 11, the accuracy of the delay time can be improved.

[0083] The controller 11 can also store a mapping relationship 3 between the control signal and the change in current level, the rate of change of current, and the delay time. This mapping relationship 3 can also be obtained in advance using methods such as testing and simulation. Figure 3 and Figure 4 Corresponding to the mapping relationship shown, when the current change range in chip 10 includes four ranges, the mapping relationship 3 can include six current range changes, the current change time corresponding to the six current range changes, and the delay time; thus, for each combination of current range change, current change time, and delay time, a control signal can be corresponding to it. Figure 6 The diagram schematically illustrates the mapping relationship between the control signal and the combination of current level change, current change rate, and delay time, and the control signal. (Example 3) Figure 6 In this context, when the current changes from level I0 to level I3, the rate of change of this current is a3, and the delay time from the controller 11 receiving the target signal to the current starting to change in the chip 20 is td3, this combination corresponds to control signal 3. Therefore, the controller 11 can determine the magnitude of the current indicated by the target signal based on mapping relationship 2, and then determine the control signal corresponding to the switching circuit 12 based on mapping relationship 3, thereby controlling the output voltage of the switching circuit 12. It should be noted that... Figure 6The mapping relationship shown in Figure 3 is only illustrative. Because different chips may have different rates of current change and delay times for the same level of change (e.g., from current I1 to current I3), therefore… Figure 6 The mapping relationship 3 shown may include more combinations. The control signals corresponding to each combination may be the same or different. This application does not make specific limitations.

[0084] based on Figure 2 The electronic device 100 shown Figure 3 , Figure 4 , Figure 6 The mapping relationship shown, and Figure 5 The interactive flow shown can be implemented in various ways by the chip 20 provided in this embodiment. Further reference... Figure 7 , Figure 7 This is a schematic diagram of the structure of chip 20 provided in an embodiment of this application. For example... Figure 7 As shown, chip 20 includes a service monitoring unit 21, a cache 22, and multiple service processing units 23. The figure schematically illustrates service processing units 231, 232, and 233, but this is not intended to limit the solution. The service monitoring unit 21 may include multiple endpoints. Figure 7The diagram schematically illustrates four connection terminals, c0 to c3. Terminal c0 is connected to ports v22 and v23 of chip 20; terminal c1 is connected to port v21 of chip 20; terminal c2 is connected to cache 22 in chip 20; and terminal c3 is connected to multiple service processing units 23 in chip 20. Furthermore, each service processing unit is connected to cache 22. The service monitoring unit 21 can be a hardware circuit, such as, but not limited to, an application-specific integrated circuit (ASIC), discrete gates, transistor logic devices, or discrete hardware components. In another possible implementation, the service monitoring unit 21 can also be a software-driven processor, such as, but not limited to, a central processing unit (CPU), other general-purpose processors, field-programmable gate arrays (FPGAs), or other types of programmable logic devices. The general-purpose processor can be a microprocessor or any conventional processor. In one possible implementation, the service monitoring unit 21 can also include timers or counters. Each service processing unit can be a processor (or processor core). The processor included in service processing unit 23 can include, but is not limited to, a GPU, NPU, ISP, or DSP. It is understood that chip 20 can also include more components, such as clocks or registers.

[0085] like Figure 7 In the chip 20 shown, the service monitoring unit 21 receives service data through ports v22 and v23, and counts the data flow of service data within a clock cycle (or the timing period of a timer); then, the service monitoring unit 21 encodes the data flow (e.g., based on...). Figure 3 (The mapping relationship shown in Figure 1 is encoded), and the generated target signal is sent to PMU10 through port v21. Furthermore, the service monitoring unit 21 can also store the service data received from ports v22 and v23 into buffer 22; the service monitoring unit 21 can also select one or more service processing units based on the data type, data flow, and load of each service processing unit, so that the one or more service processing units form a data transmission path with buffer 22 and perform service processing operations. Figure 7As shown in chip 20, the process from receiving service data through ports v22 and v23 to the start of service data processing by service processing unit 23 involves the following steps: service data is stored in buffer 22, service monitoring unit 21 selects service processing unit 23, and service processing unit 23 reads data from buffer 22. Therefore, there is a certain time delay between the receipt of service data through ports v22 and v23 and the start of service data processing by service processing unit. If the data flow of chip 20 in the current clock cycle increases significantly compared to the previous clock cycle (or the data flow of the counter in the current counting cycle increases significantly compared to the previous counting cycle), the current in chip 20 only surges when service processing unit 23 begins processing service data. Therefore, based on this time delay, the business monitoring unit 21 sends a target signal to the PMU 10 in advance, allowing the PMU 10 to predict the current flow of the chip 20 in advance and provide the required current to the chip 20 in a timely manner within the aforementioned time delay. This avoids excessive voltage drops in the chip 20 due to current surges, which could affect its normal operation and improve the operational stability of the chip 20. Since the current surge in the chip 20 has a time delay, if the PMU 10 responds to the target signal and immediately provides all the current required by the chip 20, the input voltage of the chip 20 may surge before the aforementioned time delay arrives, potentially damaging the chip or reducing its lifespan. Therefore, in one possible implementation, the PMU 10 can also determine the step size of the current supplied to the chip 20 based on the delay time and the current change rate, thereby gradually providing the required current to the chip 20 within the delay time, thus improving the chip's lifespan.

[0086] The controller 11 in the PMU10 provided in this application embodiment can include various implementation methods. For example... Figure 2 Based on the electronic device 100 shown, please refer to Figure 8 , Figure 8 This is a schematic diagram of the structure of PMU10 in one optional implementation of an embodiment of this application. Figure 8 As shown, the controller 11 may include a voltage loop 112 and a control unit 111. The voltage loop 112 includes connection terminals q1, q2, and q3. Connection terminals p0, p1, and p2 of the controller 11 are the three connection terminals of the control unit 111. In addition to these three connection terminals, the control unit 111 also includes a connection terminal p3. Connection terminal q1 is used to input the reference voltage signal vref, connection terminal q2 is connected to the voltage output terminal vo of the PMU 10, and connection terminal q3 is connected to connection terminal p3 of the control unit 111. It should be noted that, as... Figure 8The PMU10 shown may include more or fewer components. Furthermore, the number of connection terminals included in each component is illustrative and can be set according to the needs of the actual scenario; this application embodiment does not impose specific limitations. It should be noted that in the PMU10 provided in this application embodiment, the control unit 111 and voltage loop 112 can be integrated into one or more chips to form a PMU chip, and the switching circuit 12 can be selectively disposed on or outside the PMU chip.

[0087] Voltage loop 112 can be a hardware circuit, such as, but not limited to, application-specific integrated circuits (ASICs), discrete gates, transistor logic devices, or discrete hardware components. In another possible implementation, voltage loop 112 can also be a software-driven processor, such as, but not limited to, programmable logic controllers (PLCs), field-programmable gate arrays (FPGAs), or other types of programmable logic devices. When voltage loop 112 is a hardware circuit, it can include, but is not limited to, a feedback network, an error amplifier 1, and a control circuit 1. The feedback network in voltage loop 112 is used to obtain the output voltage from the voltage output terminal vo and convert the output voltage into a feedback signal 1, which is provided to the error amplifier 1. The error amplifier 1 is used to compare the feedback signal 1 with the reference voltage signal vref and provide the comparison result to the control circuit 1. The control circuit 1 is used to generate parameters for controlling the switching circuit 12 based on the comparison result. These parameters include, but are not limited to, the duty cycle of each switching element in the switching circuit 12 or the on-time of each switching element in the switching circuit 12.

[0088] The control unit 111, responding to the target signal, can obtain the current indicated by the target signal based on mapping relationship 2, and then detect whether the current indicated by the target signal has changed compared to the current, and whether the gear has changed. If the gear has not changed, the control unit 111 transmits the parameters provided by voltage loop 112 to switching circuit 12; if the gear has changed, the control unit 111 can, as follows: Figure 6 The mapping relationship 3 shown identifies the control signal corresponding to the combination of gear position change, current change rate, and delay time. This control signal is then provided to the switching circuit 12 to control its output voltage. The control signal in mapping relationship 3 can be parameters of each switching element in the switching circuit 12, including but not limited to the duty cycle or on-time of each switching element as described above.

[0089] It should be noted that the voltage loop 112 is unaware of the existence of the control unit 111. In order to avoid the control unit 111 controlling the switching circuit 12 to output an excessively high voltage, which would cause the voltage loop to malfunction, in one possible implementation of this application embodiment, after the voltage loop 112 controls the switching circuit 12 to output a high voltage for a preset time, the voltage of the chip 20 remains stable. The control unit 111 no longer controls the switching circuit 12 based on the mapping relationship 3, but instead directly provides the parameters output by the voltage loop 112 to the switching circuit 12.

[0090] above Figure 8 The PMU10 shown schematically includes a voltage loop 112, a control unit 111, and a switching circuit 12. In one possible implementation, the PMU10 may include a current loop 113, such as... Figure 9 As shown, Figure 9 This is another structural schematic diagram of the PMU10 provided in the embodiments of this application. Figure 9 In addition to the control unit 111, switching circuit 12, and voltage loop 112, PMU10 may also include a current loop 113. The structure of voltage loop 112 is similar to that of... Figure 8 The voltage loop 112 shown has the same structure; please refer to the relevant description for details, which will not be repeated here. Figure 9 In the PMU10 shown, the connection terminals p0 and p1 of the controller 11 are also the two connection terminals of the control unit 111. In addition to these two ports, the control unit 111 also includes connection terminals p3 and p4. The connection terminal p2 of the controller 11 is one connection terminal of the current loop 113. In addition to this connection terminal, the current loop 113 also includes connection terminals r0 and r1. The connection terminal r0 of the current loop 113 is connected to the connection terminal p4 of the control unit 111; the connection terminal r1 of the current loop 113 is connected to the current feedback terminal of the switching circuit 12; and the connection terminal p2 of the current loop 113 is connected to the switching circuit 12. The current loop 113 can be a hardware circuit, such as, but not limited to, an integrated circuit (ASIC), discrete gates, transistor logic devices, or discrete hardware components. In another possible implementation, the current loop 113 can also be a software-driven processor, such as, but not limited to, a programmable logic controller (PLC), a field-programmable gate array (FPGA), or other types of programmable logic devices. When the current loop 113 is a hardware circuit, the current loop 113 may include, but is not limited to, a current detection circuit, an error amplifier 2, and a control circuit 2.

[0091] like Figure 9 In the PMU10 shown, the voltage loop 112 is used to: obtain the output voltage from the voltage output terminal vo and convert the output voltage into a feedback signal 1; compare the feedback signal 1 with the reference voltage signal vref, and generate a reference current signal I01 for the current loop based on the comparison result.

[0092] Control unit 111 is configured to: respond to a target signal, obtain the current indicated by the target signal based on mapping relationship 2, then detect whether the current indicated by the target signal has changed compared with the current, and whether the gear has changed; if the gear has not changed, transmit the reference current signal I01 provided by voltage loop 112 to the voltage loop; if the gear has changed, control unit 111 can, as follows: Figure 6 The mapping relationship 3 shown identifies the control signal corresponding to the combination of gear position change, current change time, and delay time. Then, based on the control signal and the reference current signal I01, a reference current signal I02 is generated and provided to the switching circuit 12 to control the output voltage of the switching circuit 12. It should be noted that in... Figure 9 In the circuit structure shown, such as Figure 6 The control signal in the mapping relationship 3 shown can be the current signal of the current loop. The control unit 111 can further superimpose the current signal found through mapping relationship 3 on the reference current signal I01 provided by the voltage loop to achieve the reference current signal I02, and then provide the reference current signal I02 to the current loop 113.

[0093] The current loop 113 is used to: obtain the current signal output by the switching circuit 12, and generate a feedback signal 2 based on the current signal; compare the feedback signal 2 with a reference current signal, and adjust the parameters in the switching circuit 12 based on the comparison result to control the output current. The parameters of the switching circuit 12 may include, but are not limited to, the duty cycle of the switching elements in the switching circuit 12, or the on-time of each switching element in the switching circuit 12.

[0094] The above is from Figure 1 to Figure 9 The illustrated embodiments show a PMU10 and an electronic device 100 including the PMU10 provided in this application. Based on the same inventive concept, this application also provides a power supply method, which is applied to the PMU10 shown in any of the above embodiments. Please continue to refer to... Figure 10This document illustrates a flow 1000 of a power supply method provided in an embodiment of this application. This power supply method flow 1000 can be executed by the electronic device 100 shown in any of the above embodiments, and includes the following steps: Step 1001, a service monitoring unit in the chip monitors service data, and upon detecting a change in the data flow of the service data, generates a target signal indicating the change in data flow, and provides the target signal to the controller; Step 1002, the controller generates a current parameter corresponding to the target signal based on the target signal, and controls the switching circuit to output a power supply voltage to the chip according to the current parameter; Step 1003, a service processing unit in the chip processes the service data based on the power supply voltage.

[0095] In one possible implementation, the current parameters include the current magnitude and at least one of the following: the rate of change of current and the delay time; wherein the delay time is the time from when the processor receives the target signal to when the current in the chip begins to rise; the rate of change of current is the ratio of the amount of change of current to the time of change of current, and the time of change of current is the time from when the current in the chip begins to change until it reaches its maximum value.

[0096] In one possible implementation, generating a target signal indicating changes in data traffic includes: encoding the changed data traffic and generating the target signal based on the encoding result.

[0097] In one possible implementation, the controller generates current parameters corresponding to the target signal based on the target signal, and controls the switching circuit in the power management unit according to the current parameters, including: the controller obtains the current parameters corresponding to the target signal from a preset mapping relationship between signals and current parameters, generates a control signal using the current parameters, and provides the switching circuit to the switching circuit.

[0098] In one possible implementation, the current parameters include the current magnitude and at least one of the following: the rate of change of current and the delay time; wherein the delay time is the time from when the controller receives the target signal to when the current in the chip begins to rise; the rate of change of current is the ratio of the amount of change of current to the time of change of current, and the time of change of current is the time from when the current in the chip begins to change until it reaches its maximum value.

[0099] It is understood that, in order to achieve the above-mentioned functions, the electronic device 100 includes hardware and / or software modules corresponding to the execution of each function. Based on the steps of the examples described in conjunction with the embodiments disclosed herein, this application can be implemented in hardware or a combination of hardware and computer software. Whether a function is executed by hardware or by computer software driving hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application in conjunction with the embodiments, but such implementation should not be considered beyond the scope of this application. For example, Figure 2 The controller 11, service monitoring unit 21 and service processing unit 22 shown can be software-driven hardware components. That is, each component can include a corresponding processor and corresponding driver software, which can be implemented in software or hardware.

[0100] In the above-mentioned electronic device 100, at least one of the components of controller 11, service monitoring unit 21, and service processing unit 22 can call a computer program stored in the memory to control and manage the actions of the corresponding component, thereby supporting the steps executed by the electronic device 100. The memory can be used to support the electronic device 100 in storing program code and data, and includes, but is not limited to, cache, registers, or at least a portion of the storage space of the aforementioned memory. The electronic device 100 can be a combination of one or more microprocessors that implement computing functions. Furthermore, the electronic device 100 may also include other programmable logic devices, transistor logic devices, or discrete hardware components.

[0101] The chip described in this application can be implemented on integrated circuits (ICs), mixed-signal ICs, application-specific integrated circuits (ASICs), printed circuit boards (PCBs), electronic devices, etc. This multi-core processor can also be manufactured using various IC process technologies, such as complementary metal-oxide-semiconductor (CMOS), n-metal-oxide-semiconductor (NMOS), p-type metal-oxide-semiconductor (PMOS), bipolar junction transistors (BJTs), bipolar CMOS (BiCMOS), silicon-germanium (SiGe), etc.

[0102] This application also provides a computer storage medium storing computer instructions. When the computer instructions are executed on the electronic device 100, the electronic device 100 performs the aforementioned related method steps to implement the data reading method in the above embodiments.

[0103] This application also provides a computer program product containing instructions; when the instructions are executed on the electronic device 100, the electronic device 100 performs the above-mentioned related steps to implement the data reading method in the above embodiments.

[0104] It should be understood that in the various embodiments of this application, the order of the above-mentioned processes does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0105] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0106] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0107] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. An electronic device, characterized in that, Includes controllers, switching circuits, and chips; The chip includes a service monitoring unit and a service processing unit; The business monitoring unit is used to monitor business data, and when a change in the data traffic of the business data is detected, to generate a target signal indicating the change in data traffic, and to provide the target signal to the controller; The controller is configured to generate current parameters corresponding to the target signal based on the target signal, and to control the switching circuit to output a power supply voltage to the chip according to the current parameters; The service processing unit is used to process the service data based on the power supply voltage.

2. The electronic device according to claim 1, characterized in that, The chip is specifically used for: The changed data flow is encoded, and the target signal is generated based on the encoding result.

3. The electronic device according to claim 1 or 2, characterized in that, The controller is specifically used for: Obtain the current parameter corresponding to the target signal from the preset mapping relationship between signal and current parameters, and generate a control signal using the current parameter; The switching circuit outputs a power supply voltage to the chip based on the control signal.

4. The electronic device according to any one of claims 1 to 3, characterized in that, The current parameters include the current magnitude and at least one of the following: the rate of change of current and the delay time; wherein... The delay time is the time from when the controller receives the target signal to when the current in the chip begins to rise. The current change rate is the ratio of the current change amount to the current change time, and the current change time is the time from when the current in the chip starts to change until it reaches its maximum value.

5. The electronic device according to any one of claims 1 to 4, characterized in that, The chip includes a first interface, the controller includes a second interface, and the service monitoring unit is specifically used for: The target signal is sent to the controller through the first interface and the second interface; The first interface and the second interface each include one of the following: an adaptive voltage regulation interface or a power management bus interface.

6. The electronic device according to any one of claims 1 to 5, characterized in that, The chip includes at least one of the following: a communication chip, an optical switching chip, a central processing unit chip, a graphics processing unit chip, a neural network processor chip, an image signal processor chip, or a digital signal processor chip.

7. A power management unit, characterized in that, Includes controllers and switching circuits; The controller is configured to receive a target signal from the chip, generate current parameters based on the target signal, and control the switching circuit using the current parameters; wherein the target signal is used to indicate changes in the data flow of service data in the chip; The switching circuit is used to output a power supply voltage to the chip based on the control of the controller.

8. The power management unit according to claim 7, characterized in that, The controller is specifically used for: The current parameters corresponding to the target signal are obtained from the preset mapping relationship between signal and current parameters, and the control signal is generated using the current parameters. The switching circuit outputs a power supply voltage to the chip based on the control signal.

9. The power management unit according to claim 7 or 8, characterized in that, The current parameters include the current magnitude and at least one of the following: the rate of change of current and the delay time; wherein... The delay time is the time from when the controller receives the target signal to when the current in the chip begins to rise. The current change rate is the ratio of the current change amount to the current change time, and the current change time is the time from when the current in the chip starts to change until it reaches its maximum value.

10. The power management unit according to any one of claims 7 to 9, characterized in that, The controller includes a voltage loop and a control unit; The voltage loop is used to: read the power supply voltage output by the switching circuit, and generate control parameters based on the difference between the power supply voltage and the preset reference voltage. The control parameters include at least one of the duty cycle and conduction time of the switching element in the switching circuit. The control unit is configured to: receive the target signal from the chip, generate the current parameter based on the target signal, and generate the control signal using the control parameter and the current parameter.

11. The power management unit according to any one of claims 7 to 9, characterized in that, The controller includes a voltage loop, a control unit, and a current loop; The voltage loop is used to: read the power supply voltage output by the switching circuit, and generate a first reference current signal based on the difference between the power supply voltage and a preset reference voltage; The control unit is configured to: receive the target signal from the chip, generate the current parameters based on the target signal, generate a second reference current signal using the control parameters, and generate a third reference current signal based on the first reference current signal and the second reference current signal and provide it to the current loop; The current loop is used to: acquire feedback current from the switching circuit, and generate the control signal based on the feedback current and the third reference current signal.

12. A chip, characterized in that, It includes a business monitoring unit and a business processing unit; The service monitoring unit is used to monitor service data, and when a change in the data traffic of the service data is detected, to generate a target signal indicating the change in data traffic, and to provide the target signal to the power management unit. The service processing unit is used to process the service data based on the power supply voltage provided by the power management unit.

13. The chip according to claim 12, characterized in that, The service processing unit includes multiple units; the service monitoring unit is also used to: select a target service processing unit among the multiple service processing units; The target service processing unit is used to process the service data based on the power supply voltage.

14. The chip according to claim 12 or 13, characterized in that, The chip includes at least one of the following: a communication chip, an optical switching chip, a central processing unit chip, a graphics processing unit chip, a neural network processor chip, an image signal processor chip, or a digital signal processor chip.

15. A power supply method, characterized in that, include: The service monitoring unit in the chip monitors service data, and when a change in the data traffic of the service data is detected, a target signal indicating the change in data traffic is generated, and the target signal is provided to the controller. The controller generates current parameters corresponding to the target signal based on the target signal, and controls the switching circuit to output a power supply voltage to the chip according to the current parameters; The service processing unit in the chip processes the service data based on the power supply voltage.

16. The power supply method according to claim 15, characterized in that, The generation of the target signal indicating the change in data traffic includes: The changed data flow is encoded, and the target signal is generated based on the encoding result.

17. The power supply method according to claim 15 or 16, characterized in that, The step of the controller generating a current parameter corresponding to the target signal based on the target signal, and controlling the switching circuit to output a power supply voltage to the chip according to the current parameter, includes: The controller obtains the current parameters corresponding to the target signal from a preset mapping relationship, and uses the current parameters to generate a control signal; The control signal is provided to the switching circuit.

18. The power supply method according to any one of claims 15 to 17, characterized in that, The current parameters include the current magnitude and at least one of the following: the rate of change of current and the delay time; wherein... The delay time is the time from when the controller receives the target signal to when the current in the chip begins to rise. The current change rate is the ratio of the current change amount to the current change time, and the current change time is the time from when the current in the chip starts to change until it reaches its maximum value.

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