A hybrid parallel inverter life balance control method, device, equipment and medium
Patent Information
- Application Number
- CN202610972248.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-07-01
- Publication Date
- 2026-09-15
Smart Images
Figure CN122764005A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of device lifetime equalization control, and in particular to a method, apparatus, equipment and medium for lifetime equalization control of hybrid parallel inverters. Background Technology
[0002] In high-reliability power supply scenarios such as shipbuilding and marine engineering, inverters need to operate continuously under conditions of large load fluctuations, frequent operating mode switching, and complex environmental conditions. This places higher demands on power capacity, power supply reliability, operational lifespan, and output power quality. Traditional land-based inverter control methods are prone to accelerated aging, decreased reliability, and increased maintenance costs in these scenarios, making it difficult to meet the application requirements of high-reliability power conversion equipment. To balance efficiency, power density, and cost, hybrid parallel inverters based on WBG / Si partial power processing structures are gaining increasing attention. Taking a parallel structure of SiC MOSFET inverters and Si IGBT inverters (a hybrid parallel inverter with SiC / Si partial power processing structure) as an example, typically the Si IGBT branch handles low-frequency main power processing, while the SiC MOSFET branch handles high-frequency power regulation and ripple compensation, thus achieving a better cost / performance trade-off.
[0003] However, due to differences between SiC MOSFETs and Si IGBTs in terms of device materials, switching characteristics, power sharing methods, and thermal stress evolution, the damage accumulation rate and lifetime decay process of the two branches are not synchronized during long-term operation. Even under relatively balanced thermal distribution conditions, lifetime imbalance may still occur, thus limiting the overall service life of the parallel system. Furthermore, most relevant active thermal management or lifetime control methods are designed for single-device-type topologies or optimized based on the assumption of consistent device characteristics, making them difficult to apply to heterogeneous device parallel scenarios in WBG / Si partial power handling structures. In addition, these methods often focus on junction temperature suppression or thermal stress regulation, failing to adequately consider the synergistic constraints between lifetime equalization and total harmonic distortion of the output current, making it difficult to balance system lifetime and output power quality.
[0004] Therefore, how to achieve convergence of lifespan among different branches while ensuring output power quality constraints, thereby improving the overall remaining service life and operational stability of hybrid parallel inverters, has become an urgent problem to be solved. Summary of the Invention
[0005] The purpose of this application is to provide a method, device, equipment and medium for life balancing control of hybrid parallel inverters, which can achieve convergence of lifespan of different branches under the premise of ensuring output power quality constraints, thereby improving the overall remaining service life and operational stability of hybrid parallel inverters.
[0006] To achieve the above objectives, this application provides the following solution: In a first aspect, this application provides a hybrid parallel inverter lifetime equalization control method, including: The operating status parameters of the hybrid parallel inverter in the current control cycle are obtained; the hybrid parallel inverter includes: parallel SiC MOSFET branches and Si IGBT branches; the operating status parameters include: output current, ambient temperature, device damage, current ratio, switching frequency of SiC MOSFET branches and switching frequency of Si IGBT branches. The lifetime difference between the SiC MOSFET branch and the Si IGBT branch in the current control cycle is calculated based on the operating state variables of the current control cycle and the electrothermal coupling lifetime prediction model considering degradation effects. The electrothermal coupling lifetime prediction model considering degradation effects introduces the on-state voltage drop and the dynamic change of thermal resistance with damage based on the lifetime prediction model. Based on the lifetime difference of the current control cycle, the upper-level current ratio step size and the upper-level cost function are set, the current ratio is iterated to determine the upper-level optimal current ratio for the next control cycle, and the lower-level current ratio candidate set is determined based on the upper-level optimal current ratio; the upper-level cost function is determined based on the lifetime difference; the upper-level optimal current ratio is the current ratio corresponding to the minimum value of the upper-level cost function. Based on the candidate set of lower-level current ratios, the set switching frequency step size of the SiC MOSFET branch, the set switching frequency step size of the Si IGBT branch, and the lower-level cost function, the switching frequency is jointly traversed to obtain the optimal control command for the next control cycle, so as to achieve lifetime equalization control of the hybrid parallel inverter in the next control cycle. The lower-level cost function is determined based on the remaining lifetime of each branch, the lifetime difference, and the weight of the switching frequency change. The optimal control command includes: the current ratio corresponding to the minimum lower-level cost function, the switching frequency of the SiC MOSFET branch, and the switching frequency of the Si IGBT branch.
[0007] Secondly, this application provides a hybrid parallel inverter life balance control device, comprising: The operating status acquisition module is used to acquire the operating status quantities of the hybrid parallel inverter in the current control cycle; the hybrid parallel inverter includes: parallel SiC MOSFET branches and Si IGBT branches; the operating status quantities include: output current, ambient temperature, device damage, current ratio, switching frequency of SiC MOSFET branches and switching frequency of Si IGBT branches; The lifetime difference calculation module is used to calculate the lifetime difference between the SiC MOSFET branch and the Si IGBT branch in the current control cycle based on the operating status variables of the current control cycle and the electrothermal coupling lifetime prediction model considering degradation effects. The electrothermal coupling lifetime prediction model considering degradation effects introduces the on-state voltage drop and the dynamic change of thermal resistance with damage based on the lifetime prediction model. The upper-level current ratio traversal module is used to traverse the current ratio based on the lifetime difference degree of the current control cycle, the set upper-level current ratio step size, and the upper-level cost function to determine the upper-level optimal current ratio for the next control cycle, and to determine the lower-level current ratio candidate set based on the upper-level optimal current ratio; the upper-level cost function is determined based on the lifetime difference degree; the upper-level optimal current ratio is the current ratio corresponding to the minimum value of the upper-level cost function. The lower-level switching frequency traversal module is used to jointly traverse the switching frequencies based on the lower-level current ratio candidate set, the set SiC MOSFET branch switching frequency step size, the set Si IGBT branch switching frequency step size, and the lower-level cost function to obtain the optimal control command for the next control cycle, so as to achieve lifetime equalization control of the hybrid parallel inverter in the next control cycle. The lower-level cost function is determined based on the remaining lifetime of each branch, the lifetime difference, and the weight of the switching frequency change. The optimal control command includes: the current ratio corresponding to the minimum lower-level cost function, the SiC MOSFET branch switching frequency, and the Si IGBT branch switching frequency.
[0008] Thirdly, this application provides a computer device, including: a memory, a processor, and a computer program stored in the memory and capable of running on the processor, wherein the processor executes the computer program to implement the hybrid parallel inverter lifetime equalization control method described in any one of the above.
[0009] Fourthly, this application provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the hybrid parallel inverter lifetime equalization control method described above.
[0010] According to the specific embodiments provided in this application, this application has the following technical effects: This application provides a method, device, equipment, and medium for lifetime equalization control of hybrid parallel inverters. By characterizing the damage differences between the parallel SiC MOSFET branches and Si IGBT branches in the hybrid parallel inverter, and using a two-layer step-size ergonomic mechanism to achieve coordinated adjustment of current ratio and switching frequency, the lifetimes of different branches are made more similar under the premise of ensuring output power quality constraints, thereby improving the overall remaining service life and operational stability of the parallel system. Attached Figure Description
[0011] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0012] Figure 1 A flowchart illustrating a hybrid parallel inverter lifetime balancing control method provided in this application embodiment; Figure 2 A schematic diagram of a hybrid parallel inverter provided in an embodiment of this application; Figure 3 A diagram illustrating the specific implementation process of the hybrid parallel inverter lifetime equalization control method provided in this application embodiment; Figure 4 A functional module diagram of a hybrid parallel inverter life balance control device provided in this application embodiment; Figure 5 This is a schematic diagram of the structure of a computer device provided in an embodiment of this application. Detailed Implementation
[0013] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0014] This application addresses the WBG / Si partial power processing structure and proposes a hybrid parallel inverter lifetime equalization control method, device, equipment, and medium. Based on damage difference-driven lifetime equalization, it specifically characterizes the damage differences of heterogeneous device branches and combines the coordinated adjustment of current ratio and switching frequency to achieve convergence of lifetimes of different branches under the premise of ensuring output power quality constraints, thereby improving the overall remaining service life and operational stability of the parallel system.
[0015] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments.
[0016] In one exemplary embodiment, a lifetime balancing control method for a hybrid parallel inverter is provided. This method acquires the operating state information of the two branches of the parallel inverter, constructs state variables reflecting the degree of lifetime imbalance between the SiC MOSFET branch and the Si IGBT branch, and first performs a coarse search on the current ratio using a large step size based on the operating state variables. Then, it performs a joint fine search on the switching frequency and current ratio correction using a small step size. Under the conditions of satisfying lifetime difference constraints and output power quality constraints, the optimal control variables are determined, thereby completing lifetime balancing control for heterogeneous device parallel structures.
[0017] like Figure 1 As shown, the hybrid parallel inverter lifetime equalization control method includes: Step 101: Obtain the operating status of the hybrid parallel inverter in the current control cycle.
[0018] Among them, such as Figure 2 As shown, the hybrid parallel inverter includes: a SiC MOSFET branch (SiC MOSFET inverter) and a Si IGBT branch (Si IGBT inverter) connected in parallel. The Si IGBT branch is responsible for low-frequency main power processing, while the SiC MOSFET branch is responsible for high-frequency power processing.
[0019] The operating state variables of the current control cycle k include: output current. Ambient temperature Component damage, current ratio SiC MOSFET branch switching frequency and Si IGBT branch switching frequency Device damage includes: damage to SiC MOSFET branch devices. Damage to Si IGBT devices .
[0020] Step 102: Calculate the lifetime difference between the SiC MOSFET branch and the Si IGBT branch in the current control cycle based on the operating state variables of the current control cycle and the electrothermal coupling lifetime prediction model considering degradation effects.
[0021] The electrothermal coupling lifetime prediction model considering degradation effects includes an input power loss model, a thermal network model, and a lifetime prediction model. Operating state variables are input into this model to achieve online estimation of device junction temperature, thermal stress, and remaining lifetime. Device damage information is used to dynamically update degradation parameters such as on-state voltage drop and thermal resistance. Current ratio and switching frequency serve as optimization variables for the model predictive controller, coordinating the relationship between lifetime equalization and output THD (Total Harmonic Distortion), ultimately achieving lifetime equalization optimization control for the hybrid parallel inverter.
[0022] The electrothermal coupling lifetime prediction model considering degradation effects introduces a degradation update mechanism based on the dynamic changes of conduction voltage drop and thermal resistance with damage, on the basis of the traditional lifetime prediction model. It establishes a closed-loop coupling relationship of "damage-parameter degradation-power consumption increase-junction temperature rise", realizing a more realistic dynamic lifetime prediction of the aging process of power devices.
[0023] Step 103: Based on the lifetime difference of the current control cycle, the upper-level current ratio step size and the upper-level cost function, the current ratio is traversed to determine the upper-level optimal current ratio for the next control cycle, and the lower-level current ratio candidate set is determined based on the upper-level optimal current ratio.
[0024] The upper-layer cost function is determined based on the lifetime difference; the upper-layer optimal current ratio is the current ratio corresponding to the minimum value of the upper-layer cost function.
[0025] Step 104: Based on the candidate set of lower-level current ratios, the set frequency step size of the SiC MOSFET branch switching, the set frequency step size of the Si IGBT branch switching, and the lower-level cost function, the switching frequency is jointly traversed to obtain the optimal control command for the next control cycle, so as to realize the lifetime equalization control of the hybrid parallel inverter in the next control cycle.
[0026] The lower-level cost function is determined based on the remaining lifetime, lifetime difference, and switching frequency change weight of each branch; the optimal control command includes: the current ratio corresponding to the minimum lower-level cost function, the switching frequency of the SiCMOSFET branch, and the switching frequency of the Si IGBT branch.
[0027] In another exemplary embodiment of this application, step 102 specifically includes: The operating status of the current control cycle is input into the electrothermal coupling lifetime prediction model that considers degradation effects to obtain the remaining lifetime of the SiC MOSFET branch and the Si IGBT branch; the lifetime difference between the SiC MOSFET branch and the Si IGBT branch in the current control cycle is calculated based on the remaining lifetime of the SiC MOSFET branch and the Si IGBT branch.
[0028] In another exemplary embodiment of this application, the formula for calculating the lifetime difference is as follows.
[0029] .
[0030] in, This indicates the difference in lifetime between the SiC MOSFET branch and the Si IGBT branch during the current control cycle k. This indicates the remaining lifespan of the SiC MOSFET branch in the current control cycle k; This represents the remaining lifetime of the SiIGBT branch in the current control cycle k; max represents the maximum value function. The remaining lifetime of the SiC MOSFET branch. The remaining service life of the Si IGBT branch in the current control cycle k The calculation formula is as follows.
[0031] .
[0032] .
[0033] in, This indicates the junction temperature fluctuation of SiC MOSFET power devices; This indicates the junction temperature fluctuation of Si IGBT power devices; The activation energy represents the failure process of a power device; This represents the Boltzmann constant. This represents the average junction temperature of a SiC MOSFET power device. This represents the average junction temperature of a SiIGBT power device.
[0034] In another exemplary embodiment of this application, step 103 specifically includes: Determine whether the lifespan difference of the current control cycle is greater than or equal to the set threshold.
[0035] If so, based on the current ratio of the current control cycle, the current ratio is iterated by setting the upper-level current ratio step size. The corresponding lifetime difference is calculated for each upper-level iteration, and the upper-level cost function value is calculated based on the lifetime difference under the current upper-level iteration number. The current ratio corresponding to the minimum upper-level cost function value is determined as the upper-level optimal current ratio for the next control cycle. Otherwise, the current ratio of the current control cycle is directly used as the upper-level optimal current ratio for the next control cycle.
[0036] Based on the optimal current ratio of the upper layer in the next control cycle, the candidate set of lower layer current ratios is determined according to the set step size of the lower layer current ratio.
[0037] In another exemplary embodiment of this application, the expression of the upper-layer cost function is as follows.
[0038] .
[0039] in, This represents the upper-level cost function; This indicates the difference in lifetime between the SiC MOSFET branch and the Si IGBT branch in the next control cycle k+1.
[0040] In this embodiment, the threshold value can be set to 0.3. When At that time, within the pre-built safe working area, only a larger set upper-layer current ratio step size is used. For candidate current ratio Perform a traversal of the upper layers, calculate the corresponding lifetime differences, and select the optimal current ratio for the upper layer when the upper layer cost function is minimized. ;when At that time, directly ordered Determine the optimal current ratio for the upper layer.
[0041] The optimal current ratio obtained by traversing the upper layers Centered on this, the candidate set of lower-level current ratios is updated to... . This indicates the step size for setting the current ratio of the lower layer.
[0042] In another exemplary embodiment of this application, step 103 specifically includes: Based on the candidate set of lower-level current ratios, the switching frequency is jointly traversed by setting the switching frequency step size of the SiC MOSFET branch and the switching frequency step size of the SiIGBT branch. In each lower-level iteration, the remaining lifetime of the corresponding SiC MOSFET branch, the remaining lifetime of the SiIGBT branch, and the lifetime difference are calculated.
[0043] Based on the remaining lifetime of the SiC MOSFET branch in the current control cycle, the remaining lifetime of the Si IGBT branch in the current control cycle, the weight of the switching frequency change, the switching frequency change at each lower-level iteration, the remaining lifetime of the SiC MOSFET branch, the remaining lifetime of the Si IGBT branch, and the lifetime difference, calculate the lower-level cost function value at the current lower-level iteration number.
[0044] The current ratio, SiC MOSFET branch switching frequency, and Si IGBT branch switching frequency corresponding to the minimum value of the lower-level cost function are determined as the optimal control command for the next control cycle.
[0045] In another exemplary embodiment of this application, a two-layer iterative optimization is employed, with optimization achieved through layer-by-layer traversal. This embodiment provides a further detailed description of the lower-layer optimization. This is combined with setting the SiC MOSFET branch switching frequency step size. and setting the frequency step size of the Si IGBT branch switch Simultaneously, iterate through the candidate control variable combinations and calculate the remaining system lifetime at the prediction time. and and lifespan variability The optimal combination of control variables is selected according to the following lower-level cost function.
[0046] The expression for the lower-level cost function is as follows.
[0047] .
[0048] in, Represents the lower-level cost function; This indicates the remaining lifespan of the SiC MOSFET branch in the current control cycle k; This indicates the remaining service life of the Si IGBT branch in the current control cycle k; This indicates the remaining lifespan of the SiC MOSFET branch in the current control cycle k+1; This indicates the remaining service life of the Si IGBT branch in the current control cycle k+1; This indicates a positive value that prevents the denominator from being zero; Indicates the penalty coefficient for lifespan variability; This indicates the difference in lifetime between the SiC MOSFET branch and the Si IGBT branch in the next control cycle k+1. Indicates the weight of the change in switching frequency; This represents the switching frequency of the SiC MOSFET branch in the current control cycle k+1; max represents the maximum value function; min represents the minimum value function. Lower-level cost function. The switching frequency of the SiC MOSFET branch in the current control cycle k+1 can be directly obtained when it is minimum , according to and the corresponding optimal current ratio the switching frequency of the Si IGBT branch in the current control cycle k+1 can be determined synchronously value of .
[0049] the optimal control command that minimizes the lower-level cost function is output as the optimal control command for the next control cycle , so as to achieve the collaborative optimization of life equalization and output power quality under the heterogeneous device parallel structure.
[0050] In another exemplary embodiment of the present application, after obtaining the optimal control command of the next control cycle, the switching frequency variation weight is updated in real time according to the current damage value of the SiC MOSFET branch the weight of switching frequency variation is updated in real time so as to adaptively adjust the trade-off between the remaining service life target and the output current total harmonic distortion target at different damage stages; output the optimal control command to the controller of the hybrid parallel inverter to complete the life equalization control of the next control cycle.
[0051] In another exemplary embodiment of the present application, the current distribution relationship between the SiC MOSFET branch and the Si IGBT branch satisfies the following formula.
[0052] .
[0053] Wherein, 0<r<1, r represents the current ratio; is the effective value of the fundamental current output by the parallel inverter, is the effective value of the fundamental current output by the SiC MOSFET branch, is the effective value of the fundamental current output by the Si IGBT branch; and the Si IGBT branch bears the main power energy at low frequency, and the SiC MOSFET branch bears part of the power at high frequency and compensates the low-frequency ripple.
[0054] In another exemplary embodiment of the present application, the upper-level cost function characterizes the life equalization state between the SiC MOSFET branch and the Si IGBT branch. To quantify the influence of control variables on the life difference, the sensitivity of adjusting the life difference by switching frequency and the sensitivity of adjusting the life difference by current ratio are respectively: .
[0055] Wherein, represents the variation of life difference; This indicates the change in switching frequency; This indicates the change in current ratio. Based on... Higher than The sensitivity relationship is determined by prioritizing the current ratio to quickly converge the lifetime difference in the upper-level traversal, and then optimizing the remaining lifetime by combining the current ratio and the switching frequency in the lower-level traversal; and when λ≤0.05, it is determined that the parallel inverters have reached the lifetime balance state.
[0056] In another exemplary embodiment of this application, the lower-level cost function Weighting of SiC MOSFET branch switching frequency variation A variable weighting strategy based on device damage level is adopted to satisfy: .in, This represents the current damage value of the SiC MOSFET branch. The damage sensitivity coefficient of the SiC MOSFET branch; when At this time, the weight of high switching frequency operation of SiC MOSFET branches is increased to prioritize ensuring output power quality; when In this case, the constraint on the upper limit of the switching frequency of SiC MOSFET branches is reduced in order to prioritize extending the remaining lifespan of the system.
[0057] In another exemplary embodiment of this application, the upper-layer current matching step size is set. Set the step size of the lower layer current ratio Set the switching frequency step size of the SiC MOSFET branch. and setting the frequency step size of the Si IGBT branch switch The settings are as follows, depending on the working conditions: (1) Under full load conditions. =0.01, , =4kHz, =3kHz; (2) Under heavy load conditions, =0.01, , =4kHz, =3kHz; (3) Under half-load conditions, =0.01, , =4kHz, =3kHz; (4) Under light load conditions, =0.025, , =2kHz, =2kHz.
[0058] This embodiment obtains the output current, ambient temperature, current ratio, switching frequency of the two branches, and device damage status of the SiC MOSFET inverter branch and the Si IGBT inverter branch. Based on the electrothermal coupling lifetime prediction model considering degradation effects, the lifetime index and lifetime difference of the two branches are calculated. Within the pre-established safe operating area, a two-layer step-size traversal strategy is used to perform hierarchical optimization of the current ratio and switching frequency. Combined with a variable weight adjustment mechanism based on the degree of device damage, the optimal combination of control variables that meets the total harmonic distortion constraint of the output current is obtained, thereby achieving convergence of the remaining lifetime of the two branches and coordinated optimization of output power quality under different aging stages.
[0059] This embodiment addresses the sensitivity differences of different control variables to lifetime differences in the parallel structure of SiC MOSFET and Si IGBT branches. It prioritizes using current matching to quickly adjust lifetime differences, and then optimizes the switching frequency and current matching of the two branches in a coordinated manner to take into account the overall remaining lifespan of the system and the total harmonic distortion rate of the output current. Furthermore, it dynamically adjusts the weight of the SiC MOSFET branch switching changes based on the degree of device damage to improve the adaptability of the control strategy under different aging stages.
[0060] This embodiment addresses the problems in related technologies regarding the parallel structure of SiC MOSFET inverters and Si IGBT inverters, such as insufficient consideration of electrothermal parameter degradation in power device lifetime prediction, difficulty in quantitatively defining the feasible operating area under control variable coupling conditions, and the difficulty in simultaneously ensuring lifetime balance and output power quality for heterogeneous device branches at different aging stages. Taking a SiC MOSFET / Si IGBT hybrid parallel inverter as an example, this embodiment comprehensively utilizes an electrothermal coupling lifetime prediction model considering degradation effects, safe operating area constraints, two-layer step-size ergodic optimization, and a variable weight strategy based on device damage levels to achieve convergence of lifetimes for different branches and improve the overall remaining lifespan of the system.
[0061] In practical applications, a specific implementation process of the above-mentioned hybrid parallel inverter lifetime balancing control method is as follows: Figure 3 As shown, this method integrates an electrothermal coupling lifetime prediction model that considers degradation effects, a safe working area constrained by the number of failure cycles and THD, a two-layer step-size traversal optimization strategy, and a variable weight mechanism based on the degree of device damage. This method can effectively converge the lifetime difference between two branches under the condition of parallel operation of heterogeneous devices, significantly reduce the computational load of online optimization, and take into account both the overall remaining service life of the system and the output power quality at different aging stages.
[0062] Based on the same inventive concept, this application also provides a hybrid parallel inverter lifespan balancing control device for implementing the hybrid parallel inverter lifespan balancing control method described above. The solution provided by this device is similar to the solution described in the above method; therefore, the specific limitations of one or more embodiments of the hybrid parallel inverter lifespan balancing control device provided below can be found in the limitations of the hybrid parallel inverter lifespan balancing control method described above, and will not be repeated here.
[0063] In one exemplary embodiment, such as Figure 4 As shown, a hybrid parallel inverter life balance control device is provided, comprising: an operating status acquisition module for acquiring the operating status quantities of the hybrid parallel inverter in the current control cycle; the hybrid parallel inverter includes: parallel SiC MOSFET branches and Si IGBT branches; the operating status quantities include: output current, ambient temperature, device damage, current ratio, SiC MOSFET branch switching frequency and Si IGBT branch switching frequency.
[0064] The lifetime difference calculation module is used to calculate the lifetime difference between the SiC MOSFET branch and the Si IGBT branch in the current control cycle based on the operating status variables of the current control cycle and the electrothermal coupling lifetime prediction model considering degradation effects. The electrothermal coupling lifetime prediction model considering degradation effects introduces the dynamic changes of on-state voltage drop and thermal resistance with damage on the basis of the lifetime prediction model.
[0065] The upper-level current ratio traversal module is used to traverse the current ratio based on the lifetime difference degree of the current control cycle, the set upper-level current ratio step size, and the upper-level cost function to determine the upper-level optimal current ratio for the next control cycle, and to determine the lower-level current ratio candidate set based on the upper-level optimal current ratio. The upper-level cost function is determined based on the lifetime difference degree; the upper-level optimal current ratio is the current ratio corresponding to the minimum value of the upper-level cost function. This module searches for current ratios with a large step size to quickly converge on lifetime differences.
[0066] The lower-level switching frequency traversal module is used to jointly traverse the switching frequencies based on the lower-level current ratio candidate set, the set SiC MOSFET branch switching frequency step size, the set Si IGBT branch switching frequency step size, and the lower-level cost function to obtain the optimal control command for the next control cycle, thereby achieving lifetime equalization control of the hybrid parallel inverter in the next control cycle. The lower-level cost function is determined based on the remaining lifetime of each branch, the lifetime difference, and the weight of the switching frequency change. The optimal control command includes: the current ratio corresponding to the minimum lower-level cost function, the SiC MOSFET branch switching frequency, and the Si IGBT branch switching frequency. This module jointly searches for the current ratio correction and the switching frequencies of the two branches with a small step size.
[0067] As an optional implementation, the hybrid parallel inverter lifetime balancing control device further includes: a safe operating area constraint module for limiting the feasible domain of control variables; a variable weight adjustment module for adaptively coordinating lifetime targets and THD targets based on the degree of device damage; and a control output module for outputting optimal control commands.
[0068] In one exemplary embodiment, a computer device is provided, which may be a server or a terminal, and its internal structure diagram may be as follows. Figure 5 As shown, this computer device includes a processor, memory, input / output (I / O) interfaces, and a communication interface. The processor, memory, and I / O interfaces are connected via a system bus, and the communication interface is also connected to the system bus via the I / O interfaces. The processor provides computational and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system, computer programs, and a database. The internal memory provides the environment for the operation of the operating system and computer programs in the non-volatile storage media. The database stores the optimal control instructions for each control cycle. The I / O interfaces are used for exchanging information between the processor and external devices. The communication interface is used for communication with external terminals via a network connection. When the computer program is executed by the processor, it implements a hybrid parallel inverter lifetime equalization control method.
[0069] Those skilled in the art will understand that Figure 5 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer equipment to which the present application is applied. Specific computer equipment may include, for example, [the following is a list of possible additional structures]. Figure 5The embodiments show more or fewer components, combinations of certain components, or different component arrangements. In one exemplary embodiment, a computer device is provided, including a memory and a processor, the memory storing a computer program, which the processor executes to implement the steps in the above-described method embodiments.
[0070] In one exemplary embodiment, a computer-readable storage medium is provided storing a computer program that, when executed by a processor, implements the steps in the above-described method embodiments.
[0071] In one exemplary embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps in the above-described method embodiments.
[0072] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM).
[0073] The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, etc., and are not limited to these.
[0074] This application takes a parallel structure of SiC MOSFET inverter and Si IGBT inverter as an example. Addressing the issues of asynchronous lifetime evolution in heterogeneous device branches during long-term operation and the difficulty of traditional unified weight control in balancing lifetime equilibrium and output harmonic constraints, it proposes a phased collaborative optimization control scheme based on damage difference characterization. First, this application constructs the lifetime imbalance state variables of the two branches and adaptively switches the control weights according to the interval of the state variables. Second, it employs a two-layer step-size traversal mechanism. The upper layer uses a larger step size to quickly search the branch current allocation variables to converge the lifetime difference between the two branches. The lower layer uses a smaller step size to jointly search the high-frequency branch switching adjustment variables and current allocation corrections to obtain the optimal combination of control variables that satisfies the output harmonic constraints. Finally, it updates the control commands of the two branches in real time according to the optimal control variables, enabling the parallel system to achieve convergence of remaining lifetime and collaborative optimization of output power quality at different aging stages. This application avoids the control mismatch problem caused by fixed weights and single-layer search, reduces the complexity of online optimization, and improves the lifetime coordination control capability and operational stability of heterogeneous devices in some power processing structures.
[0075] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0076] This document uses specific examples to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of this application. Furthermore, those skilled in the art will recognize that, based on the ideas of this application, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of this application.
Claims
1. A method for lifetime equalization control of hybrid parallel inverters, characterized in that, include: Obtain the operating status of the hybrid parallel inverter in the current control cycle; The hybrid parallel inverter includes: parallel SiC MOSFET branches and Si IGBT branches; the operating status parameters include: output current, ambient temperature, device damage, current ratio, switching frequency of SiC MOSFET branches and switching frequency of Si IGBT branches. The lifetime difference between the SiCMOSFET branch and the Si IGBT branch in the current control cycle is calculated based on the operating state variables of the current control cycle and the electrothermal coupling lifetime prediction model considering degradation effects. The electrothermal coupling lifetime prediction model considering degradation effects introduces the on-state voltage drop and the dynamic change of thermal resistance with damage based on the lifetime prediction model. Based on the lifetime difference of the current control cycle, the upper-level current ratio step size and the upper-level cost function are set, the current ratio is iterated to determine the upper-level optimal current ratio for the next control cycle, and the lower-level current ratio candidate set is determined based on the upper-level optimal current ratio; the upper-level cost function is determined based on the lifetime difference; the upper-level optimal current ratio is the current ratio corresponding to the minimum value of the upper-level cost function. Based on the candidate set of lower-level current ratios, the set switching frequency step size of the SiC MOSFET branch, the set switching frequency step size of the Si IGBT branch, and the lower-level cost function, the switching frequency is jointly traversed to obtain the optimal control command for the next control cycle, so as to achieve lifetime equalization control of the hybrid parallel inverter in the next control cycle. The lower-level cost function is determined based on the remaining lifetime of each branch, the lifetime difference, and the weight of the switching frequency change. The optimal control command includes: the current ratio corresponding to the minimum lower-level cost function, the switching frequency of the SiC MOSFET branch, and the switching frequency of the Si IGBT branch.
2. The hybrid parallel inverter lifetime equalization control method according to claim 1, characterized in that, The lifetime difference between the SiC MOSFET branch and the SiIGBT branch in the current control cycle is calculated based on the operating state variables of the current control cycle and the electrothermal coupling lifetime prediction model considering degradation effects. Specifically, this includes: By inputting the operating status of the current control cycle into the electrothermal coupling lifetime prediction model that considers degradation effects, the remaining lifetime of the SiCMOSFET branch and the remaining lifetime of the Si IGBT branch are obtained. The difference in lifetime between the SiC MOSFET branch and the Si IGBT branch during the current control cycle is calculated based on the remaining lifetime of the SiC MOSFET branch and the remaining lifetime of the Si IGBT branch.
3. The hybrid parallel inverter lifetime equalization control method according to claim 1, characterized in that, Based on the lifetime difference of the current control cycle, the upper-level current ratio step size and the upper-level cost function are set, the current ratio is iterated to determine the upper-level optimal current ratio for the next control cycle, and the lower-level current ratio candidate set is determined based on the upper-level optimal current ratio, specifically including: Determine whether the lifespan difference of the current control cycle is greater than or equal to the set threshold; If so, based on the current ratio of the current control cycle, the current ratio is iterated by setting the upper-level current ratio step size. The corresponding lifetime difference is calculated for each upper-level iteration, and the upper-level cost function value is calculated based on the lifetime difference under the current upper-level iteration number. The current ratio corresponding to the minimum upper-level cost function value is determined as the upper-level optimal current ratio of the next control cycle. Otherwise, the current ratio of the current control cycle is directly used as the upper-level optimal current ratio of the next control cycle. Based on the optimal current ratio of the upper layer in the next control cycle, the candidate set of lower layer current ratios is determined according to the set step size of the lower layer current ratio.
4. The hybrid parallel inverter lifetime equalization control method according to claim 1, characterized in that, Based on the candidate set of lower-level current ratios, the set frequency step size of the SiC MOSFET branch switching, the set frequency step size of the Si IGBT branch switching, and the lower-level cost function, a joint traversal of the switching frequency is performed to obtain the optimal control command for the next control cycle, specifically including: Based on the candidate set of lower-level current ratios, the switching frequency is jointly traversed by setting the switching frequency step size of SiC MOSFET branch and setting the switching frequency step size of Si IGBT branch. In each lower-level iteration, the remaining lifetime of the corresponding SiC MOSFET branch, the remaining lifetime of the Si IGBT branch, and the lifetime difference are calculated. Based on the remaining lifetime of the SiC MOSFET branch in the current control cycle, the remaining lifetime of the Si IGBT branch in the current control cycle, the weight of the switching frequency change, the switching frequency change in each lower-level iteration, the remaining lifetime of the SiC MOSFET branch, the remaining lifetime of the Si IGBT branch, and the lifetime difference, calculate the lower-level cost function value for the current lower-level iteration. The current ratio, SiC MOSFET branch switching frequency, and Si IGBT branch switching frequency corresponding to the minimum value of the lower-level cost function are determined as the optimal control command for the next control cycle.
5. The hybrid parallel inverter lifetime equalization control method according to claim 1, characterized in that, The formula for calculating lifespan variability is: ； in, This indicates the difference in lifetime between the SiC MOSFET branch and the Si IGBT branch during the current control cycle k. This indicates the remaining lifespan of the SiC MOSFET branch in the current control cycle k; This indicates the remaining service life of the SiIGBT branch in the current control cycle k; max represents the maximum value function.
6. The hybrid parallel inverter lifetime equalization control method according to claim 1, characterized in that, The expression for the upper-level cost function is: ； in, This represents the upper-level cost function; This indicates the difference in lifetime between the SiC MOSFET branch and the Si IGBT branch in the next control cycle k+1.
7. The hybrid parallel inverter lifetime equalization control method according to claim 1, characterized in that, The expression for the lower-level cost function is: ； in, Represents the lower-level cost function; This indicates the remaining lifespan of the SiC MOSFET branch in the current control cycle k; This indicates the remaining service life of the Si IGBT branch in the current control cycle k; This indicates the remaining lifespan of the SiC MOSFET branch in the current control cycle k+1; This indicates the remaining service life of the Si IGBT branch in the current control cycle k+1; This indicates a positive value that prevents the denominator from being zero; Indicates the penalty coefficient for lifespan variability; This indicates the difference in lifetime between the SiC MOSFET branch and the Si IGBT branch in the next control cycle k+1. Indicates the weight of the change in switching frequency; This represents the switching frequency of the SiC MOSFET branch in the current control cycle k+1; max represents the maximum value function; min represents the minimum value function.
8. A hybrid parallel inverter life balancing control device, characterized in that, include: The operation status acquisition module is used to acquire the operation status of the hybrid parallel inverter in the current control cycle; The hybrid parallel inverter includes: parallel SiC MOSFET branches and Si IGBT branches; the operating status parameters include: output current, ambient temperature, device damage, current ratio, switching frequency of SiC MOSFET branches and switching frequency of Si IGBT branches. The lifetime difference calculation module is used to calculate the lifetime difference between the SiC MOSFET branch and the Si IGBT branch in the current control cycle based on the operating status variables of the current control cycle and the electrothermal coupling lifetime prediction model considering degradation effects. The electrothermal coupling lifetime prediction model considering degradation effects introduces the on-state voltage drop and the dynamic change of thermal resistance with damage based on the lifetime prediction model. The upper-level current ratio traversal module is used to traverse the current ratio based on the lifetime difference degree of the current control cycle, the set upper-level current ratio step size, and the upper-level cost function to determine the upper-level optimal current ratio for the next control cycle, and to determine the lower-level current ratio candidate set based on the upper-level optimal current ratio; the upper-level cost function is determined based on the lifetime difference degree; the upper-level optimal current ratio is the current ratio corresponding to the minimum value of the upper-level cost function. The lower-level switching frequency traversal module is used to jointly traverse the switching frequencies based on the lower-level current ratio candidate set, the set SiC MOSFET branch switching frequency step size, the set Si IGBT branch switching frequency step size, and the lower-level cost function to obtain the optimal control command for the next control cycle, so as to achieve lifetime equalization control of the hybrid parallel inverter in the next control cycle. The lower-level cost function is determined based on the remaining lifetime of each branch, the lifetime difference, and the weight of the switching frequency change. The optimal control command includes: the current ratio corresponding to the minimum lower-level cost function, the SiC MOSFET branch switching frequency, and the Si IGBT branch switching frequency.
9. A computer device, comprising: A memory, a processor, and a computer program stored in the memory and capable of running on the processor, characterized in that the processor executes the computer program to implement the hybrid parallel inverter lifetime equalization control method according to any one of claims 1-7.
10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the hybrid parallel inverter lifetime equalization control method according to any one of claims 1-7.