High speed brushless anti-interference motor control board and method

Abstract

The application relates to the technical field and discloses a high-speed brushless anti-interference motor control board and method. The control board comprises a three-phase full-bridge power circuit and a control IC. The control IC determines the corresponding relationship between the bus current and the phase current according to the MOS tube conduction combination in the PWM period, and determines the effective sampling interval according to the conduction time, the dead time, the switch delay, the peak blanking time and the ADC sampling holding time. The bus current is collected and the three-phase current is reconstructed in the effective sampling interval. After the residual error and the current change direction are checked, the three-phase current for control is updated. When the effective sampling interval is insufficient, the cumulative conduction time of each phase is kept unchanged and the PWM pulse is moved. When the sampling cannot be completed, the three-phase current is predicted according to the current in the last effective period, the current voltage instruction and the resistance and inductance parameters. The control IC also checks the phase sequence and the duration of the Hall edge, and calculates the rotating speed according to the complete electric period, so as to update the PWM duty ratio and the commutation state.

Description

Technical Field

[0001] This application relates to the field of motor control technology, specifically to a high-speed brushless anti-interference motor control board and method. Background Technology

[0002] Brushless DC motors are widely used in power tools, small household appliances, and drones due to their compact structure, wide speed range, and low maintenance. Existing high-speed brushless motor control boards typically use a three-phase full-bridge power circuit, where the control chip outputs pulse width modulation signals to control the switches of each bridge arm, and Hall sensors are used to complete commutation and speed detection. To reduce the number of current sensors, some solutions use a single current sensor to detect the DC bus current and then reconstruct the three-phase current based on the switch status.

[0003] Under high-speed operation and low duty cycle conditions, the proportion of the dead time, switching delay, switching spike duration, and analog-to-digital converter sampling time in the pulse width modulation period of power devices increases, shortening the time available for stable sampling of the bus current. When sampling at fixed times, the sampling point may fall into the switching transition or freewheeling phase, leading to increased three-phase current reconstruction error, which in turn affects speed regulation and overcurrent protection. At the same time, the installation angle deviation of the Hall sensor will cause the duration of each commutation interval to be inconsistent, and abnormal edges caused by external interference may also cause errors in speed calculation or commutation judgment.

[0004] In addition, the high-frequency switching current of the power circuit can easily enter the analog sampling circuit through the power supply, ground wire and adjacent traces. Although the existing solution can reduce interference through input filtering, partitioned wiring and single-point grounding, if there is no unified timing arrangement between pulse width modulation update, commutation processing and analog-to-digital conversion sampling, the sampling data may still not correspond to the actual switching state. Summary of the Invention

[0005] The purpose of this application is to provide a high-speed brushless anti-interference motor control board and method to solve the problems mentioned in the background art.

[0006] According to one aspect of this application, a high-speed brushless anti-interference motor control board is provided, comprising at least a three-phase full-bridge power circuit and a control IC, wherein the control IC is used to execute the following high-speed brushless anti-interference motor control method: The correspondence between bus current and phase current is determined based on the MOSFET conduction combination of the PWM cycle. The effective sampling interval is obtained by subtracting the dead time, switching delay, spike blanking time and ADC sampling and holding time from the conduction time determined by the PWM duty cycle. When the effective sampling interval meets the ADC sampling requirements, the bus current is collected and the reconstructed three-phase current is formed according to the corresponding relationship. The residual of the sum of the three-phase current and the direction of current change are verified. If the verification is passed, the control three-phase current is updated with the reconstructed three-phase current; otherwise, the control three-phase current is not updated. If the effective sampling interval does not meet the ADC sampling requirements, the PWM pulse is shifted and recalculated while keeping the cumulative conduction time of each phase unchanged. If the ADC sampling requirements are still not met after recalculation, the predicted three-phase current is obtained based on the control three-phase current of the previous effective cycle, the current voltage command, and the resistance and inductance parameters. The predicted three-phase current is used as the control three-phase current, and the reconstructed three-phase current that has passed the verification is used to replace the predicted three-phase current. Verify the phase sequence and duration of the Hall edge, discard unqualified Hall edges, obtain the speed from the total time of the six Hall sectors of a complete electrical cycle, and update the PWM duty cycle and commutation state with three-phase current based on the speed and control.

[0007] Preferably, the control method further includes obtaining two bus current samples within the effective sampling interval, converting the two bus current samples into two-phase currents according to the correspondence, calculating the third-phase current based on the instantaneous sum of the three-phase currents being zero, and combining the two-phase currents and the third-phase current to form a reconstructed three-phase current.

[0008] Preferably, the control method further includes: acquiring a set of ADC data when all MOSFETs are turned off and the motor is stationary; determining the average value of the ADC data as the bus current zero point; determining the maximum absolute deviation of each ADC data relative to the average value as the zero current noise range; and verifying the residual of the sum of the three-phase currents based on the zero current noise range; and re-acquiring ADC data in a shutdown state where no current is confirmed, and replacing the original values ​​with the newly determined bus current zero point and zero current noise range.

[0009] Preferably, the control method further includes verifying the current change direction of the reconstructed three-phase current based on the current Hall sector and the conduction state of the MOS transistor; if the reconstructed three-phase current fails the residual verification of the sum of the three-phase currents or the current change direction verification, the control three-phase current is not updated with the reconstructed three-phase current, and the reconstructed three-phase current is written into the fault protection judgment after being limited.

[0010] Preferably, the control method further includes verifying the phase sequence of the Hall edges according to the six-step Hall sequence corresponding to forward or reverse rotation and determining the minimum sector time; when the duration between adjacent Hall edges is shorter than the minimum sector time, the subsequent Hall edge is determined as a non-qualified Hall edge.

[0011] Preferably, the control method further includes, after entering a new Hall sector, estimating the electrical angle within the sector based on the duration of the same Hall sector in the previous complete electrical cycle; the electrical angle within the sector is written into the speed regulation calculation and short-time current prediction, and the commutation state is updated based on the verified Hall edge; after a new Hall edge arrives, the estimation error of the electrical angle within the sector is allocated to subsequent control cycles for successive correction.

[0012] Preferably, the control method further includes correcting the conduction time of the corresponding PWM pulse according to the direction of the corresponding phase current in the three-phase current used for control; increasing the compensation time when the phase current direction shortens the dead zone of the actual conduction time, and decreasing the compensation time when the dead zone of the actual conduction time is extended; the compensation time is based on the dead time and updated according to the correction value obtained from the phase current continuity test before and after commutation under no-load low speed state.

[0013] Preferably, the control method further includes: the ADC trigger is generated by the comparison event of the PWM timer; the PWM duty cycle and commutation state are updated only at the boundary of the PWM cycle; the MOSFET conduction combination of the current PWM cycle, the planned sampling time, and the ADC completion state are combined into state data; when the ADC completion state is inconsistent with the planned sampling time, the corresponding bus current sample is discarded, and the PWM duty cycle and commutation state of the previous PWM cycle are maintained for one PWM cycle; when the inconsistency occurs again in the next PWM cycle, the PWM duty cycle is reduced and the system enters the protection state.

[0014] Preferably, the power input terminal of the control board is provided with an LC filter network consisting of a common-mode inductor, an X capacitor, and a Y capacitor, as well as a varistor; the full-bridge rectifier structure and the 0.1μF high-frequency capacitor constitute a π-type filter, wherein the X capacitor is set in the differential-mode branch and the Y capacitor is set in the common-mode branch.

[0015] Preferably, the control board is a four-layer circuit board, with digital ground and analog ground connected at a single point via a 0Ω resistor; the PWM signal line has a line width of 8mil, a line spacing of not less than 12mil, and an impedance of 50±5Ω; the signal line from the single current sensor to the ADC is arranged in pairs with the analog ground return line, and returns to the analog ground area before the single-point connection; the gate driver is located close to the corresponding MOS transistor, and the gate output line is arranged in parallel with the return line; the phase node copper foil is located in the power area and does not extend below the ADC input line and Hall signal line.

[0016] This application calculates the effective sampling interval of the bus current based on the MOSFET conduction combination and sets the ADC sampling time within the current stable period. When the effective sampling time is insufficient, the PWM pulse is moved while keeping the cumulative conduction time of each phase constant. If an effective sample still cannot be obtained, the motor resistance and inductance parameters are used to make a short-term prediction of the three-phase current. After obtaining the reconstructed three-phase current that has passed the verification, the prediction result is replaced in time. This process can reduce the impact of switching delay, dead time, and switching spikes on single current sampling, so that the three-phase current reconstruction result corresponds to the actual switching state. By verifying the phase sequence and duration of the Hall edge and calculating the speed based on the total time of the six Hall sectors of the complete electrical cycle, the impact of installation deviation and abnormal edges on speed measurement and commutation can be reduced. The PWM update, commutation processing, and ADC triggering adopt a unified time base. With the help of input filtering, single-point grounding, and partitioned wiring, the probability of power supply and power circuit interference entering the analog sampling path can be further reduced, thereby improving the speed regulation stability and protection reliability under high speed, low duty cycle, and load change conditions. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0018] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings: Figure 1 A schematic diagram of a three-phase full-bridge power circuit structure provided in an embodiment of this disclosure.

[0019] Figure 2 This is a schematic diagram of a high-speed brushless anti-interference motor control method provided in an embodiment of this application.

[0020] Figure 3 This is a schematic diagram of the predicted three-phase current replacement process provided in an embodiment of this disclosure.

[0021] Figure 4 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0022] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0023] This implementation method is applicable to a high-speed brushless motor control board employing a three-phase full-bridge power circuit, a single current sensor, and a Hall sensor. The control board consists of a control IC, six MOSFETs, a gate driver, a bus current sampling circuit, a Hall signal input circuit, a power input filter circuit, and a four-layer circuit board; wherein, as shown... Figure 1 As shown, Figure 1 This is a schematic diagram of a three-phase full-bridge power circuit provided in an embodiment of this disclosure. The three-phase full-bridge power circuit is powered by the DC bus Vdc. The three bridge arms are composed of upper and lower bridge arm MOSFETs T1 / T2, T3 / T4, and T5 / T6, respectively. Each MOSFET is equipped with an anti-parallel freewheeling diode. The midpoints of the three bridge arms form three phase nodes Va, Vc, and Vb, respectively. The control IC drives the six MOSFETs through gate signals g1 to g6 and forms corresponding MOSFET conduction combinations according to the current PWM duty cycle and commutation state. The power circuit shown in the figure is used to determine the direction, phase, and phase current sign of the bus current under different effective switching states, which corresponds to the bus current sampling, effective sampling interval planning, and three-phase current reconstruction process.

[0024] The control IC outputs a high-frequency pulse width modulation signal and completes bus current sampling, three-phase current reconstruction, Hall edge verification, speed calculation, duty cycle update, and commutation status update using the PWM cycle as the basic processing unit; in order to execute the high-speed brushless anti-interference motor control method; before implementation, the number of motor pole pairs, maximum speed, resistance parameters, and inductance parameters are obtained, and the dead time, ADC sampling and holding time, MOSFET switching delay, and spike blanking time are set or calibrated.

[0025] Before implementation, the minimum allowable turn-on time of the MOSFET, the standby confirmation time, the upper limit of the number of consecutive cycles of failed three-phase current reconstruction, the maximum duty cycle, and the overcurrent protection conditions are written into the control IC parameter area. These parameters are used as fixed configuration parameters corresponding to the rated range of the current MOSFET, gate driver, PWM timer, bus current sampling circuit, and power devices; they will not automatically change during operation if the hardware configuration remains unchanged. The upper limit of the number of consecutive cycles of failed three-phase current reconstruction is an integer not less than 1.

[0026] The implementation process of the high-speed brushless anti-interference motor control method described in this application will be explained in detail below with reference to specific embodiments. It should be noted that this embodiment is only used to explain this application and is not intended to limit the scope of protection of this application. Conventional adjustments or substitutions of each step by those skilled in the art without departing from the concept of this application should be included in the protection scope of this application.

[0027] like Figure 2 As shown in the figure, this application discloses a schematic diagram of a high-speed brushless anti-interference motor control method, which includes the following method steps: S1. The correspondence between the bus current and the phase current is determined based on the MOSFET conduction combination of the PWM cycle. The effective sampling interval is obtained by subtracting the dead time, switching delay, spike blanking time and ADC sampling and holding time from the conduction time determined by the PWM duty cycle. S2, when the effective sampling interval meets the ADC sampling, the bus current is collected and the reconstructed three-phase current is formed according to the corresponding relationship. The residual of the sum of the three-phase current and the direction of current change are verified. If the verification is passed, the control three-phase current is updated with the reconstructed three-phase current; otherwise, the control three-phase current is not updated. S3, when the effective sampling interval does not meet the ADC sampling, the PWM pulse is moved and recalculated while keeping the cumulative conduction time of each phase unchanged; when the ADC sampling is still not met after recalculation, the predicted three-phase current is obtained based on the control three-phase current of the previous effective cycle, the current voltage command and the resistance and inductance parameters, and the predicted three-phase current is used as the control three-phase current, and the reconstructed three-phase current that has passed the verification is replaced by the predicted three-phase current. S4 verifies the phase sequence and duration of the Hall edge, discards unqualified Hall edges, obtains the speed from the total time of the six Hall sectors of a complete electrical cycle, and updates the PWM duty cycle and commutation state with three-phase current based on the speed and control.

[0028] In some embodiments, for step S1, the control IC pre-stores the correspondence between the MOSFET conduction combinations and the bus current and phase current based on the connection relationship of the six MOSFETs in the three-phase full-bridge circuit. This correspondence is determined by the current path of the power circuit in each effective switching state. The recorded content includes at least the current MOSFET conduction combination, the direction of the bus current, the phase corresponding to the bus current, the phase current symbol, and the allowed change category of the phase current participating in the conduction path under the corresponding Hall sector and direction. In the zero vector state, the bus current cannot directly distinguish the phase current, and the control IC does not set this state as the sampling state for three-phase current reconstruction. For effective switching states that can reflect the phase current, the control IC writes them into the correspondence table, and subsequently queries the phase and symbol based on the actual MOSFET conduction combination.

[0029] Before the start of each PWM cycle, the control IC reads the PWM duty cycle and commutation state of the next PWM cycle, and generates the MOSFET conduction combinations and switching edge times for the next PWM cycle based on these two data. The commutation state determines the bridge arm participating in modulation within the current Hall sector, and the PWM duty cycle determines the cumulative conduction time of the corresponding MOSFET in the next PWM cycle. The control IC then generates sampling planning data, which includes the MOSFET conduction combinations, candidate stable conduction time periods, and their corresponding relationships. This sampling planning data only corresponds to the next PWM cycle and takes effect after being written to the timer at the PWM cycle boundary, preventing misalignment between the currently executing PWM waveform and the newly generated sampling planning data.

[0030] For each candidate stable conduction time period in the sampling planning data, the control IC first determines the conduction time formed by the PWM duty cycle, and then deducts it according to the actual occupied position of the dead time, MOSFET switching delay, spike blanking time and ADC sampling and holding time in the candidate stable conduction time period; the remaining continuous time period after deduction is taken as the candidate effective sampling interval, and the length of the continuous time period is taken as the sampling time margin.

[0031] For example, the sampling time margin is determined by the following formula:

[0032] in, This refers to the length of the remaining continuous sampleable period after deducting the time occupied by various items. This refers to the conduction time corresponding to the candidate stable conduction time period. This represents the total dead zone time that needs to be avoided within this time period. This is the switching delay from the gate signal change to the phase node completing the transition. The spike blanking time required for the switching spike to attenuate until the bus current sampling signal returns to stability. The sample-and-hold time required for the ADC to complete one sampling is given, wherein the above time uses the same timing reference of the control IC timer.

[0033] The dead time and ADC sample-and-hold time are taken from the configuration values ​​of the control IC. The MOSFET switching delay is obtained during the prototype debugging phase. Specifically, test pulses are output under motor-stopped or low-risk current-limiting conditions, and the gate waveform and phase node waveform are observed simultaneously. The time between the gate waveform reaching an effective level and the phase node completing the main voltage transition is recorded as the switching delay. The spike blanking time is also calibrated under test pulse conditions. The phase node transition and bus current sampling signal are observed simultaneously by the control IC or an external oscilloscope. The time from the start of the phase node transition to the bus current sampling signal entering the zero current noise range or stable current fluctuation range is recorded as the spike blanking time.

[0034] In some embodiments, for step S2, when When, the continuous time period remaining after deducting the time occupied by each item constitutes the effective sampling interval; when If the effective sampling interval is not constituted, the control IC sets the ADC trigger time in the middle of the effective sampling interval; the ADC sampling and holding process is maintained at the time interval between the two switching edges before and after; if there are two effective sampling intervals corresponding to different phase currents within the same PWM cycle, the control IC generates the first planned sampling time and the second planned sampling time respectively, and writes them together with their respective MOS transistor conduction combinations into the PWM timer's comparison register; only after both planned sampling times are executed can the reconstructed three-phase current of the PWM cycle be formed.

[0035] When the PWM timer reaches the first planned sampling time, the ADC is triggered by a comparison event. The ADC reads the output of the single current sensor and forms the first bus current sample. When it reaches the second planned sampling time, the second bus current sample is formed in the same way. The control IC saves the corresponding MOSFET conduction combination and ADC completion status for each bus current sample. The ADC completion status is written when a conversion completion interrupt or direct memory access completion event occurs. The first bus current sample, the second bus current sample, the corresponding MOSFET conduction combination, and the ADC completion status together constitute the sampling record of the current PWM cycle. Subsequent three-phase current reconstructions only read data from the same sampling record.

[0036] Before entering the corresponding conversion, the raw ADC value undergoes bus current zero-point correction. When the control board is powered on, all MOSFETs are off, and the motor is stationary, the control IC continuously acquires a set of ADC data, taking the average value of this set as the bus current zero point. The maximum absolute deviation of each ADC data point relative to the bus current zero point is converted into current using the same sampling resistance and sampling amplification factor conversion relationship as the bus current sample. The maximum absolute deviation after conversion is taken as the zero-current noise range. During operation, the control IC subtracts the bus current zero point from the raw ADC value and converts it into a bus current sample using the sampling resistance and sampling amplification factor. After the equipment re-enters the confirmed no-current shutdown state, the above acquisition process can be repeated, replacing the original value with the newly acquired bus current zero point and zero-current noise range. The confirmation conditions for the shutdown state include PWM output being off, all MOSFETs being off, and the Hall edge not changing within the pre-written static confirmation time in the control IC parameter area. Zero-point update is not performed if these conditions are not met.

[0037] In some embodiments, for step S3, such as Figure 3 As shown, Figure 3This is a schematic diagram of the predicted three-phase current replacement process provided in the embodiments of this disclosure. In S301: when the effective sampling interval does not meet the ADC sampling, the PWM pulse is shifted and recalculated while keeping the cumulative conduction time of each phase unchanged.

[0038] After the control IC completes the calculation of the sampling time margin for the next PWM cycle to be executed, it processes the PWM cycle to be executed according to a fixed priority. When two effective sampling intervals corresponding to different phase currents can be formed, the control IC directly adopts the corresponding first and second planned sampling times, without performing PWM pulse shifting or generating predicted three-phase currents. When the above two effective sampling intervals cannot be formed, the control IC enters PWM pulse shifting processing.

[0039] In S302: If the ADC sampling is still not satisfied after recalculation, the predicted three-phase current is obtained based on the control three-phase current of the previous effective cycle, the current voltage command, and the resistance and inductance parameters. The predicted three-phase current is used as the control three-phase current, and the reconstructed three-phase current that has passed the verification is used to replace the predicted three-phase current.

[0040] After completing the PWM pulse shift and recalculation, if two effective sampling intervals corresponding to different phase currents can be formed, the ADC sampling is performed according to the recalculated planned sampling time. If the above two effective sampling intervals cannot be formed after recalculation, the control IC enters the prediction three-phase current processing if the reconstructed three-phase current that has passed the most recent verification has been saved.

[0041] In one implementation, the control IC calculates the maximum allowable movement amount that can be provided by forward and backward movement, and calculates the minimum movement amount required to form the first and second effective sampling intervals in the forward and backward directions, respectively. If the minimum required movement amount in a certain direction is not greater than the maximum allowable movement amount in that direction, that direction is considered feasible. If both directions are feasible, the minimum required movement amount with the smaller absolute value is selected. If only one direction is feasible, the minimum required movement amount in that direction is used. If neither direction is feasible, the PWM pulse movement is deemed to have failed. After the movement amount is determined, the control IC updates the timing of each switching edge, regenerates the MOSFET conduction combinations and candidate stable conduction time periods, and recalculates the sampling time margin. Because the rising and falling edges move as a whole, the cumulative conduction time of each phase in the current PWM cycle remains unchanged, and the corresponding average phase voltage command remains unchanged.

[0042] PWM pulse shifting only adjusts the waveform position of the next PWM cycle to be executed, without changing the PWM frequency, commutation state, or the original PWM duty cycle of the next PWM cycle. The shift amount, the planned sampling time after shift, the MOSFET conduction combination after shift, and the sampling planning data should all be calculated before the PWM cycle boundary is reached, and written to the PWM timer at that boundary; if the synchronization update is not completed, the control IC will not load the shifted PWM waveform.

[0043] When the most recently verified reconstructed three-phase current has been saved, and the PWM pulse shift still cannot form the required two effective sampling intervals, the control IC reads the control three-phase current of the previous effective cycle, the current voltage command, resistance parameters, inductance parameters, and the current PWM cycle duration, calculates the predicted phase current of each of the three phases, and combines the three predicted phase currents into a predicted three-phase current. In the first prediction cycle after the lack of effective sampling intervals, the phase current of the previous state is taken from the most recently verified reconstructed three-phase current; in continuous prediction cycles, the phase current of the previous state is taken from the predicted three-phase current of the previous PWM cycle after limiting. The control IC also retains the most recently verified reconstructed three-phase current as the source record of the continuous prediction chain, directly calculating a prediction result across multiple PWM cycles without accumulating time. For example, the predicted phase current of each phase is calculated according to a discrete resistance-inductance model:

[0044] in The predicted phase current for the current PWM cycle. This refers to the control phase current of the corresponding phase in the previous PWM cycle. In the first prediction cycle, it is the reconstructed phase current that passed the most recent verification. In continuous prediction cycles, it is the predicted phase current of the previous PWM cycle after being limited. Where (L) is the current PWM cycle duration, and (L) is the inductance parameter of the corresponding phase of the motor. (R) represents the phase voltage command for the corresponding phase in the current voltage command, and (R) represents the resistance parameter of the corresponding phase of the motor.

[0045] The resistance and inductance parameters are taken from the motor specification data or the calibration values ​​obtained from the static measurement and step test of the prototype, and are saved as fixed parameters under the same motor model. The current voltage command is the phase voltage command that has been determined before entering the current PWM cycle and is used to generate the current PWM duty cycle. The three phase voltage commands are respectively entered into the prediction calculation of the corresponding phase, and other voltage quantities that are not involved in the current commutation state are not used. The three-phase current for control formed in the current PWM cycle only participates in the PWM duty cycle update of the next PWM cycle and does not modify the current voltage command of the current PWM cycle.

[0046] The control IC performs limiting processing on the three predicted phase currents, corresponding to the rated currents of the power devices. The limited predicted three-phase currents are used as the control three-phase currents for the current PWM cycle, participating in dead-zone compensation, PWM duty cycle updates, and fault protection judgment. The predicted three-phase currents are only used in consecutive cycles where there is no effective sampling interval. When the first bus current sample and the second bus current sample are obtained again in subsequent PWM cycles and a verified reconstructed three-phase current is formed, the control IC replaces the predicted three-phase current with the reconstructed three-phase current, and at the same time, the cumulative number of PWM cycles for prediction is cleared to zero. If the number of consecutive cycles in which a verified reconstructed three-phase current is not obtained reaches the upper limit preset by the control IC, the control IC reduces the PWM duty cycle and enters the protection state to prevent the resistor-inductor model from continuously participating in control when there are no real samples for a long time.

[0047] In some embodiments, for step S4, when the ADC completion states of both the first bus current sample and the second bus current sample are valid, the control IC reads the MOSFET conduction combinations corresponding to the two samples respectively and queries the correspondence established in the previous steps; wherein, the first bus current sample is converted into the first phase current according to the first MOSFET conduction combination, and the second bus current sample is converted into the second phase current according to the second MOSFET conduction combination; the conversion process includes phase allocation and sign processing, without changing the amplitude calibration relationship of the bus current sample. If the two samples are mapped to the same phase, or if any MOSFET conduction combination does not belong to a valid switching state in the correspondence table, then the current sampling record does not form a reconstructed three-phase current, the control IC maintains the control three-phase current of the previous PWM cycle, and records this situation as a sampling planning abnormality.

[0048] When two samples correspond to two different phases, the control IC calculates the third-phase current based on the zero instantaneous sum of the three-phase currents. The three-phase currents are reconstructed in a fixed order of phase A, phase B, and phase C. In practical applications, the control IC uses an internal data format with higher accuracy than the PWM output calculation to calculate the third-phase current, followed by uniform scaling and numerical limiting. The difference between the sum of the three-phase currents after scaling and numerical limiting and zero is used as the residual of the sum of the three-phase currents. This residual does not participate in the recalculation of the third-phase current; it is only used to verify inconsistencies arising during scaling, numerical limiting, and fixed-point calculations, and is not used as an independent verification quantity for the physical consistency of the two bus current samples.

[0049] The control IC first compares the residual of the sum of the three-phase currents with the zero-current noise range expressed in the same current unit; if the absolute value of the residual is not greater than the zero-current noise range, the residual check is passed; if the absolute value of the residual is greater than the zero-current noise range, the residual check is not passed; the zero-current noise range is obtained from the shutdown sampling results.

[0050] After residual verification, the control IC verifies the current change direction based on the current Hall sector and the current MOSFET conduction combination. The control IC pre-stores the phase current direction relationship corresponding to each effective MOSFET conduction combination in the six Hall sectors. This direction relationship is determined by the three-phase full-bridge current path and the forward and reverse phase conversion sequence.

[0051] The directional relationship records at least the Hall sector, MOSFET conduction combination, phase participating in the current conduction path, the allowed phase current sign of each participating phase, and the allowed current change category. The control IC subtracts the control phase current corresponding to the previous PWM cycle from the current reconstructed phase current. When the difference is greater than zero, it is recorded as an increase; when the difference is less than zero, it is recorded as a decrease; and when the difference is equal to zero, it is recorded as unchanged. For each phase participating in the current conduction path, the actual phase current sign and the actual change category are compared with the allowed value recorded in the directional relationship table. If any participating phase does not meet the allowed value, it is determined that the current change direction verification has failed.

[0052] The control IC compares the reconstructed three-phase current with the control three-phase current of the previous PWM cycle to obtain the direction of increase or decrease of each phase current. Then it checks whether the sign and direction of increase or decrease of the phase current participating in the current conduction path conform to the stated direction relationship. If the Hall sector has not yet passed the edge verification, the previously verified Hall sector continues to be used.

[0053] When both residual verification and current change direction verification pass, the control IC updates the control three-phase current with the reconstructed three-phase current. If either verification fails, the control IC does not update the control three-phase current with the reconstructed three-phase current, and the control three-phase current of the previous PWM cycle continues to be used in the current control cycle. At the same time, the control IC limits the reconstructed three-phase current that failed the verification within the rated range and writes the limiting result into the fault protection judgment. The fault protection judgment only checks whether the limiting result meets the overcurrent protection condition, and does not send the limiting result to the initial value of speed regulation, dead zone compensation, or the current prediction of the next cycle, thus clarifying the destination of the data that failed the verification.

[0054] In one embodiment, when the reconstructed three-phase current passes two checks, the control IC first overwrites the control three-phase current with the reconstructed three-phase current of the current PWM cycle, and then saves the control three-phase current as the most recent valid result for subsequent use when there is a lack of valid sampling intervals. The saved content is written in a fixed order of phase A, phase B, and phase C, and the corresponding PWM cycle number, Hall sector, and commutation status are recorded at the same time.

[0055] When the reconstructed three-phase current fails the verification, the control IC retains the control three-phase current from the previous PWM cycle and does not write the failed reconstructed three-phase current into the most recent valid result. If the control three-phase current from the previous PWM cycle comes from the predicted three-phase current, the current PWM cycle continues to use the predicted three-phase current, and the number of cycles with consecutive failed reconstructed three-phase currents is increased by one. If the control three-phase current from the previous PWM cycle comes from a verified reconstructed three-phase current, the reconstructed three-phase current is maintained for one PWM cycle. The control IC still limits the failed reconstructed three-phase current and compares the limited three-phase current phase by phase with the overcurrent protection condition. If any phase meets the overcurrent protection condition, overcurrent protection is initiated. This limiting result is discarded after the fault protection judgment ends and is not written into the speed control input or predicted initial value of the next PWM cycle.

[0056] When the motor has just started running and before the first set of reconstructed three-phase currents that have passed the verification are formed, the control IC maintains the PWM duty cycle set during the startup phase and prioritizes obtaining the first valid sampling record through PWM pulse movement. After the first set of reconstructed three-phase currents passes the verification, the control IC writes it into the control three-phase current and the most recent valid result, and then allows the predicted three-phase current branch to participate in the processing.

[0057] In one embodiment, after the control IC obtains the three-phase current for control in the current PWM cycle, it corrects the conduction time of the corresponding PWM pulse in the next PWM cycle according to the direction of the current in each phase. For a certain phase, when the current direction of the phase causes the actual conduction time to be shortened by the dead zone, the control IC adds a compensation time to the conduction time corresponding to the original PWM duty cycle. When the current direction of the phase causes the actual conduction time to be extended by the dead zone, the control IC reduces the compensation time. After compensation, the minimum turn-on time, maximum duty cycle and dead zone constraints are still executed. The part that exceeds the allowable range is directly cut off and not transferred to other phases.

[0058] The compensation time is based on the dead time set by the control IC and the correction value is obtained through no-load low-speed tests. During the test, the motor load and power supply conditions are kept stable, the correction value is adjusted step by step, the continuity of the phase current before and after commutation is observed, and the sudden change in phase current before and after commutation corresponding to each candidate correction value is recorded. Among the candidate correction values ​​that do not show shoot-through in the same bridge arm, the correction value with the smallest absolute value of the sudden change in phase current before and after commutation is selected and written into the parameter area.

[0059] In one embodiment, the Hall input circuit sends the combined levels of the three Hall sensors to the control IC. When any Hall input changes, the control IC records the candidate Hall edge, the candidate Hall state, and the edge arrival time. Forward and reverse rotations correspond to a fixed six-step Hall sequence. The control IC compares the candidate Hall state with the previous Hall state that has passed the verification. If the two match the next Hall state corresponding to the current rotation, the Hall edge phase sequence is verified. Otherwise, the candidate Hall edge is discarded, and the previous Hall state, commutation state, and sector timing start point remain unchanged.

[0060] After the Hall edge phase sequence is verified, the control IC calculates the duration between the candidate Hall edge and the previous verified Hall edge, and compares it with the minimum sector time.

[0061] The minimum sector time is determined based on the number of pole pairs and the maximum speed of the motor, and can be expressed by the formula:

[0062] in, Minimum sector time, in seconds; This represents the number of pole pairs of the motor. When the maximum speed is measured in revolutions per minute and the duration is shorter than the minimum sector time, the control IC will identify the candidate Hall edge as an unqualified Hall edge and discard it; when the duration is not shorter than the minimum sector time, the candidate Hall edge will be identified as a valid Hall edge, the Hall state, Hall sector and sector timing start point will be updated, and the commutation state will be updated according to the new Hall sector.

[0063] The IC stores the duration of the six most recent consecutive and verified Hall sectors. After the six Hall sectors appear completely in the Hall sequence for the current direction, the six durations are added together to obtain the total time of the six Hall sectors for a complete electrical cycle, and the rotational speed is calculated using the following formula:

[0064] in, Rotational speed, measured in revolutions per minute; This represents the number of pole pairs of the motor. The total time for the six Hall sectors of a complete electrical cycle is in seconds. If a candidate Hall edge is discarded in the six Hall sectors, the control IC will not write the candidate Hall edge into the duration sequence. Instead, it will calculate the duration of the corresponding Hall sector based on the two adjacent Hall edges that pass the verification. If six consecutive Hall sectors are not collected, the control IC will maintain the rotational speed calculated in the previous complete electrical cycle.

[0065] Upon entering a new Hall sector, the control IC reads the duration of the same Hall sector in the previous complete electrical cycle, uses it as the estimated duration of the current Hall sector, and estimates the electrical angle within the sector based on the elapsed time of the current Hall sector. For example, the electrical angle within the sector is determined by the following formula:

[0066] in, For the electrical angle within the sector, The starting electrical angle of the current Hall sector. This refers to the time elapsed from the current Hall sector start point to the current control cycle. The duration of the same Hall sector in the previous complete electrical cycle; when Reaching or exceeding Furthermore, before a new verified Hall edge arrives, the control IC limits the electrical angle within the sector to the termination electrical angle of the current Hall sector, without prematurely updating the commutation state.

[0067] The electrical angle within the sector is written into the angle position calculation during the speed regulation process, and short-time current prediction is also written to determine the phase corresponding to the current voltage command; the actual commutation state is only updated based on the verified Hall edge.

[0068] After a new verified Hall edge arrives, the control IC determines the time of arrival of that edge according to the actual arrival time. The estimated electrical angle without termination angle limitation is calculated using the aforementioned electrical angle relationship within the sector. The difference between the termination electrical angle of the current Hall sector and the estimated electrical angle without limitation is defined as the signed electrical angle estimation error within the sector. The control IC determines the number of correction cycles based on the current control cycle and the expected duration of the next Hall sector. The electrical angle estimation error is evenly distributed to subsequent correction cycles, and the electrical angle within the sector is corrected cycle by cycle. The number of correction cycles is at least one and does not exceed the number of control cycles expected to be included in the next Hall sector. After the correction is completed, the estimation error is cleared.

[0069] In some embodiments, the control IC uses the speed calculated from a complete electrical cycle and the current three-phase current used for control as speed regulation inputs to generate the PWM duty cycle for the next PWM cycle; the commutation state comes from the most recently verified Hall edge; the PWM duty cycle and commutation state are only written to the PWM timer at the PWM cycle boundary, and the already effective switching edges are not rewritten during the execution of the current PWM cycle; the control IC first completes the dead-time compensation for the next PWM cycle based on the three-phase current used for control, and then generates sampling planning data based on each compensated switching edge; when the sampling interval is insufficient, the compensated PWM pulses are shifted as a whole.

[0070] ADC triggering is generated by the PWM timer's compare event. The control IC sets the corresponding ADC completion status for each planned sampling time. Before the planned sampling time arrives, the ADC completion status is cleared to zero, and after the ADC conversion is completed, it is set to complete. Before the end of the current PWM cycle, the control IC checks the planned sampling time and the ADC completion status: if the planned sampling time has arrived but the corresponding ADC completion status is still incomplete, or if the ADC completion event does not correspond to the current planned sampling time, it is determined to be an ADC timing anomaly. After an ADC timing anomaly occurs, the control IC discards the corresponding bus current sample, does not perform the reconstructed three-phase current update based on the bus current sample, and maintains the PWM duty cycle and commutation status of the previous PWM cycle for one PWM cycle.

[0071] In one embodiment, the control IC sets a continuous fault flag to distinguish between single faults and continuous faults; when the first ADC timing fault occurs, the continuous fault flag is set; when no ADC timing fault occurs in the next PWM cycle, the continuous fault flag is cleared and normal PWM duty cycle updates are restored; when the ADC timing fault occurs again in the next PWM cycle and the continuous fault flag is set, the control IC reduces the PWM duty cycle and enters the protection state, while simultaneously shutting down subsequent three-phase current updates until shutdown reset or the fault condition is cleared.

[0072] In some embodiments, such as Figure 1 As shown, the power input terminal is equipped with an LC filter network consisting of a common-mode inductor, an X capacitor, and a Y capacitor. The X capacitor is connected across the power lines, and the Y capacitor is connected to the reference ground or protective ground path. A varistor is placed on the power input side to clamp the input surge. The full-bridge rectifier structure and the high-frequency capacitor form a π-type filter. For example, the high-frequency capacitor can be configured to be 0.1 microfarads, and the specific withstand voltage level is determined according to the input voltage.

[0073] In some embodiments, the circuit board employs a four-layer structure, with digital ground and analog ground connected at a single point via a 0-ohm resistor. The signal line from the single current sensor to the ADC is arranged in pairs with the analog ground return line and returns to the analog ground region before the single-point connection. The power loop current does not pass through the analog ground return line. The gate driver is positioned close to the corresponding MOSFET, and the gate output line is arranged in parallel with the return line. The phase node copper foil is confined to the power region and does not extend below the ADC input line and Hall signal line. For example, the PWM signal line width can be configured to 8 mils, the line spacing is not less than 12 mils, and the impedance can be controlled to 50 ohms with a manufacturing tolerance of ±5 ohms allowed.

[0074] The MOSFET heat dissipation pads employ a via-in-pad process, also known as the Via-in-Pad process. The heat dissipation vias connect from the device pads to the inner layer and the back copper surface. For example, the via diameter can be configured to 12 mils and evenly distributed within the heat dissipation pad area to avoid vias being concentrated on one side. The number of vias is determined based on the MOSFET loss, copper thickness, and available pad area. The arrangement results are confirmed through continuous operation temperature rise tests during the prototype stage.

[0075] Therefore, the correspondence between bus current and phase current is determined by the MOSFET conduction combination. The effective sampling interval is calculated in each PWM cycle, and the three-phase current for control is formed according to the mutually exclusive order of effective sampling, PWM pulse movement, and short-time current prediction. After the reconstruction result is verified by residual and current change direction, it enters the speed regulation, dead zone compensation, and protection processing. The Hall edge is processed according to phase sequence, duration, and complete electrical cycle. The PWM update, commutation update, and ADC trigger use the same timing reference. With the input filtering, four-layer circuit board layout, and MOSFET heat dissipation structure, the impact of high speed narrow pulse width, Hall edge abnormality, and switching transients on the control process can be reduced.

[0076] It should be noted that although the operations of the method of this application are described in a specific order in the accompanying drawings, this does not require or imply that these operations must be performed in that specific order, or that all the operations shown must be performed to achieve the desired result. On the contrary, the steps depicted in the flowchart can be performed in a different order. Additionally or alternatively, certain steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps.

[0077] Based on the same inventive concept, this application also provides an electronic device, such as... Figure 4 As shown, Figure 4 This is a schematic diagram of an electronic device structure according to an embodiment of the present disclosure. The method corresponding to the electronic device can be the method in the foregoing embodiments, and its problem-solving principle is similar to that method. The electronic device provided in this application includes: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute the methods and / or technical solutions of the foregoing embodiments of the present application.

[0078] Specifically, the methods and / or embodiments in this application can be implemented as computer software programs. For example, the embodiments disclosed in this application include a computer program product comprising a computer program carried on a storage medium, the computer program containing program code for performing the methods shown in the flowchart. When the computer program is executed by a central processing unit, it performs the functions defined in the methods of this application.

[0079] Another embodiment of this application provides a computer-readable storage medium having computer program instructions stored thereon, which can be executed by a processor to implement the methods and / or technical solutions of any one or more embodiments of this application described above.

[0080] The flowcharts or block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of electronic devices, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-specific system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0081] The above description represents the preferred embodiments of the present invention. It should be noted that, for those skilled in the art, various improvements and modifications can be made without departing from the principles of the present invention, and these improvements and modifications are also considered to be within the scope of protection of the present invention.

Claims

1. A high-speed brushless anti-interference motor control board, characterized in that, It includes at least a three-phase full-bridge power circuit and a control IC, wherein the control IC is used to execute the following high-speed brushless anti-interference motor control method: The correspondence between bus current and phase current is determined based on the MOSFET conduction combination of the PWM cycle. The effective sampling interval is obtained by subtracting the dead time, switching delay, spike blanking time and ADC sampling and holding time from the conduction time determined by the PWM duty cycle. When the effective sampling interval meets the ADC sampling requirements, the bus current is collected and the reconstructed three-phase current is formed according to the corresponding relationship. The residual of the sum of the three-phase current and the direction of current change are verified. If the verification is passed, the control three-phase current is updated with the reconstructed three-phase current; otherwise, the control three-phase current is not updated. If the effective sampling interval does not meet the ADC sampling requirements, the PWM pulse is shifted and recalculated while keeping the cumulative conduction time of each phase unchanged. If the ADC sampling requirements are still not met after recalculation, the predicted three-phase current is obtained based on the control three-phase current of the previous effective cycle, the current voltage command, and the resistance and inductance parameters. The predicted three-phase current is used as the control three-phase current, and the reconstructed three-phase current that has passed the verification is used to replace the predicted three-phase current. Verify the phase sequence and duration of the Hall edge, discard unqualified Hall edges, obtain the speed from the total time of the six Hall sectors of a complete electrical cycle, and update the PWM duty cycle and commutation state with three-phase current based on the speed and control.

2. The high-speed brushless anti-interference motor control board according to claim 1, characterized in that, The control method further includes obtaining two bus current samples within the effective sampling interval, converting the two bus current samples into two-phase currents according to the correspondence, calculating the third-phase current based on the instantaneous sum of the three-phase currents being zero, and combining the two-phase currents and the third-phase current to form a reconstructed three-phase current.

3. The high-speed brushless anti-interference motor control board according to claim 2, characterized in that, The control method further includes: acquiring a set of ADC data when all MOSFETs are turned off and the motor is stationary; determining the average value of the ADC data as the bus current zero point; determining the maximum absolute deviation of each ADC data relative to the average value as the zero current noise range; and verifying the residual of the sum of the three-phase currents based on the zero current noise range; and re-acquiring ADC data in a shutdown state where no current is confirmed, and replacing the original values ​​with the newly determined bus current zero point and zero current noise range.

4. The high-speed brushless anti-interference motor control board according to claim 3, characterized in that, The control method further includes verifying the current change direction of the reconstructed three-phase current based on the current Hall sector and the conduction state of the MOS transistor; if the reconstructed three-phase current fails the residual verification of the sum of the three-phase currents or the current change direction verification, the control three-phase current is not updated with the reconstructed three-phase current, and the reconstructed three-phase current is written into the fault protection judgment after being limited.

5. A high-speed brushless anti-interference motor control board according to claim 4, characterized in that, The control method further includes verifying the phase sequence of the Hall edges according to the six-step Hall sequence corresponding to forward or reverse rotation and determining the minimum sector time; when the duration between adjacent Hall edges is shorter than the minimum sector time, the subsequent Hall edge is determined as a non-qualified Hall edge.

6. A high-speed brushless anti-interference motor control board according to claim 5, characterized in that, The control method further includes estimating the electrical angle within the sector based on the duration of the same Hall sector in the previous complete electrical cycle after entering a new Hall sector; the electrical angle within the sector is written into the speed regulation calculation and short-time current prediction, and the commutation state is updated based on the verified Hall edge; after the arrival of a new Hall edge, the estimation error of the electrical angle within the sector is allocated to subsequent control cycles for successive correction.

7. A high-speed brushless anti-interference motor control board according to claim 4, characterized in that, The control method further includes correcting the conduction time of the corresponding PWM pulse according to the direction of the corresponding phase current in the three-phase current used for control; increasing the compensation time when the phase current direction shortens the dead zone of the actual conduction time, and decreasing the compensation time when the dead zone of the actual conduction time is extended; the compensation time is based on the dead time and updated according to the correction value obtained from the phase current continuity test before and after phase commutation under no-load low speed state.

8. A high-speed brushless anti-interference motor control board according to claim 1, characterized in that, The control method further includes: ADC triggering is generated by the comparison event of the PWM timer; the PWM duty cycle and commutation state are updated only at the boundaries of the PWM cycle; the MOSFET conduction combination of the current PWM cycle, the planned sampling time, and the ADC completion state are combined into state data; when the ADC completion state is inconsistent with the planned sampling time, the corresponding bus current sample is discarded, and the PWM duty cycle and commutation state of the previous PWM cycle are maintained for one PWM cycle; when the inconsistency occurs again in the next PWM cycle, the PWM duty cycle is reduced and the system enters a protection state.

9. A high-speed brushless anti-interference motor control board according to claim 1, characterized in that, The power input terminal of the control board is equipped with an LC filter network consisting of a common-mode inductor, an X capacitor, and a Y capacitor, as well as a varistor; the full-bridge rectifier structure and a 0.1μF high-frequency capacitor form a π-type filter, wherein the X capacitor is set in the differential-mode branch and the Y capacitor is set in the common-mode branch.

10. A high-speed brushless anti-interference motor control board according to claim 9, characterized in that, The control board uses a four-layer circuit board, with digital ground and analog ground connected at a single point via a 0Ω resistor; the PWM signal line has a line width of 8mil, a line spacing of not less than 12mil, and an impedance of 50±5Ω; the signal line from the single current sensor to the ADC is arranged in pairs with the analog ground return line, and returns to the analog ground area before the single point connection. The gate driver is positioned close to the corresponding MOSFET, and the gate output line and return line are arranged in parallel. The phase node copper foil is located in the power area and does not extend below the ADC input line and Hall signal line.

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