Electronic load overshoot suppression circuit and control method

Abstract

The application provides an electronic load overshoot suppression circuit and a control method, and relates to the technical field of electronic loads. The circuit comprises: a control circuit, a first end of which is connected to a first end of a given circuit, a first end of a limiting circuit and a first end of a peak value detection circuit; a second end of the given circuit is connected to a first end of each power unit, a second end of the limiting circuit is connected to a second end of each power unit, a third end of each power unit is connected to form a total current output end and is connected to a second end of the peak value detection circuit, and a fourth end is used for connecting a measured power supply. The control circuit sends a current given signal and a limiting setting signal according to a target current value, the given signal passes through the given circuit to each power unit, and the limiting signal is converted into an output limiting value; the output currents of each power unit are combined into a total output current; the peak value detection circuit detects the peak value and feeds back to the control circuit; and the control circuit adjusts the limiting setting signal according to the peak current to suppress overshoot. The application realizes accurate control of overshoot in a closed loop under different working conditions.

Description

Technical Field

[0001] This invention relates to the field of electronic load technology, and more specifically, to an electronic load overshoot suppression circuit and control method. Background Technology

[0002] Electronic loads are core instruments in power supply testing, widely used in the research and development and production testing of server power supplies, communication power supplies, and other fields. With the rapid development of artificial intelligence data centers, the requirements for dynamic response performance of AI server power supplies are increasing, and electronic loads need to maintain precise control of output current under higher current slew rates and faster pulse frequencies.

[0003] In related technologies, conventional parallel electronic loads typically consist of multiple power units connected in parallel, with each unit sharing a control loop. Output current distribution and regulation are achieved through a unified current command. However, in practical testing applications, when there is a significant cable parasitic inductance between the power supply under test and the electronic load, existing architectures are prone to output current overshoot during high-current slew rate dynamic testing or high-frequency pulse testing. Furthermore, significant current overshoot is also observed under conditions such as load start-up. These problems manifest differently under varying output current levels and parasitic inductance conditions, and existing electronic loads lack effective adaptive suppression mechanisms, thus limiting their performance under high-dynamic testing conditions. Summary of the Invention

[0004] The problem solved by this invention is how to effectively suppress output current overshoot under different operating conditions while ensuring the dynamic response performance of electronic loads.

[0005] To address the above problems, this invention provides an electronic load overshoot suppression circuit and control method.

[0006] In a first aspect, the present invention provides an electronic load overshoot suppression circuit, comprising: multiple power units, a control loop setpoint circuit, a control loop limiting circuit, a peak detection circuit with zeroing function, and a control circuit; The first terminal of the control circuit is connected to the first terminal of the control loop setpoint circuit; the second terminal of the control circuit is connected to the first terminal of the control loop limiting circuit; the third terminal of the control circuit is connected to the first terminal of the peak detection circuit with zeroing function; the second terminal of the control loop setpoint circuit is connected to the first terminal of each power unit; and the second terminal of the control loop limiting circuit is connected to the second terminal of each power unit. The third terminal of each power unit is connected to form the total current output terminal, and is connected to the second terminal of the peak detection circuit with zeroing. The fourth terminal of each power unit is used to connect to the power supply under test. The control circuit is used to issue a current setpoint signal and a limiting setting signal according to the target current value. The current setpoint signal is transmitted to each power unit through the control loop setpoint circuit, and the limiting setting signal is converted into the output limiting value of each power unit through the control loop limiting circuit. Each power unit is used to output current according to the current command signal and the output limit value. The current output by all power units is summed to the total current output terminal to obtain the total output current. A peak detection circuit with zeroing is used to detect the peak current of the total output current and feed it back to the control circuit; The control circuit is also used to adjust the limiting setting signal according to the peak current in order to suppress overshoot of the total output current.

[0007] Optionally, the control loop limiting circuit includes a first digital-to-analog converter and a voltage-controlled voltage source; the input terminal of the first digital-to-analog converter is connected to the second terminal of the control circuit, the output terminal of the first digital-to-analog converter is connected to the input terminal of the voltage-controlled voltage source, and the output terminal of the voltage-controlled voltage source is connected to the second terminal of each power unit.

[0008] Optionally, the control loop given circuit includes a second digital-to-analog converter; the input terminal of the second digital-to-analog converter is connected to the first terminal of the control circuit, and the output terminal of the second digital-to-analog converter is connected to the first terminal of each power unit.

[0009] Optionally, the peak detection circuit with zeroing includes an adder, a peak hold circuit, a zeroing switch, and a first analog-to-digital converter; The first terminal of the adder is connected to the third terminal of each power unit; The peak hold circuit includes a first diode, a second diode, a pull-up resistor, and a holding capacitor; the anode of the first diode is connected to the anode of the second diode, the anode of the first diode is connected to the power supply via the pull-up resistor, and the cathode of the second diode is connected to the second terminal of the adder; the first terminal of the holding capacitor is connected to the cathode of the first diode, and the second terminal of the holding capacitor is grounded; The drain of the reset switch is connected to the first terminal of the holding capacitor, the source of the reset switch is grounded, and the gate of the reset switch is connected to the third terminal of the control circuit. The first terminal of the first analog-to-digital converter is connected to the third terminal of the control circuit, and the second terminal of the first analog-to-digital converter is connected to the cathode of the first diode.

[0010] Optionally, the control circuit compares the peak current with the target current value. When the peak current is greater than the target current value, the limit setting signal is lowered; when the peak current is less than the target current value, the limit setting signal is raised; and when the peak current is equal to the target current value, the limit setting signal is maintained.

[0011] Optionally, each power unit includes an operational amplifier, a MOSFET, a current sensing resistor, a first given resistor, a second given resistor, a first feedback resistor, a second feedback resistor, and an integrating capacitor; Each power unit has a positive input and a negative input at its first terminal. The non-inverting input of each operational amplifier is connected to the positive input via a corresponding first given resistor, and the inverting input is connected to the negative input via a corresponding second given resistor. The output of each operational amplifier is connected to the gate of a corresponding MOSFET, and the source of each MOSFET is connected to the negative terminal of the power supply under test via a corresponding current sensing resistor. One end of each current sensing resistor connected to the MOSFET is connected to the inverting input of the corresponding operational amplifier via a corresponding first feedback resistor, and the other end of each current sensing resistor is connected to the non-inverting input of the corresponding operational amplifier via a corresponding second feedback resistor. Both ends of each current sensing resistor are also used to connect a peak detection circuit with zeroing capability. Each integrating capacitor is connected between the inverting input and output of the corresponding operational amplifier. The drains of each MOSFET are connected to form a total current output terminal, which is used to connect to the positive terminal of the power supply under test.

[0012] Secondly, the present invention provides a control method for an electronic load overshoot suppression circuit, applied to the aforementioned electronic load overshoot suppression circuit. The control method for the electronic load overshoot suppression circuit includes: Obtain the target current value; Based on the target current value, a current setpoint signal and a limiting setting signal are issued to control the output current of each power unit, and the peak current of the total output current obtained by summing the output currents of each power unit is detected. When the peak current is greater than the target current value, the limit setting signal is lowered; when the peak current is less than the target current value, the limit setting signal is raised; when the peak current is equal to the target current value, the limit setting signal is maintained.

[0013] Optionally, obtaining the target current value includes: It receives a preset current value set by the user or a current command issued by the host computer, and uses the preset current value or the current command as the target current value.

[0014] Optionally, a current setpoint signal and an initial limiting setting signal are issued according to the target current value to control the output current of each power unit, and the peak current of the total output current obtained by summing the output currents of each power unit is detected, including: Generate a current command signal based on the target current value; An initial limiting setting signal is generated based on the target current value, the transconductance of the MOSFETs in the power unit, the number of power units, the turn-on voltage of the MOSFETs, and the redundant voltage. The total output current is obtained by summing the output current of each power unit, where each power unit is used to output current according to the current setting signal and the initial limiting setting signal; The peak current is obtained by summing the total output current, holding the peak value, and performing analog-to-digital conversion using a peak detection circuit with zeroing function.

[0015] Optionally, the peak current is obtained by summing the total output current, holding the peak, and performing analog-to-digital conversion using a peak detection circuit with zeroing function, including: The instantaneous value of the total output current is obtained by summing the output current of each power unit using an adder with a peak detection circuit that has a zero-reset function. The peak hold circuit with a zeroing peak detection circuit holds the instantaneous value of the total output current to the peak, generating a peak hold voltage; The peak holding voltage is converted into peak current by a first analog-to-digital converter with a zeroing peak detection circuit.

[0016] The electronic load overshoot suppression circuit and control method of the present invention provide a current setpoint signal and a limiting setting signal based on the target current value. The limiting setting signal is converted into an output limiting value for each power unit by a limiting circuit in the control loop. This limiting value can be dynamically adjusted according to the target current value. That is, it provides a sufficiently high limiting to ensure the rise rate at high currents and actively reduces the limiting to avoid overdrive at low currents. At this time, even if there is a large cable parasitic inductance between the power supply under test and the electronic load, or if the output voltage of the power supply under test changes rapidly, the output of the control loop of each power unit is limited to a reasonable voltage range, preventing overdrive of the MOSFET. This effectively suppresses the output current overshoot caused by parasitic inductance-induced voltage or loop saturation, while ensuring the integrity of the current waveform in high current slew rate dynamic testing or high frequency pulse testing, ensuring that the rise rate reaches the set value without significant overshoot.

[0017] In load start-up tests, when the electronic load starts before the power supply under test, the control loop of a conventional electronic load is prone to rapid saturation due to open-loop operation, resulting in a significant current overshoot at the moment of power supply startup. In this invention, the control circuit provides a reasonable limiting setting signal simultaneously with the current input signal, clamping the operational amplifier output of the power unit within a safe range and preventing the loop from entering deep saturation. After the power supply under test starts, the control loop can quickly adjust from near the limiting value, avoiding a long delay in recovery from the saturation region, thus significantly suppressing current overshoot during startup and ensuring the smoothness of the startup process. Furthermore, this invention incorporates a peak detection circuit with zeroing capability. This circuit acquires the instantaneous value of the total output current in real time, stores its maximum value through a peak holding capacitor, and then converts the peak voltage into a digital signal via an analog-to-digital converter, feeding it back to the control circuit. Because the peak current information is fully captured, the control circuit can obtain accurate overshoot and dynamically adjust the limiting setting signal accordingly: lowering the limit when the peak current is greater than the target current value and raising the limit when the peak current is less than the target current value. After several closed-loop iterations, the limiting value automatically converges to the optimal state, ensuring that the actual peak value of each dynamic cycle is precisely equal to the target current value, achieving precise and adaptive suppression of overshoot. Simultaneously, after each peak sampling, the control circuit sends a reset signal to reset the holding capacitor, ensuring that the peak detection in the next cycle or the next dynamic process is not disturbed by historical values. This allows for accurate capture and correction of the peak value of each pulse in high-frequency pulse testing. In steady-state operation mode where high dynamic response is not required, the limiting setting signal remains at a high level, without actively interfering with the normal output of the power units. Each power unit outputs current stably according to the current given signal, and system energy loss is only reflected in the on-state voltage drop of the linear unit. Furthermore, this invention does not change the main power topology of the electronic load, maintaining the same current accuracy and low ripple characteristics as conventional electronic loads in steady state, without sacrificing static performance. In addition, the control loop limiting circuit uniformly adjusts the output limiting value of all power units, avoiding hardware redundancy by synchronously limiting all power units and configuring a separate limiting circuit for each power unit. The peak detection circuit with zeroing function is also easy to upgrade based on existing parallel electronic loads, and has good engineering practicality.

[0018] In summary, by adding a dynamically adjustable limiting setting signal and a peak detection feedback with zeroing, this invention effectively suppresses output current overshoot under various operating conditions such as different output current levels, different cable parasitic inductances, high-frequency pulses, and load start-up, while ensuring high dynamic response speed. It achieves closed-loop adaptive precise control of overshoot, significantly improving the testing accuracy and consistency of electronic loads in high-performance AI server power supply testing. Attached Figure Description

[0019] Figure 1This is a schematic diagram of the electronic load overshoot suppression circuit in one embodiment of the present invention; Figure 2 This is a schematic diagram of the topology of the electronic load overshoot suppression circuit in another embodiment of the present invention; Figure 3 This is a flowchart of a control method for an electronic load overshoot suppression circuit in another embodiment of the present invention; Figure 4 This is a peak detection waveform diagram with zeroing in another embodiment of the present invention; Figure 5 This is a 10kHz full-load pulse waveform diagram of different cable parasitic inductances in another embodiment of the present invention; Figure 6 Waveform of a 10kHz full-load pulse for parasitic inductance of different cables in a conventional electronic load; Figure 7 This is a 10kHz light-load pulse waveform diagram of different cable parasitic inductances in another embodiment of the present invention; Figure 8 Waveform of a 10kHz light-load pulse for parasitic inductance of different cables in a conventional electronic load; Figure 9 This is a waveform diagram of a load-bearing power-on process in another embodiment of the present invention; Figure 10 This is a waveform diagram of a conventional electronic load power-on under load. Detailed Implementation

[0020] To make the above-mentioned objects, features, and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Although some embodiments of the present invention are shown in the drawings, it should be understood that the present invention can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of the present invention. It should be understood that the accompanying drawings and embodiments of the present invention are for illustrative purposes only and are not intended to limit the scope of protection of the present invention.

[0021] It should be understood that the various steps described in the method embodiments of the present invention may be performed in different orders and / or in parallel. Furthermore, the method embodiments may include additional steps and / or omit the steps shown. The scope of the present invention is not limited in this respect.

[0022] The term "comprising" and its variations as used herein are open-ended, meaning "including but not limited to"; the term "based on" means "at least partially based on"; the term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments"; and the term "optionally" means "optional embodiments". Definitions of other terms will be given in the following description. It should be noted that the concepts of "first," "second," etc., mentioned in this invention are used only to distinguish different devices, modules, or units, and are not intended to limit the order of functions performed by these devices, modules, or units or their interdependencies.

[0023] It should be noted that the terms "a" and "a plurality of" used in this invention are illustrative rather than restrictive. Those skilled in the art should understand that, unless otherwise expressly indicated in the context, they should be understood as "one or more".

[0024] The names of the messages or information exchanged between the multiple devices in the embodiments of the present invention are for illustrative purposes only and are not intended to limit the scope of these messages or information.

[0025] Combination Figure 1 As shown, an embodiment of the present invention provides an electronic load overshoot suppression circuit, including: multiple power units, a control loop setpoint circuit, a control loop limiting circuit, a peak detection circuit with zeroing, and a control circuit; The first terminal of the control circuit is connected to the first terminal of the control loop setpoint circuit; the second terminal of the control circuit is connected to the first terminal of the control loop limiting circuit; the third terminal of the control circuit is connected to the first terminal of the peak detection circuit with zeroing function; the second terminal of the control loop setpoint circuit is connected to the first terminal of each power unit; and the second terminal of the control loop limiting circuit is connected to the second terminal of each power unit. The third terminal of each power unit is connected to form the total current output terminal, and is connected to the second terminal of the peak detection circuit with zeroing. The fourth terminal of each power unit is used to connect to the power supply under test. The control circuit is used to issue a current setpoint signal and a limiting setting signal according to the target current value. The current setpoint signal is transmitted to each power unit through the control loop setpoint circuit, and the limiting setting signal is converted into the output limiting value of each power unit through the control loop limiting circuit. Each power unit is used to output current according to the current command signal and the output limit value. The current output by all power units is summed to the total current output terminal to obtain the total output current. A peak detection circuit with zeroing is used to detect the peak current of the total output current and feed it back to the control circuit; The control circuit is also used to adjust the limiting setting signal according to the peak current in order to suppress overshoot of the total output current.

[0026] Specifically, this embodiment provides an electronic load overshoot suppression circuit, such as... Figure 1 As shown, it includes: multiple power units connected in parallel (power unit 1, power unit 2, ..., power unit n), a control loop setpoint circuit, a control loop limiting circuit, a peak detection circuit with zeroing, and a control circuit.

[0027] The control circuit employs a digital signal processor (DSP) or a microcontroller (MCU). The first terminal of the control circuit (i.e., the current setpoint output) is connected to the first terminal of the control loop setpoint circuit (i.e., the input terminal). The second terminal of the control circuit (i.e., the limiting setpoint output) is connected to the first terminal of the control loop limiting circuit. The third terminal of the control circuit is connected to the first terminal of the peak detection circuit with zeroing capability. The second terminal of the control loop setpoint circuit is connected to the first terminal of each power unit (i.e., the current setpoint input). The second terminal of the control loop limiting circuit is connected to the second terminal of each power unit (i.e., the limiting control terminal). The third terminal of each power unit (i.e., the current output terminal) is connected to form a total current output terminal, which is also connected to the second terminal of the peak detection circuit with zeroing capability (i.e., the current sampling input terminal). The fourth terminal of each power unit is used to connect to the power supply under test. The positive terminal of the power supply under test is connected to the total current input terminal of the electronic load (i.e., the power unit junction point), and the negative terminal is grounded or connected to the common terminal of the electronic load.

[0028] During operation, the control circuit sends two signals based on the target current value set by the user: one is a current command signal, output from the first terminal to the control loop command circuit; the other is a limiting setting signal, output from the second terminal to the control loop limiting circuit. The control loop command circuit processes the current command signal and transmits it to the first terminal of each power unit; the control loop limiting circuit converts the limiting setting signal into an output limiting value for each power unit and outputs it from the second terminal to the second terminal of each power unit.

[0029] Each power unit outputs a corresponding current based on the received current command signal and output limit value. The currents output by all power units are summed at the total current output terminal to form the total output current, which flows into the negative terminal of the power supply under test (or the input circuit of the electronic load).

[0030] A peak detection circuit with zeroing capability samples the total output current, detects and holds the peak value of the total output current, and converts it into a voltage or digital signal (analog voltage in this embodiment), outputting it from its first terminal to the third terminal of the control circuit. In one embodiment of the invention, after receiving the peak current signal, the control circuit compares it with the target current value and dynamically adjusts the limiting setting signal according to the comparison result: if the peak current is greater than the target current value, the limiting setting signal is decreased; if the peak current is less than the target current value, the limiting setting signal is increased; if they are equal, it remains unchanged and is not adjusted further, to ensure precise control of overshoot. The waveform is as follows: Figure 4 As shown. The adjusted limiting setting signal is again applied to each power unit through the control loop limiting circuit, thus forming a closed-loop regulation process. After several iterations, the peak value of the total output current is made exactly equal to the target current value, effectively suppressing the overshoot of the output current. In addition, after each peak detection cycle, the control circuit sends a reset signal to the peak detection circuit with reset function, resetting the peak detection circuit with reset function to prepare for detecting the current peak value of the next cycle. In this embodiment of the invention, the control loop setpoint circuit can be implemented using a differential amplifier or a single-ended to differential circuit, the control loop limiting circuit can be implemented using an adjustable voltage source or an operational amplifier power supply regulation circuit, and the peak detection circuit with reset function can be implemented using an adder, a peak holding capacitor, and a reset switch in conjunction with an analog-to-digital converter. The above specific implementation methods are all conventional designs for those skilled in the art and will not be described in detail here.

[0031] In this embodiment, the electronic load overshoot suppression circuit uses a control circuit to issue a current setpoint signal and a limiting setting signal based on the target current value. The limiting setting signal is converted into an output limiting value for each power unit via a control loop limiting circuit. This limiting value can be dynamically adjusted according to the target current value. That is, it provides a sufficiently high limiting to ensure the rise rate at high currents and actively reduces the limiting to avoid overdrive at low currents. At this time, even if there is a large cable parasitic inductance between the power supply under test and the electronic load, or if the output voltage of the power supply under test changes rapidly, the output of the control loop of each power unit is limited to a reasonable voltage range, preventing overdrive of the MOSFET. This effectively suppresses output current overshoot caused by parasitic inductance-induced voltage or loop saturation, while ensuring the integrity of the current waveform in high current slew rate dynamic testing or high frequency pulse testing. The rise rate can reach the set value without significant overshoot.

[0032] In load start-up tests, when the electronic load starts before the power supply under test, the control loop of a conventional electronic load is prone to rapid saturation due to open-loop operation, resulting in a significant current overshoot at the moment of power supply startup. In this invention, the control circuit provides a reasonable limiting setting signal simultaneously with the current input signal, clamping the operational amplifier output of the power unit within a safe range and preventing the loop from entering deep saturation. After the power supply under test starts, the control loop can quickly adjust from near the limiting value, avoiding a long delay in recovery from the saturation region, thus significantly suppressing current overshoot during startup and ensuring the smoothness of the startup process. Furthermore, this invention incorporates a peak detection circuit with zeroing capability. This circuit acquires the instantaneous value of the total output current in real time, stores its maximum value through a peak holding capacitor, and then converts the peak voltage into a digital signal via an analog-to-digital converter, feeding it back to the control circuit. Because the peak current information is fully captured, the control circuit can obtain accurate overshoot and dynamically adjust the limiting setting signal accordingly: lowering the limit when the peak current is greater than the target current value and raising the limit when the peak current is less than the target current value. After several closed-loop iterations, the limiting value automatically converges to the optimal state, ensuring that the actual peak value of each dynamic cycle is precisely equal to the target current value, achieving precise and adaptive suppression of overshoot. Simultaneously, after each peak sampling, the control circuit sends a reset signal to reset the holding capacitor, ensuring that the peak detection in the next cycle or the next dynamic process is not disturbed by historical values. This allows for accurate capture and correction of the peak value of each pulse in high-frequency pulse testing. In steady-state operation mode where high dynamic response is not required, the limiting setting signal remains at a high level, without actively interfering with the normal output of the power units. Each power unit outputs current stably according to the current given signal, and system energy loss is only reflected in the on-state voltage drop of the linear unit. Furthermore, this invention does not change the main power topology of the electronic load, maintaining the same current accuracy and low ripple characteristics as conventional electronic loads in steady state, without sacrificing static performance. In addition, the control loop limiting circuit uniformly adjusts the output limiting value of all power units, avoiding hardware redundancy by synchronously limiting all power units and configuring a separate limiting circuit for each power unit. The peak detection circuit with zeroing function is also easy to upgrade based on existing parallel electronic loads, and has good engineering practicality.

[0033] In summary, this embodiment effectively suppresses output current overshoot under various operating conditions, such as different output current levels, different cable parasitic inductances, high-frequency pulses, and load start-up, while ensuring high dynamic response speed by adding a dynamically adjustable limiting setting signal and peak detection feedback with zeroing. It achieves closed-loop adaptive precise control of overshoot, significantly improving the test accuracy and consistency of electronic loads in high-performance AI server power supply testing.

[0034] Optionally, the control loop limiting circuit includes a first digital-to-analog converter and a voltage-controlled voltage source; the input terminal of the first digital-to-analog converter is connected to the second terminal of the control circuit, the output terminal of the first digital-to-analog converter is connected to the input terminal of the voltage-controlled voltage source, and the output terminal of the voltage-controlled voltage source is connected to the second terminal of each power unit.

[0035] Specifically, the control loop limiting circuit includes a first digital-to-analog converter and a voltage-controlled voltage source. For example... Figure 2 As shown, the input terminal of the first digital-to-analog converter U2 is connected to the second terminal of the control circuit (i.e., the limiting setting output terminal), the output terminal of U2 is connected to the input terminal of the voltage-controlled voltage source S1, and the output terminal of the voltage-controlled voltage source S1 is connected to the power supply terminal of the operational amplifier (e.g., OP1 in power unit 1) in each power unit, i.e., the second terminal (limiting control terminal) of each power unit.

[0036] The control circuit calculates the required initial limiting value based on the target current value and preset MOSFET parameters (such as transconductance, turn-on voltage, etc.) and sends the corresponding digital value to U2. U2 converts this digital value into an analog voltage signal and outputs it to the voltage-controlled voltage source S1. S1 is a voltage-controlled DC voltage source with a gain of Gvcvs, capable of linearly amplifying or following the input analog voltage. The output voltage of S1 directly serves as the positive power supply voltage (or supply voltage) for the operational amplifiers in each power unit. Since the output voltage swing of the operational amplifier is limited by its supply voltage, the maximum output voltage of the operational amplifiers in all power units can be uniformly controlled by adjusting the output voltage of S1. This output voltage, after being driven by the MOSFET gate, determines the maximum output current of the MOSFET. Therefore, adjusting the output voltage of S1 is essentially adjusting the output limiting value of each power unit. When it is necessary to reduce the limiting to suppress overshoot, the control circuit reduces the output digital value of U2, the output voltage of S1 decreases, the supply voltage of the operational amplifier decreases, its upper limit of output voltage decreases, and the MOSFET gate drive voltage is clamped at a lower value, thereby limiting the peak value of the output current. Conversely, when it is necessary to increase the limiting to ensure the current rise rate, the output digital value of U2 is increased. In this embodiment, the voltage-controlled voltage source S1 can be implemented using a linear regulator or a follower composed of operational amplifiers; its specific circuit configuration is existing technology and will not be described in detail here. By simultaneously powering all power unit operational amplifiers through a shared voltage-controlled voltage source S1, batch and unified adjustment of the output limiting value of each power unit is achieved. There is no need to configure a separate limiting circuit for each power unit, resulting in a simple circuit structure, low cost, and ensuring the consistency of the limiting of each power unit.

[0037] In this optional embodiment, by specifically configuring the control loop limiting circuit as a first digital-to-analog converter connected in series with a voltage-controlled voltage source (VDC), and with the output of the VDC connected to the power supply of the operational amplifier in each power unit, batch and unified adjustment of the output limiting values ​​of all power units is achieved. Compared to configuring a separate limiting circuit for each power unit, this structure only requires one digital-to-analog converter and one VDC to control all power units simultaneously, significantly reducing hardware costs and circuit complexity. Furthermore, since the output of the VDC directly powers the operational amplifier, and the output voltage swing of the operational amplifier is limited by the supply voltage, changing the output voltage of the VDC linearly and quickly adjusts the upper limit of the MOSFET gate drive voltage of each power unit, thereby precisely limiting the maximum output current of each power unit. This supply voltage adjustment method has a fast response speed and can adjust in real time following the limiting setting signal issued by the control circuit, avoiding the nonlinearity or delay problems that may be introduced by traditional limiting circuits (such as clamping diodes). In addition, the shared VDC ensures a high degree of consistency in the limiting values ​​of each power unit, preventing uneven current distribution due to differences in limiting between units, and improving the reliability and test repeatability of the system.

[0038] Optionally, the control loop given circuit includes a second digital-to-analog converter; the input terminal of the second digital-to-analog converter is connected to the first terminal of the control circuit, and the output terminal of the second digital-to-analog converter is connected to the first terminal of each power unit.

[0039] Specifically, the control loop setpoint circuit includes a second digital-to-analog converter, such as... Figure 2As shown, the input terminal of the second digital-to-analog converter U3 is connected to the first terminal (i.e., the current setpoint output terminal) of the control circuit. The output terminals of U3 are connected to the first terminal (i.e., the current setpoint input terminal) of each power unit. The control circuit calculates the corresponding digital current setpoint value internally based on the target current value set by the user, and sends this digital value to U3 through its first terminal. U3 converts the received digital quantity into an analog voltage signal. To improve anti-interference capability and adapt to differential signal transmission, U3 in this embodiment uses a differential output type digital-to-analog converter with a positive output terminal (Iset+) and a negative output terminal (Iset-). Iset+ and Iset- are respectively connected to the positive and negative input terminals of the first terminal of each power unit (e.g., the non-inverting input terminal of the operational amplifier in each power unit is connected to Iset+ via a first given resistor, and the inverting input terminal is connected to Iset- via a second given resistor). This differential connection method transmits the current command signal simultaneously to all parallel power units in differential form, ensuring that the amplitude and phase of the command signal received by each power unit are exactly the same. This achieves synchronous and equal distribution of the output current of each unit, avoiding current circulation or response delay caused by inconsistent command signals. The analog voltage amplitude output by U3 is proportional to the target current value. The control circuit can adjust the current command value of each power unit in real time and accurately by changing the digital input of U3. Since the command input terminals of all power units are connected in parallel to the output terminal of U3, there is no need to configure a separate digital-to-analog converter or conditioning circuit for each power unit, which greatly simplifies the circuit structure and reduces costs. At the same time, the differential output method gives the command signal higher immunity to common-mode interference during long-distance transmission, making it suitable for actual test scenarios where there may be long cables between the electronic load and the power supply under test.

[0040] In other implementations, if the system is not sensitive to noise or the number of power units is small, U3 can also be a single-ended output digital-to-analog converter, whose output is directly connected in parallel to the first end of each power unit, thus achieving a unified current setting function.

[0041] With the above configuration, the control loop setpoint circuit achieves unified and synchronous transmission of current setpoint signals for each power unit in a simple and low-cost manner, providing a precise instruction basis for subsequent overshoot suppression control.

[0042] In this optional embodiment, by setting the control loop setpoint circuit as a single second digital-to-analog converter (DAC), whose input is connected to the first terminal of the control circuit and whose output is connected to the first terminal of each power unit, unified and synchronous transmission of the current setpoint signal for all parallel power units is achieved. Compared to the scheme of configuring a separate DAC for each power unit, this structure only requires one DAC to drive all power units simultaneously, significantly reducing hardware costs and circuit complexity, and avoiding the problem of inconsistent setpoint signals caused by gain errors or temperature drift differences between multiple converters, thereby ensuring equal distribution and synchronous response of the output current of each power unit. The control circuit only needs to change the digital input value of the second DAC to adjust the current setpoint value of all power units in real time and accurately, without the need for additional multi-output or channel matching circuits. In high-speed dynamic testing, the unified setpoint signal ensures that the MOSFETs of each power unit are turned on or off simultaneously, avoiding current rise edge segmentation or fall edge tailing caused by differences in the arrival time of the setpoint signal, effectively maintaining waveform integrity under high current slew rate. Furthermore, when a differential output digital-to-analog converter is used, the given signal is transmitted to each power unit in a differential form over long lines, which has excellent common-mode interference immunity and is suitable for scenarios where there may be long cable connections between electronic loads and the power supply under test, further improving the stability and reliability of testing under conditions of large parasitic inductance.

[0043] Optionally, the peak detection circuit with zeroing includes an adder, a peak hold circuit, a zeroing switch, and a first analog-to-digital converter; The first terminal of the adder is connected to the third terminal of each power unit; The peak hold circuit includes a first diode, a second diode, a pull-up resistor, and a holding capacitor; the anode of the first diode is connected to the anode of the second diode, the anode of the first diode is connected to the power supply via the pull-up resistor, and the cathode of the second diode is connected to the second terminal of the adder; the first terminal of the holding capacitor is connected to the cathode of the first diode, and the second terminal of the holding capacitor is grounded; The drain of the reset switch is connected to the first terminal of the holding capacitor, the source of the reset switch is grounded, and the gate of the reset switch is connected to the third terminal of the control circuit. The first terminal of the first analog-to-digital converter is connected to the third terminal of the control circuit, and the second terminal of the first analog-to-digital converter is connected to the cathode of the first diode.

[0044] Specifically, in combination Figure 2As shown, the specific connection relationship of the circuit is as follows: the adder includes operational amplifier OP2, resistors Rf1a and Rf1b, and together with the summing resistors of each power unit (such as Ri13a and Ri13b in power unit 1, Ri23a and Ri23b in power unit 2, ..., Rin3a and Rin3b in power unit n) to realize the addition function. The input terminal of the adder is connected to the third terminal of each power unit (i.e., the current detection point at the source of the MOSFET in the power unit) through the summing resistor of each power unit. The output terminal of the adder (the output terminal of OP2) is connected to the first terminal of the peak hold circuit (i.e., the cathode of the second diode D2). The function of the adder is to convert the output current of each power unit into voltage and sum them to obtain the instantaneous value of the total output current voltage.

[0045] The peak hold circuit includes a first diode D1, a second diode D2, a pull-up resistor Ru1, and a holding capacitor Ch1. The connections are as follows: the cathode of the first diode D1 is connected to the input terminal of the first analog-to-digital converter U4; the anode of the first diode D1 is connected to the anode of the second diode D2; and the anodes of both diodes D1 and D2 are connected to the internal power supply Vcc1 via the pull-up resistor Ru1. The first terminal of the holding capacitor Ch1 is connected to the cathode of the first diode D1, and the second terminal of Ch1 is grounded. Working principle: When the instantaneous voltage output by the adder rises, both D1 and D2 conduct, charging Ch1, causing its voltage to follow the input peak value. When the input voltage drops, D1 is cut off, and since there is no discharge circuit, the voltage of Ch1 remains essentially unchanged, thus achieving the peak hold function.

[0046] The reset switch is implemented using MOSFET Qs1. The drain of Qs1 is connected to the first terminal of the holding capacitor Ch1, the source of Qs1 is grounded, and the gate of Qs1 is connected to the third terminal of the control circuit. When the control circuit needs to reset the peak detection, it sends a high-level pulse to the gate of Qs1, turning on Qs1 and short-circuiting and discharging the two ends of the holding capacitor Ch1, causing its voltage to return to zero, thereby clearing the currently held peak value and preparing for the next cycle.

[0047] The first analog-to-digital converter is... Figure 2 In the circuit, U4's input is connected to the first terminal of the holding capacitor Ch1 (i.e., the peak voltage point), and its output is connected to the first terminal of the control circuit, i.e., the peak feedback input. U4 converts the analog peak voltage into a digital signal for the control circuit to read.

[0048] It should be noted that the peak detection circuit with zeroing function in this embodiment also includes a second analog-to-digital converter U5 for instantaneous current sampling. The input of U5 is connected to the output of the adder (i.e., the output of OP2), and the output of U5 is connected to the control circuit. Figure 2(Connected to the corresponding ADC input terminal of the processor). This instantaneous current sampling branch is used to monitor the instantaneous waveform of the total output current in real time, providing auxiliary functions such as overcurrent protection or waveform display, which will not be elaborated here. The adder in this embodiment corresponds to... Figure 2 The summing circuit consisting of OP2 and resistors, the peak hold circuit, and the clear switch correspond to D1, D2, Ru1, Ch1, and Qs1, respectively. The first analog-to-digital converter corresponds to U4. These circuits collectively realize the detection, holding, clearing, and digital conversion of the total output current peak value, providing a precise overshoot feedback signal for the control circuit. In this embodiment, the current signal from the power unit is collected by the peak detection circuit with clear function. The signal is added to calculate the total output current, then converted to digital by U5 and transmitted to the control circuit. The peak detection circuit detects the latched peak value, which is then converted to digital by U4 and transmitted to the control circuit. The control circuit sends a clear signal to the peak detection circuit with clear function.

[0049] In this optional embodiment, the instantaneous value of the total output current is obtained by summing the output currents of each power unit using an adder. A peak hold circuit consisting of a first diode, a second diode, a pull-up resistor, and a holding capacitor stores the peak voltage of the instantaneous current on the holding capacitor, solving the technical problem that the overshoot current duration is extremely short (nanosecond level) and ordinary analog-to-digital converters cannot directly capture the peak value. A reset switch is connected in parallel across the holding capacitor, and its gate is connected to the reset signal output of the control circuit. After each peak sampling is completed, the control circuit sends a reset pulse to quickly discharge and reset the holding capacitor, ensuring that the peak value of each pulse cycle in high-frequency pulse testing (e.g., 10kHz) is independently and accurately detected without historical value accumulation errors. The first analog-to-digital converter converts the analog peak voltage on the holding capacitor into a digital signal and feeds it back to the control circuit, providing a precise and reliable overshoot basis for the closed-loop adjustment of the limiting setting signal. Furthermore, the instantaneous current output by the adder is also simultaneously fed into another analog-to-digital converter U5 for real-time monitoring of the total output current waveform, providing auxiliary functions such as overcurrent protection or waveform display. In summary, this peak detection circuit with zeroing feature achieves the capture, holding, zeroing, and digitization of short-time peak current using a simple analog circuit. This enables electronic loads to have periodic and precise overshoot feedback capability for the first time, laying a key foundation for subsequent adaptive limiting regulation. It is also low in cost, fast in response, and easy to integrate.

[0050] Optionally, the control circuit compares the peak current with the target current value. When the peak current is greater than the target current value, the limit setting signal is lowered; when the peak current is less than the target current value, the limit setting signal is raised; and when the peak current is equal to the target current value, the limit setting signal is maintained.

[0051] Specifically, control circuits (such as...) Figure 2the processor in) after receiving the peak current fed back by the peak detection circuit with reset, performs the following comparison and adjustment operations. The control circuit internally stores a target current value set by a user (recorded as Iset). After the control circuit reads the digital peak current value (recorded as Ipeak) sent by the first analog-to-digital converter U4 from its third terminal (peak feedback input terminal), it first compares Ipeak with Iset. The comparison result is divided into three cases: Case 1: Ipeak>Iset, indicating that the peak of the current total output current exceeds the target value, that is, overshoot occurs. At this time, the control circuit reduces the amplitude limiting setting signal output from its second terminal (amplitude limiting setting output terminal). Specifically, the control circuit decreases the current amplitude limiting setting digital quantity by one step ( can be preset as a fixed value or dynamically adjusted according to the overshoot amount), and then the new digital quantity is sent to the first digital-to-analog converter U2. The analog voltage output by U2 decreases, after passing through the voltage-controlled voltage source S1, the supply voltage of the operational amplifier in each power unit decreases, thereby reducing the upper limit of the MOSFET gate drive voltage. In the next dynamic cycle, the output capability of the power unit is weakened, the current rise will be gentler, and the overshoot amount will decrease accordingly.

[0052] Case 2: Ipeak<Iset, indicating that the peak of the current total output current has not reached the target value, which may be caused by too low amplitude limiting resulting in insufficient rising rate or the current failing to reach the set value. At this time, the control circuit increases the amplitude limiting setting signal. The control circuit increases the current amplitude limiting setting digital quantity by one step after passing through U2 and S1, the supply voltage of the operational amplifier in each power unit rises, and the upper limit of the MOSFET gate drive voltage increases, thereby allowing a larger output current. In the next dynamic cycle, the current rising capability is enhanced, making it closer to the target value.

[0053] Case 3: Ipeak = Iset, indicating that the peak of the current total output current is exactly equal to the target value, which means that the amplitude limiting setting value is appropriate, with neither overshoot nor non-compliance. At this time, the control circuit maintains the current amplitude limiting setting signal unchanged and makes no adjustment.

[0054] The above comparison and adjustment process is repeated in each dynamic cycle (or after each peak sampling is completed). If Figure 3As shown in the control flowchart, the control circuit continuously detects the peak current and corrects the limiting setting signal accordingly, forming a closed-loop iterative control. After several cycles of adjustment, the deviation between Ipeak and Iset will converge to the allowable range, ultimately achieving Ipeak = Iset. At this point, overshoot is completely suppressed and the current amplitude precisely reaches the target value. In actual programming implementation, the control circuit can employ proportional or integral adjustment algorithms, such as dynamically adjusting the step size based on the deviation magnitude to accelerate convergence and avoid overshoot, always adhering to the basic principle of reducing the limiting when the peak value is too large, increasing the limiting when the peak value is too small, and maintaining the limit when they are equal. Through the above method, the control circuit utilizes peak current feedback to achieve closed-loop adaptive adjustment of the limiting setting signal, automatically converging to the optimal limiting value under different operating conditions without manual intervention, thereby accurately suppressing output current overshoot while ensuring dynamic response speed.

[0055] In one embodiment, such as Figure 9 The diagram shown illustrates the load-bearing power-on waveform in this embodiment. The cable parasitic inductance is 150nH, and the current is 150A. Overshoot is suppressed while maintaining a constant current slew rate. For example... Figure 10 The image shows the waveform of a typical electronic load starting up under load. The cable parasitic inductance is 150nH, the current is 150A, and there is a large overshoot.

[0056] In this optional embodiment, the control circuit compares the feedback peak current with the target current value in real time, and dynamically adjusts the limit setting signal according to the rule that if the peak value is too large, the limit is reduced; if the peak value is too small, the limit is increased; and if they are equal, the limit is maintained, thus forming a closed-loop adaptive control. This mechanism can automatically correct overshoot deviations caused by factors such as cable parasitic inductance, component differences, and temperature changes: when overshoot occurs, the limit value is immediately reduced to make the current rise in the next cycle more gradual and suppress overshoot; when the current rise is insufficient, the limit value is increased to ensure that the dynamic response speed is not lost due to the limit being too low. After several iterations, the limit value automatically converges to the optimal state, so that the actual output current peak value in each dynamic cycle is exactly equal to the target current value, achieving precise suppression of overshoot without manual intervention. Compared to existing electronic loads that use fixed limiting or experience-based debugging in an open-loop manner, this embodiment uses a simple comparison and step adjustment strategy to adaptively adapt to different output current levels, different parasitic inductances, and various operating conditions such as load start-up while ensuring a high current slew rate. This significantly improves the consistency and reliability of the test. At the same time, the algorithm is simple and easy to implement on low-cost processors.

[0057] Optionally, each power unit includes an operational amplifier, a MOSFET, a current sensing resistor, a first given resistor, a second given resistor, a first feedback resistor, a second feedback resistor, and an integrating capacitor; Each power unit has a positive input and a negative input at its first terminal. The non-inverting input of each operational amplifier is connected to the positive input via a corresponding first given resistor, and the inverting input is connected to the negative input via a corresponding second given resistor. The output of each operational amplifier is connected to the gate of a corresponding MOSFET, and the source of each MOSFET is connected to the negative terminal of the power supply under test via a corresponding current sensing resistor. One end of each current sensing resistor connected to the MOSFET is connected to the inverting input of the corresponding operational amplifier via a corresponding first feedback resistor, and the other end of each current sensing resistor is connected to the non-inverting input of the corresponding operational amplifier via a corresponding second feedback resistor. Both ends of each current sensing resistor are also used to connect a peak detection circuit with zeroing capability. Each integrating capacitor is connected between the inverting input and output of the corresponding operational amplifier. The drains of each MOSFET are connected to form a total current output terminal, which is used to connect to the positive terminal of the power supply under test.

[0058] Specifically, each power unit has as follows Figure 2 The structure shown is illustrated using power unit 1 as an example. The structures of the other power units (power unit 2, ..., power unit n) are exactly the same.

[0059] Power unit 1 includes: operational amplifier OP1, MOSFET Q1, current sensing resistor Rs1, first given resistor Ri11a, second given resistor Ri11b, first feedback resistor Ri12a, second feedback resistor Ri12b and integrating capacitor Cf1.

[0060] Each power unit has a positive input terminal and a negative input terminal, which are used to connect to the positive output terminal (Iset+) and the negative output terminal (Iset-) of the control loop reference circuit, respectively. The specific connection relationship is as follows: The non-inverting input of operational amplifier OP1 is connected to the positive input (Iset+) via a first given resistor Ri11a; the inverting input of operational amplifier OP1 is connected to the negative input (Iset-) via a second given resistor Ri11b; the output of operational amplifier OP1 is connected to the gate of MOSFET Q1; the source of MOSFET Q1 is connected via current sensing resistor Rs1 to the sources of MOSFET Q2 and MOSFET Qn of the other power units via current sensing resistor Rs2 and Rsn, respectively, for connecting to the negative terminal of the power supply under test; the source of MOSFET Q1 is also connected to the inverting input of operational amplifier OP1 via a first feedback resistor Ri12a; the other end of current sensing resistor Rs1 is connected to the non-inverting input of operational amplifier OP1 via a second feedback resistor Ri12b; an integrating capacitor Cf1 is connected between the inverting input and output of operational amplifier OP1; the drain of MOSFET Q1 serves as the current output terminal of this power unit. The drains of all power units are connected to form a total current output terminal, which is used to connect to the positive terminal of the power supply under test.

[0061] The circuit described above constitutes a differential input PI regulator: the given differential signal (Iset+ minus Iset-) is subtracted from the voltage feedback signal (reflecting the output current) from the current sensing resistor Rs1 through a resistor network, integration compensation is achieved by the integrating capacitor Cf1, and the output voltage of the operational amplifier OP1 drives the gate of MOSFET Q1, thereby regulating the output current in a closed loop. By designing Ri11a = Ri11b and Ri12a = Ri12b, common-mode interference is suppressed, and the transfer function is made symmetrical. The current sensing resistor Rs1 linearly converts the output current into a voltage signal, which is used for internal feedback and also sent to the external peak detection circuit through the summing resistor. This power unit has a simple structure, fast dynamic response, and multiple units connected in parallel share the same pair of differential given signals (Iset+ and Iset-), ensuring the consistency and synchronization of the current given signals of each unit, which is beneficial for the uniform distribution of the output current and high-speed pulse response.

[0062] In this optional embodiment, each power unit employs a differential input PI regulator structure. The non-inverting and inverting inputs of the operational amplifier are connected to the positive and negative outputs of the control loop's given circuit via a first and a second given resistor, respectively, achieving common-mode rejection and anti-interference transmission of the differential current given signal. The current sensing resistor at the MOSFET source converts the output current into a voltage feedback signal, which is then introduced to the non-inverting and inverting inputs of the operational amplifier via the first and second feedback resistors, respectively, forming a differential subtraction with the given signal. This, combined with an integrating capacitor connected between the inverting input and output, constitutes a standard integral regulator, which controls the MOSFET's gate voltage in a closed loop, thereby precisely regulating the output current. This structure allows the given signal and feedback signal to be differentially compared directly at the same operational amplifier input, avoiding the delay and error introduced by an additional subtractor, resulting in a fast dynamic response speed. Furthermore, the current sensing resistor is grounded, simplifying the sampling circuit. Each power unit shares the same pair of differential input signals (Iset+ and Iset-), ensuring that the input amplitude and phase of each unit are completely consistent when connected in parallel. Furthermore, the identical internal feedback parameters of each unit achieve equal distribution of output current and synchronous switching, preventing circulating current or response order discrepancies caused by inconsistent inputs. All MOSFET drains are connected to form the total current output terminal, which is directly connected to a peak detection circuit with zeroing capability, facilitating unified monitoring of the total current peak value. This power unit has a simple structure, low cost, and is easily expanded by parallel connection of multiple units.

[0063] This invention provides a control method for an electronic load overshoot suppression circuit, applied to the aforementioned electronic load overshoot suppression circuit. The control method for the electronic load overshoot suppression circuit includes: Obtain the target current value; Based on the target current value, a current setpoint signal and a limiting setting signal are issued to control the output current of each power unit, and the peak current of the total output current obtained by summing the output currents of each power unit is detected. When the peak current is greater than the target current value, the limit setting signal is lowered; when the peak current is less than the target current value, the limit setting signal is raised; when the peak current is equal to the target current value, the limit setting signal is maintained.

[0064] Specifically, with Figure 2 Taking the circuit shown as an example, the method includes the following steps: Step 1: Obtain the target current value and control the circuit (e.g., ...). Figure 1 The processor in the system receives the target current value Iset set by the user through the user interface or the host computer communication interface. This value represents the expected current amplitude of the electronic load output. For example, in the power supply test of an AI server, the target current value can be set to 50A, 100A, or 150A, etc., according to the test specifications.

[0065] Step 2: outputting a current given signal and an amplitude limiting setting signal, controlling the output of a power unit and detecting a peak current, wherein a control circuit outputs a corresponding digital current given signal at a first end thereof according to a target current value Iset, the digital current given signal is converted into differential analog signals (Iset+, Iset-) by a control loop given circuit (a second digital-to-analog converter U3), and the differential analog signals are respectively sent to a first end (a positive input end and a negative input end) of each power unit. Meanwhile, the control circuit utilizes a formula based on the target current value, preset MOSFET parameters (transconductance gm, threshold voltage Vth, etc.) and a redundant voltage Vr to calculate an initial amplitude limiting setting signal, wherein Vgl is a control loop amplitude limiting value; Iset is an output current setting value; gm is MOSFET transconductance; nm is the number of power units; Vth is MOSFET threshold voltage; Vr is a redundant voltage increased in consideration of device consistency; the initial amplitude limiting setting signal is output from a second end of the control circuit to a control loop amplitude limiting circuit (a first digital-to-analog converter U2 and a voltage-controlled voltage source S1), and an output voltage of S1 is used as a power supply voltage for operational amplifiers in each power unit, thereby limiting the maximum output capability of each power unit. Each power unit outputs corresponding current according to the received current given signal and the output amplitude limiting value. Current output ends (MOSFET drains) of all power units are converged to form a total output current. A peak detection circuit with a clearing function sums the output current of each power unit through an adder to obtain an instantaneous value of the total output current; a peak holding circuit (D1, D2, Ru1, Ch1) stores the peak value of the instantaneous value on a holding capacitor Ch1; a first analog-to-digital converter U4 converts the analog peak voltage on Ch1 into a digital peak current Ipeak, and feeds back the digital peak current Ipeak to a third end of the control circuit.

[0066] Step 3: adjusting the amplitude limiting setting signal according to a comparison result between the peak current and the target current value, wherein after reading Ipeak, the control circuit compares Ipeak with the target current value Iset, and performs the following three adjustment operations according to the comparison result: When Ipeak>Iset (indicating that the output current is overshot): the control circuit reduces the amplitude limiting setting signal. Specifically, the control circuit decreases the current digital amplitude limiting setting value by one step and sends the new digital value to the first digital-to-analog converter U2. The output voltage of U2 decreases, and after passing through the voltage-controlled voltage source S1, the power supply voltage of the operational amplifier of each power unit drops, thereby reducing the upper limit of the MOSFET gate driving voltage and weakening the output capability of the power units. In the next dynamic cycle, the current rises more gently, and the overshoot amount is reduced.

[0067] When Ipeak<Iset (indicating that the current does not reach the target value or the rising speed is too slow): the control circuit increases the amplitude limiting setting signal. The control circuit increases the current digital amplitude limiting setting value by one step After passing through U2 and S1, the operational amplifier's supply voltage is increased, enhancing the power unit's output capability and making the subsequent current peak value closer to the target value.

[0068] When Ipeak = Iset (indicating that the current limiting value makes the peak value equal to the target value): the control circuit maintains the limiting setting signal unchanged and does not make any adjustments.

[0069] Steps two and three above are repeated in each dynamic cycle (or at the peak sampling time after each pulse rising edge). Figure 3 As shown in the control flowchart, through continuous closed-loop iteration of peak detection, comparison, limit adjustment, and re-detection, the limit setting signal will automatically converge to the optimal value, so that the actual output current peak value in each cycle is exactly equal to the target current value, thereby effectively suppressing the overshoot of the output current while ensuring high dynamic response speed.

[0070] In another embodiment, in practical applications, the control circuit can also calculate and output the initial limiting value according to the theoretical formula after step one and before step two, in order to shorten the convergence time; in step three, the step size... The convergence speed and stability can be improved by dynamically adjusting the step size according to the deviation (using a large step size for rapid approximation when the deviation is large, and using a small step size for fine adjustment when the deviation is small).

[0071] Combination Figure 5 As shown, the waveforms of the 10kHz full-load pulse with parasitic inductance of different cables in this embodiment are displayed, suppressing overshoot while maintaining a constant current slew rate. The comparison results are as follows... Figure 6 The image shows a 10kHz full-load pulse waveform of a conventional electronic load with different cable parasitic inductances. It is clearly visible that a significant overshoot occurs as the parasitic inductance increases. Furthermore, combined with… Figure 7 As shown, the waveforms of different cables with parasitic inductance under a 10kHz light load in this embodiment are illustrated, demonstrating how overshoot was suppressed while maintaining a constant current slew rate. The comparison results are as follows... Figure 8 As shown, the waveform of a 10kHz light-load pulse with parasitic inductance of different cables in a conventional electronic load is displayed. It can be clearly seen that there is a large overshoot after the parasitic inductance increases.

[0072] The electronic load overshoot suppression control method of this invention first acquires the target current value, then issues a current command signal and a limiting setting signal based on the target current value to drive the output current of each power unit and simultaneously detects the peak value of the total output current. Finally, it dynamically adjusts the limiting setting signal based on the comparison between the peak current and the target current value (lowering the limit if the peak value is too large, raising the limit if the peak value is too small, and maintaining the limit if they are equal), forming a closed-loop adaptive adjustment process. It can correct the limiting value in real time based on the actual detected overshoot after each dynamic cycle or each pulse rising edge, so that the limiting value automatically converges to the optimal state, ultimately achieving that the actual peak output current in each cycle is precisely equal to the target current value. Compared to existing electronic loads that employ fixed limiting or open-loop control methods relying solely on theoretical calculations, this embodiment can adapt to various complex operating conditions, including different output current levels, varying cable parasitic inductances, and load-bearing startup, without manual intervention. When large parasitic inductance leads to overshoot, the limiting is automatically reduced to suppress overshoot. When excessive limiting occurs under low-current conditions, the effective proportion of the error signal in the analog-to-digital conversion quantization range is increased to prevent excessively low loop gain during small-signal adjustment. When the current rise is insufficient, the limiting is correspondingly increased to ensure response speed. The entire process accurately eliminates overshoot while maintaining a high current slew rate, significantly improving test consistency and reliability. Furthermore, this embodiment requires only simple comparison and step adjustment logic, has low algorithm complexity, is easy to implement on low-cost processors, and is highly compatible with the hardware architecture of existing parallel electronic loads, demonstrating significant engineering practical value.

[0073] Optionally, obtaining the target current value includes: It receives a preset current value set by the user or a current command issued by the host computer, and uses the preset current value or the current command as the target current value.

[0074] Specifically, the control circuit obtains the target current value in one of two ways.

[0075] Method 1: Receive a preset current value set by the user. The human-machine interface (such as a touchscreen, knob, or button) of the electronic load device allows the user to manually input the desired test current value. The control circuit reads this preset current value through an internal interface and uses it as the target current value Iset in subsequent steps. This method is suitable for stand-alone manual testing or on-site debugging scenarios.

[0076] Method 2: The electronic load receives a current command from a host computer. It connects to the host computer (such as an industrial computer, PC, or automated testing system) via a communication interface (e.g., RS485, CAN, Ethernet, or GPIB). The host computer sends a data frame containing the current command to the electronic load according to the test sequence. The control circuit parses the command, extracts the current value, and uses it as the target current value Iset. This method is suitable for automated testing systems, mass production testing, or remote control scenarios.

[0077] In both of the above methods, regardless of whether the target current value originates from a local user setting or a remote host computer command, the control circuit stores it in an internal register for subsequent current command signal generation and limiting setting signal calculation. The two methods can coexist; the control circuit selects one as the valid input based on the current operating mode (such as the local / remote switch status or communication priority), or it can support simultaneous operation and switch between them via flag bits. Through this configuration, this embodiment satisfies both the flexibility of stand-alone manual operation and adapts to the integration requirements of automated testing systems, exhibiting good applicability and scalability.

[0078] Optionally, a current setpoint signal and an initial limiting setting signal are issued according to the target current value to control the output current of each power unit, and the peak current of the total output current obtained by summing the output currents of each power unit is detected, including: Generate a current command signal based on the target current value; An initial limiting setting signal is generated based on the target current value, the transconductance of the MOSFETs in the power unit, the number of power units, the turn-on voltage of the MOSFETs, and the redundant voltage. The total output current is obtained by summing the output current of each power unit, where each power unit is used to output current according to the current setting signal and the initial limiting setting signal; The peak current is obtained by summing the total output current, holding the peak value, and performing analog-to-digital conversion using a peak detection circuit with zeroing function.

[0079] Specifically, control circuits (such as...) Figure 2 The processor in the control loop generates a corresponding digital current reference signal based on the acquired target current value and outputs it to the control loop reference circuit through its first terminal. The second digital-to-analog converter U3 in the control loop reference circuit converts this digital signal into analog differential current reference signals (Iset+, Iset-), which are then sent to the first terminals (positive and negative input terminals) of each power unit, respectively. The control circuit calculates the initial control loop limiting value Vgl using the following formula based on the target current value Iset, the transconductance gm of the MOSFET in the power unit, the number of power units nm, the MOSFET turn-on voltage Vth, and the redundancy voltage Vr: ; In the formula, Vgl is the control loop limiting value; Iset is the output current setting value (i.e., the target current value); gm is the MOSFET transconductance; nm is the number of power units; Vth is the MOSFET turn-on voltage; and Vr is the redundant voltage added to consider device consistency.

[0080] The control circuit also calculates the voltage value Vda that the first digital-to-analog converter U2 should output based on the op-amp output voltage drop Vdrp and the voltage-controlled voltage source gain Gvcvs: ; The control circuit sends the digital value corresponding to Vda from its second terminal to U2. U2 outputs an analog voltage, which is amplified by the voltage-controlled voltage source S1 and used as the power supply voltage for the operational amplifiers in each power unit, thereby setting the initial output limit value.

[0081] Each power unit outputs a corresponding current based on the received differential current command signal (Iset+, Iset-) and the operational amplifier's supply voltage (i.e., the initial limiting value). The currents output by all power units are connected at their current output terminals (MOSFET drains) and summed to form the total output current.

[0082] The peak detection circuit with zeroing performs the following processing on the total output current: Summation: The adder (composed of operational amplifier OP2, resistors Rf1a, Rf1b, and summing resistors Ri13a, Ri13b of each power unit, etc.) sums the output current of each power unit to obtain the instantaneous value of the total output current. Peak Hold: The peak hold circuit (first diode D1, second diode D2, pull-up resistor Ru1, holding capacitor Ch1) receives the instantaneous voltage output by the adder and stores the peak voltage on the holding capacitor Ch1. Analog-to-Digital Conversion: The first analog-to-digital converter U4 converts the analog peak voltage on the holding capacitor Ch1 into a digital form of peak current and sends it to the third terminal of the control circuit (peak feedback input terminal).

[0083] In this optional embodiment, a current-given signal is first generated based on the target current value. Then, the initial limiting setting signal is precisely calculated based on the target current value, MOSFET transconductance, number of power units, MOSFET turn-on voltage, and redundant voltage. This ensures that the initial limiting value matches the theoretically required drive voltage, avoiding the problems of overdrive at low currents or insufficient response at high currents caused by fixed limiting. After the power units output current based on the given signal and the initial limiting value and the current is summed, the peak detection circuit with zeroing function captures the short-term peak value of the total output current (even if the overshoot only lasts for microseconds) through adder summation, diode-capacitor peak hold, and analog-to-digital conversion. This provides accurate and real-time feedback data for subsequent closed-loop adjustment. The theoretical initial limiting ensures the rationality of the startup phase and shortens the closed-loop convergence time. The peak detection circuit achieves accurate extraction of high-speed pulse current peaks in a low-cost analog manner, overcoming the shortcomings of insufficient sampling rate of conventional ADCs.

[0084] Optionally, the peak current is obtained by summing the total output current, holding the peak, and performing analog-to-digital conversion using a peak detection circuit with zeroing function, including: The instantaneous value of the total output current is obtained by summing the output current of each power unit using an adder with a peak detection circuit that has a zero-reset function. The peak hold circuit with a zeroing peak detection circuit holds the instantaneous value of the total output current to the peak, generating a peak hold voltage; The peak holding voltage is converted into peak current by a first analog-to-digital converter with a zeroing peak detection circuit.

[0085] Specifically, such as Figure 2As shown, the adder in the peak detection circuit with zeroing consists of operational amplifier OP2, resistors Rf1a and Rf1b, and summing resistors for each power unit (such as Ri13a and Ri13b in power unit 1, Ri23a and Ri23b in power unit 2, ..., Rin3a and Rin3b in power unit n). The MOSFET source current of each power unit generates a voltage across the current sensing resistor Rs1, which is sent to the input of the adder via the corresponding summing resistors (e.g., Ri13a and Ri13b) for each power unit. The adder sums the output currents of all power units and converts them into a voltage. The total voltage obtained at its output terminal (the output terminal of OP2) is proportional to the sum of the output currents of each power unit, reflecting the instantaneous value of the total output current. The peak hold circuit includes a first diode D1, a second diode D2, a pull-up resistor Ru1, and a holding capacitor Ch1. The specific connections are as follows: the anode of D1 is connected to the output terminal of the adder, and the cathode of D1 is connected to the anode of D2 and the first terminal of the holding capacitor Ch1; the cathode of D2 is connected to the internal power supply Vcc1 via the pull-up resistor Ru1; the second terminal of Ch1 is grounded. When the instantaneous voltage of the adder output rises, D1 conducts, charging Ch1, and the voltage on Ch1 rises with the input voltage; when the instantaneous voltage begins to fall, D1 is cut off, and the voltage on Ch1 cannot be discharged through D1, only slowly decreasing through the tiny leakage current of D1 (which is negligible in practice), so Ch1 basically maintains the peak value of the input voltage. In this way, the peak holding voltage corresponding to the peak value of the total output current is obtained at the first terminal of Ch1. The input terminal of the first analog-to-digital converter U4 is connected to the first terminal of the holding capacitor Ch1 (i.e., the peak holding voltage point), and the output terminal of U4 is connected to the third terminal of the control circuit (peak feedback input terminal). U4 converts the analog peak holding voltage into a digital quantity, which is the peak current value Ipeak of the total output current. After reading this digital quantity, the control circuit uses it for subsequent comparison and limiting adjustment.

[0086] In this optional embodiment, the instantaneous value of the total output current is directly obtained by summing the output currents of each power unit using an adder, avoiding the delay and error caused by sampling multiple currents separately and then digitally summing them. This instantaneous value is then peak held, converting the extremely short-duration overshoot current peak into a stable analog voltage stored on a holding capacitor. This solves the problem that constant-amplitude converters cannot capture the true overshoot peak due to insufficient sampling rate or inaccurate triggering timing. Finally, the held voltage is converted into a digital peak current by a first analog-to-digital converter for accurate reading by the control circuit. In this embodiment, the adder ensures the integrity and real-time performance of the total current information, the peak-hold circuit captures and stores the transient peak, and the analog-to-digital converter performs high-precision analog-to-digital conversion. The entire detection link does not require a high-speed ADC or complex triggering logic, achieving accurate capture of the current peak for each cycle under high-frequency pulses (e.g., 10kHz) using low-cost analog circuitry, providing reliable and complete feedback data for subsequent closed-loop limiting adjustment.

[0087] While the present invention has been disclosed above, its scope of protection is not limited thereto. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, and all such changes and modifications will fall within the scope of protection of the present invention.

Claims

1. An electronic load overshoot suppression circuit, characterized in that, include: Multiple power units, control loop setpoint circuit, control loop limiting circuit, peak detection circuit with zeroing and control circuit; The first terminal of the control circuit is connected to the first terminal of the control loop setpoint circuit, the second terminal of the control circuit is connected to the first terminal of the control loop limiting circuit, the third terminal of the control circuit is connected to the first terminal of the peak detection circuit with zeroing, the second terminal of the control loop setpoint circuit is connected to the first terminal of each power unit, and the second terminal of the control loop limiting circuit is connected to the second terminal of each power unit. The third terminal of each power unit is connected to form the total current output terminal, and is connected to the second terminal of the peak detection circuit with zeroing. The fourth terminal of each power unit is used to connect to the power supply under test. The control circuit is used to issue a current setpoint signal and a limiting setting signal according to the target current value. The current setpoint signal is transmitted to each power unit through the control loop setpoint circuit, and the limiting setting signal is converted into an output limiting value for each power unit through the control loop limiting circuit. Each of the power units is used to output current according to the current given signal and the output limiting value, and the current output by all the power units is summed to the total current output terminal to obtain the total output current; The peak detection circuit with zeroing function is used to detect the peak current of the total output current and feed it back to the control circuit. The control circuit is also used to adjust the limiting setting signal according to the peak current to suppress the overshoot of the total output current.

2. The electronic load overshoot suppression circuit according to claim 1, characterized in that, The control loop limiting circuit includes a first digital-to-analog converter and a voltage-controlled voltage source; the input terminal of the first digital-to-analog converter is connected to the second terminal of the control circuit, the output terminal of the first digital-to-analog converter is connected to the input terminal of the voltage-controlled voltage source, and the output terminal of the voltage-controlled voltage source is connected to the second terminal of each power unit.

3. The electronic load overshoot suppression circuit according to claim 1, characterized in that, The control loop given circuit includes a second digital-to-analog converter; the input terminal of the second digital-to-analog converter is connected to the first terminal of the control circuit, and the output terminal of the second digital-to-analog converter is connected to the first terminal of each of the power units.

4. The electronic load overshoot suppression circuit according to claim 1, characterized in that, The peak detection circuit with zeroing includes an adder, a peak hold circuit, a zeroing switch, and a first analog-to-digital converter; The first end of the adder is connected to the third end of each of the power units; The peak hold circuit includes a first diode, a second diode, a pull-up resistor, and a holding capacitor; the anode of the first diode is connected to the anode of the second diode, the anode of the first diode is connected to the power supply via the pull-up resistor, and the cathode of the second diode is connected to the second terminal of the adder; the first terminal of the holding capacitor is connected to the cathode of the first diode, and the second terminal of the holding capacitor is grounded; The drain of the reset switch is connected to the first terminal of the holding capacitor, the source of the reset switch is grounded, and the gate of the reset switch is connected to the third terminal of the control circuit. The first terminal of the first analog-to-digital converter is connected to the third terminal of the control circuit, and the second terminal of the first analog-to-digital converter is connected to the cathode of the first diode.

5. The electronic load overshoot suppression circuit according to claim 1, characterized in that, The control circuit is used to compare the peak current with the target current value. When the peak current is greater than the target current value, the limiting setting signal is reduced; when the peak current is less than the target current value, the limiting setting signal is increased; and when the peak current is equal to the target current value, the limiting setting signal is maintained.

6. The electronic load overshoot suppression circuit according to claim 1, characterized in that, Each of the power units includes an operational amplifier, a MOSFET, a current sensing resistor, a first given resistor, a second given resistor, a first feedback resistor, a second feedback resistor, and an integrating capacitor; Each power unit has a positive input terminal and a negative input terminal at its first end; the non-inverting input terminal of each operational amplifier is connected to the positive input terminal via a corresponding first given resistor, and the inverting input terminal of each operational amplifier is connected to the negative input terminal via a corresponding second given resistor; the output terminal of each operational amplifier is connected to the gate of a corresponding MOSFET, and the source of each MOSFET is connected to a corresponding current sensing resistor for connecting to the negative terminal of the power supply under test; one end of each current sensing resistor connected to the MOSFET is connected to the inverting input terminal of the corresponding operational amplifier via a corresponding first feedback resistor, and the other end of each current sensing resistor is connected to the non-inverting input terminal of the corresponding operational amplifier via a corresponding second feedback resistor; both ends of each current sensing resistor are also used to connect to the peak detection circuit with zeroing function; each integrating capacitor is connected between the inverting input terminal and the output terminal of the corresponding operational amplifier; the drains of each MOSFET are connected to form the total current output terminal for connecting to the positive terminal of the power supply under test.

7. A control method for an electronic load overshoot suppression circuit, characterized in that, The method for controlling the electronic load overshoot suppression circuit as described in any one of claims 1 to 6 includes: Obtain the target current value; Based on the target current value, a current setting signal and a limiting setting signal are issued to control the output current of each power unit, and the peak current of the total output current obtained by summing the output currents of each power unit is detected. When the peak current is greater than the target current value, the limiting setting signal is reduced; when the peak current is less than the target current value, the limiting setting signal is increased; when the peak current is equal to the target current value, the limiting setting signal is maintained.

8. The control method for the electronic load overshoot suppression circuit according to claim 7, characterized in that, The acquisition of the target current value includes: The system receives a preset current value set by the user or a current command issued by the host computer, and uses the preset current value or the current command as the target current value.

9. The control method for the electronic load overshoot suppression circuit according to claim 8, characterized in that, The step of issuing a current command signal and an initial limiting setting signal based on the target current value, controlling the output current of each power unit, and detecting the peak current of the total output current obtained by summing the output currents of each power unit includes: Generate a current command signal based on the target current value; An initial limiting setting signal is generated based on the target current value, the transconductance of the MOSFET in the power unit, the number of power units, the turn-on voltage of the MOSFET, and the redundant voltage. The total output current is obtained by summing the output currents of each of the power units, wherein each of the power units is used to output current according to the current setting signal and the initial limiting setting signal; The peak current is obtained by summing the total output current, holding the peak value, and performing analog-to-digital conversion using a peak detection circuit with zeroing function.

10. The control method for the electronic load overshoot suppression circuit according to claim 9, characterized in that, The step of summing, holding, and converting the total output current using a peak detection circuit with zeroing function to obtain the peak current includes: The instantaneous value of the total output current is obtained by summing the output current of each power unit using the adder with the zero-clearing peak detection circuit. The peak hold circuit with the zeroing peak detection circuit holds the instantaneous value of the total output current to the peak, generating a peak hold voltage; The peak holding voltage is converted into the peak current by a first analog-to-digital converter with a zeroing peak detection circuit.

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