A miniaturized filter SIP package structure and optimization method suitable for frequency hopping communication system

Abstract

The application discloses a SIP (System In Package) structure design and manufacturing method of a frequency hopping filter, and belongs to the field of radio frequency microwave communication and high-integration packaging technology. The method is aimed at the problems of the traditional frequency hopping filter under the conditions of miniaturization, high frequency and high integration, such as serious influence of parasitic parameters, obvious standing wave deformation, resonance point deviation and poor bandwidth consistency, etc. Through the establishment of a filter parasitic parameter equivalent model, the pad, capacitor array, ground via and interconnection structure are cooperatively analyzed and optimally designed. Meanwhile, the frequency response characteristics of the filter are optimized by combining damping adjustment, asymmetric structure compensation and resonance point alignment technology. Through the joint regulation of different inter-stage coupling relationships and parasitic effects, the effects of standing wave deformation suppression, in-band flatness improvement, insertion loss reduction and bandwidth optimization are realized. The application further proposes a miniaturized layout and manufacturing process suitable for SIP packaging, including device layout optimization, ground structure design, microstrip line matching and multi-layer packaging cooperative design method, which can effectively reduce the packaging size and improve the system integration. The method takes into account the electrical performance and process realizability, can improve the stability and consistency of the frequency hopping filter under complex working environment, and reduce the frequency drift and performance degradation problems caused by parasitic parameters.

Description

Technical Field

[0001] This invention belongs to the field of radio frequency and microwave circuit design and system-in-package (SIP) technology, specifically relating to a tunable filter structure design method and its packaging implementation technology for frequency hopping communication systems. It involves miniaturized integrated design technology for multi-stage LC resonant filters, tunable capacitor array technology, and multi-stage resonant network coupling design technology. Specifically, it includes binary weighted capacitor arrays, segmented tuning strategies, and resonant point distribution optimization methods to achieve rapid switching of center frequency and stable bandwidth control during frequency hopping. It also involves high-density multilayer printed circuit board (PCB) and SIP packaging co-design technology, including multilayer stack-up structure design, optimized grounding via array layout, and power and signal integrity co-design, to improve the overall system's electromagnetic compatibility (EMC) and signal integrity (SI). Background Technology

[0002] With the rapid development of modern wireless communication, electronic countermeasures, radar detection, and satellite communication technologies, radio frequency (RF) front-end systems are placing increasingly higher demands on filter performance. Especially in complex electromagnetic environments and application scenarios involving multiple frequency bands and standards, traditional fixed-frequency filters are struggling to meet the system's requirements for wide bandwidth coverage, high selectivity, miniaturization, and rapid switching capabilities. Frequency-hopping communication technology, due to its strong anti-interference and anti-interception capabilities and good spectrum utilization efficiency, is widely used in military communications, UAV data links, satellite communications, software-defined radio (SDR) platforms, and new wireless networks. In frequency-hopping systems, filters not only need to possess good out-of-band rejection performance but also need to achieve fast, stable, and low-loss switching between multiple operating frequency bands. Therefore, tunable frequency-hopping filters are gradually becoming an important research direction in RF front-end systems.

[0003] Currently, most traditional filters are designed with fixed parameters, and their center frequency and bandwidth are difficult to change after manufacturing. When a system needs to cover multiple operating frequency bands, multiple independent filters are usually required, and different channels are switched via RF switches to achieve operating frequency conversion. Although this approach is simple in structure, it leads to increased system size, power consumption, and insertion loss, while also reducing the overall reliability of the system, which is detrimental to the development of modern electronic devices towards high integration and miniaturization.

[0004] In recent years, tunable filter technology has gradually developed, including various implementation methods such as varactor diodes, MEMS switches, capacitor array switching, and PIN diode control. Among them, capacitor array tuning technology has received widespread attention in engineering applications due to its advantages such as simple structure, wide tuning range, flexible control, and ease of integration. By switching different capacitor combinations, the equivalent capacitance value in the LC resonant network can be changed, thereby achieving dynamic adjustment of the filter's center frequency. However, in practical applications, due to the coupling effect between different resonant stages, the filter is prone to problems such as resonant point drift, bandwidth instability, VSWR deterioration, and decreased out-of-band rejection during frequency hopping, affecting the overall system performance.

[0005] Furthermore, under high-frequency microwave conditions, parasitic parameters in the PCB layout significantly impact filter performance. For example, pad parasitic capacitance, grounding via distribution, power traces, intermetallic coupling, and package structure all affect the filter's actual resonant frequency and frequency response characteristics. Especially in the GHz band, traditional two-dimensional PCB structures are insufficient to meet the design requirements of high density, small size, and low loss. System-in-Package (SIP) technology, by integrating active devices, passive devices, and control circuitry within a single package, effectively shortens signal transmission paths, reduces the impact of parasitic parameters, and improves system integration, thus gradually becoming an important development direction for RF front-end modules.

[0006] SiP (System-in-Package) packaging technology not only enables multi-layer three-dimensional interconnection but also improves the electromagnetic compatibility (EMC) and signal integrity (SI) of the system through the rational design of grounding structures, shielding structures, and power distribution networks. By using multi-layer PCB stacking, co-design of microstrip and stripline lines, optimized via fence layout, and local shielding structure design, high-frequency signal crosstalk and parasitic coupling can be effectively reduced, improving the stability and consistency of the filter. Simultaneously, SIP technology can reduce system size and overall weight, making it more suitable for applications such as portable devices, miniaturized communication terminals, and airborne equipment. Currently, domestic and international research on tunable filters and SIP packaging mainly focuses on single-module optimization, such as studying only resonant network tuning methods or only miniaturized packaging structures, while comprehensive research on "frequency-hopping filter structure design and SIP co-packaging" is relatively scarce.

[0007] The following problems still exist in the existing technology: First, the center frequency stability of the filter is insufficient during frequency switching, which easily leads to frequency deviation. Second, the coupling between multi-stage resonant networks is complex, making bandwidth control difficult. Third, parasitic parameters have a significant impact under high-frequency conditions, and there are deviations between actual test results and theoretical simulations. Fourth, power integrity and electromagnetic compatibility issues are prominent after system integration, affecting overall performance. Summary of the Invention

[0008] This invention aims to provide a method for designing and fabricating a SIP (System-in-Package) structure for frequency-hopping filters, addressing the problems of poor frequency stability, significant parasitic parameter influence, large structural size, and insufficient packaging consistency in existing frequency-hopping filters for high-frequency, miniaturized, and highly integrated applications. By combining a multi-stage LC resonant network, a capacitor array tuning structure, and SIP system-in-package technology, the filter achieves rapid and stable switching between multiple frequency bands, improving overall system performance and reliability in engineering applications.

[0009] Another objective of this invention is to improve the center frequency stability and bandwidth consistency of the filter in frequency-hopping operation while reducing the overall size of the filter. Addressing the problems of resonant point drift, VSWR degradation, and increased insertion loss that traditional filters easily experience during frequency switching, this invention optimizes the multi-stage resonant circuit structure, adjusts the inter-stage coupling relationship, and introduces a damping adjustment mechanism. This enables the filter to maintain good frequency response characteristics at different operating frequencies, thereby improving the system's stable operation in complex electromagnetic environments.

[0010] This invention also aims to achieve miniaturization and high integration of RF front-end modules by employing a collaborative design method using chip capacitors, bare die diodes, and high-density multilayer PCBs. By rationally designing the pad structure, grounding via array, and gold wire bonding path, the influence of parasitic inductance and capacitance under high-frequency conditions is reduced, minimizing signal transmission loss and unnecessary electromagnetic coupling, thereby improving the filter's quality factor (Q value) and out-of-band rejection capability.

[0011] Furthermore, this invention aims to improve the electromagnetic compatibility (EMC) and signal integrity (SI) of filters under SIP packaging conditions. Through coordinated optimization of the grounding structure, power network, and RF signal path, crosstalk effects and return path impedance within the system are reduced, improving the transmission stability of high-frequency signals and ensuring good anti-interference capability and consistency of the filter even under high-speed frequency hopping operation. Simultaneously, the designed structure needs to achieve rapid frequency adjustment according to different operating requirements, while also considering low insertion loss, high selectivity, high reliability, and ease of mass production to meet the demands of modern wireless communication equipment towards high performance, miniaturization, and modularity. Moreover, through optimization of the layout and process, product manufacturing consistency and engineering feasibility are improved, reducing performance deviations caused by processing errors, soldering errors, and changes in packaging parasitic references, thereby improving product yield and long-term operational stability.

[0012] To achieve the above objectives, the present invention adopts the following technical solution: a SIP structure for a frequency hopping filter, comprising: - Multi-level LC resonant units constitute the main resonant network of the filter; - Capacitor array module, used to achieve frequency tuning; - The radio frequency inductor unit, together with the capacitor array, forms a resonant circuit; - Pad structure for connection between chip and substrate; - Gold wire bonding structure for electrical interconnection; - Grounding via array to reduce return path impedance; - Damping adjustment unit for suppressing standing wave anomalies.

[0013] Wherein: 1. The capacitor array adopts a multi-weighted structure and asymmetric parameter configuration is performed for different levels; 2. A damping resistor is connected in series in the intermediate stage resonant circuit; 3. Different pad sizes are designed to adjust parasitic capacitance for different grades; 4. The length and number of gold wires connected in parallel are optimized according to the current path; 5. Install multiple vias at critical grounding nodes to reduce parasitic inductance.

[0014] Compared with the prior art, the present invention has the following advantages: 1. Effectively suppresses standing wave deformation and improves input-output matching consistency; 2. Achieve multi-level resonant point alignment to improve frequency stability; 3. Improve the controllability of filter bandwidth; 4. Significantly improves the consistency between simulation and actual measurement; 5. Suitable for high-integration, miniaturized SIP packaging scenarios. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the overall structure; Figure 2 This is a schematic diagram of a capacitor array switch structure; Figure 3 This is a diagram of the parasitic equivalent model of the solder pads. Figure 4 A diagram of the equivalent model of parasitic gold thread; Figure 5 A schematic diagram illustrating the performance optimization of the filter model; Detailed Implementation

[0016] The filter's basic structure is designed as a third-order LC filter, with each stage consisting of an inductor and a capacitor array. The coupling between different stages forms the target passband and stopband characteristics. The capacitor array is designed using a binary weighted method, with diodes controlling the switching to achieve frequency adjustability. During the design process, an ideal LC equivalent model is established based on the target center frequency, bandwidth, and return loss. Preliminary parameter calculations are performed using ADS software, subsequently determining the required inductance and capacitance values ​​for each stage to ensure the overall design meets the requirements for passband flatness and out-of-band rejection. In practical implementation, to achieve miniaturization and integration, smaller chip-level diodes and capacitors are used in a symmetrical layout to reduce parasitic coupling effects under high-frequency conditions.

[0017] Based on the ideal LC model described above, the parasitic parameter modeling method introduces parasitic capacitance of pads, parasitic inductance of gold wires, parasitic inductance of vias, and trace distribution parameters to establish a complete parasitic equivalent model. Parasitic capacitance of pads is positively correlated with pad area; the larger the pad area, the more pronounced the capacitance to ground, leading to a decrease in resonant frequency. Parasitic inductance of gold wires is positively correlated with the length of the gold wire; longer bonding wires increase parasitic inductance, thus affecting high-frequency performance. Grounding vias, due to their parasitic inductance, increase grounding impedance, thereby affecting filter bandwidth and matching performance.

[0018] Furthermore, a parasitic model was established using a step-by-step superposition method. First, an ideal model was built, and then parasitic parameters for pads, vias, and gold wires were gradually added. Their effects on return loss, insertion loss, and resonant frequency were analyzed respectively. In the specific implementation process, a three-dimensional electromagnetic model was established using HFSS and jointly simulated with an ADS circuit model to extract and correct various parasitic parameters, thereby improving model accuracy.

[0019] Finally, the established model will be compared and analyzed with the measured structure, and the parasitic model will be optimized and calibrated to obtain a high-precision equivalent model suitable for SIP integrated structures.

[0020] Based on my experimental results, the standing wave (SWR) deformation of the filter, and the parasitic parameter modeling of the embodiment, shows that it is related to the gold wire parasitic effect. In this example, a method for optimizing the SWR deformation is proposed. In the third-order filter, a damping resistor is connected in series on the resonant branch of the intermediate stage, adjusted within the range of 0.5-2Ω. This small resistor slightly improves the SWR by introducing appropriate losses to suppress excessive coupling between multiple resonant stages. Simultaneously, the changes in S-parameters under different resistance values ​​are analyzed using a parameter sweep method. When the added resistance value is small, the improvement effect on SWR deformation is small; when the added series damping resistor is too large, it leads to increased insertion loss and reduced passband gain, while also causing significant bandwidth changes. Therefore, adding a suitable resistor, within a controllable insertion loss range, improves the filter's SWR deformation, enhances SWR smoothness, and improves the stability of the overall frequency response.

[0021] In this example, asymmetric parameter optimization was implemented using pads and gold wires. Even with a perfectly symmetrical structure, different capacitor arrays introduce parasitic effects, and manufacturing errors can cause multiple resonant points to split, leading to VSWR distortion in the designed filter. To address this issue, this example employs asymmetric optimization for different resonant units and capacitor arrays, making 10%-20% differential adjustments to redistribute the resonant frequencies at each stage. Simultaneously, parameter scanning is used to analyze the VSWR changes under different parameter variations, identifying the optimal combination to achieve a smooth VSWR and improve the filter's in-band stability.

[0022] In the parasitic parameter modeling method of this embodiment, the co-optimization of pads and vias reveals through comparative experiments that pad parasitism has a significant impact, and this parasitism is related to the pad area and the distance from the pad to ground. To reduce parasitism, pads can be optimized. Reducing the pad size can decrease parasitic capacitance, thereby reducing resonant frequency shift. Simultaneously, adding multiple parallel ground vias at the ground loop location improves high-frequency grounding performance by reducing the equivalent inductance of the ground loop. Furthermore, the distance between pads and ground vias is jointly optimized. When the pad is too close to the via, additional coupling increases; when the distance is too far, the grounding effect deteriorates. Therefore, a three-dimensional electromagnetic model is established using HFSS to analyze the return loss and bandwidth variations under different pad sizes and different numbers of vias. Ultimately, the method described in this embodiment can reduce the impact of parasitic parameters and improve filter bandwidth and impedance matching performance.

[0023] The filter is integrated into a SIP (System-in-Package) using a multi-layer PCB structure. The resonant network, capacitor array, control switch, and matching network are integrated within the same package module. A complete reference ground structure is provided between the high-frequency signal layer and the ground layer to improve electromagnetic shielding and reduce crosstalk between modules. In the compact structure of the integrated SIP, each resonant unit adopts a compact layout, reducing additional parasitic parameters by shortening the signal transmission path. The packaged casing maximizes electromagnetic shielding and minimizes crosstalk between modules. Diodes are used in the capacitor array control section to achieve switching between different frequency points. The control and RF circuits employ a layered wiring structure to reduce the impact of digital noise on RF performance.

Claims

1. A SIP structure for a frequency hopping filter, characterized in that it includes a multi-stage LC resonant unit, a capacitor array module, an RF inductor unit, a pad structure, a gold wire bonding structure, a grounding via array, and a damping adjustment unit.

2. The SIP structure according to claim 1, characterized in that the capacitor array is a multi-weighted structure and adopts an asymmetric parameter configuration.

3. The SIP structure according to claim 1, characterized in that a damping resistor is connected in series in the intermediate stage resonant circuit.

4. The SIP structure according to claim 1, characterized in that the areas of different levels of pads are set to different values ​​to adjust parasitic capacitance.

5. The SIP structure according to claim 1, characterized in that the gold wire bonding structure uses multiple wires connected in parallel or configured with different lengths to adjust the parasitic inductance.

6. The SIP structure according to claim 1, characterized in that a via array is provided at the grounding node to reduce the return path impedance.

7. A SIP structure design method for a frequency hopping filter, characterized by the following steps: (1) establishing an ideal LC filter model; (2) introducing the parasitic parameter model of pads, gold wires and vias; (3) performing damping adjustment optimization; (4) performing capacitor array asymmetric optimization; (5) completing the layout design and implementing SIP packaging.

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