A slope detection circuit, method and electronic device

Abstract

The application discloses a slope detection circuit, a method and an electronic device, relates to the field of signal processing, and can detect the real slope of a pulse signal and improve detection precision. The slope detection circuit comprises a first comparator, a second comparator, a delay device, an XOR gate, a NOT gate, a first AND gate, a second AND gate and a processor. The processor is used for: obtaining a first pulse signal and a second pulse signal; obtaining a falling slope of a target pulse signal based on a reference voltage difference value and a first pulse width of the first pulse signal; the reference voltage difference value is a difference value between a first reference voltage input to the first comparator and a second reference voltage input to the second comparator; and obtaining a rising slope of the target pulse signal based on the reference voltage difference value and a second pulse width of the second pulse signal.

Description

Technical Field

[0001] This application relates to the field of signal processing, and more particularly to a slope detection circuit, method, and electronic device. Background Technology

[0002] Currently, for the pulse signal output from a switching transistor driver, the rise and fall slopes are typically adjusted using either a fixed slope value or a dynamically adjusted slope to reduce electromagnetic interference (EMI) and high-frequency noise. The fixed slope value method adjusts the slope by directly setting a fixed value, without considering the true slope of the pulse signal. The dynamically adjusted slope method typically uses capacitive coupling to detect the slope, which measures the relative rate of change of the qualitative edge of the output pulse signal, not the true slope. Therefore, neither method can detect the true slope, resulting in poor detection accuracy. Summary of the Invention

[0003] This application provides a slope detection circuit, method, and electronic device that can detect the true slope of a pulse signal and improve detection accuracy.

[0004] To achieve the objective, the embodiments of this application adopt the following technical solutions:

[0005] In a first aspect, a slope detection circuit is provided, comprising a first comparator, a second comparator, a delay unit, an XOR gate, a NOT gate, a first AND gate, a second AND gate, and a processor; a first input terminal of the first comparator is used to input a first reference voltage; a first input terminal of the second comparator is used to input a second reference voltage; the second input terminals of the first and second comparators and the delay unit are all used to input a target pulse signal; the output terminal of the first comparator is connected to the first input terminal of the XOR gate; the output terminal of the second comparator is connected to the second input terminal of the XOR gate; the output terminal of the XOR gate is connected to the first input terminal of the first AND gate and the second AND gate. The first input terminal is connected; the output terminal of the delay unit is connected to the second input terminal of the first AND gate and the input terminal of the NOT gate; the output terminal of the NOT gate is connected to the second input terminal of the second AND gate; the output terminal of the first AND gate is used to output a first pulse signal; the output terminal of the second AND gate is used to output a second pulse signal; the processor is used to: acquire the first pulse signal and the second pulse signal; obtain the falling slope of the target pulse signal based on the reference voltage difference and the first pulse width of the first pulse signal; the reference voltage difference is the difference between the first reference voltage and the second reference voltage; and obtain the rising slope of the target pulse signal based on the reference voltage difference and the second pulse width of the second pulse signal.

[0006] The slope detection circuit described above, through a logic circuit including a first comparator, a second comparator, a delay unit, an XOR gate, a NOT gate, a first AND gate, and a second AND gate, extracts the rising and falling edges of the target pulse signal using two reference voltages to obtain the corresponding first and second pulse signals. Based on the voltage difference and the corresponding first and second pulse widths, the rising and falling slopes are then determined. This slope detection circuit can detect the true slope of the pulse signal, improving detection accuracy.

[0007] In one possible implementation of the first aspect, obtaining the falling slope of the target pulse signal based on the reference voltage difference and the first pulse width of the first pulse signal includes: obtaining the falling slope of the target pulse signal based on the ratio of the reference voltage difference to the first pulse width of the first pulse signal.

[0008] In this implementation, the first pulse width of the first pulse signal corresponds to the duration of the falling edge between the first reference voltage and the second reference voltage in the target pulse signal. According to the slope formula: slope = amplitude difference / duration, the falling slope of the target pulse signal can be obtained based on the ratio of the reference voltage difference to the first pulse width of the first pulse signal.

[0009] In one possible implementation of the first aspect, obtaining the rising slope of the target pulse signal based on the reference voltage difference and the second pulse width of the second pulse signal includes: obtaining the rising slope of the target pulse signal based on the ratio of the reference voltage difference and the second pulse width of the second pulse signal.

[0010] In this implementation, the second pulse width of the second pulse signal corresponds to the duration of the rising edge between the first reference voltage and the second reference voltage in the target pulse signal. According to the slope formula: slope = amplitude difference / duration, the rising slope of the target pulse signal can be obtained based on the ratio of the reference voltage difference and the second pulse width of the second pulse signal.

[0011] In one possible implementation of the first aspect, the delay time of the delayer is greater than or equal to a first duration and less than or equal to a second duration; the first duration is the duration of the falling edge of the target pulse signal within one cycle, and the second duration is the duration of the target pulse signal stabilizing at a high level within one cycle.

[0012] In this implementation, to extract both the rising and falling edges of the target pulse signal, the sustained high-level portion of the target delayed pulse signal within one cycle must completely cover the falling edge of the target pulse signal. Firstly, the end time of the target delayed pulse signal stabilizing at a high level must be greater than or equal to the end time of the falling edge of the target pulse signal to include the end of the falling edge. The time difference between these two times is the duration of the falling edge of the target pulse signal. Therefore, the delay time between the target delayed pulse signals is greater than or equal to the first duration, i.e., the duration of the falling edge of the target pulse signal within one cycle. Secondly, the start time of the target delayed pulse signal stabilizing at a high level must be less than or equal to the end time of this stabilization to include the beginning of the falling edge of the target pulse signal. The time difference between these two times is the duration of the target pulse signal stabilizing at a high level. Therefore, the delay time between the target delayed pulse signals is less than or equal to the second duration, i.e., the duration of the target pulse signal stabilizing at a high level within one cycle.

[0013] In one possible implementation of the first aspect, the first pulse width of the first pulse signal is less than or equal to the duration of the falling edge signal of the target pulse signal.

[0014] In this implementation, the first pulse signal is the falling edge portion of the time period during which the output voltage of the target pulse signal is greater than a first reference voltage and less than a second reference voltage. Depending on the amplitudes of the first and second reference voltages, the first pulse signal can be the entire falling edge of the target pulse signal, or only a portion of it. Therefore, the first pulse width of the first pulse signal is less than or equal to the duration of the falling edge of the target pulse signal.

[0015] In one possible implementation of the first aspect, the second pulse width of the second pulse signal is less than or equal to the duration of the rising edge signal of the target pulse signal.

[0016] In this implementation, the second pulse signal is the rising edge portion of the time period during which the output voltage of the target pulse signal is greater than the first reference voltage and less than the second reference voltage. Depending on the amplitudes of the first and second reference voltages, the second pulse signal can extract the entire rising edge of the target pulse signal or only a portion of it. Therefore, the second pulse width of the second pulse signal is less than or equal to the duration of the rising edge of the target pulse signal.

[0017] In one possible implementation of the first aspect, the second reference voltage is greater than the first reference voltage.

[0018] In this implementation, by setting the magnitude relationship between the first reference voltage and the second reference voltage, the target pulse signal, which includes the rising edge portion and the falling edge portion of the target pulse signal, can be obtained after XOR logic operation, within the voltage amplitude range between the first reference voltage and the second reference voltage.

[0019] In one possible implementation of the first aspect, the amplitude of the first reference voltage is 10% of the amplitude of the output voltage of the target pulse signal, and the amplitude of the second reference voltage is 90% of the amplitude of the output voltage of the target pulse signal.

[0020] In this implementation, the range of the rising and falling edges of the extracted target pulse signal can be obtained by setting the magnitudes of the first and second reference voltages.

[0021] In one possible implementation of the first aspect, the target pulse signal is the output signal of a Class D amplifier.

[0022] In this implementation, by setting the target pulse signal to the output signal of a Class D amplifier, a target pulse signal including both rising and falling edges can be obtained, which facilitates subsequent slope detection.

[0023] Secondly, a slope detection method is provided, applied to an electronic device, the electronic device including a first comparator, a second comparator, and a delay unit; the first comparator is used to compare a first reference voltage and the output voltage of a target pulse signal to obtain a first comparison signal; the second comparator is used to compare a second reference voltage and the output voltage of the target pulse signal to obtain a second comparison signal; the delay unit is used to obtain a target delayed pulse signal of the target pulse signal; the method includes: acquiring a first pulse signal and a second pulse signal; the first pulse signal and the second pulse signal are obtained based on the first comparison signal, the second comparison signal, and the target delayed pulse signal; the first pulse signal is used to characterize the falling edge signal of the target pulse signal, and the second pulse signal is used to characterize the rising edge signal of the target pulse signal; the falling slope of the target pulse signal is obtained based on the reference voltage difference and the first pulse width of the first pulse signal; the reference voltage difference is the difference between the first reference voltage and the second reference voltage; the rising slope of the target pulse signal is obtained based on the reference voltage difference and the second pulse width of the second pulse signal.

[0024] The slope detection method described above compares a first reference voltage and the output voltage of the target pulse signal in a first comparator to obtain a first comparison signal. It then compares a second reference voltage and the output voltage of the target pulse signal in a second comparator to obtain a second comparison signal. Finally, it inputs the target pulse signal into a delay unit to obtain a target delayed pulse signal. Based on the first comparison signal, the second comparison signal, and the target delayed pulse signal, it obtains a first pulse signal characterizing the falling edge of the target pulse signal and a second pulse signal characterizing the rising edge of the target pulse signal. This method can accurately detect the rising and falling edges of the target pulse signal, facilitating the subsequent determination of the falling and rising slopes.

[0025] In one possible implementation of the second aspect, the first pulse signal is obtained based on a first comparison signal, a second comparison signal, and a target delayed pulse signal, including: obtaining an edge target pulse signal based on the first comparison signal and the second comparison signal; obtaining the edge target pulse signal by XORing the first comparison signal and the second comparison signal; obtaining the first pulse signal based on the edge target pulse signal and the target delayed pulse signal; and obtaining the first pulse signal by ANDing the edge target pulse signal and the target delayed pulse signal.

[0026] In this implementation, after the target pulse signal undergoes logical operations such as comparison, delay, XOR, and AND, the first pulse signal, which is used to characterize the falling edge signal of the target pulse signal, can be extracted. The logic is simple and can extract the real pulse signal.

[0027] In one possible implementation of the second aspect, the second pulse signal is obtained based on the first comparison signal, the second comparison signal, and the target delayed pulse signal, including: obtaining an edge target pulse signal based on the first comparison signal and the second comparison signal; obtaining the edge target pulse signal by XORing the first comparison signal and the second comparison signal; obtaining the second pulse signal based on the edge target pulse signal and the target delayed pulse signal; and obtaining the second pulse signal by ANDing the inverted signals of the edge target pulse signal and the target delayed pulse signal.

[0028] In this implementation, after the target pulse signal undergoes logical operations such as comparison, delay, XOR, inversion, and AND, a second pulse signal that represents the rising edge signal of the target pulse signal can be extracted. The logic is simple and can extract the real pulse signal.

[0029] In one possible implementation of the second aspect, obtaining the falling slope of the target pulse signal based on the reference voltage difference and the first pulse width of the first pulse signal includes: obtaining the falling slope of the target pulse signal based on the ratio of the reference voltage difference to the first pulse width of the first pulse signal.

[0030] In one possible implementation of the second aspect, obtaining the rising slope of the target pulse signal based on the reference voltage difference and the second pulse width of the second pulse signal includes: obtaining the rising slope of the target pulse signal based on the ratio of the reference voltage difference and the second pulse width of the second pulse signal.

[0031] In one possible implementation of the second aspect, the delay time between the target delayed pulse signal and the target pulse signal is greater than or equal to a first duration and less than or equal to a second duration; the first duration is the duration of the falling edge of the target pulse signal within one cycle, and the second duration is the duration of the target pulse signal stabilizing at a high level within one cycle.

[0032] In one possible implementation of the second aspect, the first pulse width of the first pulse signal is less than or equal to the duration of the falling edge signal of the target pulse signal.

[0033] In one possible implementation of the second aspect, the second pulse width of the second pulse signal is less than or equal to the duration of the rising edge signal of the target pulse signal.

[0034] In one possible implementation of the second aspect, the second reference voltage is greater than the first reference voltage.

[0035] In one possible implementation of the second aspect, the amplitude of the first reference voltage is 10% of the amplitude of the output voltage of the target pulse signal, and the amplitude of the second reference voltage is 90% of the amplitude of the output voltage of the target pulse signal.

[0036] In one possible implementation of the second aspect, the target pulse signal is the output signal of a Class D amplifier.

[0037] Thirdly, an electronic device is provided, including a slope detection circuit and a Class D amplifier as described in the first aspect and any embodiment thereof; the slope detection circuit is used to detect the rising slope and falling slope of a target pulse signal output by the Class D amplifier.

[0038] Fourthly, an electronic device is provided, including a memory and one or more processors, the memory being coupled to the processors; wherein the memory stores computer program code, the computer program code including computer instructions, which, when executed by the processor, cause the electronic device to perform the slope detection method as described in the second aspect and any embodiment thereof.

[0039] Fifthly, a computer-readable storage medium is provided, including computer instructions that, when executed on an electronic device, cause the electronic device to perform the slope detection method as described in the second aspect and any embodiment thereof.

[0040] In a sixth aspect, a computer program product is provided that, when run on an electronic device, causes the electronic device to perform the slope detection method as described in the second aspect and any embodiment thereof.

[0041] The technical effects of the design methods in the second, third, fourth, fifth, and sixth aspects can be found in the technical effects of the different design methods in the first aspect, and will not be repeated here. Attached Figure Description

[0042] Figure 1 This is a schematic diagram of a possible hardware structure of an electronic device provided in an embodiment of this application;

[0043] Figure 2 This is a schematic diagram of a possible software structure of an electronic device provided in an embodiment of this application;

[0044] Figure 3 This is a schematic diagram of the structure of a slope detection circuit provided in an embodiment of this application;

[0045] Figure 4 A schematic diagram of the circuit structure of a Class D amplifier provided in an embodiment of this application;

[0046] Figure 5 A flowchart of a slope detection method provided in an embodiment of this application;

[0047] Figure 6 A schematic diagram of the waveforms of various pulse signals in a slope detection method provided in an embodiment of this application;

[0048] Figure 7 This is a waveform diagram of the target pulse signal and the target delayed pulse signal in a slope detection method provided in an embodiment of this application;

[0049] Figure 8 A flowchart of a slope detection method that also includes a slope adjustment step, provided for an embodiment of this application. Detailed Implementation

[0050] The technical solutions of the embodiments of this application will be described below with reference to the accompanying drawings. In the description of this application, unless otherwise stated, " / " indicates that the objects before and after are in an "or" relationship. For example, A / B can represent A or B. "And / or" in this application is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, and B alone, where A and B can be singular or plural. Furthermore, in the description of this application, unless otherwise stated, "multiple" refers to two or more. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can represent: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple. Furthermore, to facilitate a clear description of the technical solutions in the embodiments of this application, the terms "first" and "second" are used in the embodiments of this application to distinguish identical or similar items with substantially the same function and effect. Those skilled in the art will understand that the terms "first" and "second" do not limit the quantity or execution order, and that "first" and "second" are not necessarily different. Meanwhile, in the embodiments of this application, the words "exemplary" or "for example" are used to indicate that something is being used as an example, illustration, or description. Any embodiment or design scheme described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design schemes. Specifically, the use of "exemplary" or "for example" is intended to present related concepts in a concrete manner for ease of understanding. The terms "coupling" and "connection" involved in the embodiments of this application should be interpreted broadly. For example, it can refer to a physical direct connection or an indirect connection implemented through electronic devices, such as a connection implemented through resistors, inductors, capacitors, or other electronic devices.

[0051] A pulse signal is a non-periodic, short-lived electrical signal with a specific amplitude and width. It is commonly used in digital circuits, communication systems, control systems, and measuring equipment. Pulse signals have rapid rise and fall times, as well as large amplitude and long duration.

[0052] A Class D amplifier is a high-efficiency audio power amplifier that converts the input signal into a pulse width modulation (PWM) or pulse density modulation (PDM) signal, and further amplifies the power through switching transistors to drive loads such as speakers.

[0053] This application provides an electronic device with a display function. The electronic device can be mobile or fixed. It can be deployed on land (e.g., indoors or outdoors, handheld or vehicle-mounted), on water (e.g., on ships), or in the air (e.g., airplanes, balloons, and satellites). This electronic device can be referred to as user equipment (UE), access terminal, terminal unit, subscriber unit, terminal station, mobile station (MS), mobile station, terminal agent, or terminal device. For example, it can be a mobile phone, tablet computer, laptop computer, smart bracelet, smart screen, smartwatch, virtual reality (VR) device, augmented reality (AR) device, terminal in industrial control, terminal in self-driving, terminal in remote medical care, terminal in smart grid, terminal in transportation safety, terminal in smart city, terminal in smart home, etc. This application does not limit the specific type and structure of the electronic device. The following describes one possible structure of the electronic device.

[0054] Taking mobile phones as an example, the attached document... Figure 1 A possible structure of an electronic device 100 is shown. This electronic device 100 may include a processor 9, an external memory interface 220, an internal memory 221, a universal serial bus (USB) interface 230, a power management module 240, a battery 241, a wireless charging coil 242, a mobile communication module 250, a wireless communication module 260, a slope detection circuit 10, antennas 251 and 261, an audio module 270, a speaker 12, a receiver 270B, a microphone 270C, a headphone jack 270D, a sensor module 280, buttons 290, a motor 291, an indicator 292, a camera 293, a display screen 294, and a subscriber identification module (SIM) card interface 295, etc. Optionally, in some embodiments, it may also include an audio digital signal processor (ADSP) 243.

[0055] It is understood that the structures illustrated in the embodiments of this application do not constitute a specific limitation on the electronic device 100. In other embodiments of this application, the electronic device 100 may include more or fewer components than illustrated, or combine some components, or split some components, or have different component arrangements. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

[0056] Processor 9 may include one or more processing units, such as: a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), a system-on-chip (SoC), a central processing unit (CPU), an application processor (AP), a network processor (NP), a digital signal processor (DSP), a microcontroller unit (MCU), a programmable logic device (PLD), a modem processor, a graphics processing unit (GPU), an image signal processor (ISP), a controller, a video codec, and a neural network processing unit (NPU), etc. Different processing units may be independent devices or integrated into one or more processors. For example, processor 9 may be an application processor (AP). Alternatively, processor 9 may be integrated into a system-on-chip (SoC). Or, processor 9 may be integrated into an integrated circuit (IC) chip. The processor 9 may include an analog front end (AFE) and a micro-controller unit (MCU) in an IC chip.

[0057] The processor 9 may also include a memory for storing computer instructions and data. In some embodiments, the memory in the processor 9 is a cache memory. This memory can store computer instructions or data that the processor 9 has just used or that are being used repeatedly. If the processor 9 needs to use the same computer instructions or data again, it can retrieve them directly from the memory. This avoids repeated accesses, reduces the waiting time of the processor 9, and thus improves the efficiency of the system.

[0058] In some embodiments, the processor 9 may include one or more interfaces. Interfaces may include an inter-integrated circuit (I2C) interface, an inter-integrated circuit sound (I2S) interface, a pulse code modulation (PCM) interface, a universal asynchronous receiver / transmitter (UART) interface, a mobile industry processor interface (MIPI), a general-purpose input / output (GPIO) interface, a subscriber identity module (SIM) interface, and / or a USB interface, etc.

[0059] In some embodiments, the processor may be a processor or controller, such as a central processing unit (CPU), a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. It can implement or execute the various exemplary logic blocks, modules, and circuits described in connection with this disclosure. The processor described above may also be a combination that implements computational functions, such as a combination of one or more microprocessors, a combination of a DSP and a microprocessor, etc.

[0060] The ADSP 243 can be coupled to the audio module 270 and the sensor module 280. The ADSP 243 can process audio signals and sensor data. Even when the processor 9 is in sleep mode, the ADSP 243 can remain operational, thereby reducing the power consumption of the electronic device 100.

[0061] It is understood that the interface connection relationships between the modules illustrated in the embodiments of this application are merely illustrative and do not constitute a structural limitation on the electronic device 100. In other embodiments of this application, the electronic device 100 may also employ different interface connection methods or a combination of multiple interface connection methods.

[0062] The external memory interface 220 can be used to connect an external memory card, thereby expanding the storage capacity of the electronic device 100. The external memory card communicates with the processor 9 through the external memory interface 220 to perform data storage functions. For example, music, video, and other files can be saved on the external memory card.

[0063] Internal memory 221 can be used to store computer executable program code, which includes computer instructions. Processor 9 executes various functional applications and data processing of electronic device 100 by running the computer instructions stored in internal memory 221. In addition, internal memory 221 may include high-speed random access memory, and may also include non-volatile memory, such as at least one disk storage device, flash memory device, universal flash storage (UFS), etc.

[0064] In this embodiment of the application, when the computer instructions are executed by the processor 9, the electronic device 100 executes the slope detection method in this embodiment of the application.

[0065] The memory involved in the embodiments of this application can be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. The non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous linked dynamic random access memory (SLDRAM), and direct rambus RAM (DR RAM). It should be noted that the memory used in the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0066] Electronic device 100 can implement audio functions, such as music playback and recording, through audio module 270, speaker 12, receiver 270B, microphone 270C, headphone jack 270D, and application processor.

[0067] In this embodiment, the audio module 270 may include a slope detection circuit 10.

[0068] Buttons 290 include power buttons, volume buttons, etc. Buttons 290 can be mechanical buttons or touch buttons. Electronic device 100 can receive button inputs and generate key signal inputs related to user settings and function control of electronic device 100. Motor 291 can generate vibration alerts. Motor 291 can be used for incoming call vibration alerts or for touch vibration feedback. Indicator 292 can be an indicator light, used to indicate charging status, battery level changes, or to indicate messages, missed calls, notifications, etc. SIM card interface 295 is used to connect a SIM card. The SIM card can be inserted into or removed from the SIM card interface 295 to achieve contact and separation with electronic device 100. Electronic device 100 can support one or N SIM card interfaces, where N is a positive integer greater than 1. SIM card interface 295 can support Nano SIM cards, Micro SIM cards, SIM cards, etc. In some embodiments, the electronic device 100 employs an embedded SIM (eSIM) card, which can be embedded in the electronic device 100 and cannot be separated from the electronic device 100.

[0069] The electronic device 100 can implement its shooting function through an ISP, a camera 293, a video codec, a GPU, a display 294, and an application processor. The ISP is used to process data fed back from the camera 293. In some embodiments, the ISP can be located within the camera 293. The camera 293 is used to capture still images or videos. In some embodiments, the electronic device 100 may include one or N cameras 293, where N is a positive integer greater than 1.

[0070] Electronic device 100 can implement display functions through a GPU, display screen 294, and application processor. The GPU is a microprocessor for image processing, connected to the display screen 294 and the application processor. The GPU is used to perform mathematical and geometric calculations and for graphics rendering. Processor 9 may include one or more GPUs, which execute computer instructions to generate or modify display information.

[0071] The power management module 240 is used to receive charging input from a charger. The charger can be a wireless charger, such as a wireless charging dock, or other electronic device 100 with reverse wireless charging capability. The power management module 240 can receive wireless charging input via the wireless charging coil 242 of the electronic device. The charger can also be a wired charger; for example, the power management module 240 can receive charging input from a wired charger via a USB interface 230. The power management module 240 is also referred to as a charging chip.

[0072] The power management module 240 is used to connect to the battery 241. The power management module 240 receives input from the battery 241 and supplies power to the processor 9, internal memory 221, display screen 294, camera 293, and wireless communication module 260, etc. The power management module 240 can also be used to monitor parameters such as battery 241 capacity, battery cycle count, and battery health status (leakage current, impedance). In some other embodiments, the power management module 240 may also be located within the processor 9.

[0073] The wireless communication function of the electronic device 100 can be realized through antenna 251, antenna 261, mobile communication module 250, wireless communication module 260, modem processor, etc.

[0074] Mobile communication module 250 can provide wireless communication solutions including 2G / 3G / 4G / 5G for use on electronic device 100. Wireless communication module 260 can provide wireless communication solutions including wireless local area networks (WLAN) (such as wireless fidelity (Wi-Fi) networks), Bluetooth (BT), global navigation satellite system (GNSS), frequency modulation (FM), near field communication (NFC), and infrared (IR) for use on electronic device 100.

[0075] As attached Figure 2 As shown, taking the Android operating system running on electronic device 100 as an example, the software architecture running on processor 9 includes the application layer, framework layer, system runtime library layer, hardware abstraction layer (HAL), and kernel layer.

[0076] The kernel layer is the layer between hardware and software. For example, the kernel layer includes a display driver, a camera driver, and a slope detection driver. The display driver is used to drive the display screen to show images or receive user touch operations, the camera driver is used to drive the camera to capture image data, and the slope detection driver is used to drive the slope detection circuit.

[0077] In this embodiment of the application, the slope detection driver is used to drive the slope detection circuit 10, thereby detecting the slope of the target pulse signal.

[0078] The Hardware Abstraction Layer (HAL) is used to abstract hardware. The HAL hides the hardware interface details of a specific platform, providing the operating system with a virtual hardware platform and exhibiting hardware independence. For example, the HAL includes a display module, a camera module, and a slope detection module. The display module provides a virtual display, the camera module provides a virtual camera, and the slope detection module provides a virtual slope detection circuit.

[0079] The system runtime library layer includes C / C++ libraries and runtime libraries. Many core components and services of the Android operating system are built from native code and require C / C++ libraries. When an application is first installed, it is pre-compiled into machine code form as a runtime library; this process is called pre-compilation. This allows for faster startup and execution of the application by running the machine code.

[0080] The framework layer provides application programming interfaces (APIs) and programming frameworks for applications in the application layer. The framework layer includes predefined implementation methods. For example, it includes a window manager, content providers, a view system, and a notification manager.

[0081] The application layer can include a series of application packages, such as photo, camera, and music applications (app).

[0082] In related technologies, adjusting the slope of the rising and falling edges of the pulse signal output by a switching transistor driver typically employs a fixed slope value. This fixed slope value is used to adjust the slope, thereby reducing EMI and high-frequency noise interference. However, this method does not consider the true slope of the pulse signal. Related technologies have also proposed a dynamic slope adjustment method. This method requires detecting the true slope of the output pulse signal. Currently, capacitive coupling is commonly used to detect the slope; however, this method detects the relative rate of change of the qualitative edge of the output pulse signal, not the true slope of the output pulse signal.

[0083] The two methods for adjusting the slope of the pulse signal mentioned above cannot detect the true slope, resulting in poor detection accuracy.

[0084] Therefore, this application provides a slope detection circuit. Using a logic circuit including a first comparator, a second comparator, a delay unit, an XOR gate, a NOT gate, a first AND gate, and a second AND gate, the rising and falling edges of a pulse signal are extracted using two reference voltages to obtain the corresponding first and second pulse signals. Based on the voltage difference and the corresponding first and second pulse widths, the rising and falling slopes are obtained. This slope detection circuit can detect the true slope of the pulse signal, improving detection accuracy.

[0085] The slope detection circuit provided in this application embodiment can be as shown in the attached... Figure 1 The slope detection circuit 10 in the illustrated electronic device 100. The processor can be as shown in the attached... Figure 1 The processor 9 is shown in the electronic device 100. This application uses an electronic device 100 including a slope detection circuit 10 as an example to specifically describe the slope detection circuit 10.

[0086] For example, see attached Figure 3 As shown, the slope detection circuit 10 includes a first comparator 2, a second comparator 3, a delay unit 4, an XOR gate 5, a NOT gate 6, a first AND gate 7, a second AND gate 8, and a processor 9. The first input terminal of the first comparator 2 is used to input a first reference voltage V1. The first input terminal of the second comparator 3 is used to input a second reference voltage V2. The second input terminals of the first comparator 2, the second comparator 3, and the delay unit 4 are all used to input a target pulse signal P(t). The output terminal of the first comparator 2 is connected to the first input terminal of the XOR gate 5. The output terminal of the second comparator 3 is connected to the second input terminal of the XOR gate 5. The output terminal of the XOR gate 5 is connected to the first input terminals of the first AND gate 7 and the second AND gate 8. The output terminal of the delay unit 4 is connected to the second input terminal of the first AND gate 7 and the input terminal of the NOT gate 6. The output terminal of the NOT gate 6 is connected to the second input terminal of the second AND gate 8. The output terminal of the first AND gate 7 is used to output a first pulse signal Pf(t). The output terminal of the second AND gate 8 is used to output a second pulse signal Pr(t).

[0087] Processor 9 is used to: acquire a first pulse signal Pf(t) and a second pulse signal Pr(t). Based on the reference voltage difference ΔV and the first pulse width Δtf of the first pulse signal Pf(t), the falling slope kf of the target pulse signal P(t) is obtained. The reference voltage difference ΔV is the difference between the first reference voltage V1 and the second reference voltage V2. Based on the reference voltage difference ΔV and the second pulse width Δtr of the second pulse signal Pr(t), the rising slope kr of the target pulse signal P(t) is obtained.

[0088] In one possible implementation, the first comparator 2 and the second comparator 3 can be single-supply comparators or dual-supply comparators. The embodiments of this application do not limit the type of the first comparator 2 and the second comparator 3.

[0089] In one possible implementation, the first comparator 2 and the second comparator 3 can be either low-speed or high-speed comparators. This application does not limit the types of the first comparator 2 and the second comparator 3. If the first comparator 2 and the second comparator 3 are low-speed comparators, only low-frequency target pulse signals P(t) can be applied. If the first comparator 2 and the second comparator 3 are high-speed comparators, then high-frequency target pulse signals P(t) can also be applied.

[0090] In one possible implementation, the first input terminal of the first comparator 2 can be either a non-inverting input terminal or an inverting input terminal. This application embodiment does not limit the type of the first input terminal of the first comparator 2. In this application embodiment, the first input terminal of the first comparator 2 is a non-inverting input terminal.

[0091] In one possible implementation, the first input terminal of the second comparator 3 can be either a non-inverting input terminal or an inverting input terminal. This application embodiment does not limit the type of the first input terminal of the second comparator 3. In this application embodiment, the first input terminal of the second comparator 3 is a non-inverting input terminal.

[0092] In one possible implementation, the delay unit 4 can be a fixed delay unit or an adjustable delay unit. The type of delay unit 4 is not limited in the embodiments of this application.

[0093] As attached Figure 3 The working principle of the slope detection circuit 10 shown is as follows:

[0094] The target pulse signal P(t) is input to the first input terminals of the first comparator 2 and the second comparator 3, respectively, and compared with the first reference voltage V1 and the second reference voltage V2, respectively, to obtain a first comparison signal u1(t) greater than the first reference voltage V1 and a second comparison signal u2(t) greater than the second reference voltage V2. The first comparison signal u1(t) and the second comparison signal u2(t) are input into the XOR gate 5 to obtain an edge target pulse signal Pe(t) greater than the first reference voltage V1 and less than the second reference voltage V2. The edge target pulse signal Pe(t) is a pulse signal including the rising edge and falling edge of the target pulse signal P(t). The target pulse signal P(t) is input into the delay unit 4 to obtain the target delayed pulse signal Pd(t). The target delayed pulse signal Pd(t) is a pulse signal after delaying the target pulse signal P(t). The target pulse signal Pe(t) and the target delayed pulse signal Pd(t) are input into the first AND gate 7 to extract the falling edge signal of the target pulse signal P(t), obtaining the first pulse signal Pf(t). The target delayed pulse signal Pd(t) is input into the NOT gate 6 to obtain the inverted target delayed pulse signal Pd(t), i.e., the inverted target delayed pulse signal Pid(t). The target pulse signal Pe(t) and the inverted target delayed pulse signal Pid(t) are input into the first AND gate 7 to extract the rising edge signal of the target pulse signal P(t), obtaining the second pulse signal Pr(t). Thus, the processor 9 obtains the falling slope kf and rising slope kr of the target pulse signal P(t) based on the reference voltage difference ΔV between the first reference voltage V1 and the second reference voltage V2, the first pulse width Δtf of the first pulse signal Pf(t), and the second pulse width Δtr of the second pulse signal Pr(t). Therefore, this slope detection circuit 10 can detect the true slope of the target pulse signal P(t), improving the detection accuracy.

[0095] In one possible implementation, the target pulse signal P(t) can be the output signal of a Class D amplifier or the output signal of a switching power supply. The source of the target pulse signal P(t) is not limited in the embodiments of this application.

[0096] Corresponding to the source of the target pulse signal P(t), in one possible implementation, the slope detection circuit 10 can be applied in the audio field, or in the fields of automotive electronics, medical electronics, etc. The application of the slope detection circuit 10 is not limited in the embodiments of this application.

[0097] In the embodiments of this application, exemplarily, as shown in the appendix Figure 3 As shown, the target pulse signal P(t) is the output signal of the Class D amplifier 11. The target pulse signal P(t) is used to drive the speaker 12 to produce sound. The Class D amplifier 11 is also connected to the processor 9.

[0098] The specific circuit structure of the Class D amplifier 11, as exemplified, is shown in the attached figure. Figure 4 As shown, the Class D amplifier 11 includes a triangular wave generator 101, a pre-amplifier circuit 102, a third comparator 103, a driver circuit 104, a switching transistor circuit 105, and a filter circuit 106. The triangular wave generator 101 is connected to the first input terminal of the third comparator 103. The input terminal of the pre-amplifier circuit 102 is used to input an audio signal, and the output terminal of the pre-amplifier circuit 102 is connected to the second input terminal of the third comparator 103. The output terminal of the third comparator 103 is connected to the input terminal of the driver circuit 104. The output terminal of the driver circuit 104 is connected to the input terminal of the switching transistor circuit 105. The output terminal of the switching transistor circuit 105 is connected to the input terminal of the filter circuit 106. The output terminal of the filter circuit 106 is used to output a target pulse signal P(t) corresponding to the audio signal. The target pulse signal P(t) is used to drive the speaker 12 to produce sound.

[0099] In one possible implementation, the Class D amplifier 11 may include a pre-amplification circuit 102 or may not include a pre-amplification circuit 102. The embodiments of this application do not limit the composition of the Class D amplifier 11.

[0100] In one possible implementation, the Class D amplifier 11 may include a filter circuit 106 or may not include a filter circuit 106. The embodiments of this application do not limit the composition of the Class D amplifier 11.

[0101] As attached Figure 4 The working principle of the Class D amplifier 11 shown is as follows:

[0102] The audio signal is input to the input terminal of the pre-amplification circuit 102, which is used to set the amplification gain of the audio signal to facilitate volume adjustment. A triangular wave generator 101 generates a triangular wave, which, along with the amplified audio signal, is input to the third comparator 103 for comparison. The frequency of the triangular wave is much higher than the frequency of the audio signal. The output signal of the third comparator 103 is a square wave signal, the amplitude of which is proportional to the amplitude of the input audio signal, and its frequency is the same as the triangular wave frequency. The square wave signal drives the switching transistor in the switching transistor circuit 105 to turn on or off via the driving circuit 104. Finally, after filtering by the filtering circuit 106, the output is the target pulse signal P(t) corresponding to the audio signal.

[0103] In one possible implementation, the switching transistor circuit 105 can be a full-bridge circuit or a half-bridge circuit. The type of the switching transistor circuit 105 is not limited in the embodiments of this application.

[0104] In one possible implementation, the switching transistor can be a MOSFET or an IGBT. This application does not limit the type of switching transistor.

[0105] In the embodiments of this application, as shown in the appendix Figure 4 In the Class D amplifier 11 shown, the driving circuit 104 and the switching transistor circuit 105 constitute a switching transistor driver, and the switching transistor in the switching transistor circuit 105 is the switching transistor in the switching transistor driver.

[0106] In related technologies, EMI and high-frequency noise interference problems in systems including switching transistor drivers (e.g., Class D amplifiers) can be suppressed by performing spread spectrum modulation on the system or adjusting the slope of the target pulse signal P(t) output by the switching transistor driver. While spread spectrum modulation can suppress high-frequency harmonic amplitudes, it correspondingly raises the noise floor across the entire high-frequency band, further exacerbating high-frequency noise. Therefore, interference is typically suppressed by adjusting the slope of the target pulse signal P(t) output by the switching transistor driver.

[0107] In this method, adjusting the slope of the target pulse signal P(t) to suppress interference is employed. However, when using a fixed slope method, since this adjustment is independent of the actual slope of the output signal, it increases the dead time of the switching transistor, thus reducing system efficiency. For example, one main implementation of the fixed slope method is through register configuration, changing the number of internal source resistors in the switching transistor driver to set the dead time of the transistor and reduce the rising and falling edge slopes of the output pulse waveform. This method adjusts the slope using only a fixed slope regardless of how the slope of the target pulse signal P(t) changes. Specifically, when the configured fixed slope value is small, a large slope of the target pulse signal P(t) increases the dead time of the switching transistor, leading to reduced efficiency. In a dynamic slope adjustment method, the slope can be detected through capacitive coupling, detecting the relative rate of change of the qualitative edge of the output pulse signal, rather than the actual slope. This detection method suffers from insufficient detection accuracy, limiting the effectiveness of the dynamic slope adjustment.

[0108] To address the aforementioned issues, this application also provides a slope detection method capable of detecting the true slope of the target pulse signal P(t), thereby improving detection accuracy. Furthermore, after detecting the true slope of the target pulse signal P(t), the slope of the target pulse signal P(t) can be dynamically adjusted based on the true slope, improving the dynamic adjustment effect. It also allows for flexible adjustment of the dead time of the switching transistor, improving efficiency while reducing interference. This application uses the application of this slope detection method to an electronic device 100 as an example to specifically illustrate the slope detection method of this application.

[0109] For example, see attached Figure 5 As shown in the embodiment of this application, a slope detection method is applied to an electronic device 100, which includes a first comparator 2, a second comparator 3, and a delay unit 4. The first comparator 2 compares a first reference voltage V1 with the output voltage of a target pulse signal P(t) to obtain a first comparison signal u1(t). The second comparator 3 compares a second reference voltage V2 with the output voltage of the target pulse signal P(t) to obtain a second comparison signal u2(t). The delay unit 4 obtains a target delayed pulse signal Pd(t) of the target pulse signal P(t). This slope detection method may include steps S501-S503:

[0110] In step S501, the processor 9 acquires a first pulse signal Pf(t) for characterizing the falling edge signal of the target pulse signal P(t), and a second pulse signal Pr(t) for characterizing the rising edge signal of the target pulse signal P(t).

[0111] The first pulse signal Pf(t) and the second pulse signal Pr(t) are both obtained based on the first comparison signal u1(t), the second comparison signal u2(t), and the target delayed pulse signal Pd(t). Specifically, the target pulse signal P(t) is delayed by a certain time by the delay unit 4 to obtain the target delayed pulse signal Pd(t). The target pulse signal P(t) is compared with the first reference voltage V1 by the first comparator 2 to obtain the first comparison signal u1(t). The target pulse signal P(t) is compared with the second reference voltage V2 by the second comparator 3 to obtain the second comparison signal u2. The processor 9 extracts the rising edge and falling edge portions of the target pulse signal P(t) through logical operations based on the first comparison signal u1(t) and the second comparison signal u2(t) to obtain the edge target pulse signal Pe(t). Then, by combining the target delayed pulse signal Pd(t), the rising edge and falling edge parts of the edge target pulse signal Pe(t) are separated, and finally the first pulse signal Pf(t) used to characterize the falling edge signal of the target pulse signal P(t) and the second pulse signal Pr(t) used to characterize the rising edge signal of the target pulse signal P(t) are obtained.

[0112] In one possible implementation, the first comparison signal u1(t) and the second comparison signal u2(t) are XORed to obtain the edge target pulse signal Pe(t). The edge target pulse signal Pe(t) is ANDed with the target delayed pulse signal Pd(t) to obtain the first pulse signal Pf(t).

[0113] The edge target pulse signal Pe(t) is obtained by XORing the first comparison signal u1(t) and the second comparison signal u2(t), as exemplified in the attached diagram. Figure 3As shown, the first comparison signal u1(t) output by the first comparator 2 and the second comparison signal u2(t) output by the second comparator 3 can be input to the input terminal of the XOR gate 5. The first comparison signal u1(t) and the second comparison signal u2(t) are subjected to XOR logic operation to obtain the edge target pulse signal Pe(t).

[0114] For example, see attached Figure 6 As shown, the target pulse signal P(t) is a pulse signal including both rising and falling edges. After passing the target pulse signal P(t) through the first comparator 2 and the second comparator 3, and then through the XOR gate 5, an edge target pulse signal Pe(t) including the rising and falling edge portions of the extracted target pulse signal P(t) can be obtained. The edge target pulse signal Pe(t) is high during the time period when the output voltage of the target pulse signal P(t) is greater than the first reference voltage V1 and less than the second reference voltage V2, and low during the time period when the output voltage of the target pulse signal P(t) is less than or equal to the first reference voltage V1 and greater than or equal to the second reference voltage V2. Therefore, in the edge target pulse signal Pe(t), the pulse width corresponding to the high level of the rising edge of the target pulse signal P(t) is the duration of the extracted rising edge, i.e., Δtr = t2 - t1; and in the edge target pulse signal Pe(t), the pulse width corresponding to the high level of the falling edge of the target pulse signal P(t) is the duration of the extracted falling edge, i.e., Δtf = t4 - t3.

[0115] The target delayed pulse signal Pd(t) is obtained by delaying the target pulse signal P(t) by a certain time using delay unit 4. For example, see attached... Figure 6 As shown, the target delayed pulse signal Pd(t) has the same pulse signal as the target pulse signal P(t). The difference is that the target delayed pulse signal Pd(t) is delayed by a certain time relative to the target pulse signal P(t).

[0116] Since the edge target pulse signal Pe(t) is the rising and falling edge portions of the extracted target pulse signal P(t), it is related to the target pulse signal P(t), that is, the target delayed pulse signal Pd(t) delayed by a certain time. For example, see the attached diagram. Figure 3 As shown, by ANDing with the first AND gate 7, the first pulse signal Pf(t), which is used to characterize the falling edge signal of the target pulse signal P(t), can be extracted.

[0117] For example, see attached Figure 6As shown, during the AND operation of the edge-target pulse signal Pe(t) and the target delayed pulse signal Pd(t), the rising edge portion of the edge-target pulse signal Pe(t) corresponding to the rising edge of the target pulse signal P(t) is at a low level due to the delay in the target delayed pulse signal Pd(t). After ANDing with the target delayed pulse signal Pd(t), it becomes low. Conversely, the falling edge portion of the edge-target pulse signal Pe(t) corresponding to the falling edge of the target pulse signal P(t) is at a high level due to the delay in the target delayed pulse signal Pd(t). After ANDing with the target delayed pulse signal Pd(t), it becomes high. Therefore, the AND operation of the edge-target pulse signal Pe(t) and the target delayed pulse signal Pd(t) essentially extracts the falling edge portion of the edge-target pulse signal Pe(t) corresponding to the falling edge of the target pulse signal P(t). Thus, the resulting first pulse signal Pf(t) is used to characterize the falling edge signal of the target pulse signal P(t).

[0118] In summary, after logical operations such as comparison, delay, XOR, and AND, the falling edge signal Pf(t) of the target pulse signal P(t) can be extracted. This method is logically simple and can extract the true pulse signal.

[0119] In one possible implementation, the first comparison signal u1(t) and the second comparison signal u2(t) are XORed to obtain the edge target pulse signal Pe(t). The edge target pulse signal Pe(t) is ANDed with the inverted signal of the target delayed pulse signal Pd(t) to obtain the second pulse signal Pr(t).

[0120] The process of XORing the first comparison signal u1(t) and the second comparison signal u2(t) to obtain the edge target pulse signal Pe(t), and obtaining the target delayed pulse signal Pd(t) based on the target pulse signal P(t) has been described in detail in the above steps, and will not be repeated here.

[0121] The target delayed pulse signal Pd(t), for example, is shown in the attached figure. Figure 3 As shown, after passing through NOT gate 6, the inverted target delayed pulse signal Pd(t) can be obtained. By ANDing the inverted target delayed pulse signal Pd(t) and the edge target pulse signal Pe(t) through the second AND gate 8, the second pulse signal Pr(t) used to characterize the rising edge signal of the target pulse signal P(t) can be extracted.

[0122] For example, see attached Figure 6As shown, after inverting the target delayed pulse signal Pd(t), the high-level portion becomes low-level, and the low-level portion becomes high-level, resulting in the inverted target delayed pulse signal Pid(t). During the AND operation between the edge-delayed target pulse signal Pe(t) and the inverted target delayed pulse signal Pid(t), the rising edge portion of the edge-delayed target pulse signal Pe(t) corresponding to the rising edge of the target pulse signal P(t) is high-level because the inverted target delayed pulse signal Pid(t) is delayed by a certain time and its level is inverted. After ANDing with the inverted target delayed pulse signal Pid(t), it becomes high-level. Similarly, the falling edge portion of the edge-delayed target pulse signal Pe(t) corresponding to the falling edge of the target pulse signal P(t) is low-level because the inverted target delayed pulse signal Pid(t) is delayed by a certain time and its level is inverted. After ANDing with the inverted target delayed pulse signal Pid(t), it becomes low-level. Therefore, ANDing the edge target pulse signal Pe(t) with the inverted target delayed pulse signal Pid(t) essentially extracts the rising edge portion of the target pulse signal P(t) from the edge target pulse signal Pe(t). Thus, the resulting second pulse signal Pr(t) is used to characterize the rising edge signal of the target pulse signal P(t).

[0123] Similarly, in summary, after performing logical operations such as comparison, delay, XOR, inversion, and AND on the target pulse signal P(t), a second pulse signal Pr(t) can be extracted to represent the rising edge signal of the target pulse signal P(t). This method is logically simple and can extract the true pulse signal.

[0124] In one possible implementation, the delay time between the target delayed pulse signal Pd(t) and the target pulse signal P(t) is greater than or equal to a first duration Δt1 and less than or equal to a second duration Δt2.

[0125] Wherein, the first duration Δt1 is the duration of the falling edge of the target pulse signal P(t) within one period T, and the second duration Δt2 is the duration of the target pulse signal P(t) remaining at a high level within one period T.

[0126] For example, see attached Figure 3 As shown, the delay time between the target delayed pulse signal Pd(t) and the target pulse signal P(t) is essentially the delay time of delayer 4.

[0127] For example, see attached Figure 7As shown, in order to extract both the rising and falling edges of the target pulse signal P(t), the portion of the target delayed pulse signal Pd(t) that remains high within one period T must include the entire falling edge of the target pulse signal P(t). On one hand, the end time of the target delayed pulse signal Pd(t) stabilizing at a high level must be greater than or equal to the end time t7 of the falling edge of the target pulse signal P(t) to include the end of the falling edge of the target pulse signal P(t). The time difference Δt between the two is the duration of the falling edge of the target pulse signal P(t), i.e., t7-t6. Therefore, the delay time between the target delayed pulse signal Pd(t) and the target pulse signal P(t) is greater than or equal to the first duration Δt1, i.e., the duration of the falling edge of the target pulse signal P(t) within one period T. On the other hand, the start time of the target delayed pulse signal Pd(t) stabilizing at a high level must be less than or equal to the end time t6 of the target delayed pulse signal Pd(t) stabilizing at a high level in order to include the beginning of the falling edge of the target pulse signal P(t). The time difference between the two is the duration of the target pulse signal P(t) stabilizing at a high level, i.e., t6-t5. Therefore, the delay time between the target delayed pulse signal Pd(t) and the target pulse signal P(t) is less than or equal to the second duration Δt2, i.e., the duration of the target pulse signal P(t) stabilizing at a high level within one period T.

[0128] In one possible implementation, the second reference voltage V2 is greater than the first reference voltage V1.

[0129] In one possible implementation, the second reference voltage V2 can be greater than or less than the first reference voltage V1. This application embodiment does not limit the magnitude of the first reference voltage V1 and the second reference voltage V2. Regardless of whether the second reference voltage V2 is greater than or less than the first reference voltage V1, after an XOR logic operation, the edge target pulse signal Pe(t) of the voltage amplitude range between the first reference voltage V1 and the second reference voltage V2 can be obtained.

[0130] In one possible implementation, the amplitude of the first reference voltage V1 can be 10% or 15% of the output voltage amplitude of the target pulse signal. The embodiments of this application do not limit the magnitude of the amplitude of the first reference voltage.

[0131] In one possible implementation, the amplitude of the second reference voltage V2 can be 85% or 90% of the output voltage amplitude of the target pulse signal. The present application does not limit the magnitude of the amplitude of the second reference voltage.

[0132] Since the first reference voltage V1 and the second reference voltage V2 are set to extract the rising and falling edges of the target pulse signal P(t), it is sufficient to extract only the rising and falling edges of the target pulse signal P(t). The range of the extracted portion can be set according to actual needs.

[0133] In one possible implementation of this application, the amplitude of the first reference voltage V1 is 10% of the output voltage amplitude of the target pulse signal P(t), and the amplitude of the second reference voltage V2 is 90% of the output voltage amplitude of the target pulse signal P(t).

[0134] The slope detection method described in step S501 above involves inputting the first reference voltage V1 and the output voltage of the target pulse signal P(t) into the first comparator 2 for comparison to obtain the first comparison signal u1(t). The second reference voltage V2 and the output voltage of the target pulse signal P(t) are input into the second comparator 3 for comparison to obtain the second comparison signal u2(t). The target pulse signal P(t) is input into the delay unit 4 to obtain the target delayed pulse signal Pd(t). Based on the first comparison signal u1(t), the second comparison signal u2(t), and the target delayed pulse signal Pd(t), a first pulse signal Pf(t) characterizing the falling edge signal of the target pulse signal P(t) and a second pulse signal Pr(t) characterizing the rising edge signal of the target pulse signal P(t) are obtained. This step S501 can accurately detect the rising and falling edge signals of the target pulse signal P(t), thereby enabling subsequent steps S502 and S503 to obtain the falling slope kf and the rising slope kr.

[0135] In step S502, the processor 9 obtains the falling slope kf of the target pulse signal P(t) based on the reference voltage difference ΔV and the first pulse width Δtf of the first pulse signal Pf(t); the reference voltage difference ΔV is the difference between the first reference voltage V1 and the second reference voltage V2.

[0136] For example, see attached Figure 6 As shown, the first pulse signal Pf(t) is the falling edge portion of the time period during which the output voltage of the target pulse signal P(t) is greater than the first reference voltage V1 and less than the second reference voltage V2. The first pulse width Δtf of the first pulse signal Pf(t) corresponds to the duration between the first reference voltage V1 and the second reference voltage V2 corresponding to the falling edge in the target pulse signal P(t), i.e., Δtf = t4 - t3.

[0137] In one possible implementation, the falling slope kf of the target pulse signal P(t) is obtained based on the ratio of the reference voltage difference ΔV to the first pulse width Δtf of the first pulse signal Pf(t).

[0138] For example, see attached Figure 6 As shown, the first pulse width Δtf of the first pulse signal Pf(t) corresponds to the duration of the falling edge between the first reference voltage V1 and the second reference voltage V2 in the target pulse signal P(t). According to the slope formula: slope = amplitude difference / duration, the falling slope kf of the target pulse signal P(t) can be expressed by the following formula (1):

[0139] kf=ΔV / Δtf Formula (1);

[0140] In one possible implementation, the first pulse width Δtf of the first pulse signal Pf(t) is less than or equal to the duration of the falling edge signal of the target pulse signal P(t).

[0141] For example, see attached Figure 6 As shown, the first pulse signal Pf(t) is the falling edge portion of the time period during which the output voltage of the target pulse signal P(t) is greater than the first reference voltage V1 and less than the second reference voltage V2. Depending on the amplitudes of the first and second reference voltages V1 and V2, the first pulse signal Pf(t) can be the entire falling edge of the target pulse signal P(t), or only a portion of the falling edge. Therefore, the first pulse width Δtf of the first pulse signal Pf(t) is less than or equal to the duration Δt1 of the falling edge signal of the target pulse signal P(t).

[0142] The slope detection method described in step S502 above is based on the falling edge portion of the time period during which the output voltage of the target pulse signal P(t) is greater than the first reference voltage V1 and less than the second reference voltage V2, i.e., the first pulse signal Pf(t). Based on the first pulse width Δtf of the first pulse signal Pf(t), and the ratio of the reference voltage difference ΔV to the first pulse width Δtf, the falling slope kf is obtained. This slope detection method can detect the true falling slope of the target pulse signal P(t), improving detection accuracy.

[0143] In step S503, the processor 9 obtains the rising slope kr of the target pulse signal P(t) based on the reference voltage difference ΔV and the second pulse width Δtr of the second pulse signal Pr(t).

[0144] For example, see attached Figure 6As shown, the second pulse width Δtr is the rising edge portion of the time period during which the output voltage of the target pulse signal P(t) is greater than the first reference voltage V1 and less than the second reference voltage V2. The second pulse width Δtr of the second pulse signal Pr(t) corresponds to the duration between the first reference voltage V1 and the second reference voltage V2 corresponding to the rising edge of the target pulse signal P(t), i.e., Δtr = t2 - t1.

[0145] In one possible implementation, the rising slope kr of the target pulse signal P(t) is obtained based on the ratio of the reference voltage difference ΔV to the second pulse width Δtr of the second pulse signal Pr(t).

[0146] For example, see attached Figure 6 As shown, the second pulse width Δtr of the second pulse signal Pr(t) corresponds to the duration of the rising edge between the first reference voltage V1 and the second reference voltage V2 in the target pulse signal P(t). According to the slope formula: slope = amplitude difference / duration, the rising slope kr of the target pulse signal P(t) can be expressed by the following formula (2):

[0147] kr=ΔV / Δtr Formula (2);

[0148] In one possible implementation, the second pulse width Δtr of the second pulse signal Pr(t) is less than or equal to the duration of the rising edge of the target pulse signal P(t).

[0149] For example, see attached Figure 6 As shown, the second pulse signal Pr(t) is the rising edge portion of the time period during which the output voltage of the target pulse signal P(t) is greater than the first reference voltage V1 and less than the second reference voltage V2. Depending on the amplitudes of the first and second reference voltages V1 and V2, the second pulse signal Pr(t) can be the entire rising edge of the target pulse signal P(t), or only a portion of the rising edge. Therefore, the second pulse width Δtr of the second pulse signal Pr(t) is less than or equal to the duration of the rising edge signal of the target pulse signal P(t).

[0150] The slope detection method described in step S503 above is based on the rising edge portion of the time period during which the output voltage of the target pulse signal P(t) is greater than the first reference voltage V1 and less than the second reference voltage V2, i.e., the second pulse signal Pr(t). The rising slope kr is obtained based on the ratio of the reference voltage difference ΔV and the second pulse width Δtr of the second pulse signal Pr(t). This slope detection method can detect the true rising slope of the target pulse signal P(t), improving detection accuracy.

[0151] The slope detection method described in steps S501-S503 above is essentially based on the rising and falling edges of the time period when the output voltage of the input target pulse signal P(t) is greater than the first reference voltage V1 and less than the second reference voltage V2, i.e., the first pulse signal Pf(t) and the second pulse signal Pr(t). The falling slope kf and rising slope kr are obtained according to the first pulse width Δtr of the first pulse signal Pf(t) and the second pulse width Δtr of the second pulse signal Pr(t), respectively. This slope detection method can detect the true slope of the target pulse signal P(t), improving detection accuracy.

[0152] Furthermore, to address the issues of the adjusted slope being unrelated to the true slope, leading to increased dead time of the switching transistor and reduced system efficiency, and insufficient detection accuracy limiting the effectiveness of dynamic slope adjustment, the slope detection method in this application embodiment may further include a slope adjustment step. This slope adjustment step dynamically adjusts the slope of the target pulse signal P(t) based on the true slope after detection, improving the dynamic adjustment effect. It also allows for flexible adjustment of the dead time of the switching transistor, improving efficiency while reducing interference. This application embodiment uses the slope detection method further including a slope adjustment step as an example to specifically illustrate the slope detection method of this application. For example, see the appendix. Figure 8 The slope detection method may further include steps S504-S506:

[0153] In step S504, the processor 9 dynamically adjusts the slope of the target pulse signal P(t) based on the falling slope kf and the rising slope kr, and flexibly adjusts the dead time of the switching transistor according to the dynamically adjusted slope.

[0154] After detecting the falling slope kf and rising slope kr of the target pulse signal P(t), the rising and falling trends of the target pulse signal P(t) can be determined. Therefore, based on the falling slope kf and rising slope kr, the slope of the target pulse signal P(t) can be dynamically adjusted, improving the dynamic adjustment effect. Furthermore, the dead time of the switching transistor can be flexibly adjusted, improving efficiency while reducing interference.

[0155] For example, see attached Figure 3 As shown, after obtaining the falling slope kf and rising slope kr of the target pulse signal P(t), the processor 9 dynamically adjusts the slope of the target pulse signal P(t) output by the Class D amplifier 11, thereby improving the dynamic adjustment effect. Furthermore, the dead time of the switching transistor in the Class D amplifier 11 can be flexibly adjusted to improve efficiency while reducing interference.

[0156] In step S505, if the falling slope kf is greater than the first falling slope threshold and / or the rising slope kr is greater than the first rising slope threshold, the processor 9 reduces the slope of the target pulse signal P(t) and adjusts the dead time of the switching transistor according to the reduced slope.

[0157] If the falling slope kf is greater than the first falling slope threshold, and / or the rising slope kr is greater than the first rising slope threshold, it indicates that the rising edge signal and / or falling edge signal of the target pulse signal P(t) changes too rapidly, leading to increased interference in the system. The slope of the target pulse signal P(t) can be appropriately reduced based on the falling slope kf and rising slope kr to improve the dynamic adjustment effect. After reducing the slope, the change in the switching speed of the switching transistor may result in insufficient or excessive dead time. It is necessary to remeasure the switching time of the switching transistor based on the reduced slope, calculate and adjust the dead time of the switching transistor to avoid shoot-through (simultaneous conduction of the upper and lower transistors) and optimize efficiency. Therefore, efficiency is improved while reducing interference.

[0158] For example, see attached Figure 3 As shown, when the falling slope kf is greater than the first falling slope threshold and / or the rising slope kr is greater than the first rising slope threshold, the processor 9 reduces the slope of the target pulse signal P(t) output by the Class D amplifier 11 according to the falling slope kf and the rising slope kr, and adjusts the dead time of the switching transistor in the Class D amplifier 11 according to the reduced slope.

[0159] The dead time of the switching transistor can be adjusted flexibly. Specifically, if the dead time is insufficient, the dead time should be increased and the switching time should be remeasured. If the dead time is too long, the dead time should be appropriately reduced to ensure safety.

[0160] In step S506, if the falling slope kf is less than the second falling slope threshold and / or the rising slope kr is less than the first rising slope threshold, the processor 9 increases the slope of the target pulse signal P(t) and adjusts the dead time of the switching transistor according to the increased slope.

[0161] If the falling slope kf is less than the second falling slope threshold, and / or the rising slope kr is less than the first rising slope threshold, it indicates that the rising edge signal and / or falling edge signal of the target pulse signal P(t) changes too slowly, and the switching speed of the switching transistor is too slow. The slope of the target pulse signal P(t) can be appropriately increased based on the falling slope kf and the rising slope kr to improve the dynamic adjustment effect. After increasing the slope, the change in the switching speed of the switching transistor may lead to insufficient or excessive dead time. It is necessary to remeasure the switching time of the switching transistor based on the increased slope, calculate and adjust the dead time of the switching transistor to avoid shoot-through (simultaneous conduction of the upper and lower transistors) and optimize efficiency. Therefore, efficiency is improved while reducing interference.

[0162] For example, see attached Figure 3 As shown, when the falling slope kf is less than the second falling slope threshold and / or the rising slope kr is less than the first rising slope threshold, the processor 9 increases the slope of the target pulse signal P(t) output by the Class D amplifier 11 according to the falling slope kf and the rising slope kr, and adjusts the dead time of the switching transistor in the Class D amplifier 11 according to the increased slope.

[0163] Similarly, the dead time of the switching transistor can be flexibly adjusted as described in step S505, and will not be repeated here.

[0164] The slope detection method described in steps S504-S506 above dynamically adjusts the slope of the target pulse signal P(t) based on the detected falling slope kf and rising slope kr, thus improving the dynamic adjustment effect. Furthermore, it allows for flexible adjustment of the switching transistor's dead time, improving efficiency while reducing interference.

[0165] The slope detection circuit, method, and electronic device provided in this application embodiment can extract the rising and falling edges of a pulse signal using two reference voltages through a logic circuit including a first comparator, a second comparator, a delay unit, an XOR gate, a NOT gate, a first AND gate, and a second AND gate, to obtain the corresponding first and second pulse signals. Based on the voltage difference and the corresponding first and second pulse widths, the rising and falling slopes are obtained. This slope detection circuit can detect the true slope of the pulse signal, improving detection accuracy. Furthermore, it can dynamically adjust the slope based on the detected true slope, improving the dynamic adjustment effect. It can also flexibly adjust the dead time of the switching transistor, improving efficiency while reducing interference.

[0166] It is understood that, in order to achieve the above functions, the electronic device includes hardware and / or software modules that perform the respective functions. Based on the algorithm steps of the examples described in the embodiments disclosed herein, this application can be implemented in hardware or a combination of hardware and computer software. Whether a function is executed by hardware or by computer software driving hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application in conjunction with the embodiments, but such implementation should not be considered beyond the scope of this application. This embodiment can divide the electronic device into functional modules according to the above method examples. For example, each function can be divided into separate functional modules, or two or more functions can be integrated into one processing module. The integrated modules can be implemented in hardware. It should be noted that the module division in this embodiment is illustrative and only represents one logical functional division; other division methods may be used in actual implementation.

[0167] This application also provides a computer-readable storage medium storing computer program code. When the processor executes the computer program code, the electronic device executes the relevant method steps in the above method embodiments.

[0168] This application also provides a computer program product that, when run on a computer, causes the computer to execute the relevant method steps described in the above method embodiments.

[0169] The electronic devices, computer storage media, or computer program products provided in this application are all used to execute the corresponding methods provided above. Therefore, the beneficial effects they can achieve can be referred to the beneficial effects in the corresponding methods provided above, and will not be repeated here.

[0170] Through the above description of the embodiments, those skilled in the art can clearly understand that, for the sake of convenience and brevity, only the division of the above functional modules is used as an example. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above.

[0171] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of modules or units described above is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another device, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0172] The units described above as separate components may or may not be physically separate. A component shown as a unit can be one or more physical units; that is, it can be located in one place or distributed in multiple different locations. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs. Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The functions of the integrated unit can be implemented in hardware or as software functional units.

[0173] If the integrated units described above are implemented as software functional units and sold or used as independent products, they can be stored in a readable storage medium. Based on this understanding, the technical solutions of the embodiments of this application, in essence, or the contributing parts, or all or part of the technical solutions, can be embodied in the form of a software product. This software product is stored in a storage medium and includes several instructions to cause a device (which may be a microcontroller, chip, etc.) or processor to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0174] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A slope detection circuit, characterized in that, The slope detection circuit includes a first comparator, a second comparator, a delay unit, an XOR gate, a NOT gate, a first AND gate, a second AND gate, and a processor; the first input terminal of the first comparator is used to input a first reference voltage; the first input terminal of the second comparator is used to input a second reference voltage; the second input terminals of the first comparator, the second comparator, and the delay unit are all used to input a target pulse signal. The output of the first comparator is connected to the first input of the XOR gate; the output of the second comparator is connected to the second input of the XOR gate; the output of the XOR gate is connected to the first input of the first AND gate and the first input of the second AND gate; the output of the delay unit is connected to the second input of the first AND gate and the input of the NOT gate; the output of the NOT gate is connected to the second input of the second AND gate; the output of the first AND gate is used to output a first pulse signal; the output of the second AND gate is used to output a second pulse signal. The processor is used for: Acquire the first pulse signal and the second pulse signal; The falling slope of the target pulse signal is obtained based on the reference voltage difference and the first pulse width of the first pulse signal; The reference voltage difference is the difference between the first reference voltage and the second reference voltage; The rising slope of the target pulse signal is obtained based on the reference voltage difference and the second pulse width of the second pulse signal.

2. The slope detection circuit according to claim 1, characterized in that, The step of obtaining the falling slope of the target pulse signal based on the reference voltage difference and the first pulse width of the first pulse signal includes: The falling slope of the target pulse signal is obtained based on the ratio of the reference voltage difference to the first pulse width of the first pulse signal.

3. The slope detection circuit according to claim 1, characterized in that, The process of obtaining the rising slope of the target pulse signal based on the reference voltage difference and the second pulse width of the second pulse signal includes: The rising slope of the target pulse signal is obtained based on the ratio of the reference voltage difference to the second pulse width of the second pulse signal.

4. The slope detection circuit according to any one of claims 1-3, characterized in that, The delay time of the delay device is greater than or equal to a first duration and less than or equal to a second duration; the first duration is the duration of the falling edge of the target pulse signal within one cycle, and the second duration is the duration of the target pulse signal stabilizing at a high level within one cycle.

5. The slope detection circuit according to any one of claims 1-4, characterized in that, The first pulse width of the first pulse signal is less than or equal to the duration of the falling edge signal of the target pulse signal.

6. The slope detection circuit according to any one of claims 1-5, characterized in that, The second pulse width of the second pulse signal is less than or equal to the duration of the rising edge of the target pulse signal.

7. The slope detection circuit according to any one of claims 1-6, characterized in that, The second reference voltage is greater than the first reference voltage.

8. The slope detection circuit according to claim 7, characterized in that, The amplitude of the first reference voltage is 10% of the output voltage amplitude of the target pulse signal, and the amplitude of the second reference voltage is 90% of the output voltage amplitude of the target pulse signal.

9. The slope detection circuit according to any one of claims 1-8, characterized in that, The target pulse signal is the output signal of a Class D amplifier.

10. A slope detection method, characterized in that, The invention is applied to an electronic device, which includes a first comparator, a second comparator, and a delay unit; the first comparator is used to compare a first reference voltage with the output voltage of a target pulse signal to obtain a first comparison signal; the second comparator is used to compare a second reference voltage with the output voltage of the target pulse signal to obtain a second comparison signal. The delay unit is used to obtain a target delayed pulse signal of the target pulse signal; The method includes: A first pulse signal and a second pulse signal are acquired; the first pulse signal and the second pulse signal are obtained based on the first comparison signal, the second comparison signal and the target delayed pulse signal; the first pulse signal is used to characterize the falling edge signal of the target pulse signal, and the second pulse signal is used to characterize the rising edge signal of the target pulse signal; The falling slope of the target pulse signal is obtained based on the reference voltage difference and the first pulse width of the first pulse signal; the reference voltage difference is the difference between the first reference voltage and the second reference voltage. The rising slope of the target pulse signal is obtained based on the reference voltage difference and the second pulse width of the second pulse signal.

11. The slope detection method according to claim 10, characterized in that, The first pulse signal is obtained based on the first comparison signal, the second comparison signal, and the target delayed pulse signal, and includes: An edge target pulse signal is obtained based on the first comparison signal and the second comparison signal; the edge target pulse signal is obtained by XORing the first comparison signal and the second comparison signal. The first pulse signal is obtained based on the edge target pulse signal and the target delayed pulse signal; the first pulse signal is obtained by ANDing the edge target pulse signal and the target delayed pulse signal.

12. The slope detection method according to claim 10 or 11, characterized in that, The second pulse signal is obtained based on the first comparison signal, the second comparison signal, and the target delayed pulse signal, and includes: An edge target pulse signal is obtained based on the first comparison signal and the second comparison signal; the edge target pulse signal is obtained by XORing the first comparison signal and the second comparison signal. The second pulse signal is obtained based on the edge target pulse signal and the target delayed pulse signal; the second pulse signal is obtained by ANDing the inverted signals of the edge target pulse signal and the target delayed pulse signal.

13. The slope detection method according to any one of claims 10-12, characterized in that, The step of obtaining the falling slope of the target pulse signal based on the reference voltage difference and the first pulse width of the first pulse signal includes: The falling slope of the target pulse signal is obtained based on the ratio of the reference voltage difference to the first pulse width of the first pulse signal.

14. The slope detection method according to any one of claims 10-13, characterized in that, The process of obtaining the rising slope of the target pulse signal based on the reference voltage difference and the second pulse width of the second pulse signal includes: The rising slope of the target pulse signal is obtained based on the ratio of the reference voltage difference to the second pulse width of the second pulse signal.

15. The slope detection method according to any one of claims 10-14, characterized in that, The delay time between the target delayed pulse signal and the target pulse signal is greater than or equal to a first duration and less than or equal to a second duration; the first duration is the duration of the falling edge of the target pulse signal within one cycle, and the second duration is the duration of the target pulse signal remaining stable at a high level within one cycle.

16. The slope detection method according to any one of claims 10-15, characterized in that, The first pulse width of the first pulse signal is less than or equal to the duration of the falling edge signal of the target pulse signal.

17. The slope detection method according to any one of claims 10-16, characterized in that, The second pulse width of the second pulse signal is less than or equal to the duration of the rising edge of the target pulse signal.

18. The slope detection method according to any one of claims 10-17, characterized in that, The second reference voltage is greater than the first reference voltage.

19. The slope detection method according to any one of claims 10-18, characterized in that, The amplitude of the first reference voltage is 10% of the output voltage amplitude of the target pulse signal, and the amplitude of the second reference voltage is 90% of the output voltage amplitude of the target pulse signal.

20. The slope detection method according to any one of claims 10-19, characterized in that, The target pulse signal is the output signal of a Class D amplifier.

21. An electronic device, characterized in that, Includes a slope detection circuit and a Class D amplifier as described in any one of claims 1-9; the slope detection circuit is used to detect the rising slope and falling slope of the target pulse signal output by the Class D amplifier.

22. An electronic device, characterized in that, include: A memory and one or more processors, the memory being coupled to the processors; wherein the memory is used to store instructions executable by the one or more processors, the memory storing computer program code including computer instructions that, when executed by the processor, cause the electronic device to perform the slope detection method as described in any one of claims 10-20.

23. A computer-readable storage medium, characterized in that, Includes computer instructions that, when executed on an electronic device, cause the electronic device to perform the slope detection method as described in any one of claims 10-20.

24. A computer program product, characterized in that, When the computer program product is run on a computer, the computer performs the slope detection method as described in any one of claims 10-20.

Images