A clock data recovery method and circuit

Abstract

This application relates to the field of communication technology and provides a clock data recovery method and circuit. It does not require the deployment of multi-stage equalizers on the front-end circuit. By integrating a circuit structure with adaptive compensation for high-frequency channel attenuation inside the clock data recovery circuit, it utilizes multiphase oversampling and digital weighted compensation technology, and optimizes the design in terms of design complexity, convergence speed, and tracking accuracy. It solves problems such as overcompensation runaway and locking instability, and simultaneously realizes phase tracking and high-frequency attenuation compensation inside the clock data recovery circuit.

Description

Technical Field

[0001] This application relates to the field of communication technology, specifically to the field of high-speed serial communication technology, and in particular to a clock data recovery method and circuit. Background Technology

[0002] In high-speed serial communication applications, devices and systems employing serializer / deserializer (SerDes) technology, such as SerDes transceivers, optical module receivers, and high-speed interface chips, require clock and data recovery (CDR) technology to extract the synchronization clock directly from the level transitions of the serial data stream for data reconstruction. Because the channels used for data transmission, such as circuit board traces, cables, and optical fibers, inherently have low-pass characteristics, the attenuation of high-frequency components in the transmitted data is generally greater than that of low-frequency components. This can lead to significant inter-symbol interference (ISI) at the receiving end, causing eye diagram closure and preventing proper clock and data recovery. In existing technologies, to address the high-frequency attenuation problem in channels, one approach is to place a multi-stage equalizer before the clock data recovery circuit. This could be a continuous-time linear equalizer (CTLE) or a decision feedback equalizer (DFE). This performs channel compensation on the received signal before it enters the clock data recovery circuit, thus preventing premature locking before the eye diagram is fully open. However, deploying a multi-stage equalizer before the clock data recovery circuit has several drawbacks. First, it requires independent adaptive loops and closed-loop control systems for each equalizer, increasing the overall convergence time and introducing interference. Second, it occupies additional circuit area and requires high-precision analog circuitry and calibration networks, increasing chip area and overall power consumption, and making the circuit susceptible to variations in process voltage-temperature (PVT) conditions. Existing clock data recovery circuit solutions sometimes include a multiphase clock generator, which reduces the frequency deviation and phase difference between the output multiphase clock signal and the input data under control voltage adjustment. However, these existing clock data recovery circuit solutions are limited by the lock-in decision based on phase error, making it difficult to deal with functional misjudgments caused by extreme signals or the problem of premature lock-in before the eye diagram is fully open. Examples include Chinese patents with authorization publication number CN105703767B, Chinese patent application publication number CN119834797A, US patents with authorization publication numbers US7916820B2 and US8989333B2, and US patent application publication number US20240146500A1.

[0003] To address this technical challenge, this application proposes a clock data recovery method and circuit. Summary of the Invention

[0004] In a first aspect, this application provides a clock data recovery method. The clock data recovery method includes: locking a reference frequency for input serial data using a multi-phase clock generator; and generating N reference clock signals based on the locked reference frequency, wherein the adjacent phase interval of the N reference clock signals is fixed to one-Nth of the unit time interval associated with the input serial data, where N is an even number not less than 4; oversampling the input serial data by N times using a sampling clock signal through a multi-channel sampler to obtain parallel sampled data, wherein the sampling clock signal is generated using the N reference clock signals as input references and through adjacent phase weighted interpolation; and extracting an edge slope signal from the parallel sampled data using an edge slope estimation module to estimate the channel high-frequency attenuation. The parallel sampling data is compensated for high-frequency attenuation based on the channel high-frequency attenuation using a digital weighted compensation module to obtain compensated sampling data. A phase detection and adjustment module detects the transition edge position of the compensated sampling data to generate a phase error signal, and adjusts the phase of the sampling clock signal based on the phase error signal. A dual-mode lock-in decision module determines whether to stably lock the input serial data in capture mode based on the edge slope signal and the phase error signal, and determines whether the lock has been lost in tracking mode based on the phase error signal.

[0005] According to the first aspect of this application, it is not necessary to deploy a multi-stage equalizer on the front-end circuit. By integrating a circuit structure with adaptive compensation for high-frequency channel attenuation inside the clock data recovery circuit, and utilizing multiphase oversampling and digital weighted compensation technology, and optimizing the design in terms of design complexity, convergence speed, and tracking accuracy, the problems of overcompensation runaway and locking instability are solved. Phase tracking and high-frequency attenuation compensation are realized simultaneously inside the clock data recovery circuit.

[0006] In one possible implementation of the first aspect of this application, N is 8, the N reference clock signals are 8 reference clock signals, and the adjacent phase interval of the 8 reference clock signals is fixed to one-eighth of the unit time interval.

[0007] In one possible implementation of the first aspect of this application, the edge slope signal indicates the amplitude difference between adjacent sampling points of a series of consecutive sampling points within the same sliding window in the parallel sampling data, wherein the amplitude difference between adjacent sampling points of the series of consecutive sampling points is used to calculate the edge slope fluctuation and the signal average edge slope.

[0008] In one possible implementation of the first aspect of this application, the average edge slope of the signal is used to estimate the high-frequency attenuation of the channel based on a preset slope-attenuation correspondence table, wherein the preset slope-attenuation correspondence table is obtained by calibration during the production process of the clock data recovery circuit or after leaving the factory.

[0009] In one possible implementation of the first aspect of this application, the dual-mode locking decision module determines whether to stably lock the input serial data based on the edge slope signal and the phase error signal in the capture mode, including: when the phase error signal indicates that the absolute value of the phase error of M consecutive transition edges is less than a first phase error threshold and the edge slope signal indicates that the edge slope fluctuation of M consecutive unit time intervals is less than the slope fluctuation threshold, it is determined that the input serial data is stably locked and the tracking mode is switched; otherwise, the edge slope signal is continuously extracted, wherein M is the upper limit of the number of consecutive sampling points in the tracking mode.

[0010] In one possible implementation of the first aspect of this application, the dual-mode locking decision module determines whether the lock is lost based on the phase error signal in the tracking mode, including: when the phase error signal indicates that the absolute value of the phase error of more than a preset number of transition edges in S consecutive transition edges exceeds a second phase error threshold, determining that the lock is lost and switching to the capture mode; otherwise, maintaining the tracking mode to continuously monitor the phase error signal, wherein S is the lower limit of the number of consecutive sampling points in the tracking mode.

[0011] Secondly, this application provides a clock data recovery circuit. The clock data recovery circuit includes: a multi-phase clock generator for locking a reference frequency for input serial data, and generating N reference clock signals based on the locked reference frequency, wherein the adjacent phase interval of the N reference clock signals is fixed to one-Nth of the unit time interval associated with the input serial data, where N is an even number not less than 4; a multi-channel sampler for oversampling the input serial data N times using the sampling clock signals to obtain parallel sampled data, wherein the sampling clock signals are generated using the N reference clock signals as input references and through adjacent phase weighted interpolation; and an edge slope estimation module for estimating the edge slope from the parallel sampled data. The system extracts edge slope signals from the data to estimate the channel high-frequency attenuation; a digital weighted compensation module compensates the parallel sampled data for channel high-frequency attenuation based on the channel high-frequency attenuation to obtain compensated sampled data; a phase detection and adjustment module detects the transition edge position of the compensated sampled data to generate a phase error signal, and adjusts the phase of the sampling clock signal based on the phase error signal; a dual-mode lock-in decision module determines whether to stably lock the input serial data based on the edge slope signal and the phase error signal in capture mode, and determines whether to lose lock based on the phase error signal in tracking mode.

[0012] Through the second aspect of this application, it is not necessary to deploy a multi-stage equalizer on the front-end circuit. By integrating a circuit structure with adaptive compensation for high-frequency channel attenuation inside the clock data recovery circuit, and utilizing multiphase oversampling and digital weighted compensation technology, and optimizing the design in terms of design complexity, convergence speed, and tracking accuracy, problems such as overcompensation runaway and locking instability are solved. Phase tracking and high-frequency attenuation compensation are simultaneously achieved inside the clock data recovery circuit.

[0013] In one possible implementation of the second aspect of this application, N is 8, the N reference clock signals are 8 reference clock signals, and the adjacent phase interval of the 8 reference clock signals is fixed to one-eighth of the unit time interval.

[0014] In one possible implementation of the second aspect of this application, N is 16, the N reference clock signals are 16 reference clock signals, and the adjacent phase interval of the 16 reference clock signals is fixed to one-sixteenth of the unit time interval.

[0015] In one possible implementation of the second aspect of this application, the multiphase clock generator includes a phase-locked loop circuit and a phase interpolator. The phase-locked loop circuit includes a multiphase ring voltage-controlled oscillator for generating the N reference clock signals with uniformly distributed phases. The phase interpolator is used to generate the sampled clock signal by using the N reference clock signals as input references and by weighted interpolation of adjacent phases.

[0016] In one possible implementation of the second aspect of this application, the phase-locked loop circuit includes a phase detector, a charge pump, and a loop filter, and the multiphase ring voltage-controlled oscillator is an 8-phase ring voltage-controlled oscillator used to generate an 8-phase uniformly distributed reference clock and the clock interval of each phase is one-eighth of the unit time interval.

[0017] In one possible implementation of the second aspect of this application, the phase error signal indicates whether the position of the transition edge of the compensated sampled data is leading or lagging relative to the sampling point of the sampling clock signal, and the phase error signal is used to adjust the phase of the sampling clock signal by a phase interpolator.

[0018] In one possible implementation of the second aspect of this application, the edge slope signal indicates the amplitude difference between adjacent sampling points of a plurality of consecutive sampling points within the same sliding window in the parallel sampling data, wherein the amplitude difference between adjacent sampling points of the plurality of consecutive sampling points is used to calculate the edge slope fluctuation and the signal average edge slope.

[0019] In one possible implementation of the second aspect of this application, the average edge slope of the signal is used to estimate the high-frequency attenuation of the channel based on a preset slope-attenuation correspondence table, wherein the preset slope-attenuation correspondence table is obtained by calibration during the production process of the clock data recovery circuit or after it leaves the factory.

[0020] In one possible implementation of the second aspect of this application, the digital weighted compensation module includes a 5-tap symmetric phase domain differential finite impulse response (FIR) filter. The digital weighted compensation module is used to determine the main tap coefficients, first-order high-frequency compensation coefficients, and second-order high-frequency compensation coefficients of the 5-tap symmetric phase domain differential finite impulse response filter based on the channel high-frequency attenuation using a preset correspondence table of compensation coefficients, slopes, and attenuation amounts. It also performs channel high-frequency attenuation compensation on the parallel sampled data using the 5-tap symmetric phase domain differential finite impulse response filter.

[0021] In one possible implementation of the second aspect of this application, the number of consecutive sampling points is a first number in the capture mode and a second number in the tracking mode, the first number being less than the second number, and the second number being configured according to the system noise intensity.

[0022] In one possible implementation of the second aspect of this application, the dual-mode lock-in decision module is configured to determine whether to stably lock the input serial data based on the edge slope signal and the phase error signal in the capture mode, comprising: when the phase error signal indicates that the absolute value of the phase error of M consecutive transition edges is less than a first phase error threshold and the edge slope signal indicates that the edge slope fluctuation of M consecutive unit time intervals is less than the slope fluctuation threshold, determining that the input serial data is stably locked and switching to the tracking mode; otherwise, continuously extracting the edge slope signal, wherein M is an upper limit of the number of consecutive sampling points in the tracking mode.

[0023] In one possible implementation of the second aspect of this application, the dual-mode locking decision module is used to determine whether the lock is lost based on the phase error signal in the tracking mode, including: when the phase error signal indicates that the absolute value of the phase error of more than a preset number of transition edges in S consecutive transition edges exceeds a second phase error threshold, determining that the lock is lost and switching to the capture mode; otherwise, maintaining the tracking mode to continuously monitor the phase error signal, wherein S is the lower limit of the number of consecutive sampling points in the tracking mode. Attached Figure Description

[0024] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 A flowchart illustrating a clock data recovery method provided in an embodiment of this application; Figure 2 A schematic diagram of a clock data recovery circuit provided in an embodiment of this application; Figure 3 A schematic diagram illustrating the switching between capture mode and tracking mode of a dual-mode locking decision module provided in an embodiment of this application; Figure 4 This is a schematic diagram of a clock data recovery circuit in a multi-channel application scenario provided by an embodiment of this application. Detailed Implementation

[0026] The embodiments of this application will now be described in further detail with reference to the accompanying drawings.

[0027] It should be understood that in the description of this application, "at least one" means one or more, and "multiple" means two or more. In addition, the words "first," "second," etc., unless otherwise stated, are used only for the purpose of distinguishing descriptions and should not be construed as indicating or implying relative importance or order.

[0028] Figure 1 This is a flowchart illustrating a clock data recovery method provided in an embodiment of this application. Figure 1 As shown, the clock data recovery method includes the following steps.

[0029] Step S101: Lock the reference frequency of the input serial data using a multiphase clock generator, and generate N reference clock signals based on the locked reference frequency, wherein the adjacent phase interval of the N reference clock signals is fixed to one-Nth of the unit time interval associated with the input serial data, and N is an even number not less than 4.

[0030] Step S103: Using a multi-channel sampler and a sampling clock signal, the input serial data is oversampled N times to obtain parallel sampled data. The sampling clock signal is generated by using the N reference clock signals as input references and by adjacent phase weighted interpolation.

[0031] Step S105: Extract the edge slope signal from the parallel sampling data through the edge slope estimation module in order to estimate the channel high-frequency attenuation.

[0032] Step S107: The parallel sampling data is compensated for by the channel high-frequency attenuation based on the channel high-frequency attenuation using the digital weighted compensation module, thereby obtaining the compensated sampling data.

[0033] Step S109: The phase detection and adjustment module detects the position of the transition edge of the compensated sampled data to generate a phase error signal, and adjusts the phase of the sampled clock signal based on the phase error signal.

[0034] Step S111: The dual-mode locking decision module determines whether to stably lock the input serial data based on the edge slope signal and the phase error signal in capture mode, and determines whether to lose lock based on the phase error signal in tracking mode.

[0035] See Figure 1Clock and Data Recovery (CDR) circuits are core components of the receiver in high-speed serial communication systems. They extract the synchronization clock from the level transitions of the serial data stream to restore the data, and then convert the serial data stream into parallel data. CDR is a core component of devices and systems employing serializer / deserializer (SerDes) technology, such as SerDes transceivers, optical module receivers, and high-speed interface chips. Because the channels used for data transmission, such as circuit board traces, cables, and optical fibers, inherently have low-pass characteristics, the attenuation of high-frequency components in the transmitted data is generally greater than the attenuation of low-frequency components. This can lead to severe inter-symbol interference (ISI) at the receiver, causing eye diagram closure and preventing proper clock and data recovery. If multiple equalizers, such as continuous-time linear equalizers (CTLEs) and decision feedback equalizers (DFEs), are placed in the pre-stage of the clock data recovery circuit, channel compensation can be performed on the signal before it enters the clock data recovery circuit, which can improve the locking performance of the clock data recovery circuit. However, deploying additional multiple equalizers in the pre-stage circuit will inevitably lead to additional circuit area and require the introduction of high-precision analog circuits and calibration networks. Furthermore, decision feedback equalizers require high-speed adders, tapped delay lines, and adaptive algorithm circuits. Moreover, the performance of analog equalizers is greatly affected by changes in process voltage-temperature (PVT) conditions, requiring complex on-chip calibration circuits to ensure performance. Furthermore, the multi-stage equalizer deployed in the front-end circuit requires an independent adaptive loop, resulting in a long overall convergence time. Moreover, the equalizer and the clock data recovery circuit are two independent closed-loop control systems, which can easily lead to mutual interference, causing locking anomalies and performance degradation. This is especially true under extreme signal conditions, which can cause the adaptive continuous-time linear equalizer to misjudge its function, resulting in the clock data recovery circuit being unable to lock stably. However, relying solely on the clock data recovery circuit's own frequency-locking and phase-locking functions is insufficient, as the locking decision is mainly based on phase error, making it difficult to handle functional misjudgments caused by extreme signals or premature locking before the eye diagram is fully open. Figure 1The clock data recovery method shown does not require the deployment of multi-stage equalizers on the front-end circuit. It integrates a circuit structure with adaptive compensation for high-frequency channel attenuation inside the clock data recovery circuit. It utilizes multiphase oversampling and digital weighted compensation techniques and optimizes the design in terms of complexity, convergence speed, and tracking accuracy. This solves problems such as overcompensation runaway and locking instability. Phase tracking and high-frequency attenuation compensation are simultaneously achieved inside the clock data recovery circuit.

[0036] Continue reading Figure 1Internally, the clock data recovery circuit constructs a closed-loop control chain that starts with N times oversampled data, proceeds to real-time calculation of edge slope, adaptively updates compensation coefficients for high-frequency channel attenuation compensation, and finally locks the data based on a dual criterion of edge slope signal and phase error signal. The internal phase-locked loop (PLL) circuit of the clock data recovery circuit locks the frequency of the input serial data. Then, a multi-phase clock generator uniformly generates N reference clock signals based on the locked reference frequency, requiring that the adjacent phase interval of the N reference clock signals be fixed to one-Nth of the unit interval (UI) associated with the input serial data. Phase tracking is achieved through clock sampling and phase interpolation. Using the entire set of N reference clock signals with fixed division as input references, the sampling clock signal is generated through adjacent phase weighted interpolation. This sampling clock signal is then used to oversample the input serial data by N times, thereby obtaining parallel sampled data. Thus, under normal conditions, without changing the frequency of the reference clock, continuous fine-tuning of the phase interpolation is equivalent to adjusting the frequency, allowing tracking of minute frequency shifts in the input signal. Furthermore, by performing oversampling and digital equalization internally within the clock data recovery circuit, and by forcibly setting the adjacent phase intervals of N reference clock signals, the intervals between adjacent sampling points are made sufficiently small to determine whether the edge is leading or lagging. This provides enough sampling points to fit linear edges and accurately calculate edge slopes, enabling the differentiation of subtle high-frequency attenuation even under noise. Additionally, by setting the number of N, such as 8 or 16, the scale of logic devices such as the phase interpolator, parallel sampling register, and multiplexer digital gates can be controlled, avoiding excessive digital dynamic power consumption and thus controlling the overall scale of the analog circuit. This achieves complete coverage of both rising and falling edges of the signal while controlling the calculation error of the linear fitting edge within an acceptable range, and simultaneously controlling the power consumption of the digital hardware. Generally, when N equals 4, which means using 4-phase sampling, it's possible to roughly determine whether the edge is leading or lagging. When N equals 16, a relatively larger number of logic devices are required. When N equals 8, which means using 8-phase sampling, and the 8-phase clock signal is evenly divided into a unit time interval (i.e., the interval between adjacent phases is one-eighth of the unit time interval, corresponding to 45 degrees), this allows the 8 sampling points to completely cover both the rising and falling edges of the signal, while simultaneously controlling the calculation error of the linear fitting edge to within 5%, and achieving controllable incremental power consumption in the digital hardware.

[0037] Continue reading Figure 1 The following explanation uses N equal to 8 as an example. Figure 1The clock data recovery method shown achieves both phase tracking and high-frequency attenuation compensation simultaneously. After system power-on, it enters capture mode and initializes all data. A multi-phase clock generator generates eight uniformly distributed (45-degree intervals) reference clock signals. A multi-channel sampler uses the multi-phase clock to achieve eight times oversampling of the input serial data, resulting in parallel sampled data. Then, an edge slope estimation module extracts the edge slope signal from the parallel sampled data to estimate the channel's high-frequency attenuation. In some embodiments, the edge slope estimation module calculates the amplitude difference between adjacent sampling points to obtain the average edge slope of the signal. The channel's high-frequency attenuation is estimated based on a preset slope-attenuation correspondence table. This preset slope-attenuation correspondence table is obtained through calibration during the production process of the clock data recovery circuit or after it leaves the factory. For example, during testing, the corresponding curve can be measured by artificially applying high-frequency attenuation. In practice, the current high-frequency attenuation can be deduced from the edge slope calculated from the sampling point data. The edge slope estimation module calculates the average edge slope of the signal by averaging through a sliding window. That is, the edge slope signal indicates the amplitude difference between adjacent sampling points of multiple consecutive sampling points within the same sliding window in the parallel sampled data. In some embodiments, the sliding window size is 128 to 1024 sampling points. The formula for calculating the edge slope is: SlopeAVG = (1 / Num) × Σ|D(i+1) D(i)| / Δt. Where D(i+1) is the amplitude value of the (i+1)th sampling point, D(i) is the amplitude value of the ith sampling point, Δt is the time interval between adjacent sampling points (e.g., 5 picoseconds), and Num is the number of sampling points within the sliding window. The number of sampling points within the sliding window, i.e., the number of consecutive sampling points, is a first number (e.g., 128) in capture mode and a second number (e.g., 256) in tracking mode. By setting different sliding window sizes for capture and tracking modes, a constraint on convergence speed is provided in capture mode. This requires quickly calculating the average edge slope of the signal, updating the equalization compensation coefficients, and rapidly reducing phase errors. Therefore, a relatively small sliding window avoids lengthening the lock-in time, helping to meet the fast lock-in requirements of bursty data transmission. Generally, the first number is set to 128, meaning the sliding window size in capture mode is 128 sampling points. This achieves a lower limit balance between lock-in speed and noise suppression, avoiding drastic slope fluctuations and frequent jumps in the equalization coefficients caused by noise, thus contributing to a stable convergence loop. In addition, after locking in acquisition mode, it automatically switches to tracking mode. By setting a relatively large sliding window, mean filtering can be performed within a larger window, effectively suppressing small channel fluctuations and random jitter, smoothing the slope calculation results, and avoiding repeated opening and closing of the eye diagram caused by frequent jitter of the equalization coefficient. Generally, the second number is set to 256 to 1024, that is, the size of the sliding window in tracking mode is 256 to 1024 sampling points. Setting the upper limit to 1024 helps to avoid slow loop response speed, which would lead to failure to update the compensation coefficient in time when the channel changes abruptly. Furthermore, the second number is configured according to the system noise intensity, that is, the number of consecutive sampling points in the tracking mode is in the range of 256 to 1024, which can be flexibly configured according to the system noise intensity, which helps to adapt to different optical modules and backplane channel noise environments. Table 1 below illustrates how to obtain the slope and attenuation correspondence table through calibration during production: Table 1

[0038] Continue reading Figure 1The digital weighted compensation module compensates for the high-frequency attenuation of the parallel sampled data based on the high-frequency attenuation of the channel, thereby obtaining compensated sampled data. Thus, the weighting coefficients are adaptively adjusted according to the high-frequency attenuation, and the N sampled data are weighted and summed to compensate for the high-frequency attenuation of the channel. In some embodiments, the digital weighted compensation module includes a 5-tap Symmetric Phase-Domain Differential Finite Impulse Response Filter. Using a 5-tap Symmetric Phase-Domain Differential Finite Impulse Response Filter, the DC gain can be kept close to 1, only boosting the high-frequency components. The output expression of this filter is: Y(k) = w0 × D(k) + w1 × (D(k+1) - D(k-1)) / 2 + w2 × (D(k+2) - D(k-2)) / 4. In the expression for this filter, w0 is the main tap coefficient, fixed at 1; w1 is the first-order high-frequency compensation coefficient; and w2 is the second-order high-frequency compensation coefficient. Furthermore, the ratio of w2 to w1 is approximately 2:1 to minimize phase nonlinearity. The maximum allowable value for w1 is 4.5, and the maximum allowable value for w2 is 9.0, enabling continuous high-frequency compensation from 0 to 15 dB. Additionally, the coefficient update step size is 0.02 in capture mode and 0.005 in tracking mode, which helps adapt to the different characteristics of capture and tracking modes. Moreover, the 5-tap symmetric phase-domain differential finite impulse response filter not only achieves lossless low-frequency component processing and enhances high-frequency components, but also adapts to the multi-coupling design constraints of the entire closed-loop control chain. Compared to first-order differential finite impulse response (FIR) filters, which can only achieve small-amplitude high-frequency compensation and cannot cover the high-frequency attenuation compensation requirements of the entire channel range, high-order multi-tap FIR filters increase circuit area and power consumption. Furthermore, the adaptive update process of infinite impulse response (IIR) filters is prone to oscillations and can disrupt the tracking stability of the CDR loop. Here, a 5-tap symmetric phase domain differential finite impulse response filter is used. By limiting the ratio of the second-order high-frequency compensation coefficient w2 to the first-order high-frequency compensation coefficient w1 to approximately 2:1, the phase nonlinearity distortion introduced by the differentiation operation is effectively offset, while ensuring the phase error detection accuracy under 8-phase oversampling. Through this dedicated weight constraint (limiting the ratio of the second-order high-frequency compensation coefficient w2 to the first-order high-frequency compensation coefficient w1 to approximately 2:1), the tap delay interval of the 5-tap symmetric phase domain differential finite impulse response filter is natively matched to the fixed division of the 8-phase clock, i.e., one-eighth of the unit time interval, without the need for additional delay units. Furthermore, the filter adaptive coefficient update step size and the preset slope and attenuation correspondence table of the factory calibration are all based on the filter characteristic matching design, and are also adapted to the adaptive logic of dual-mode acquisition and tracking.Thus, the digital weighted compensation module is used to determine the main tap coefficients, first-order high-frequency compensation coefficients, and second-order high-frequency compensation coefficients of the 5-tap symmetric phase domain differential finite impulse response filter based on the channel high-frequency attenuation using a preset table of compensation coefficients, slopes, and attenuation amounts. It also performs channel high-frequency attenuation compensation on the parallel sampled data using the 5-tap symmetric phase domain differential finite impulse response filter. Table 2 below exemplarily illustrates the preset table of compensation coefficients, slopes, and attenuation amounts. Table 2

[0039] Continue reading Figure 1 The phase detection and adjustment module detects the transition edge position of the compensated sampled data, that is, it detects the phase error between the compensated sampled data and the sampled clock signal, in order to generate a phase error signal. Using a phase interpolator, the phase of the sampled clock signal is adjusted based on the phase error signal, generating a sampled clock signal with arbitrarily fine phase among multi-phase clocks. Thus, under normal conditions, without changing the frequency of the reference clock, continuous fine-tuning of the phase interpolation is equivalent to adjusting the frequency, allowing tracking of minute frequency shifts in the input signal. Furthermore, by performing oversampling and digital equalization internally within the clock data recovery circuit, and by forcibly setting the adjacent phase intervals of N reference clock signals, the interval between adjacent sampling points is sufficiently small to determine whether the edge is leading or lagging, and a sufficient number of sampling points are provided to fit linear edges and accurately calculate the edge slope, thereby distinguishing subtle high-frequency attenuation even under noise. In some embodiments, the phase error is detected based on the compensated sampled data, and the phase of the sampled clock signal is adjusted so that the sampling points are aligned with the center of the eye diagram. For example, a Bang-Bang phase detector can be used to detect the position of the transition edge in the compensated sampled data. If the transition edge occurs before the sampling point, the phase interpolator lags the phase; if the transition edge occurs after the sampling point, the phase interpolator leads the phase. In some embodiments, the phase adjustment step size for the capture mode can be set to 1 ps, and the phase adjustment step size for the tracking mode can be set to 0.2 ps. This helps to adapt to the different characteristics of the capture and tracking modes.

[0040] Continue reading Figure 1A dual-mode locking decision module is used to determine whether the input serial data is stably locked based on the edge slope signal and the phase error signal in capture mode, and to determine whether the lock is lost based on the phase error signal in tracking mode. This enables automatic switching between capture and tracking modes, optimizing loop dynamic performance. A data decision unit uses the optimal phase clock to decide on the compensated data and outputs the recovered parallel data. Thus, stable locking is determined based on a combination of the phase error signal and the edge slope signal. For example, the dual locking criteria are: the absolute value of the phase error for 1024 consecutive transition edges is less than ±1 / 16 UI; and the edge slope fluctuation for 1024 consecutive UIs is less than ±5%. Stable locking is only determined when both conditions are met simultaneously. Thus, by requiring a statistical judgment based on 1024 consecutive transition edges for the lock criterion, if the statistical length is too small, such as 128 or 256, random jitter and instantaneous channel noise may cause short-term phase attainment, resulting in false lock. This leads to temporary phase alignment but large edge slope fluctuations, insufficient high-frequency compensation, and the eye diagram not fully opening, ultimately causing the system's bit error rate to exceed the standard. Furthermore, if the statistical length is greater than 1024, the lock determination may take too long, resulting in substandard synchronization efficiency in burst transmission scenarios. Therefore, by setting 1024 transition edges, the maximum sliding window length of the tracking mode can be matched, the hardware register array can be reused without adding storage circuitry, and the lock reliability and chip area are balanced. In addition, with the second judgment, namely the slope fluctuation threshold, a lock is only determined when both phase and slope conditions are met simultaneously for 1024 consecutive edges, overcoming the defect of traditional CDR relying solely on phase locking, which results in the eye diagram not opening. Thus, by monitoring the absolute value of the phase error and the edge slope fluctuation, it can be determined whether the CDR has successfully locked the frequency of the input serial data, that is, whether it has successfully recovered the clock signal frequency of the clock domain on the transmitting side. When the absolute value of the phase error is small and the edge slope fluctuation is small, it indicates that the lock is successful; otherwise, the lock is unsuccessful, and it is necessary to continue to try to capture and continuously extract the edge slope signal. If the lock is successful, it automatically switches to tracking mode, continuously monitors the channel attenuation and phase error, and determines whether the lock has been lost. If the lock has not been lost, it remains in tracking mode and continuously monitors the phase error signal; otherwise, it re-enters capture mode. Because both tracking mode and capture mode are performed internally by the CDR, the participation of the CDR's front-end or back-end circuitry is not required. The CDR can be integrated as a module into the transceiver or signal receiving side, making it convenient to deploy in various transceivers, interface chips, and other scenarios. Finally, through data decision output, the compensated sampled data is judged, and the optimal phase clock is used to judge the compensated data, outputting the recovered serial data.

[0041] In short, Figure 1The clock data recovery method shown eliminates the need for multi-stage equalizers in the pre-amplifier circuit, completely removing the pre-amplifier CTLE and DFE circuits, resulting in reduced chip area, lower power consumption, and significantly reduced hardware overhead. By integrating a circuit structure with adaptive channel high-frequency attenuation compensation within the clock data recovery circuit, and utilizing multiphase oversampling and digital weighted compensation techniques, all compensation and control logic is digital, unaffected by PVT variations, eliminating the need for complex analog calibration circuits and significantly reducing design complexity. Phase tracking and amplitude compensation are implemented in the same loop, accelerating convergence time and significantly improving convergence speed. The method eliminates mutual interference between the equalizer and CDR loops, making system locking more stable and reliable. The adaptive algorithm for edge slope estimation has a natural negative feedback self-limiting mechanism, avoiding the positive feedback runaway phenomenon of "overcompensation - misjudgment leading to further undercompensation - further overcompensation" in traditional architectures. Even if overcompensation occurs, the system will automatically adjust back to the optimal state. The dual locking criteria of phase error and edge slope can accurately distinguish between true and false locking, avoiding the problem of premature locking before the eye diagram is fully open. The design has been optimized in terms of complexity, convergence speed, and tracking accuracy. Only a PLL with frequency locking function is needed to achieve phase tracking based on the frequency of the input signal, solving problems such as overcompensation runaway and locking instability. Phase tracking and high-frequency attenuation compensation are simultaneously implemented inside the clock data recovery circuit.

[0042] See Figure 1 In one possible implementation, N is 8, and the N reference clock signals are 8 reference clock signals, with the adjacent phase interval of the 8 reference clock signals fixed at one-eighth of the unit time interval. Thus, by setting the number of N, for example, to 8 or 16, the scale of logic devices such as phase interpolators, parallel sampling registers, and multiplexer digital gates can be controlled, avoiding excessive digital dynamic power consumption, thereby controlling the overall scale of the analog circuit. This achieves complete coverage of both the rising and falling edges of the signal while controlling the calculation error of the linear fitting edge within an acceptable range, and simultaneously controlling the power consumption of the digital hardware. Generally, when N is set to 4, that is, using 4-phase sampling, it is possible to roughly determine whether the edge is leading or lagging. When N is set to 16, a relatively larger scale of logic devices is required. When N is set to 8, which means 8-phase sampling is used, and the 8-phase clock signal is evenly divided into a unit time interval, that is, the interval between adjacent phases is one-eighth of the unit time interval, which corresponds to 45 degrees. In this way, the rising edge and falling edge of the signal can be completely covered by 8 sampling points, while controlling the calculation error of the linear fitting edge to within 5%, and realizing controllable incremental power consumption of digital hardware.

[0043] See Figure 1In one possible implementation, the edge slope signal indicates the amplitude difference between adjacent sampling points of a series of consecutive sampling points within the same sliding window in the parallel sampled data. This amplitude difference is used to calculate the edge slope fluctuation and the average edge slope of the signal. Thus, the edge slope estimation module obtains the average edge slope of the signal by calculating the amplitude difference between adjacent sampling points. The channel high-frequency attenuation is estimated based on a preset slope-attenuation correspondence table. This preset slope-attenuation correspondence table is obtained through calibration during the production process of the clock data recovery circuit or after it leaves the factory. For example, during testing, the corresponding curve can be measured by artificially applying high-frequency attenuation. In practice, the current high-frequency attenuation can be deduced from the edge slope calculated from the sampling point data. The edge slope estimation module calculates the average edge slope of the signal by averaging within a sliding window; that is, the edge slope signal indicates the amplitude difference between adjacent sampling points of a series of consecutive sampling points within the same sliding window in the parallel sampled data.

[0044] In some embodiments, the average edge slope of the signal is used to estimate the high-frequency attenuation of the channel based on a preset slope-attenuation correspondence table, wherein the preset slope-attenuation correspondence table is obtained through calibration during the manufacturing process of the clock data recovery circuit or after it leaves the factory. Thus, during testing, the corresponding curve can be measured by artificially applying high-frequency attenuation. In practice, the current high-frequency attenuation can be deduced from the edge slope calculated based on the sampling point data.

[0045] In some embodiments, the dual-mode lock-in decision module determines whether the input serial data is stably locked based on the edge slope signal and the phase error signal in the capture mode. This includes: when the phase error signal indicates that the absolute value of the phase error over M consecutive transition edges is less than a first phase error threshold, and the edge slope signal indicates that the edge slope fluctuation over M consecutive unit time intervals is less than a slope fluctuation threshold, the input serial data is determined to be stably locked, and the tracking mode is switched; otherwise, the edge slope signal is continuously extracted. Here, M is the upper limit of the number of consecutive sampling points in the tracking mode. Thus, assuming M is 1024, the dual-lock-in criterion is: the absolute value of the phase error over 1024 consecutive transition edges is less than ±1 / 16 UI; and the edge slope fluctuation over 1024 UIs is less than ±5%. Only when both conditions are met simultaneously is a stable lock-in determined. Thus, by requiring a statistical judgment based on 1024 consecutive transition edges for the lock criterion, if the statistical length is too small, such as 128 or 256, random jitter and transient channel noise may cause short-term phase alignment, resulting in false locks. This leads to temporary phase alignment but large fluctuations in edge slope, insufficient high-frequency compensation, and an incomplete eye diagram, ultimately causing the system's bit error rate to exceed the limit. Furthermore, if the statistical length is greater than 1024, the lock determination may take too long, resulting in substandard synchronization efficiency in burst transmission scenarios. By setting M as the upper limit of the number of consecutive sampling points in the tracking mode, for example, if the consecutive sampling points in the tracking mode are in the range of 256 to 1024, the upper limit is 1024. By setting 1024 transition edges, the maximum sliding window length of the tracking mode can be matched, the hardware register array can be reused without adding storage circuitry, and the lock reliability and chip area are balanced. Furthermore, a second decision, namely the slope fluctuation threshold, is employed. Locking is only confirmed when 1024 consecutive edges simultaneously satisfy both phase and slope conditions. This mechanism overcomes the deficiency of traditional CDRs that rely solely on phase locking, resulting in an unopened eye diagram. Thus, by monitoring the absolute value of the phase error and the edge slope fluctuation, it can be determined whether the CDR has successfully locked the frequency of the input serial data, i.e., whether it has successfully recovered the clock signal frequency of the transmitting side's clock domain. When the absolute value of the phase error is small and the edge slope fluctuation is small, locking is successful; otherwise, locking is unsuccessful, and further attempts to capture are needed, continuously extracting the edge slope signal. If locking is successful, it automatically switches to tracking mode, continuously monitoring channel attenuation and phase error, and determining whether lock has been lost. If lock has not been lost, it remains in tracking mode, continuously monitoring the phase error signal; otherwise, it re-enters capture mode. Because both tracking and capture modes are performed internally within the CDR, no involvement of the CDR's pre- or post-stage circuitry is required.CDR can be integrated as a module into the transceiver or signal receiver, facilitating deployment in various transceivers, interface chips, and other scenarios. Finally, through data decision output, the compensated sampled data is evaluated, and the optimal phase clock is used to determine the correct value, outputting the recovered serial data.

[0046] In some embodiments, the dual-mode locking decision module determines whether the lock has been lost based on the phase error signal in the tracking mode. This includes: when the phase error signal indicates that the absolute value of the phase error exceeds a second phase error threshold for more than a preset number of transition edges in S consecutive transition edges, a lock loss is determined and the system switches to the capture mode; otherwise, the system continues to monitor the phase error signal in the tracking mode. Here, S is the lower limit of the number of consecutive sampling points in the tracking mode. For example, if the consecutive sampling points are in the range of 256 to 1024 in the tracking mode, the upper limit is 1024 and the lower limit is 256. For example, if the absolute value of the phase error exceeds ±1 / 8 UI for more than 32 of the 256 consecutive transition edges, a lock loss is determined, and the system re-enters the capture mode. By setting S as the lower limit of the number of consecutive sampling points in the tracking mode, the minimum sliding window length of the tracking mode can be matched, balancing locking reliability and chip area.

[0047] Figure 2 This is a schematic diagram of a clock data recovery circuit provided in an embodiment of this application. Figure 2As shown, the clock data recovery circuit 200 includes: a multiphase clock generator 210, a multi-channel sampler 220, an edge slope estimation module 230, a digital weighted compensation module 240, a phase detection and adjustment module 250, and a dual-mode lock-in decision module 260. The multiphase clock generator 210 is used to lock the reference frequency of the input serial data and, based on the locked reference frequency, generate N reference clock signals. The adjacent phase interval of the N reference clock signals is fixed to one-Nth of the unit time interval associated with the input serial data, where N is an even number not less than 4. The multi-channel sampler 220 is used to oversample the input serial data N times using the sampling clock signals to obtain parallel sampled data. The sampling clock signals are generated using the N reference clock signals as input references and through adjacent phase weighted interpolation. The edge slope estimation module 230 is used to extract the edge slope signal from the parallel sampled data to estimate the channel high-frequency attenuation. A digital weighted compensation module 240 is used to compensate the parallel sampled data for high-frequency attenuation based on the channel high-frequency attenuation, thereby obtaining compensated sampled data. A phase detection and adjustment module 250 is used to detect the transition edge position of the compensated sampled data to generate a phase error signal, and to adjust the phase of the sampling clock signal based on the phase error signal. A dual-mode lock-on decision module 260 is used to determine whether the input serial data is stably locked based on the edge slope signal and the phase error signal in capture mode, and to determine whether the lock has been lost based on the phase error signal in tracking mode.

[0048] Figure 2The clock data recovery circuit 200 shown eliminates the need for multi-stage equalizers in the pre-amplifier circuit, completely removing the pre-amplifier CTLE and DFE circuits, resulting in reduced chip area, lower power consumption, and significantly reduced hardware overhead. By integrating a circuit structure with adaptive channel high-frequency attenuation compensation within the clock data recovery circuit, and utilizing multiphase oversampling and digital weighted compensation techniques, all compensation and control logic is digital, unaffected by PVT variations, eliminating the need for complex analog calibration circuits, and significantly reducing design complexity. Phase tracking and amplitude compensation are implemented in the same loop, accelerating convergence time and significantly improving convergence speed. The mutual interference between the equalizer and CDR loops is eliminated, making system locking more stable and reliable. The adaptive algorithm for edge slope estimation has a natural negative feedback self-limiting mechanism, avoiding the positive feedback runaway phenomenon of "overcompensation - misjudgment leading to further undercompensation - further overcompensation" in traditional architectures. Even if overcompensation occurs, the system will automatically adjust back to the optimal state. The dual locking criteria of phase error and edge slope can accurately distinguish between true and false locking, avoiding the problem of premature locking before the eye diagram is fully open. The design has been optimized in terms of complexity, convergence speed, and tracking accuracy. Only one frequency-locking PLL is needed to achieve phase tracking based on the frequency of the input signal, solving problems such as overcompensation runaway and locking instability. Phase tracking and high-frequency attenuation compensation are simultaneously implemented inside the clock data recovery circuit 200.

[0049] Figure 3 This is a schematic diagram illustrating the switching between acquisition mode and tracking mode of a dual-mode locking decision module provided in an embodiment of this application. Step S310: In acquisition mode, the dual-mode locking decision module determines that locking has failed based on the edge slope signal and phase error signal, and continues to attempt acquisition. Step S312: In acquisition mode, the dual-mode locking decision module determines stable locking based on the edge slope signal and phase error signal, and switches to tracking mode. Step S314: In tracking mode, the dual-mode locking decision module determines that there has been no loss of lock based on the phase error signal, and continues to monitor channel attenuation and phase error in tracking mode. Step S316: In tracking mode, the dual-mode locking decision module determines that the lock has been lost based on the phase error signal, and re-enters acquisition mode. Thus, through... Figure 3The closed-loop logic chain between the various steps shown enables automatic switching between capture and tracking modes, optimizing loop dynamic performance. A data decision unit uses the optimal phase clock to determine the compensated data and outputs the recovered parallel data. Thus, by monitoring the absolute value of the phase error and edge slope fluctuations, it can be determined whether the CDR has successfully locked the frequency of the input serial data, i.e., whether it has successfully recovered the clock signal frequency of the transmitting side's clock domain. When the absolute value of the phase error is small and the edge slope fluctuation is small, the lock is successful; otherwise, the lock is unsuccessful, and capture attempts need to continue, continuously extracting the edge slope signal. If the lock is successful, it automatically switches to tracking mode, continuously monitoring channel attenuation and phase error, and determining whether the lock has been lost. If the lock has not been lost, it remains in tracking mode, continuously monitoring the phase error signal; otherwise, it re-enters capture mode. Because both tracking and capture modes are performed internally within the CDR, no pre- or post-stage circuitry of the CDR is required. The CDR can be integrated as a module into the transceiver or signal receiving side, facilitating deployment in various transceivers, interface chips, and other scenarios. Finally, the compensated sampled data is judged through data decision output, and the optimal phase clock is used to judge the compensated data to output the recovered serial data.

[0050] Figure 4 This is a schematic diagram of a clock data recovery circuit in a multi-channel application scenario provided by an embodiment of this application. Figure 4 As shown, the clock data recovery method and circuit provided in the specific embodiments of this application support multi-channel application scenarios, such as multi-channel SerDes and high-bandwidth memory (HBM). By sharing the same 8-phase reference multi-phase clock, only one main PLL is set up inside the chip. Figure 4 The main phase-locked loop (410) and the 8-phase ring voltage-controlled oscillator (VCO) are also known as... Figure 4 The multi-channel shared 8-phase ring voltage-controlled oscillator 820, after power-on, completes global reference frequency self-test and locks, and distributes the 8 multi-phase clocks with a phase interval of 1 / 8UI to the CDRs of all channels, such as... Figure 4 The example shown includes the CDRs for channel A, channel B, channel C, and channel D. This enables support for multi-channel application scenarios.

[0051] See Figures 1 to 4In one possible implementation, N is 8, and the N reference clock signals are 8 reference clock signals, with the adjacent phase interval of the 8 reference clock signals fixed at one-eighth of the unit time interval. Thus, by setting the number of N, for example, to 8 or 16, the scale of logic devices such as phase interpolators, parallel sampling registers, and multiplexer digital gates can be controlled, avoiding excessive digital dynamic power consumption, thereby controlling the overall scale of the analog circuit. This achieves complete coverage of both the rising and falling edges of the signal while controlling the calculation error of the linear fitting edge within an acceptable range, and simultaneously controlling the power consumption of the digital hardware. Generally, when N is set to 4, that is, using 4-phase sampling, it is possible to roughly determine whether the edge is leading or lagging. When N is set to 16, a relatively larger scale of logic devices is required. When N is set to 8, which means 8-phase sampling is used, and the 8-phase clock signal is evenly divided into a unit time interval, that is, the interval between adjacent phases is one-eighth of the unit time interval, which corresponds to 45 degrees. In this way, the rising edge and falling edge of the signal can be completely covered by 8 sampling points, while controlling the calculation error of the linear fitting edge to within 5%, and realizing controllable incremental power consumption of digital hardware.

[0052] See Figures 1 to 4 In one possible implementation, N is 16, and the N reference clock signals are 16 reference clock signals, with the adjacent phase interval of the 16 reference clock signals fixed at 1 / 16th of the unit time interval. This fully covers both the rising and falling edges of the signal.

[0053] See Figures 1 to 4In one possible implementation, the multiphase clock generator includes a phase-locked loop (PLL) circuit and a phase interpolator. The PLL circuit includes a multiphase ring voltage-controlled oscillator (VCO) for generating the N reference clock signals with uniformly distributed phases. The phase interpolator uses the N reference clock signals as input references and generates the sampled clock signal through weighted interpolation of adjacent phases. Thus, the optimized design of the multiphase clock generator adapts to the multi-coupling design constraints of the entire closed-loop control chain. Compared to other multiphase clock generation methods, such as delay-locked loops (DLLs), LC-VCOs, pre-phase interpolation, and shift registers, these existing multiphase clock generation methods have various drawbacks when integrated within the clock data recovery circuit. For example, the architecture of a delay-locked loop cannot independently adjust the overall frequency of the reference clock over a large range, and the frequency modulation process becomes complex when a low reference frequency or scale distortion is detected. For example, the inductor in an inductor-capacitor voltage-controlled oscillator occupies a large area, which is not conducive to multi-channel sharing and overhead reduction. Furthermore, multi-stage pre-amplifier phase interpolation and shift registers introduce phase nonlinearity and jitter accumulation, disrupting the 8-phase uniform indexing and leading to a significant increase in edge slope calculation error. Also, injection-locked oscillators are only usable in a narrow frequency domain and cannot be compatible with high-frequency compensation across the entire 0 to 15 dB range. Therefore, the multiphase clock generator includes a phase-locked loop circuit and a phase interpolator. The phase-locked loop circuit includes a multiphase ring voltage-controlled oscillator for generating the N reference clock signals with uniform phase distribution. The phase interpolator uses the N reference clock signals as input references and generates the sampled clock signal through weighted interpolation of adjacent phases. Thus, assuming N is 8, a multi-phase generation scheme using an 8-stage differential ring VCO paired with a main PLL can achieve continuous global frequency modulation and stable 1 / 8 UI phase output under a single set of analog hardware. It also boasts advantages such as low hardware overhead and low matching edge slope estimation loss. Furthermore, it meets the collaborative requirements of a unified factory calibration mapping table, multi-channel global shared reference, and hierarchical clock adjustment architecture. This achieves normal locking of the reference multi-phase clock, independent phase interpolation tracking for each channel, replacement of the pre-amplifier CTLE / DFE with a pure digital FIR, and dual slope locking decision.

[0054] In some embodiments, the phase-locked loop circuit includes a phase detector, a charge pump, and a loop filter. The multiphase ring voltage-controlled oscillator is an 8-phase ring voltage-controlled oscillator used to generate an 8-phase uniformly distributed reference clock, with each phase clock interval being one-eighth of the unit time interval. Thus, assuming N is 8, using an 8-stage differential ring VCO combined with a main PLL for multiphase generation, continuous global frequency modulation and stable 1 / 8 UI phase output can be achieved with a single set of analog hardware. It also has the advantages of low hardware overhead and low matching edge slope estimation loss, and can meet the collaborative requirements of a unified factory calibration mapping table, multi-channel global shared reference, and hierarchical clock adjustment architecture. This achieves normal locking of the reference multiphase clock, independent phase interpolation tracking for each channel, replacement of the pre-amplifier CTLE / DFE with a pure digital FIR, and dual slope locking decision.

[0055] See Figures 1 to 4 In one possible implementation, the phase error signal indicates whether the edge position of the compensated sampled data is leading or lagging relative to the sampling point of the sampling clock signal. The phase error signal is used to adjust the phase of the sampling clock signal via a phase interpolator. Thus, under normal conditions, without changing the frequency of the reference clock, continuous fine-tuning of the phase interpolation is equivalent to adjusting the frequency, allowing tracking of minute frequency shifts in the input signal. Furthermore, by performing oversampling and digital equalization internally within the clock data recovery circuit, and by forcibly setting the adjacent phase intervals of N reference clock signals, the interval between adjacent sampling points is made sufficiently small to determine whether the edge is leading or lagging. This provides enough sampling points to fit linear edges and accurately calculate edge slopes, thereby enabling the differentiation of subtle high-frequency attenuation even under noise.

[0056] See Figures 1 to 4 In one possible implementation, the edge slope signal indicates the amplitude difference between adjacent sampling points of a consecutive plurality of sampling points within the same sliding window in the parallel sampled data. This amplitude difference is used to calculate the edge slope fluctuation and the average edge slope of the signal. Thus, the edge slope estimation module calculates the average edge slope of the signal by averaging through a sliding window; that is, the edge slope signal indicates the amplitude difference between adjacent sampling points of a consecutive plurality of sampling points within the same sliding window in the parallel sampled data. In some embodiments, the sliding window size is 128 to 1024 sampling points. The formula for calculating the edge slope is: SlopeAVG = (1 / Num) × Σ|D(i+1) D(i)| / Δt. Where D(i+1) is the amplitude value of the (i+1)th sampling point, D(i) is the amplitude value of the ith sampling point, Δt is the time interval between adjacent sampling points (e.g., 5 picoseconds), and Num is the number of sampling points within the sliding window. The number of sampling points within the sliding window, i.e., the number of consecutive sampling points, is a first number (e.g., 128) in capture mode and a second number (e.g., 256) in tracking mode. By setting different sliding window sizes for capture and tracking modes, a constraint on convergence speed is provided in capture mode. This requires quickly calculating the average edge slope of the signal, updating the equalization compensation coefficients, and rapidly reducing phase errors. Therefore, a relatively small sliding window avoids lengthening the lock-in time, helping to meet the fast lock-in requirements of bursty data transmission. Generally, the first number is set to 128, meaning the sliding window size in capture mode is 128 sampling points. This achieves a lower limit balance between lock-in speed and noise suppression, avoiding drastic slope fluctuations and frequent jumps in the equalization coefficients caused by noise, thus contributing to a stable convergence loop. Furthermore, after locking in acquisition mode, it automatically switches to tracking mode. By setting a relatively large sliding window, mean filtering can be performed within a larger window, effectively suppressing small channel fluctuations and random jitter, smoothing the slope calculation results, and avoiding repeated opening and closing of the eye diagram caused by frequent jitter of the equalization coefficient. Generally, the second number is set to 256 to 1024, that is, the size of the sliding window in tracking mode is 256 to 1024 sampling points. Setting the upper limit to 1024 helps to avoid slow loop response speed, which could lead to failure to update the compensation coefficient in time when the channel changes abruptly. Moreover, the second number is configured according to the system noise intensity. That is, the number of consecutive sampling points in the tracking mode is in the range of 256 to 1024, which can be flexibly configured according to the system noise intensity, helping to adapt to different optical modules and backplane channel noise environments.

[0057] In some embodiments, the average edge slope of the signal is used to estimate the high-frequency attenuation of the channel based on a preset slope-attenuation correspondence table, wherein the preset slope-attenuation correspondence table is obtained through calibration during the manufacturing process of the clock data recovery circuit or after it leaves the factory. Thus, the weighting coefficients are adaptively adjusted according to the high-frequency attenuation, and the N sampled data are weighted and summed to compensate for the high-frequency attenuation of the channel.

[0058] In some embodiments, the digital weighted compensation module includes a 5-tap symmetric phase-domain differential finite impulse response (FIR) filter. The digital weighted compensation module is used to determine the main tap coefficients, first-order high-frequency compensation coefficients, and second-order high-frequency compensation coefficients of the 5-tap symmetric phase-domain differential finite impulse response filter based on the channel high-frequency attenuation using a preset table of compensation coefficients, slopes, and attenuation amounts. It also performs channel high-frequency attenuation compensation on the parallel sampled data using the 5-tap symmetric phase-domain differential finite impulse response filter. Thus, using the 5-tap symmetric phase-domain differential finite impulse response filter, the DC gain can be kept close to 1, only boosting the high-frequency components. The output expression of this filter is: Y(k) = w0 × D(k) + w1 × (D(k+1) - D(k-1)) / 2 + w2 × (D(k+2) - D(k-2)) / 4. In the expression for this filter, w0 is the main tap coefficient, fixed at 1; w1 is the first-order high-frequency compensation coefficient; and w2 is the second-order high-frequency compensation coefficient. Furthermore, the ratio of w2 to w1 is approximately 2:1 to minimize phase nonlinearity. The maximum allowable value for w1 is 4.5, and the maximum allowable value for w2 is 9.0, enabling continuous high-frequency compensation from 0 to 15 dB. Additionally, the coefficient update step size is 0.02 in capture mode and 0.005 in tracking mode, which helps adapt to the different characteristics of capture and tracking modes. Moreover, the 5-tap symmetric phase-domain differential finite impulse response filter not only achieves lossless low-frequency component processing and enhances high-frequency components, but also adapts to the multi-coupling design constraints of the entire closed-loop control chain. Compared to first-order differential finite impulse response (FIR) filters, which can only achieve small-amplitude high-frequency compensation and cannot cover the high-frequency attenuation compensation requirements of the entire channel range, high-order multi-tap FIR filters increase circuit area and power consumption. Furthermore, the adaptive update process of infinite impulse response (IIR) filters is prone to oscillations and can disrupt the tracking stability of the CDR loop. Here, a 5-tap symmetric phase domain differential finite impulse response filter is used. By limiting the ratio of the second-order high-frequency compensation coefficient w2 to the first-order high-frequency compensation coefficient w1 to approximately 2:1, the phase nonlinearity distortion introduced by the differentiation operation is effectively offset, while ensuring the phase error detection accuracy under 8-phase oversampling. Through this dedicated weight constraint (limiting the ratio of the second-order high-frequency compensation coefficient w2 to the first-order high-frequency compensation coefficient w1 to approximately 2:1), the tap delay interval of the 5-tap symmetric phase domain differential finite impulse response filter is natively matched to the fixed division of the 8-phase clock, i.e., one-eighth of the unit time interval, without the need for additional delay units. Furthermore, the filter adaptive coefficient update step size and the preset slope and attenuation correspondence table of the factory calibration are all based on the filter characteristic matching design, and are also adapted to the adaptive logic of dual-mode acquisition and tracking.Thus, the digital weighted compensation module is used to determine the main tap coefficients, first-order high-frequency compensation coefficients, and second-order high-frequency compensation coefficients of the 5-tap symmetric phase domain differential finite impulse response filter based on the channel high-frequency attenuation using a preset table of compensation coefficients, slopes, and attenuation amounts, and to perform channel high-frequency attenuation compensation on the parallel sampled data through the 5-tap symmetric phase domain differential finite impulse response filter.

[0059] In some embodiments, the number of consecutive sampling points is a first number in the capture mode and a second number in the tracking mode, where the first number is less than the second number, and the second number is configured based on the system noise intensity. Thus, the number of sampling points within the sliding window, i.e., the number of consecutive sampling points, is the first number, such as 128, in capture mode and the second number, such as 256, in tracking mode. By setting different sliding window sizes for capture and tracking modes, a constraint on convergence speed is provided in capture mode. This requires rapid calculation of the average edge slope of the signal, updating the equalization compensation coefficients, and quickly reducing phase errors. Therefore, a relatively small sliding window can avoid lengthening the lock-in time, helping to meet the fast lock-in requirements of bursty data transmission. Generally, the first number is set to 128, meaning the sliding window size in capture mode is 128 sampling points. This achieves a lower limit balance between lock-in speed and noise suppression, avoiding drastic slope fluctuations and frequent jumps in the equalization coefficients caused by noise, thus contributing to a stable convergence loop. Furthermore, after locking in acquisition mode, it automatically switches to tracking mode. By setting a relatively large sliding window, mean filtering can be performed within a larger window, effectively suppressing small channel fluctuations and random jitter, smoothing the slope calculation results, and avoiding repeated opening and closing of the eye diagram caused by frequent jitter of the equalization coefficient. Generally, the second number is set to 256 to 1024, that is, the size of the sliding window in tracking mode is 256 to 1024 sampling points. Setting the upper limit to 1024 helps to avoid slow loop response speed, which could lead to failure to update the compensation coefficient in time when the channel changes abruptly. Moreover, the second number is configured according to the system noise intensity. That is, the number of consecutive sampling points in the tracking mode is in the range of 256 to 1024, which can be flexibly configured according to the system noise intensity, helping to adapt to different optical modules and backplane channel noise environments.

[0060] In some embodiments, the dual-mode lock-in decision module is used to determine whether the input serial data is stably locked based on the edge slope signal and the phase error signal in the capture mode. This includes: when the phase error signal indicates that the absolute value of the phase error over M consecutive transition edges is less than a first phase error threshold and the edge slope signal indicates that the edge slope fluctuation over M consecutive unit time intervals is less than a slope fluctuation threshold, determining that the input serial data is stably locked and switching to the tracking mode; otherwise, continuously extracting the edge slope signal, where M is the upper limit of the number of consecutive sampling points in the tracking mode. Thus, assuming M is 1024, the dual-lock-in criterion is: the absolute value of the phase error over 1024 consecutive transition edges is less than ±1 / 16 UI; and the edge slope fluctuation over 1024 UIs is less than ±5%. Only when both conditions are met simultaneously is it determined to be a stable lock-in. Thus, by requiring a statistical judgment based on 1024 consecutive transition edges for the lock criterion, if the statistical length is too small, such as 128 or 256, random jitter and transient channel noise may cause short-term phase alignment, resulting in false locks. This leads to temporary phase alignment but large fluctuations in edge slope, insufficient high-frequency compensation, and an incomplete eye diagram, ultimately causing the system's bit error rate to exceed the limit. Furthermore, if the statistical length is greater than 1024, the lock determination may take too long, resulting in substandard synchronization efficiency in burst transmission scenarios. By setting M as the upper limit of the number of consecutive sampling points in the tracking mode, for example, if the consecutive sampling points in the tracking mode are in the range of 256 to 1024, the upper limit is 1024. By setting 1024 transition edges, the maximum sliding window length of the tracking mode can be matched, the hardware register array can be reused without adding storage circuitry, and the lock reliability and chip area are balanced. Furthermore, a second decision, namely the slope fluctuation threshold, is employed. Locking is only confirmed when 1024 consecutive edges simultaneously satisfy both phase and slope conditions. This mechanism overcomes the deficiency of traditional CDRs that rely solely on phase locking, resulting in an unopened eye diagram. Thus, by monitoring the absolute value of the phase error and the edge slope fluctuation, it can be determined whether the CDR has successfully locked the frequency of the input serial data, i.e., whether it has successfully recovered the clock signal frequency of the transmitting side's clock domain. When the absolute value of the phase error is small and the edge slope fluctuation is small, locking is successful; otherwise, locking is unsuccessful, and further attempts to capture are needed, continuously extracting the edge slope signal. If locking is successful, it automatically switches to tracking mode, continuously monitoring channel attenuation and phase error, and determining whether lock has been lost. If lock has not been lost, it remains in tracking mode, continuously monitoring the phase error signal; otherwise, it re-enters capture mode. Because both tracking and capture modes are performed internally within the CDR, no involvement of the CDR's pre- or post-stage circuitry is required.CDR can be integrated as a module into the transceiver or signal receiver, facilitating deployment in various transceivers, interface chips, and other scenarios. Finally, through data decision output, the compensated sampled data is evaluated, and the optimal phase clock is used to determine the correct value, outputting the recovered serial data.

[0061] In some embodiments, the dual-mode locking decision module is used to determine whether a lock has been lost based on the phase error signal in the tracking mode, including: when the phase error signal indicates that the absolute value of the phase error of more than a preset number of transition edges in S consecutive transition edges exceeds a second phase error threshold, determining a lock loss and switching to the capture mode; otherwise, maintaining the tracking mode and continuously monitoring the phase error signal, where S is the lower limit of the number of consecutive sampling points in the tracking mode. For example, if the consecutive sampling points in the tracking mode are in the range of 256 to 1024, then the upper limit is 1024 and the lower limit is 256. For example, if the absolute value of the phase error of more than 32 transition edges in 256 consecutive transition edges exceeds ±1 / 8 UI, then a lock loss is determined, and the capture mode is re-entered. By setting S as the lower limit of the number of consecutive sampling points in the tracking mode, the minimum sliding window length of the tracking mode can be matched, balancing locking reliability and chip area.

[0062] The methods and devices provided in this application are based on the same inventive concept. Since the principles by which the methods and devices solve problems are similar, the embodiments, implementation methods, examples, or methods of implementation of the methods and devices can be referred to each other, and repeated details will not be repeated. This application also provides a system comprising multiple computer devices, the structure of each computer device of which can refer to the structure of the computer devices described above. The functions or operations achievable by this system can refer to the specific implementation steps in the above method embodiments and / or the specific functions described in the above device embodiments, and will not be repeated here.

[0063] This application also provides a computer-readable storage medium storing computer instructions. When these computer instructions are executed on a computer device (such as one or more processors), they can implement the method steps described in the above method embodiments. The specific implementation of the above method steps by the processor of the computer-readable storage medium can refer to the specific operations described in the above method embodiments and / or the specific functions described in the above device embodiments, and will not be repeated here.

[0064] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. This application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Embodiments of this application can be implemented wholly or partially by software, hardware, firmware, or any other combination. When implemented in software, the above embodiments can be implemented wholly or partially as a computer program product. This application can take the form of a computer program product embodied on one or more computer-usable storage media containing computer-usable program code. The computer program product includes one or more computer instructions. When the computer program instructions are loaded or executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line) or wireless (e.g., infrared, wireless network communication, microwave, etc.) means. Computer-readable storage media can be any available medium that a computer can access, or a data storage device such as a server or data center that contains one or more sets of available media. Available media can be magnetic media (such as floppy disks, hard disks, and magnetic tapes), optical media, or semiconductor media. Semiconductor media can be solid-state drives, random access memory, flash memory, read-only memory, erasable programmable read-only memory, electrically erasable programmable read-only memory, registers, or any other suitable form of storage medium.

[0065] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. Each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The functions specified in one or more boxes. These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable apparatus for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0066] In the above embodiments, the descriptions of each embodiment have their own emphasis. Parts not described in detail in a certain embodiment can be referred to in the relevant descriptions of other embodiments. Obviously, those skilled in the art can make various modifications and variations to the embodiments of this application without departing from the spirit and scope of the embodiments of this application. The steps in the methods of the embodiments of this application can be adjusted in order, combined, or deleted according to actual needs; the modules in the systems of the embodiments of this application can be divided, combined, or deleted according to actual needs. If these modifications and variations of the embodiments of this application fall within the scope of the claims of this application and their equivalents, then this application also intends to include these modifications and variations.

Claims

1. A clock data recovery method, characterized in that, The clock data recovery method includes: A multiphase clock generator is used to lock the reference frequency of the input serial data, and based on the locked reference frequency, N reference clock signals are generated, wherein the adjacent phase interval of the N reference clock signals is fixed to one-Nth of the unit time interval associated with the input serial data, and N is an even number not less than 4. By using a multi-channel sampler and a sampling clock signal, the input serial data is oversampled N times to obtain parallel sampled data. The sampling clock signal is generated by using the N reference clock signals as input references and by adjacent phase weighted interpolation. The edge slope estimation module extracts the edge slope signal from the parallel sampling data to estimate the high-frequency attenuation of the channel. The parallel sampling data is compensated for by a digital weighted compensation module based on the channel high-frequency attenuation amount, thereby obtaining compensated sampling data. The phase detection and adjustment module detects the position of the transition edge of the compensated sampled data to generate a phase error signal, and adjusts the phase of the sampled clock signal based on the phase error signal. The dual-mode locking decision module determines whether to stably lock the input serial data based on the edge slope signal and the phase error signal in capture mode, and determines whether to lose lock based on the phase error signal in tracking mode.

2. The clock data recovery method according to claim 1, characterized in that, N is 8, and the N reference clock signals are 8 reference clock signals. The adjacent phase interval of the 8 reference clock signals is fixed to one-eighth of the unit time interval.

3. The clock data recovery method according to claim 1, characterized in that, The edge slope signal indicates the amplitude difference between adjacent sampling points of a series of consecutive sampling points within the same sliding window in the parallel sampling data, wherein the amplitude difference between adjacent sampling points of the series of consecutive sampling points is used to calculate the edge slope fluctuation and the average edge slope of the signal.

4. The clock data recovery method according to claim 3, characterized in that, The average edge slope of the signal is used to estimate the high-frequency attenuation of the channel based on a preset slope-attenuation correspondence table, wherein the preset slope-attenuation correspondence table is obtained through calibration during the production process of the clock data recovery circuit or after leaving the factory.

5. The clock data recovery method according to claim 3, characterized in that, The dual-mode lock-in decision module determines whether to stably lock the input serial data based on the edge slope signal and the phase error signal in the capture mode, including: When the phase error signal indicates that the absolute value of the phase error of M consecutive transition edges is less than the first phase error threshold and the edge slope signal indicates that the edge slope fluctuation of M consecutive unit time intervals is less than the slope fluctuation threshold, the input serial data is determined to be stably locked and the tracking mode is switched; otherwise, the edge slope signal is continuously extracted, where M is the upper limit of the number of consecutive sampling points in the tracking mode.

6. The clock data recovery method according to claim 5, characterized in that, The dual-mode locking decision module determines whether the lock has been lost based on the phase error signal in the tracking mode, including: When the phase error signal indicates that the absolute value of the phase error of more than a preset number of transition edges in S consecutive transition edges exceeds the second phase error threshold, it is determined that the lock is lost and the capture mode is switched; otherwise, the phase error signal is continuously monitored in the tracking mode, where S is the lower limit of the number of consecutive sampling points in the tracking mode.

7. A clock data recovery circuit, characterized in that, The clock data recovery circuit includes: A multiphase clock generator is used to lock a reference frequency for input serial data and, based on the locked reference frequency, generate N reference clock signals, wherein the adjacent phase interval of the N reference clock signals is fixed to one-Nth of the unit time interval associated with the input serial data, and N is an even number not less than 4. A multi-channel sampler is used to oversample the input serial data by N times using a sampling clock signal to obtain parallel sampled data, wherein the sampling clock signal is generated by using the N reference clock signals as input references and by adjacent phase weighted interpolation. An edge slope estimation module is used to extract the edge slope signal from the parallel sampling data in order to estimate the high-frequency attenuation of the channel. A digital weighted compensation module is used to perform channel high-frequency attenuation compensation on the parallel sampling data based on the channel high-frequency attenuation amount, thereby obtaining compensated sampling data. A phase detection and adjustment module is used to detect the position of the transition edge of the compensated sampled data in order to generate a phase error signal, and to adjust the phase of the sampled clock signal based on the phase error signal; The dual-mode locking decision module is used to determine whether to stably lock the input serial data based on the edge slope signal and the phase error signal in capture mode, and to determine whether to lose lock based on the phase error signal in tracking mode.

8. The clock data recovery circuit according to claim 7, characterized in that, N is 8, and the N reference clock signals are 8 reference clock signals. The adjacent phase interval of the 8 reference clock signals is fixed to one-eighth of the unit time interval.

9. The clock data recovery circuit according to claim 7, characterized in that, N is 16, and the N reference clock signals are 16 reference clock signals. The adjacent phase interval of the 16 reference clock signals is fixed to one-sixteenth of the unit time interval.

10. The clock data recovery circuit according to claim 7, characterized in that, The multiphase clock generator includes a phase-locked loop circuit and a phase interpolator. The phase-locked loop circuit includes a multiphase ring voltage-controlled oscillator for generating the N reference clock signals with uniformly distributed phases. The phase interpolator is used to generate the sampled clock signal by using the N reference clock signals as input references and by weighted interpolation of adjacent phases.

11. The clock data recovery circuit according to claim 10, characterized in that, The phase-locked loop circuit includes a phase detector, a charge pump, and a loop filter. The multiphase ring voltage-controlled oscillator is an 8-phase ring voltage-controlled oscillator used to generate an 8-phase uniformly distributed reference clock, and the clock interval of each phase is one-eighth of the unit time interval.

12. The clock data recovery circuit according to claim 7, characterized in that, The phase error signal indicates whether the position of the transition edge of the compensated sampled data is leading or lagging behind the sampling point of the sampling clock signal. The phase error signal is used to adjust the phase of the sampling clock signal through a phase interpolator.

13. The clock data recovery circuit according to claim 7, characterized in that, The edge slope signal indicates the amplitude difference between adjacent sampling points of a series of consecutive sampling points within the same sliding window in the parallel sampling data, wherein the amplitude difference between adjacent sampling points of the series of consecutive sampling points is used to calculate the edge slope fluctuation and the average edge slope of the signal.

14. The clock data recovery circuit according to claim 13, characterized in that, The average edge slope of the signal is used to estimate the high-frequency attenuation of the channel based on a preset slope-attenuation correspondence table, wherein the preset slope-attenuation correspondence table is obtained by calibration during the production process of the clock data recovery circuit or after it leaves the factory.

15. The clock data recovery circuit according to claim 14, characterized in that, The digital weighted compensation module includes a 5-tap symmetric phase domain differential finite impulse response (FIR) filter. The digital weighted compensation module is used to determine the main tap coefficients, first-order high-frequency compensation coefficients, and second-order high-frequency compensation coefficients of the 5-tap symmetric phase domain differential finite impulse response filter based on the channel high-frequency attenuation using a preset table of compensation coefficients, slopes, and attenuation amounts. It also performs channel high-frequency attenuation compensation on the parallel sampled data using the 5-tap symmetric phase domain differential finite impulse response filter.

16. The clock data recovery circuit according to claim 13, characterized in that, The number of consecutive sampling points is a first number in the capture mode and a second number in the tracking mode. The first number is less than the second number, and the second number is configured according to the system noise intensity.

17. The clock data recovery circuit according to claim 13, characterized in that, The dual-mode lock-in decision module is used to determine whether to stably lock the input serial data based on the edge slope signal and the phase error signal in the capture mode, including: When the phase error signal indicates that the absolute value of the phase error of M consecutive transition edges is less than the first phase error threshold and the edge slope signal indicates that the edge slope fluctuation of M consecutive unit time intervals is less than the slope fluctuation threshold, the input serial data is determined to be stably locked and the tracking mode is switched; otherwise, the edge slope signal is continuously extracted, where M is the upper limit of the number of consecutive sampling points in the tracking mode.

18. The clock data recovery circuit according to claim 17, characterized in that, The dual-mode locking decision module is used to determine whether the lock has been lost based on the phase error signal in the tracking mode, including: When the phase error signal indicates that the absolute value of the phase error of more than a preset number of transition edges in S consecutive transition edges exceeds the second phase error threshold, it is determined that the lock is lost and the capture mode is switched; otherwise, the phase error signal is continuously monitored in the tracking mode, where S is the lower limit of the number of consecutive sampling points in the tracking mode.

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