Real-time under-sampling and computation based wideband spectrum analysis system, method and apparatus

Abstract

The application discloses a kind of wideband spectrum analysis systems based on real-time undersampling and calculation, the system includes the following module: ADC sampling module includes two ADC units, each ADC unit includes the sampling submodule, low-noise amplifier and sample holder connected in turn, polyphase decomposition module is converted into parallel data using asynchronous FIFO to achieve serial data;Polyphase filter module completes filtering operation using serial multiply-accumulate method;IDFT module completes inverse discrete Fourier transform calculation using coprime factor algorithm in two stages;Cross-correlation module carries out cross-correlation operation to two-way data;Modulus module uses CORDIC module to obtain modulus value and output power spectrum;Two ADC units each output a way digital signal, respectively after polyphase decomposition module, polyphase filter module and IDFT module processing, input to cross-correlation module and carry out cross-correlation operation, cross-correlation operation result is input to modulus module, and power spectrum is output by modulus module.The application is suitable for radio spectrum monitoring and the like field.

Description

Technical Field

[0001] This invention relates to the field of radio broadband spectrum sensing technology, and in particular to a broadband spectrum analysis system, method and device based on real-time undersampling and calculation. Background Technology

[0002] Currently, with the rapid development of wireless communication technology and the increasing scarcity of spectrum resources, the occupancy of wireless frequency bands in fields such as radar, wireless communication, and electronic warfare is showing a continuous upward trend. Wideband spectrum detection, as a core technology of cognitive radio systems, requires real-time, dynamic scanning and monitoring of radio spectrum resources across a wide frequency band to obtain spectrum occupancy information and available frequency bands, supporting dynamic spectrum management and subsequent communication transmission. However, with the continuous expansion of the detection bandwidth, balancing rapid response, low hardware cost, and high detection accuracy in spectrum detection performance has become a major challenge.

[0003] Traditional broadband receiver solutions mainly include superheterodyne receivers, instantaneous frequency measurement receivers, compressed receivers, and channelized receivers. The most representative of these is the superheterodyne receiver, which utilizes the mixing principle, mixing the high-frequency signal with the radio frequency signal through a local oscillator to convert the high-frequency signal to a fixed intermediate frequency, which is then sampled and processed by an ADC. However, this solution suffers from problems such as slow detection speed, large device size, high power consumption, and significantly increased hardware costs when the detection range expands. It struggles to meet the demands of lightweight, portable, and high real-time applications, especially lacking the ability to quickly intercept transient and short-duration burst signals in non-cooperative electromagnetic environments.

[0004] To overcome the bottlenecks of high sampling rate and high data volume caused by Nyquist sampling, researchers have proposed spectrum detection schemes based on sub-Nyquist sampling, mainly divided into two categories: compressed sensing (CS) and coprime frequency undersampling. Compressed sensing theory utilizes the sparsity of signals in a specific transform domain to reconstruct signals through observations at rates far lower than the Nyquist rate. Its main architecture includes analog information converters (AIC), modulation-bandwidth converters (MWC), and multiple co-collection sampling (MCS). Although these methods reduce the amount of data, they have high requirements for signal sparsity and are complex and costly to implement, making them unsuitable for broadband spectrum detection in high-precision, dense signal environments.

[0005] Coprime frequency undersampling, proposed by Vaidyanathan et al., utilizes a parallel sub-sampling structure with two low-speed sampling rates, combined with digital signal processing methods such as polyphase filter banks and IDFT, to achieve broadband spectral analysis. This method requires only a low-speed ADC, significantly reducing the sampling rate and hardware cost, and demonstrates advantages in DOA estimation, beamforming, and spectrum analysis. However, existing coprime spectral analysis implementations suffer from the following main drawbacks:

[0006] (1) The processing delay is large, which cannot meet the real-time acquisition requirements of transient signals in scenarios such as electronic reconnaissance;

[0007] (2) Large-capacity cache is required, which increases storage resource consumption and system complexity;

[0008] (3) The efficiency is low, and it is difficult to achieve unblocked and efficient processing from ADC sampling to power spectrum output;

[0009] (4) On hardware platforms such as FPGA, traditional serial or non-optimized implementations result in high resource consumption, which limits actual engineering deployment.

[0010] In summary, while existing technologies can achieve low-cost, high-precision broadband spectrum detection, they struggle to simultaneously meet the requirements of true real-time performance (simultaneous acquisition and computation) and low latency. There is an urgent need for a pipelined real-time coprime spectrum analysis method based on an FPGA platform to support highly reliable and efficient spectrum sensing in non-cooperative blind detection scenarios. Summary of the Invention

[0011] This invention provides a broadband spectrum analysis system, method, and device based on real-time undersampling and calculation to solve the technical problems existing in the prior art.

[0012] The technical solution adopted by this invention to solve the technical problems existing in the prior art is as follows:

[0013] A broadband spectral analysis system based on real-time undersampling and computation includes, in sequence, an ADC sampling module, a multiphase decomposition module, a multiphase filtering module, an IDFT module, a cross-correlation module, and a modulus calculation module; wherein:

[0014] The ADC sampling module includes two ADC units. Each ADC unit includes a sampling submodule, a low-noise amplifier, and a sample-and-hold circuit connected in sequence. The sampling submodules of the two ADC units undersample the input signal at different sampling rates to capture electromagnetic signals from 300 MHz to 6 GHz. The low-noise amplifier is used to amplify the signal sampled by the sampling submodule. The sample-and-hold circuit is used to capture the voltage value of the input analog signal during analog-to-digital conversion and keep it constant during the conversion.

[0015] The multiphase decomposition module is used to convert serial data to parallel data using an asynchronous FIFO;

[0016] The multiphase filter module is used to perform filtering operations using a serial multiplication-accumulation method;

[0017] The IDFT module is used to perform the inverse discrete Fourier transform calculation in two stages using the coprime factor algorithm;

[0018] The cross-correlation module is used to perform cross-correlation calculations on two data streams;

[0019] The modulus module is used to calculate the modulus value using the CORDIC module and output the power spectrum;

[0020] Each of the two ADC units outputs a digital signal, which is processed by the polyphase decomposition module, the polyphase filtering module, and the IDFT module, respectively, and then input to the cross-correlation module for cross-correlation calculation. The cross-correlation calculation result is input to the modulus calculation module, which outputs the power spectrum.

[0021] Furthermore, the two ADC units are referred to as the first ADC unit and the second ADC unit, respectively; the polyphase decomposition module includes the first polyphase decomposition unit and the second polyphase decomposition unit; the polyphase filtering module includes the first polyphase filtering unit and the second polyphase filtering unit; the IDFT module includes the first IDFT unit and the second IDFT unit; and the cross-correlation module includes the first signal input terminal and the second signal input terminal.

[0022] The first ADC unit outputs a first digital signal, which is processed by the first polyphase decomposition unit, the first polyphase filtering unit and the first IDFT unit, and then input to the first signal input terminal of the cross-correlation module.

[0023] The second ADC unit outputs a second digital signal, which is processed by the second polyphase decomposition unit, the second polyphase filtering unit, and the second IDFT unit, and then input to the second signal input terminal of the cross-correlation module.

[0024] Furthermore, the system adopts a heterogeneous multi-core system-on-a-chip, which is formed by interconnecting and integrating a multi-core processor and a programmable gate array via an AXI bus.

[0025] This invention also provides a broadband spectrum analysis method based on real-time undersampling and calculation using the aforementioned broadband spectrum analysis system based on real-time undersampling and calculation. The method includes the following steps:

[0026] Step 1, set Let the reference sampling frequency be denoted as . The highest frequency of the actual signal. ≥2 Let M and N be integers and coprime. , , , Let the integer be: , ;

[0027] The input analog signal is sampled by two ADC units. Corresponding to sampling rates Coprime undersampling is performed to obtain two digital signals. , ;

[0028] Step 2, , After being converted from serial to parallel and processed by the sliding buffer by the multiphase decomposition module, the corresponding data are stored in the upper and lower channels of the FIFO.

[0029] Step 3: The multiphase filtering module performs parallel filtering on the upper and lower channel signals stored in the FIFO.

[0030] Step 4: The IDFT module uses the coprime factor algorithm to perform IDFT processing on the upper and lower channel signals of the filtered FIFO in two stages.

[0031] Step 5: The cross-correlation module performs cross-correlation processing on the two-stage IDFT processing results of the upper and lower channel signals of the FIFO; to obtain... One cross-correlation result;

[0032] Step 6: The modulus calculation module calls the CORDIC module to perform... Perform a modulo operation on the cross-correlation results and output the result. Power spectral density values.

[0033] Furthermore, in step 2, the method for the multiphase decomposition module to perform serial-to-parallel conversion and sliding buffer processing includes the following steps:

[0034] The multiphase decomposition module calls the asynchronous FIFO IP core for serial-to-parallel conversion, using asynchronous FIFO to achieve 1:8 burst reads. Let: , The asynchronous FIFO is divided into K and L FIFO sub-units. The K FIFO sub-units serve as the upper channel signal storage area, used to buffer data from the M-point sliding window; the L FIFO sub-units serve as the lower channel signal storage area, used to buffer data from the N-point sliding window. Under the system clock domain, data writing and sliding updates are completed using a circular buffer array and a counter as follows: 8 samples are written each time, sequentially writing the data from the M channels into the K FIFO sub-units and the data from the N channels into the L asynchronous FIFO sub-units. After writing enough snapshots, the low-rate data streams of the M and N channels are read out in parallel. Simultaneously, by monitoring the window update enable signals of the upper and lower channels, edge detection and logical AND processing are used to generate a synchronization enable signal, ensuring that the data from the two different sampling rates are aligned in time, providing a synchronous wide-bit-width data bus output for the subsequent multiphase filtering module.

[0035] Further, in step 3, the method of using a multiphase filtering module to perform parallel filtering processing on the upper and lower channel signals stored in the FIFO includes the following steps: The multiphase filtering module adopts a serial multiply-accumulate architecture. When multiplying and accumulating the low-speed data stream with the set filter coefficients, the Multiplier IP core is called. Assuming the data after multiphase decomposition is 12 bits wide, it is multiplied by a complex number with the pre-written 16-bit wide filter coefficients. Since the sampled signal is a real signal, the sampled signal is multiplied by the real and imaginary parts of the filter coefficients respectively. The internal delay of the multiplier is set to 3 clock cycles, that is, after the multiplication is completed, a 3-clock clock cycle operation is performed before accumulation. After accumulation, the upper and lower channels obtain M / N point filtering results respectively.

[0036] Furthermore, step 4 includes the following sub-steps:

[0037] Step A1: The IDFT module performs the first stage IDFT processing on the upper and lower channel signals of the FIFO as follows: First, the data filtered by the polyphase filter module is rearranged according to the Good-Thomas IDFT input index to obtain... and Two-dimensional arrays, respectively Groups of independent parallel Point IDFT calculation and Groups of independent parallel Point-wise IDFT calculation, i.e., parallel correspondence between upper and lower channels and pre-converted floating-point numbers into 16-bit fixed-point signed numbers. and The rotation factor of the point is used for multiplication and accumulation. One multiplication operation is performed every clock cycle, and the result is entered into the accumulator after a 3-clock delay. The first-stage IDFT processing result is obtained after one clock cycle;

[0038] Step A2, the IDFT module performs the second-stage IDFT processing on the upper and lower channel signals of the FIFO as follows: First, the upper and lower channels are processed separately... independent groups Point IDFT calculation and independent groups Point-wise IDFT calculation, i.e., parallel correspondence between upper and lower channels and pre-converted floating-point numbers into 16-bit fixed-point signed numbers. and The rotation factor of the point is used for multiplication and accumulation. One multiplication operation is performed every clock cycle, and the result is entered into the accumulator after a 3-clock delay. The second stage of IDFT processing is obtained after one clock cycle.

[0039] Further, in step 5, the multiphase filtering module reads 24 snapshots from the FIFO, divides them into eight groups of three snapshots each, calculates a cross-correlation every three snapshots, and performs eight cross-correlation operations on every 24 snapshots. Each cross-correlation operation is performed in parallel using eight multipliers over one clock cycle. Based on the symmetric nature of the spectrum, this requires… Each clock cycle completes one set of cross-correlation calculations; eight sets of cross-correlation calculations require a total of [time period missing]. It takes one clock cycle to complete.

[0040] Furthermore, in step 6, a modulo operation is performed once per clock cycle. The delay of the CORDIC IP core is 63 clock cycles, meaning it requires... The modulus calculation is completed in one clock cycle, and the real-time power spectrum result is obtained.

[0041] The present invention also provides an apparatus for implementing a broadband spectral analysis method based on real-time undersampling and computation, comprising a memory and a processor, wherein the memory is used to store a computer program; and the processor is used to execute the computer program and, when executing the computer program, implement the broadband spectral analysis method steps based on real-time undersampling and computation as described above.

[0042] The advantages and positive effects of this invention are:

[0043] (1) This invention addresses the inherent flaw of existing spectrum analyzers that "buffer complete snapshots first and then process them centrally," providing a real-time processing solution with end-to-end pipelined sampling and calculation. From ADC sampling to power spectrum output, the entire process is unblocked, supporting efficient processing of continuous data streams and significantly reducing system processing latency, thus meeting the requirements for all-weather spectrum detection in electronic reconnaissance scenarios. It significantly reduces system processing latency, achieving true "sampling and calculation." This invention breaks through the inherent mode of traditional spectrum analyzers that "buffer complete snapshots first and then process them centrally," adopting an end-to-end pipelined architecture. The entire process from ADC sampling to power spectrum output is unblocked and requires no large-capacity buffer, supporting efficient processing of continuous data streams. Sampling and spectrum analysis calculations are performed synchronously, with a single panoramic spectrum output time of approximately 5.26 μs, far lower than the processing latency of traditional solutions, fully meeting the stringent requirements of rapid acquisition of transient signals and high real-time performance in scenarios such as electronic reconnaissance and cognitive radio.

[0044] (2) This invention addresses the inherent defect of narrow instantaneous bandwidth in existing spectrum analyzers. Existing spectrum analyzers generally employ a superheterodyne receiver mechanism, whose instantaneous bandwidth is determined by the resolution bandwidth (RBW) of the intermediate frequency filter, resulting in long scan times. This invention fully utilizes the high parallelism inherent in the digital processing flow of coprime spectrum analysis. Based on traditional dual-path coprime spectrum analysis, it further optimizes filtering accuracy, suppresses spectral leakage, and improves computational efficiency through parallel filtering, IDFT structure, and subsequent cross-correlation modulus operations, thereby extending the instantaneous bandwidth to the entire spectrum detection coverage. This significantly expands the instantaneous bandwidth, enabling real-time panoramic spectrum detection. This invention fully utilizes the high parallelism of coprime spectrum analysis. Through optimized polyphase filtering, Good-Thomas algorithm decomposition of IDFT, and cross-correlation structure, while ensuring spectral resolution (approximately 7MHz) and suppressing spectral leakage, it extends the instantaneous bandwidth to the entire detection coverage (0~6GHz), overcoming the problems of narrow instantaneous bandwidth and long scan times caused by RBW limitations in traditional superheterodyne spectrum analyzers, and significantly improving broadband spectrum sensing capabilities.

[0045] (3) This invention addresses the inherent limitation of existing spectrum analyzers in capturing "short-duration burst signals." It supports non-cooperative blind detection scenarios, enabling real-time scanning and transient capture of burst signals with millisecond-level low intercept probability within a 6GHz broadband range, even in the absence of prior information. This improves carrier frequency positioning accuracy and system real-time performance, providing key technical support for the engineering implementation of broadband spectrum sensing receivers with low latency, low power consumption, and high engineering feasibility. This invention enhances the capture capability of short-duration burst signals and supports non-cooperative blind detection. For millisecond-level low intercept probability burst signals, this invention can still achieve real-time scanning and transient capture within a 6GHz broadband range even in the absence of prior information, improving carrier frequency positioning accuracy and system robustness. It provides key technical support for the engineering deployment of broadband spectrum sensing receivers with low latency, low power consumption, low hardware resource consumption, and high reliability, exhibiting good scalability and practical application value.

[0046] While maintaining high detection accuracy and low hardware cost, this invention comprehensively solves the shortcomings of existing technologies in terms of real-time performance, instantaneous bandwidth, and burst signal acquisition capability, providing an efficient and practical solution for fields such as radio spectrum monitoring and electronic countermeasures. Attached Figure Description

[0047] Figure 1 This is a flowchart of a broadband spectral analysis method based on real-time undersampling and calculation according to the present invention.

[0048] Figure 2 This is a flowchart of traditional coprime spectrum analysis.

[0049] Figure 3 This is a diagram showing the FIFO IP core configuration during the multiphase decomposition module's decomposition process.

[0050] Figure 4 This is a diagram showing the configuration of the Multiplier IP core during the filtering process of the multiphase filter module.

[0051] Figure 5 This is a schematic diagram illustrating the computation time at each stage in the simulation of a broadband spectral analysis method based on real-time undersampling and computation.

[0052] Figure 6 This is a schematic diagram of the panoramic spectrum and system computation time generated from the simulation results of a broadband spectrum analysis method based on real-time undersampling and computation according to the present invention.

[0053] Figure 7 The results are from a broadband spectrum analyzer based on real-time undersampling and computation.

[0054] Figure 8 This is a block diagram of a broadband spectral analysis system based on real-time undersampling and computation according to the present invention.

[0055] In the picture:

[0056] FIFO_0 indicates the first first-in-first-out buffer;

[0057] FIFO_1 indicates the second first-in-first-out buffer;

[0058] FIFO_K represents the first... A first-in-first-out buffer memory;

[0059] FIFO_L indicates the first A first-in-first-out buffer memory;

[0060] This represents the first sub-data after multiphase decomposition of the upper channel;

[0061] This represents the second sub-data after multiphase decomposition of the upper channel;

[0062] This represents the Mth sub-data after multiphase decomposition of the upper channel;

[0063] This represents the first sub-data after multiphase decomposition of the lower channel;

[0064] This represents the second sub-data after multiphase decomposition of the lower channel;

[0065] This represents the Nth sub-data after multiphase decomposition of the lower channel;

[0066] This represents the first sub-data after multiphase filtering in the upper channel;

[0067] This represents the second sub-data after the upper channel has undergone multiphase filtering;

[0068] This represents the Mth sub-data after multiphase filtering in the upper channel;

[0069] This represents the first sub-data after the lower channel has undergone multiphase filtering;

[0070] This represents the second sub-data after the lower channel has undergone multiphase filtering;

[0071] This represents the Nth sub-data after the lower channel has undergone polyphase filtering;

[0072] This represents the first sub-data after the IDFT stage in the upper channel;

[0073] This represents the second sub-data after the IDFT stage in the upper channel;

[0074] This represents the Mth sub-data after the IDFT stage in the upper channel;

[0075] This represents the first data segment after the IDFT stage in the lower channel;

[0076] This represents the second sub-data after the IDFT stage in the lower channel;

[0077] This represents the Nth sub-data after the IDFT stage in the lower channel;

[0078] This represents the digital signal of the upper channel after undersampling;

[0079] This represents the digital signal of the lower channel after undersampling;

[0080] Indicates the input analog signal;

[0081] This represents the unit delay for one sampling point;

[0082] Indicates the sampling rate of the upper channel;

[0083] Indicates the sampling rate of the lower channel;

[0084] Indicates the reference sampling frequency;

[0085] Indicates the coprime sampling factor of the lower channel;

[0086] Indicates the coprime sampling factor of the upper channel;

[0087] ADC stands for Analog-to-Digital Converter;

[0088] FPGA stands for Field Programmable Gate Array;

[0089] P represents the product;

[0090] A represents the multiplier;

[0091] B represents the multiplier. Detailed Implementation

[0092] The present invention will now be described in detail with reference to the accompanying drawings and embodiments. It should be understood that the preferred embodiments described herein are for illustration and explanation only and are not intended to limit the present invention.

[0093] In the description of this invention, the terms "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," and "bottom," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and do not require the invention to be constructed and operated in a specific orientation; therefore, they should not be construed as limitations on the invention. The terms "connected" and "linked" used in this invention should be interpreted broadly. For example, they can refer to a fixed connection or a detachable connection; a direct connection or an indirect connection through intermediate components; or an electrical connection or signal transmission. Those skilled in the art can understand the specific meaning of the above terms according to the specific circumstances.

[0094] The following are the Chinese definitions of English words, phrases, and abbreviations:

[0095] ADC: Analog-to-Digital Converter;

[0096] FPGA: Field Programmable Gate Array;

[0097] IDFT: Inverse Discrete Fourier Transform;

[0098] FIFO: First-In-First-Out buffer;

[0099] CORDIC: A numerical calculation method for coordinate rotation;

[0100] CORDIC IP: Intellectual Property Core for Coordinate Rotation Digital Computation Method;

[0101] Multiplier IP: Intellectual Property Core for Multipliers;

[0102] AXI: Advanced Extensible Interface;

[0103] Good-Thomas IDFT: Inverse Fast Fourier Transform of Coprime Factors;

[0104] Bit: A unit of data width;

[0105] RBW, resolution BandWidth;

[0106] Data Port Parameters: Data port parameters;

[0107] Asymmetric Port Width: Asymmetric port width;

[0108] Write Width: The write width of the first-in-first-out buffer memory;

[0109] Write Depth: The write depth of the first-in-first-out buffer memory;

[0110] Actual Write Depth: The actual write depth of the first-in-first-out buffer.

[0111] Read Width: The read width of the first-in-first-out buffer memory;

[0112] Read Depth: The read depth of the first-in-first-out buffer memory;

[0113] Actual Read Depth: The actual read depth of the first-in-first-out buffer.

[0114] Input Options: Input options;

[0115] Data Type: Data type;

[0116] Signed: a number with a signed symbol;

[0117] Width: Data bit width;

[0118] Range: Bit width range;

[0119] Multiplier Construction: The construction of a multiplier;

[0120] Use Mults:Use multipliers;

[0121] Optimization Options:Optimization options;

[0122] Speed Optimized:Speed optimization;

[0123] Name:Name;

[0124] Value:Value;

[0125] coprime_en:Enable signal for coprime spectrum analysis algorithm;

[0126] filter_out_value:Filter output valid signal;

[0127] idft_val:Inverse discrete Fourier transform output valid signal;

[0128] corr_val:Cross-correlation output valid signal;

[0129] clk:Clock;

[0130] rst_n:Reset;

[0131] analyzer_out:Full-spectrum analysis output result;

[0132] Figure:Figure.

[0133] See Figures 1 to 8 , a wideband spectrum analysis system based on real-time undersampling and computation, the system comprises an ADC sampling module, a polyphase decomposition module, a polyphase filtering module, an IDFT module, a cross-correlation module and a modulus calculation module connected in sequence; wherein:

[0134] The ADC sampling module comprises two ADC units, each ADC unit comprises a sampling sub-module, a low-noise amplifier and a sample-and-hold circuit connected in sequence. The sampling sub-modules of the two ADC units perform undersampling on input signals at different sampling rates respectively, to capture 300 MHz~6 GHz electromagnetic signals; the low-noise amplifier is configured to amplify the signal sampled by the sampling sub-module; the sample-and-hold circuit is configured to capture the voltage value of the input analog signal during the analog-to-digital conversion process and keep it constant during the conversion.

[0135] The polyphase decomposition module is configured to convert serial data to parallel data by means of an asynchronous FIFO.

[0136] The polyphase filtering module is configured to complete filtering operation by adopting a serial multiply-accumulate mode.

[0137] The IDFT module is used to perform the inverse discrete Fourier transform calculation in two stages using the coprime factor algorithm;

[0138] The cross-correlation module is used to perform cross-correlation calculations on two data streams;

[0139] The modulus module is used to calculate the modulus value using the CORDIC module and output the power spectrum;

[0140] Each of the two ADC units outputs a digital signal, which is processed by the polyphase decomposition module, the polyphase filtering module, and the IDFT module, respectively, and then input to the cross-correlation module for cross-correlation calculation. The cross-correlation calculation result is input to the modulus calculation module, which outputs the power spectrum.

[0141] The CORDIC module is a hardware acceleration unit built on the Coordinate Rotation Digital Computer algorithm. It is mainly used to efficiently calculate complex mathematical problems such as trigonometric functions, hyperbolic functions, and vector rotations through addition, subtraction, and displacement operations without the need for multipliers.

[0142] Preferably, the two ADC units can be referred to as the first ADC unit and the second ADC unit, respectively; the polyphase decomposition module includes the first polyphase decomposition unit and the second polyphase decomposition unit; the polyphase filtering module may include the first polyphase filtering unit and the second polyphase filtering unit; the IDFT module may include the first IDFT unit and the second IDFT unit; and the cross-correlation module may include the first signal input terminal and the second signal input terminal.

[0143] The first ADC unit outputs a first digital signal, which can be processed by the first polyphase decomposition unit, the first polyphase filtering unit and the first IDFT unit respectively, and then input to the first signal input terminal of the cross-correlation module.

[0144] The second ADC unit outputs a second digital signal, which can be processed by the second polyphase decomposition unit, the second polyphase filtering unit, and the second IDFT unit, and then input to the second signal input terminal of the cross-correlation module.

[0145] Preferably, the system can be a heterogeneous multi-core system-on-a-chip, which is formed by interconnecting and integrating a multi-core processor and a programmable gate array via an AXI bus.

[0146] Multi-core processors are used to execute program instructions, process data, and coordinate hardware resources, while programmable gate arrays define hardware logic through software programming.

[0147] This invention also provides a broadband spectrum analysis method based on real-time undersampling and calculation using the aforementioned broadband spectrum analysis system based on real-time undersampling and calculation. The method includes the following steps:

[0148] Step 1, set Let the reference sampling frequency be denoted as . The highest frequency of the actual signal. ≥2 Let M and N be integers and coprime. , , , Let the integer be: , ;

[0149] The input analog signal is sampled by two ADC units. Corresponding to sampling rates Coprime undersampling is performed to obtain two digital signals. , ;

[0150] Step 2, , After being converted from serial to parallel and processed by the sliding buffer by the multiphase decomposition module, the corresponding data are stored in the upper and lower channels of the FIFO.

[0151] Step 3: The multiphase filtering module performs parallel filtering on the upper and lower channel signals stored in the FIFO.

[0152] Step 4: The IDFT module uses the coprime factor algorithm to perform IDFT processing on the upper and lower channel signals of the filtered FIFO in two stages.

[0153] Step 5: The cross-correlation module performs cross-correlation processing on the two-stage IDFT processing results of the upper and lower channel signals of the FIFO; to obtain... One cross-correlation result;

[0154] Step 6: The modulus calculation module calls the CORDIC module to perform... Perform a modulo operation on the cross-correlation results and output the result. Power spectral density values.

[0155] Preferably, in step 2, the method for the multiphase decomposition module to perform serial-to-parallel conversion and sliding buffer processing may include the following steps:

[0156] The multiphase decomposition module calls the asynchronous FIFO IP core for serial-to-parallel conversion, using asynchronous FIFO to achieve 1:8 burst reads. Let: , The asynchronous FIFO is divided into K and L FIFO sub-units. The K FIFO sub-units serve as the upper channel signal storage area, used to buffer data for the M-point sliding window; the L FIFO sub-units serve as the lower channel signal storage area, used to buffer data for the N-point sliding window. Under the system clock domain, data writing and sliding updates are completed using a circular buffer array and a counter as follows: 8 sampled data are written each time, sequentially writing the data of the M channels into the K FIFO sub-units storing the upper channel signal, and sequentially writing the data of the N channels into the L asynchronous FIFO sub-units storing the lower channel signal, thus realizing the continuous sliding window required for multiphase decomposition. After writing enough snapshots, the low-rate data streams of the M and N channels are read out in parallel. Simultaneously, by monitoring the window update enable signals of the upper and lower channels, edge detection and logical AND processing are used to generate a synchronization enable signal, ensuring that the data from the two different sampling rates are aligned in time, providing a synchronous wide-bit-width data bus output for the subsequent multiphase filtering module.

[0157] Preferably, in step 3, the method of using a multiphase filtering module to perform parallel filtering processing on the upper and lower channel signals stored in the FIFO may include the following steps: The multiphase filtering module adopts a serial multiply-accumulate architecture. When multiplying and accumulating the low-speed data stream with the set filter coefficients, the Multiplier IP core is called. Assuming the data after multiphase decomposition is 12 bits wide, it is multiplied by a pre-written 16-bit wide filter coefficient. Since the sampled signal is a real signal, the sampled signal is multiplied by the real and imaginary parts of the filter coefficients respectively. The internal delay of the multiplier is set to 3 clock cycles, that is, after the multiplication is completed, a 3-clock clock cycle operation is performed before accumulation. After accumulation, the upper and lower channels obtain M / N point filtering results respectively.

[0158] Multiply-accumulate (MAC) is a fundamental operation that involves performing multiplication first, then adding the product to the original accumulated value. MAC is a special operation in digital signal processors and microprocessors that combines multiplication and accumulation; its hardware unit is called a multiplier-accumulator. This operation adds the product to the accumulator value using a single instruction, improving the execution efficiency of algorithms such as convolution and dot product.

[0159] Preferably, the multiphase filtering module can read 24 snapshots of data from the FIFO, that is, two-dimensional data streams with M / N rows and 24 columns in the upper and lower channels respectively. The upper and lower channels are multiplied and accumulated in parallel with the filter coefficients that have been converted from floating-point numbers to fixed-point signed numbers with a bit width of 16 bits. One multiplication operation is performed every clock cycle, and the multiplication result is delayed by 3 clock cycles before entering the accumulator, that is, the filtering result is obtained after 27 clock cycles.

[0160] Preferably, step 4 may include the following sub-steps:

[0161] Step A1: The IDFT module performs the first stage IDFT processing on the upper and lower channel signals of the FIFO as follows: First, the data filtered by the polyphase filter module is rearranged according to the Good-Thomas IDFT input index to obtain... and Two-dimensional arrays, respectively Groups of independent parallel Point IDFT calculation and Groups of independent parallel Point-wise IDFT calculation, i.e., parallel correspondence between upper and lower channels and pre-converted floating-point numbers into 16-bit fixed-point signed numbers. and The rotation factor of the point is used for multiplication and accumulation. One multiplication operation is performed every clock cycle, and the result is entered into the accumulator after a 3-clock delay. The first-stage IDFT processing result is obtained after one clock cycle;

[0162] Step A2, the IDFT module performs the second-stage IDFT processing on the upper and lower channel signals of the FIFO as follows: First, the upper and lower channels are processed separately... independent groups Point IDFT calculation and independent groups Point-wise IDFT calculation, i.e., parallel correspondence between upper and lower channels and pre-converted floating-point numbers into 16-bit fixed-point signed numbers. and The rotation factor of the point is used for multiplication and accumulation. One multiplication operation is performed every clock cycle, and the result is entered into the accumulator after a 3-clock delay. The second stage of IDFT processing is obtained after one clock cycle.

[0163] Preferably, in step 5, the multiphase filtering module can read 24 snapshots of data from the FIFO, divide the 24 snapshots into eight groups of three snapshots each, calculate the cross-correlation once for every three snapshots, and perform eight cross-correlation operations for every 24 snapshots. Each cross-correlation operation uses eight multipliers in parallel calculation for one clock cycle. Based on the symmetric nature of the spectrum, it requires... Each clock cycle completes one set of cross-correlation calculations; eight sets of cross-correlation calculations require a total of [time period missing]. It takes one clock cycle to complete.

[0164] Each sampled point represents one snapshot. To obtain a panoramic spectrum, 24 snapshots are required, which is 24... One sampling point.

[0165] Preferably, in step 6, a modulo operation can be performed once per clock cycle, and the delay of the CORDIC IP core can be 63 clock cycles, meaning it requires... The modulus calculation is completed in one clock cycle, and the real-time power spectrum result is obtained.

[0166] The present invention also provides an apparatus for implementing a broadband spectral analysis method based on real-time undersampling and computation, comprising a memory and a processor, wherein the memory is used to store a computer program; and the processor is used to execute the computer program and, when executing the computer program, implement the broadband spectral analysis method steps based on real-time undersampling and computation as described above.

[0167] The workflow and working principle of the present invention will be further described below with reference to a preferred embodiment:

[0168] A broadband spectral analysis system based on real-time undersampling and computation is proposed, which utilizes a two-channel coprime spectrum driving system. Figure 1 The illustrated hardware architecture system design is based on an FPGA. This system includes, in sequence, an ADC sampling module, a polyphase decomposition module, a polyphase filtering module, an IDFT module, a cross-correlation module, and a modulus calculation module; wherein:

[0169] The ADC sampling module includes two ADC units. Each ADC unit includes a sampling submodule, a low-noise amplifier, and a sample-and-hold circuit connected in sequence. The sampling submodules of the two ADC units undersample the input signal at different sampling rates to capture electromagnetic signals from 300 MHz to 6 GHz. The low-noise amplifier is used to amplify the signal sampled by the sampling submodule. The sample-and-hold circuit is used to capture the voltage value of the input analog signal during analog-to-digital conversion and keep it constant during the conversion.

[0170] The multiphase decomposition module is used to convert serial data to parallel data using an asynchronous FIFO;

[0171] The multiphase filter module is used to perform filtering operations using a serial multiplication-accumulation method;

[0172] The IDFT module is used to perform the inverse discrete Fourier transform calculation in two stages using the coprime factor algorithm;

[0173] The cross-correlation module is used to perform cross-correlation calculations on two data streams;

[0174] The modulus module is used to calculate the modulus value using the CORDIC module and output the power spectrum;

[0175] Each of the two ADC units outputs a digital signal, which is processed by the polyphase decomposition module, the polyphase filtering module, and the IDFT module, respectively, and then input to the cross-correlation module for cross-correlation calculation. The cross-correlation calculation result is input to the modulus calculation module, which outputs the power spectrum.

[0176] set up Let the reference sampling frequency be denoted as . The highest frequency of the actual signal. ≥2 This design adopts =2 Let M and N be integers and coprime. , , , Let the integer be: , ;

[0177] The input analog signal is sampled by two ADC units. Corresponding to sampling rates Coprime undersampling is performed to obtain two digital signals. , ;

[0178] (1) System parameters

[0179] Coprime sampling parameters: Select , M and N are coprime.

[0180] System clock: 300MHz.

[0181] Each batch processes 24 snapshots.

[0182] The filter coefficients and twitch factor are 16-bit fixed-point numbers.

[0183] Detection frequency range: 0~6GHz.

[0184] Spectral resolution: approximately 7 MHz.

[0185] (2) Hardware implementation structure

[0186] The system uses a heterogeneous multi-core system-on-a-chip Xilinx Zynq Ultrascale+ FPGA, specifically model XCZU15EG-2FFVB1156I.

[0187] A broadband spectrum analysis method based on real-time undersampling and computation using the above-mentioned broadband spectrum analysis system based on real-time undersampling and computation includes the following steps: ADC sampling, polyphase decomposition, polyphase filtering, IDFT, cross-correlation and modulus calculation.

[0188] Input: Let the input analog signal be... Let M and N be integers and coprime. , , , Let the integer be: , ;set up Let the reference sampling frequency be denoted as . The highest frequency of the actual signal. =2 ;

[0189] Initialization settings: Frequency axis coverage value (The upper limit of the corresponding real signal frequency detection is) Given two integer values ​​M and N that satisfy the coprime relation, and any integer can be further expressed as a product of integer factors. , .

[0190] Step 1 ADC Sampling:

[0191] right By sampling rate , Perform coprime undersampling to obtain two digital signals. , .

[0192] Step 2: Multiphase decomposition treatment:

[0193] The following serial-to-parallel conversion and sliding buffer operation is used for undersampled data streams. , Perform multiphase decomposition. In the upper channel, Convert to M-channel parallel low-speed data The data is cached in a FIFO; similarly, in the next channel, the coprime undersampled data stream is cached in a FIFO. Convert to N-way parallel low-speed data stream Cache it in FIFO.

[0194] The sampled data is serially fed into the multiphase decomposition module. After multiphase decomposition, parallel data is obtained. Low-speed data stream of the path.

[0195] The multiphase decomposition module calls the asynchronous FIFO IP core to perform serial-to-parallel conversion. Because asynchronous FIFOs are used to achieve 1:8 burst reads, each FIFO serially writes 12 bits of ADC sampling data and reads out 96 bits of data. K and L FIFOs are set for the upper and lower channels respectively. , Data caching is performed for sliding windows at points M and N respectively. The FIFO IP core configuration is as follows: Figure 3 As shown, efficient data writing and sliding updates are achieved in the system clock domain through a circular buffer array and a counter: 8 samples are written each time and stored sequentially in the corresponding positions of the FIFOs. Specifically, data from M and N channels are written sequentially to K and L FIFOs to achieve the continuous sliding window required for multiphase decomposition. After writing enough snapshots, the low-rate data streams of M and N channels are read out in parallel. At the same time, by monitoring the window update enable signals of the two channels, edge detection and logical AND operation are used to generate a synchronous enable signal to ensure that the data from the two different sampling rates are precisely aligned in time, providing a stable and synchronous wide-bit-width data bus output for the subsequent multiphase filter bank.

[0196] Step 3: Multiphase filtering processing:

[0197] Parallel filtering is performed on the upper and lower channel signals of the Step 2 output stored in the FIFO. In the upper channel, the low-speed data stream obtained from polyphase decomposition is filtered. Perform a multiplication and accumulation operation with the written filter coefficients to obtain Similarly, the lower channel will receive the low-speed data stream obtained from multiphase decomposition. Multiply and accumulate the results by the written filter coefficients. .

[0198] The low-rate data streams of M / N paths obtained by multiphase decomposition are filtered in parallel. After the designed multiply-accumulate operation, the filtered result of M / N points is obtained.

[0199] Multiply-accumulate operations call the Multiplier IP core; specific settings are as follows: Figure 4 As shown, the data after polyphase decomposition is 12 bits wide. It is then multiplied by pre-written 16-bit filter coefficients using complex numbers. Since the sampled signal is a real signal, only the sampled signal needs to be multiplied by the real and imaginary parts of the filter coefficients. The internal delay of the multiplier is set to 3 clock cycles, meaning that a 3-clock-cycle timing operation is required after multiplication before accumulation. After accumulation, the upper and lower channels obtain M / N-point filtering results respectively. Using a serial multiply-accumulate architecture, compared to fully parallel FIR filtering, the number of multipliers is reduced from 48 to 2, significantly reducing the number of multipliers used and achieving higher-order complex filtering with fewer DSP resources.

[0200] After multiphase decomposition, the sampled data is converted into a parallel low-rate data stream with M upper channels and N lower channels. The low-rate data stream enters the filtering calculation in parallel. The multiphase filtering module reads 24 snapshots of data from the FIFO, that is, a two-dimensional data stream with M / N rows and 24 columns for the upper and lower channels respectively. The upper and lower channels are multiplied and accumulated in parallel with the filter coefficients that have been converted from floating-point numbers to fixed-point signed numbers with a bit width of 16 bits. One multiplication operation is performed every clock cycle. The multiplication result is entered into the accumulator after a delay of 3 clock cycles, that is, the filtering result is obtained after 27 clock cycles.

[0201] Step 4 IDFT processing:

[0202] IDFT Phase 1:

[0203] First, the filtered results are rearranged according to the Good-Thomas IDFT input index to obtain... and Two-dimensional arrays, respectively Groups of independent parallel Point IDFT calculation and Groups of independent parallel Point-wise IDFT computation, i.e., parallel processing of upper and lower channels and pre-conversion of floating-point numbers to 16-bit fixed-point signed numbers. and The rotation factor of the point is multiplied and accumulated. One multiplication operation is performed every clock cycle. The multiplication result is delayed by 3 clock cycles before entering the accumulator. The larger clock cycle number from the upper and lower channels is used for calculation. The IDFT first-stage result is obtained after one clock cycle.

[0204] In the upper channel, the output data of the multiphase filtering stage will be... Rearrange the data and break it down into Group The sub-data stream of a point, for any set of sub-data streams and the pre-written... The IDFT twitch factor of each point is multiplied and accumulated to obtain a parallel output. Group IDFT one-stage transformation results (output per group) (Data points).

[0205] Similarly, in the next channel, the output data from the multiphase filtering stage will be... Rearrange the data and decompose it into Group The sub-data stream of a point, for any set of sub-data streams and the pre-written... The IDFT twitch factor of the point is multiplied and accumulated to obtain... The transformation results of the first stage of group IDFT (output of each group) (Data points).

[0206] IDFT Phase 2:

[0207] First, proceed with the upper and lower passages separately. independent groups Point IDFT calculation and independent groups Point-wise IDFT computation, i.e., parallel processing of upper and lower channels and pre-conversion of floating-point numbers to 16-bit fixed-point signed numbers. and The rotation factor of the point is multiplied and accumulated. One multiplication operation is performed every clock cycle. The multiplication result is delayed by 3 clock cycles before entering the accumulator. The larger clock cycle of the upper and lower channels is used for calculation. The second-stage IDFT result is obtained after one clock cycle.

[0208] In the upper channel, the transformation results obtained from the first stage of IDFT are first organized as follows: Group Parallel sub-data streams of points, for any set of sub-data streams and pre-written... The IDFT twitch factors of the points are multiplied and accumulated to obtain the two-stage IDFT transformation result. After rearranging the output data, the final IDFT result is obtained. ;

[0209] Similarly, in the next channel, the transformation results obtained from the first stage of IDFT are first organized as follows: Group Parallel sub-data streams of points, for any set of sub-data streams and pre-written... The IDFT twitch factors of the points are multiplied and accumulated to obtain the two-stage IDFT transformation result. After rearranging the output data, the final IDFT result is obtained. .

[0210] Step 5: Cross-correlation processing:

[0211] Due to real-time limitations, the cross-correlation module divides the 24 snapshots into eight groups, with three snapshots in each group. Cross-correlation is calculated every three snapshots, for a total of eight cross-correlation operations per 24 snapshots. Each cross-correlation operation is performed in parallel using eight multipliers over one clock cycle. Furthermore, due to the symmetric nature of the spectrum, it requires… Each clock cycle completes one set of cross-correlation calculations; eight sets of cross-correlation calculations require a total of [time period missing]. It takes one clock cycle to complete.

[0212] The cross-correlation module will use the IDFT results obtained from the upper channel. IDFT results obtained from the lower channel Perform cross-correlation operations.

[0213] Step 6: Modulus Calculation

[0214] Modulus calculation requires two multiplications and a square root calculation, both of which are computationally expensive. The CORDIC algorithm, however, uses a shift operation to replace multiplication, performing a pseudo-rotation, and obtains the complex modulus without requiring a square root calculation, making it highly suitable for FPGA implementation. Therefore, this design chooses the CORDIC algorithm for modulus calculation, performing one modulus operation per clock cycle. The CORDIC IP core has a delay of 63 clock cycles, meaning it requires... The modulus calculation is completed in one clock cycle, and the real-time power spectrum result is obtained.

[0215] Call the CORDIC module to Perform a modulo operation on the cross-correlation results (which are complex values) and output the result. Power spectral values .

[0216] In the above steps:

[0217] This represents the discrete-time index, also known as the sampling point number, i.e., the nth sampling point;

[0218] This represents the digital signal sequence after undersampling in the upper channel;

[0219] This represents the digital signal sequence after undersampling in the lower channel;

[0220] Indicates the 0th to the 1st Parallel low-speed signals from the upper channel after multiphase decomposition;

[0221] Indicates the 0th to the 1st Parallel low-speed signals from the upper channel after multiphase filtering;

[0222] Indicates the 0th to the 1st Parallel low-speed signals from each lower channel after multiphase decomposition;

[0223] Indicates the 0th to the 1st Parallel low-speed signals from each lower channel after multiphase filtering;

[0224] Indicates the 0th to the 1st Parallel low-speed signals after the IDFT stage in each upper channel;

[0225] Indicates the 0th to the 1st Parallel low-speed signals after the IDFT stage in each lower channel;

[0226] The above signals all correspond to the nth sampling point.

[0227] This represents the frequency index, used to indicate the i-th frequency point in the spectrum;

[0228] This represents the i-th normalized angular frequency;

[0229] This represents the estimated power spectral density.

[0230] This represents the amplitude value of the power spectrum, which is the final output power spectrum result.

[0231] Technical principles of traditional coprime spectrum analysis algorithms:

[0232] Under undersampling conditions, spectral aliasing occurs due to the violation of the Nyquist sampling theorem, making direct spectral analysis of the signal impossible. However, coprime spectral analysis, by utilizing the correlation characteristics of two coprime undersampling sequences and reconstructing the spectrum based on the Chinese remainder theorem, avoids the problem of frequency point identification due to spectral aliasing.

[0233] Traditional coprime spectral analysis analyzes two discrete signals acquired by two coprime downsampling factors M and N. However, this analysis is not suitable for two coprime undersampled discrete signals. and First, two prototype filters need to be designed. and Among them, the ideal and The cutoff frequency should be:

[0234] ;

[0235] ;

[0236] in:

[0237] Indicates angular frequency;

[0238] Represents the imaginary unit;

[0239] This represents the frequency response of the prototype filter in the upper channel;

[0240] This represents the frequency response of the lower channel prototype filter;

[0241] In the formula, 𝑀 and 𝑁 are coprime integers.

[0242] Specifically, for discrete signals Perform M-channel multiphase decomposition to obtain the upper channel M-channel low-rate data streams. For discrete signals Perform N-channel multiphase decomposition to obtain N low-rate data streams in the lower channel. After downsampling the prototype filter, a sub-filter bank is used. and To each and Perform polyphase filtering decomposition to obtain the following results: and Then, an M-point IDFT is performed on the upper half-channel data sequence to obtain... Similarly, performing an N-point IDFT on the data sequence of the lower half channel yields... Then, cross-correlation calculations are performed on the output points of each channel in the upper and lower channels sequentially, and the estimated power spectrum values ​​are output. ,Right now:

[0243] ;

[0244] ;

[0245] in:

[0246] c represents the coefficients related to M, N, and the filter;

[0247] Indicates the first channel after IDFT One output sequence;

[0248] Indicates the first channel IDFT after the current channel. The conjugate of each output sequence;

[0249] Represents the mathematical expectation;

[0250] Indicates the frequency resolution interval;

[0251] The Good-Thomas algorithm is an important variant of the Fast Fourier Transform (FFT). It is particularly suitable for cases where the length P of the DFT / IDFT can be decomposed into coprime factors, i.e. and The specific principle is to use the Chinese Remainder Theorem to remap a one-dimensional P-point IDFT into a two-dimensional form. IDFT, utilizing the special structure of two coprime factor sizes, decomposes a large IDFT into a combination of smaller IDFTs, thus enabling... Point IDFT conversion indivual Point IDFT and indivual The number of multiplications required for point IDFT also increases from Reduced to This avoids multiplicative damage to the rotation factor.

[0252] The specific process is as follows:

[0253] (1) Perform index transformation on the input sequence to rearrange the one-dimensional array into Two-dimensional arrays, that is, input rearrangement according to the following rules:

[0254]

[0255] in, ; ;

[0256] (2) Perform independent groups Point IDFT.

[0257] (3) Perform independent groups Point IDFT.

[0258] (4) Perform index transformation on the obtained sequence To rearrange a two-dimensional array into a one-dimensional array, the output should be rearranged according to the following rules:

[0259] ;

[0260] Obtain the IDFT output result at point P.

[0261] in:

[0262] Indicates the total number of points in the IDFT;

[0263] Indicates the first coprime factor;

[0264] Indicates the second coprime factor;

[0265] A one-dimensional index representing the input sequence, i.e., the original signal of the input sequence;

[0266] This represents the index of the first dimension of the input sequence, i.e., the row index of the rearranged two-dimensional array input;

[0267] This represents the index of the second dimension of the input sequence, i.e., the column index of the rearranged two-dimensional array input;

[0268] A one-dimensional index representing the output sequence, i.e., the final sequence number of the output data;

[0269] This represents the index of the first dimension of the output sequence, i.e., the row index of the rearranged two-dimensional array output;

[0270] This represents the index of the second dimension of the output sequence, i.e., the column index of the rearranged two-dimensional array output;

[0271] Table 1: 12-point Good-Thomas FFT Input Transform Index

[0272]

[0273] Table 2: 12-point Good-Thomas FFT output transform index

[0274]

[0275] Verification experiment:

[0276] To verify the functionality and performance of the designed coprime spectrum analyzer, experiments were conducted to test the spectral analysis results and processing speed at a system clock frequency of 300MHz.

[0277] Assume the input real signal , among which the signal The preset frequency axis coverage range is 0 to 6.006 GHz. Coprime factors are used. , If the spectral resolution is set to 7MHz, then the actual sampling rates for each channel are as follows:

[0278] ;

[0279] ;

[0280] Each simulation uses 24 snapshots. The filter coefficients and twitch factors are pre-written as 16-bit fixed-point signed numbers.

[0281] Time consumption at each stage is as follows Figure 5 and Figure 6As shown, `coprime_en` is the algorithm enable signal, `filter_out_value` is the end signal for the filtering stage, `idft_val` is the end signal for the IDFT stage, and `corr_val` is the end signal for cross-correlation. The ADC sampling rates are 273MHz and 308MHz, respectively. The upper channel needs to... At each point, the lower passage needs to be adopted. The ADC sampling time was calculated to be 3.43 μs at each point. The time of each stage was shorter than the ADC sampling time. Since the overall structure is a pipeline design architecture, real-time analysis of coprime spectra can be achieved by sampling and calculating simultaneously.

[0282] Coprime spectrum analysis results are as follows Figure 6 As shown, analyzer_out outputs the panoramic spectrum results, and the time to complete one panoramic spectrum output is approximately 5.26 μs.

[0283] This invention, based on the theory of two-channel coprime undersampling, proposes a broadband spectrum analyzer design based on real-time undersampling and computation. Through a fully pipelined architecture, it achieves simultaneous data acquisition and spectral analysis processing, avoiding large-capacity buffering and significantly reducing processing latency and hardware resource consumption. Its core is the combination of direct RF sampling and fully digital processing to achieve high-resolution panoramic spectral analysis of broadband signals under coprime M and N parameters.

[0284] The ADC sampling module, multiphase decomposition module, multiphase filtering module, IDFT module, cross-correlation module, modulus calculation module, AXI, Multiplier IP core, CORDIC IP core, and CORDIC module can all adopt applicable functional modules in the prior art, or adopt functional modules, algorithms, and software in the prior art and construct them using conventional technical means.

[0285] The embodiments described above are only used to illustrate the technical ideas and features of the present invention. Their purpose is to enable those skilled in the art to understand the content of the present invention and implement it accordingly. The patent scope of the present invention should not be limited by these embodiments. That is, any equivalent changes or modifications made in accordance with the spirit disclosed in the present invention still fall within the patent scope of the present invention.

Claims

1. A broadband spectral analysis system based on real-time undersampling and computation, characterized in that, The system includes, in sequence, an ADC sampling module, a polyphase decomposition module, a polyphase filtering module, an IDFT module, a cross-correlation module, and a modulus calculation module; wherein: The ADC sampling module includes two ADC units. Each ADC unit includes a sampling submodule, a low-noise amplifier, and a sample-and-hold circuit connected in sequence. The sampling submodules of the two ADC units undersample the input signal at different sampling rates to capture electromagnetic signals from 300 MHz to 6 GHz. The low-noise amplifier is used to amplify the signal sampled by the sampling submodule. The sample-and-hold circuit is used to capture the voltage value of the input analog signal during analog-to-digital conversion and keep it constant during the conversion. The multiphase decomposition module is used to convert serial data to parallel data using an asynchronous FIFO; The multiphase filter module is used to perform filtering operations using a serial multiplication-accumulation method; The IDFT module is used to perform the inverse discrete Fourier transform calculation in two stages using the coprime factor algorithm; The cross-correlation module is used to perform cross-correlation calculations on two data streams; The modulus module is used to calculate the modulus value using the CORDIC module and output the power spectrum; Each of the two ADC units outputs a digital signal, which is processed by the polyphase decomposition module, the polyphase filtering module, and the IDFT module, respectively, and then input to the cross-correlation module for cross-correlation calculation. The cross-correlation calculation result is input to the modulus calculation module, which outputs the power spectrum.

2. The broadband spectral analysis system based on real-time undersampling and calculation according to claim 1, characterized in that, The two ADC units are referred to as the first ADC unit and the second ADC unit, respectively. The polyphase decomposition module includes the first polyphase decomposition unit and the second polyphase decomposition unit. The polyphase filtering module includes the first polyphase filtering unit and the second polyphase filtering unit. The IDFT module includes the first IDFT unit and the second IDFT unit. The cross-correlation module includes the first signal input terminal and the second signal input terminal. The first ADC unit outputs a first digital signal, which is processed by the first polyphase decomposition unit, the first polyphase filtering unit and the first IDFT unit, and then input to the first signal input terminal of the cross-correlation module. The second ADC unit outputs a second digital signal, which is processed by the second polyphase decomposition unit, the second polyphase filtering unit, and the second IDFT unit, and then input to the second signal input terminal of the cross-correlation module.

3. The broadband spectral analysis system based on real-time undersampling and calculation according to claim 1, characterized in that, The system adopts a heterogeneous multi-core system-on-a-chip, which is formed by interconnecting and integrating a multi-core processor and a programmable gate array via an AXI bus.

4. A broadband spectral analysis method based on real-time undersampling and computation using the broadband spectral analysis system based on real-time undersampling and computation as described in any one of claims 1 to 3, characterized in that, The method includes the following steps: Step 1, set Let the reference sampling frequency be denoted as . The highest frequency of the actual signal. ≥2 Let M and N be integers and coprime. , , , Let the integer be: , ; The input analog signal is sampled by the sampling submodules of two ADC units. Corresponding to sampling rates Coprime undersampling is performed to obtain two digital signals. , ; Step 2, , After being converted from serial to parallel and processed by the sliding buffer by the multiphase decomposition module, the corresponding data are stored in the upper and lower channels of the FIFO. Step 3: The multiphase filtering module performs parallel filtering on the upper and lower channel signals stored in the FIFO. Step 4: The IDFT module uses the coprime factor algorithm to perform IDFT processing on the upper and lower channel signals of the filtered FIFO in two stages. Step 5: The cross-correlation module performs cross-correlation processing on the two-stage IDFT processing results of the upper and lower channel signals of the FIFO; to obtain... One cross-correlation result; Step 6: The modulus calculation module calls the CORDIC module to perform... Perform a modulo operation on the cross-correlation results and output the result. Power spectral density values.

5. The broadband spectral analysis method based on real-time undersampling and calculation according to claim 4, characterized in that, In step 2, the method for serial-to-parallel conversion and sliding buffer processing by the multiphase decomposition module includes the following steps: The multiphase decomposition module calls the asynchronous FIFO IP core for serial-to-parallel conversion, using asynchronous FIFO to achieve 1:8 burst reads. Let: , The asynchronous FIFO is divided into K FIFO sub-units and L FIFO sub-units. The K FIFO sub-units serve as the upper channel signal storage area, used to buffer the data of the M-point sliding window; the L FIFO sub-units serve as the lower channel signal storage area, used to buffer the data of the N-point sliding window. Under the system clock domain, data writing and sliding updates are completed using a circular buffer array and a counter as follows: 8 sampled data are written each time, sequentially writing the data of the M channels into the K FIFO sub-units, and the data of the N channels into the L asynchronous FIFO sub-units. After writing enough snapshots, the low-rate data streams of M and N channels are read out in parallel. At the same time, by monitoring the window update enable signals of the upper and lower channels, edge detection and logical AND processing are used to generate a synchronous enable signal to ensure that the data of the two different sampling rates are aligned in time, providing a synchronous wide bit-width data bus output for the subsequent multiphase filtering module.

6. The broadband spectral analysis method based on real-time undersampling and calculation according to claim 4, characterized in that, In step 3, the method of using a multiphase filtering module to perform parallel filtering on the upper and lower channel signals stored in the FIFO includes the following steps: The multiphase filtering module adopts a serial multiply-accumulate architecture. When multiplying and accumulating the low-speed data stream with the set filter coefficients, the Multiplier IP core is called. Assuming the data after multiphase decomposition is 12 bits wide, it is multiplied by a complex number with the pre-written 16-bit wide filter coefficients. Since the sampled signal is a real signal, the sampled signal is multiplied by the real and imaginary parts of the filter coefficients respectively. The internal delay of the multiplier is set to 3 clock cycles, that is, after the multiplication is completed, a 3-clock clock cycle operation is performed before accumulation. After accumulation, the upper and lower channels obtain M / N point filtering results respectively.

7. The broadband spectral analysis method based on real-time undersampling and calculation according to claim 4, characterized in that, Step 4 includes the following sub-steps: Step A1: The IDFT module performs the first stage IDFT processing on the upper and lower channel signals of the FIFO as follows: First, the data filtered by the polyphase filter module is rearranged according to the Good-Thomas IDFT input index to obtain... and Two-dimensional arrays, respectively Groups of independent parallel Point IDFT calculation and Groups of independent parallel The point-wise IDFT calculation, i.e., the parallel correspondence between the upper and lower channels and the pre-converted floating-point numbers into 16-bit fixed-point signed numbers. and The rotation factor of the point is used for multiplication and accumulation. One multiplication operation is performed every clock cycle, and the result is entered into the accumulator after a 3-clock delay. The first-stage IDFT processing result is obtained after one clock cycle; Step A2, the IDFT module performs the second-stage IDFT processing on the upper and lower channel signals of the FIFO as follows: First, the upper and lower channels are processed separately... independent groups Point IDFT calculation and independent groups The point-wise IDFT calculation, i.e., the parallel correspondence between the upper and lower channels and the pre-converted floating-point numbers into 16-bit fixed-point signed numbers. and The rotation factor of the point is used for multiplication and accumulation. One multiplication operation is performed every clock cycle, and the result is entered into the accumulator after a 3-clock delay. The second stage of IDFT processing is obtained after one clock cycle.

8. The broadband spectral analysis method based on real-time undersampling and calculation according to claim 4, characterized in that, In step 5, the multiphase filtering module reads 24 snapshots from the FIFO, divides them into eight groups of three snapshots each, calculates a cross-correlation every three snapshots, and performs eight cross-correlation operations on every 24 snapshots. Each cross-correlation operation is performed in parallel using eight multipliers over one clock cycle. Due to the symmetry of the spectrum, this requires... Each clock cycle completes one set of cross-correlation calculations; eight sets of cross-correlation calculations require a total of [time period missing]. It takes one clock cycle to complete.

9. The broadband spectral analysis method based on real-time undersampling and calculation according to claim 4, characterized in that, In step 6, a modulo operation is performed once per clock cycle. The delay of the CORDIC IP core is 63 clock cycles, meaning it requires... The modulus calculation is completed in one clock cycle, and the real-time power spectrum result is obtained.

10. An apparatus for implementing a broadband spectral analysis method based on real-time undersampling and computation, comprising a memory and a processor, characterized in that, The memory is used to store a computer program; the processor is used to execute the computer program and, when executing the computer program, implement the steps of the broadband spectral analysis method based on real-time undersampling and calculation as described in any one of claims 4 to 9.

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