Multi-channel digital vector signal source system

Abstract

The application relates to the communication technical field and discloses a multi-channel digital vector signal source system, which comprises an FPGA module and one or more analog front-end modules connected in parallel with the FPGA module, the FPGA module is used for receiving signal modulation modes, frequencies, bandwidths, output powers and phase parameters configured by a user, generating I / Q two-way digital baseband signals through an internal DDS core; the analog front-end module comprises a double-channel DAC chip and a signal conditioning module, the double-channel DAC chip is used for converting the digital baseband signals into analog signals; the signal conditioning module is used for filtering, frequency up-converting and level adjusting the analog signals output by the double-channel DAC chip, and outputting radio frequency signals; the FPGA module adopts an internal global clock network to provide a unified system clock for each channel, synchronizes the sampling clock of the double-channel DAC chip of each channel with the phase accumulator clock of the DDS core through a phase alignment circuit, and dynamically compensates the phase of each channel through a configurable phase offset.

Description

Technical Field

[0001] This application relates to the field of radio frequency signal processing technology, and more specifically, to a multi-channel digital vector signal source system. Background Technology

[0002] With the rapid development of modern communication technologies, especially the widespread application of 5G, the Internet of Things (IoT), satellite communication, and Software-Defined Radio (SDR), higher requirements are being placed on radio frequency (RF) signal source systems. Traditional signal sources mostly employ analog circuit designs, occupying a large space and hindering integrated deployment, particularly in embedded or portable devices. Existing signal sources are mostly single-channel or dual-channel systems, lacking scalability and failing to meet the testing requirements of multi-channel communication systems such as MIMO and multi-user interference simulation. Some low-end signal sources only support basic amplitude modulation (AM) / frequency modulation (FM) signals and cannot simulate complex digital communication modulation signals such as QAM and OFDM. They also lack the flexibility to configure modulation type, frequency, bandwidth, power, and other parameters according to application scenarios, limiting their applicability in modern communication system simulation. Summary of the Invention

[0003] The main purpose of this application is to provide a multi-channel digital vector signal source system that can solve the shortcomings of large size, high cost, few channels and single modulation style of signal source equipment, and can fully cover the testing and interference simulation needs of the current mainstream communication system.

[0004] To achieve the above objectives, the first aspect of this application proposes a multi-channel digital vector signal source system, comprising: an FPGA module and one or more analog front-end modules connected in parallel with the FPGA module. The FPGA module is used to receive the signal modulation method, frequency, bandwidth, output power, and phase parameters configured by the user, and generates I / Q dual-channel digital baseband signals through its internal DDS core. The analog front-end module includes a dual-channel DAC chip and a signal conditioning module. The dual-channel DAC chip is used to convert the digital baseband signal into an analog signal. The signal conditioning module is used to filter, up-convert, and level-adjust the analog signal output by the dual-channel DAC chip to output an RF signal. The FPGA module uses an internal global clock network to provide a unified system clock for each channel, synchronizes the sampling clock of the dual-channel DAC chip of each channel with the phase accumulator clock of the DDS core through a phase alignment circuit, and dynamically compensates the phase of each channel through a configurable phase offset.

[0005] Furthermore, the signal conditioning module includes an analog low-pass filter, an IQ modulator, a PLL phase-locked loop, and a power adjustment module. The analog low-pass filter is used to band-limit the analog signal output from the dual-channel DAC chip to remove high-frequency noise and spurious signals. The IQ modulator is used to up-convert the filtered analog signal to obtain the radio frequency signal. The PLL phase-locked loop is used to perform feedback control on the local oscillator frequency and phase of the radio frequency signal. The power amplifier and the Π-type attenuator are used to amplify and adjust the radio frequency signal to the target power.

[0006] Furthermore, the FPGA module internally deploys a dual-phase accumulator, an orthogonal lookup table, and configurable modulation mapping logic to achieve hardware-level parallel generation of any digital modulation scheme among ASK, FSK, PSK, QPSK, QAM, and OFDM.

[0007] Furthermore, the FPGA module employs a 32nd-order FIR low-pass filter to band-limit the IQ baseband signal. The filter's passband ripple is <0.1dB, and its stopband attenuation is >60dB, effectively suppressing out-of-band noise and interpolated image spectrum. Oversampling is achieved through 4x interpolation upsampling, increasing the signal sampling rate to four times the original (i.e., the new Nyquist frequency is four times the original Nyquist frequency).

[0008] Furthermore, the system incorporates an adaptive calibration module based on the least mean square algorithm, which automatically and iteratively adjusts the gain compensation coefficient and phase compensation coefficient in the FPGA digital domain until the image power is minimized.

[0009] Furthermore, the system achieves concurrent output of multi-channel independent RF signals by time-division multiplexing of FPGA parallel logic resources and stacking of analog front-end modules. Each channel is isolated by an independent metal shield, and isolation slots are set on the PCB. The digital power supply and RF power supply are powered independently.

[0010] Furthermore, the system achieves multi-board cascading through the IEEE 1588 precision time protocol and external trigger signals.

[0011] Furthermore, the system utilizes FPGA-based dynamic partial reconfiguration technology to update the modulation algorithm and signal processing logic online without interrupting operation.

[0012] As can be seen from the above technical solution, this system reconstructs the architecture of traditional RF signal sources using software-defined hardware, and can generate almost all mainstream modulation signals such as ASK, FSK, PSK, QAM, and OFDM in parallel. It employs zero-IF direct up-conversion, with the FPGA precisely controlling the DAC output of the IQ baseband signal, which is then directly transferred to the RF via the IQ modulator. This eliminates the intermediate frequency filter and multi-stage mixer required in the superheterodyne architecture, fundamentally reducing cost, size, and combinational spurious signals. The FPGA manages multiple independently programmable RF channels through common clock and synchronization logic, achieving sub-nanosecond synchronization and strict coherence. This solves the expansion problem from single-channel to dozens of channels at extremely low cost, adapting to MIMO testing and beamforming verification. Attached Figure Description

[0013] The accompanying drawings, which form part of this application, are used to provide a further understanding of the application and to make other features, objects, and advantages of the application more apparent. The illustrative embodiments and descriptions of this application are used to explain the application and do not constitute an undue limitation of the application. In the drawings: Figure 1 The system architecture diagram of the multi-channel digital vector signal source provided in this application; Figure 2 A schematic diagram of the structure of the multi-channel digital vector signal source system provided in this application. Detailed Implementation

[0014] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0015] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this application described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0016] The current communications industry urgently needs miniaturized, low-cost, multi-system compatible, and highly flexible general-purpose signal sources that can cover the entire frequency band from kHz-level IoT bands to millimeter waves and even terahertz, support all mainstream communication systems and modulation methods, and also support user-defined waveforms and custom interference patterns, with a size that allows for portable or even embedded multi-channel synchronous output.

[0017] This disclosure provides a multi-channel vector signal source system based on a native software-defined radio (SDR) architecture. The core logic for generating radio frequency signals is completely digitized and moved forward to the FPGA baseband domain. All signal parameters (frequency, modulation method, bandwidth, power, phase) are configured through digital logic. Full-format signal generation from narrowband FSK to wideband OFDM can be achieved without changing the hardware. Zero-IF direct upconversion eliminates intermediate frequency filtering, mixing, and secondary frequency conversion stages, retaining only the most essential analog radio frequency front-end. Thus, it achieves a comprehensive surpassing of traditional analog or hybrid architectures in terms of performance, flexibility, cost, and scalability.

[0018] The FPGA internally uses digital logic, such as DDS, high-speed multipliers, and FIR filters, to adjust signal parameters such as frequency, phase, modulation scheme, and bandwidth in real time. This allows for instantaneous parameter switching, dynamic frequency hopping, and the configuration of any new modulation scheme in the future via software, without requiring hardware changes. The I / Q signals generated by the digital baseband directly drive the high-speed DAC. The analog baseband signal output by the DAC is then shifted to the target RF frequency in a single pass through a wideband IQ modulator, avoiding the combined spurious emissions, image interference, and group delay problems introduced by multi-stage mixing and the intermediate frequency filter.

[0019] This system adopts a modular design, enabling multi-channel expansion through a unified digital baseband and distributed analog front-end design. Digital resource utilization increases linearly with the number of channels. Each channel has an independent frequency synthesizer (PLL) that can operate in different frequency bands and supports asynchronous or synchronous modes. Internally, the FPGA utilizes parallel logic resources and time-division multiplexing mechanisms to efficiently drive multiple independent DDS engines and data processing paths. Each RF output consists of an independent, standardized analog front-end module consisting of a DAC, an IQ modulator, and a power amplifier. Increasing the number of channels simply requires physically stacking this module. Through PCB partitioning, power isolation, and electromagnetic shielding, channel isolation >60dB can be achieved, ensuring minimal inter-channel crosstalk during MIMO, multi-user interference simulation, and other tests.

[0020] Reference Figure 1As shown, the device includes: one or more analog front-end modules connected in parallel with an FPGA module. The FPGA module is used to receive the modulation method, frequency, bandwidth, output power and phase parameters configured by the user, and generate two digital baseband signals sI(n) and sQ(n) through a DDS. The modulation method includes any one of ASK, FSK, PSK, QPSK, QAM and OFDM. The analog front-end module includes a dual-channel DAC chip and a signal conditioning module. The dual-channel DAC chip is used to convert the digital baseband signals sI(n) and sQ(n) into analog signals sI(t) and sQ(t). The signal conditioning module is used to filter, up-convert and level-adjust the analog signals output by the dual-channel DAC chip to output radio frequency signals.

[0021] The signal conditioning module includes an analog low-pass filter, an IQ modulator, a PLL phase-locked loop, and a power adjustment module. The analog low-pass filter is used to band-limit the analog signal output by the dual-channel DAC chip to remove high-frequency noise and spurious signals. The IQ modulator is used to up-convert the filtered analog signal to obtain the radio frequency signal. The PLL phase-locked loop is used to perform feedback control on the local oscillator frequency and phase of the radio frequency signal. The power amplifier and the Π-type attenuator are used to amplify the radio frequency signal and adjust it to the target power.

[0022] The selection of the above-mentioned components follows the principle of "high performance + low cost + potential for domestic adaptation". In one embodiment of this disclosure, the dual-channel DAC chip adopts the dual-channel DAC5652IPFB chip, the PLL phase-locked loop adopts the ADF4350 chip with integrated VCO, the IQ modulator adopts the ADL5375-05ACPZ-R7 chip, and the power amplifier adopts the GVA-63+ chip.

[0023] All of the above-mentioned devices have domestic alternatives. For example, the DAC can be replaced with the Innosilicon DAC2167LFP-250, the PLL phase-locked loop can be replaced with the Core Interconnect CLF2574, and although there is no direct domestic alternative chip for the IQ modulator, it can be replaced with Unisoc's V510 through system-level design. After localization, the overall system cost can be reduced by more than 30%, and the performance indicators are basically the same.

[0024] The FPGA module undertakes four major functions: waveform generation, modulation mapping, channel synchronization, and interface communication. It is the core of low-cost, multi-modulation implementation. Without nanosecond-level or subdegree-level synchronization between channels, multi-channel MIMO testing is meaningless. Furthermore, the error vector amplitude (EVM) of each channel is poor. Even with initial synchronization, the analog links (such as amplifiers, filters, and transmission lines) will experience phase drift over time due to temperature changes, device aging, and power supply fluctuations. This leads to a deterioration in the phase relationship between multiple channels, affecting the test results of the entire array.

[0025] To address the issue of time reference and phase uniformity in multi-channel signals, the FPGA module employs an internal global clock network (GCLK) to provide a unified system clock for all channels. A phase alignment circuit synchronizes the sampling clock of the dual-channel DAC chip in each channel with the phase accumulator clock of the DDS core. A configurable phase offset is used to dynamically compensate for the phase of each channel, achieving an initial phase deviation of <1° between channels and a clock jitter of <10ps.

[0026] In one embodiment of this disclosure, the FPGA module provides a programmable phase rotator for each channel. By comparing the output signal of each channel with an internally generated reference signal, the phase error of each channel is calculated in real time, and the offset of the phase rotator for each channel is adjusted based on the phase error. This can improve the long-term phase stability of the system to <0.5° / hour, with a calibration accuracy of 0.1°.

[0027] While ensuring multi-channel synchronization, the modulation signal generated by each channel must have extremely high fidelity to meet the stringent requirements of error vector amplitude (EVM) for high-order modulation (64QAM / 256QAM). This system performs bandwidth constraint on the baseband IQ signal in the FPGA digital domain to prevent image spectrum and aliasing interference caused by DAC sampling at the source. Specifically, a 32nd-order linear-phase finite impulse response (FIR) low-pass filter is used to band-limit the IQ baseband signal. Its excellent passband flatness (ripple <0.1dB) and stopband attenuation >60dB effectively remove out-of-band energy. Simultaneously, the time-domain smoothness of the signal is further improved by increasing the signal sampling rate to four times the Nyquist frequency.

[0028] To address the amplitude / phase imbalance and local oscillator (LO) signal leakage issues in the IQ modulator, the system incorporates an adaptive calibration module based on the least mean square (LMS) algorithm. This module automatically and iteratively adjusts the gain and phase compensation coefficients in the FPGA digital domain until the image power is minimized. The system transmits a known calibration sequence, such as a signal only on the I or Q channels, or a known symmetrical signal. The image power (or LO leakage power) in the output signal is measured. The LMS algorithm automatically and iteratively adjusts the gain and phase compensation coefficients in the digital domain based on the error signal until the image power is minimized. After calibration, the amplitude imbalance is <0.1dB, the phase imbalance is <0.5°, and the image rejection ratio (IRR) is improved to >50dBc. A reverse DC bias is added to the I / Q channels in the digital domain to counteract the modulator's DC offset, resulting in LO leakage rejection of <-60dBc.

[0029] In multi-channel scenarios, the system achieves concurrent output of independent RF signals from multiple channels by time-division multiplexing of FPGA parallel logic resources and stacking of analog front-end modules. Each channel is isolated by an independent metal shield, and isolation slots are set on the PCB. The digital power supply and RF power supply are powered independently, achieving an isolation of >60dB between channels, effectively suppressing multi-channel crosstalk, and ensuring signal purity in complex test scenarios.

[0030] When the number of channels on a single board is insufficient (e.g., 100+ channels are required), multiple devices need to work collaboratively. The FPGA module achieves multi-board cascading through the IEEE 1588 Precision Time Protocol and external trigger signals. The IEEE 1588 PTP (Precision Time Protocol) is a standard protocol for distributing high-precision time information over a network. Through an Ethernet switch, the master clock can broadcast nanosecond-level timestamps to all slave devices. Each slave device calibrates its own clock accordingly, achieving inter-board time synchronization accuracy of <10ns.

[0031] By configuring the PLL's frequency division coefficients through the FPGA, reference local oscillator signals of different frequency bands can be flexibly output, covering the entire frequency band for industrial applications: 433 / 868 / 915MHz (IoT), 2.4 / 5.2 / 5.8GHz (WiFi / Bluetooth), Sub-6G band (5G industrial private network n1 / n3 / n28 / n41 / n78, etc.).

[0032] Multi-channel implementation is divided into two modes to adapt to different application scenarios: Fully parallel mode: Repeatedly list the baseband conditioning, DAC, and upconversion modules, with each group of modules corresponding to one independent signal output, supporting 10 parallel outputs, suitable for scenarios that require multiple signals to be output simultaneously, such as MIMO testing and multi-link interference testing; Time-division multiplexing mode: A single hardware module processes baseband signals from different channels in a time-division manner, and the FPGA logic switches inputs and outputs in a time-division manner, resulting in lower costs and suitability for scenarios such as automated production line testing where concurrent output is not required. Multi-channel synchronization adopts a unified reference clock architecture: All PLLs of all channels share the same 10MHz reference clock, and the FPGA baseband generation logic shares the same system clock, ensuring that the time difference between multiple signals is ≤1ns and the phase difference is ≤0.1°, meeting the synchronization requirements of coherent communication and MIMO beamforming testing. The isolation between channels is ≥60dB, avoiding crosstalk between multiple signals.

[0033] Reference Figure 2As shown, by arranging repeated electronic components (such as multiple DAC+IQ modulator+PA combinations, the PLL phase-locked loop can use the ADF4350 chip, the power amplifier uses the GVA-63+ chip, and the IQ modulator uses the ADL5375-05ACPZ-R7 chip), it is possible to achieve concurrent output of 1 to 10 channels of RF signals with different frequency points and different modulation methods within the 400MHz-6.2GHz frequency band.

[0034] The FPGA module is configured to output multiple digital baseband signals in parallel. Each channel can be independently configured with different modulation schemes, frequencies, and power levels. Channels can be independently controlled for switching and synchronization, supporting asynchronous or synchronous clock sources (depending on the FPGA system architecture) and cross-band operation (L-band, S-band, C-band, etc.). The DAC clock and PLL reference clock for all channels come from the same clock fan-out chip, ensuring strict synchronization of sampling clocks and local oscillator clocks between channels. The FPGA synchronizes the DDS data updates of all channels through a global trigger signal, ensuring the simultaneity and phase consistency of multi-channel signals. Each RF channel is isolated by an independent metal shield, and isolation slots are set on the PCB. The digital power supply and RF power supply are independently powered to avoid crosstalk between multiple signals.

[0035] In summary, this system reconstructs the traditional RF signal source architecture using software-defined hardware. Within the FPGA, a dual-phase accumulator, orthogonal lookup table, and configurable mapping logic enable parallel hardware-level generation of almost all mainstream modulation signals, including ASK, FSK, PSK, QAM, and OFDM. Zero-IF direct upconversion is employed, with the FPGA precisely controlling the DAC output of the IQ baseband signal, which is then directly transferred to the RF frequency via the IQ modulator. This eliminates the need for IF filters and multi-stage mixers in superheterodyne architectures, fundamentally reducing cost, size, and combinational spurious signals. The FPGA manages multiple independently programmable RF channels through shared clock and synchronization logic, achieving sub-nanosecond synchronization and strict coherence. This solves the expansion challenge from single-channel to dozens of channels at extremely low cost (without expensive synchronization backplanes), making it suitable for MIMO testing and beamforming verification.

[0036] It should be noted that this system architecture is not a closed design, but rather reserves clear upgrade interfaces for future technologies: DDS Engine Upgrade: The DDS core inside the FPGA can be iterated to a more advanced multi-delay-line phase interpolation DDS and CORDIC lookup-free DDS to improve instantaneous bandwidth and SFDR.

[0037] RF link upgrade: can be seamlessly replaced with RFDAC (high-speed DAC integrated RF output) or higher performance PLL / DAC chips, evolving towards millimeter wave band, >2 GHz bandwidth, SFDR>80 dBc.

[0038] Application scenario expansion: Currently used for communication testing, it can smoothly support cutting-edge fields such as 6G integrated sensing, quantum bit control array, and spaceborne software radio in the future.

[0039] It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions, and although a logical order is shown in the flowchart, in some cases the steps shown or described may be executed in a different order than that shown here.

[0040] Obviously, those skilled in the art should understand that the various units or steps of this application described above can be implemented using general-purpose computing devices. They can be centralized on a single computing device or distributed across a network of multiple computing devices. Optionally, they can be implemented using computer-executable program code, thereby storing them in a storage device for execution by a computing device, or fabricating them separately as individual integrated circuit modules, or fabricating multiple modules or steps into a single integrated circuit module. Thus, this application is not limited to any particular combination of hardware and software.

[0041] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A multi-channel digital vector signal source system, characterized in that, include: The system includes an FPGA module and one or more analog front-end modules connected in parallel with the FPGA module. The FPGA module receives user-configured signal modulation scheme, frequency, bandwidth, output power, and phase parameters, and generates I / Q dual-channel digital baseband signals through its internal DDS core. The analog front-end modules include a dual-channel DAC chip and a signal conditioning module. The dual-channel DAC chip converts the digital baseband signals into analog signals. The signal conditioning module filters, up-converts, and adjusts the level of the analog signals output by the dual-channel DAC chip to output radio frequency signals. The FPGA module uses an internal global clock network to provide a unified system clock for each channel, synchronizes the sampling clock of the dual-channel DAC chip of each channel with the phase accumulator clock of the DDS core through a phase alignment circuit, and dynamically compensates for the phase of each channel through a configurable phase offset.

2. The multi-channel digital vector signal source system according to claim 1, characterized in that, The signal conditioning module includes an analog low-pass filter, an IQ modulator, a PLL phase-locked loop, and a power adjustment module. The analog low-pass filter is used to band-limit the analog signal output by the dual-channel DAC chip to remove high-frequency noise and spurious signals. The IQ modulator is used to up-convert the filtered analog signal to obtain a radio frequency (RF) signal. The PLL is used to provide feedback control over the local oscillator frequency and phase of the RF signal. The power amplifier and the Π-type attenuator are used to amplify and adjust the RF signal to the target power.

3. The multi-channel digital vector signal source system according to claim 1, characterized in that, The FPGA module internally deploys a dual-phase accumulator, an orthogonal lookup table, and configurable modulation mapping logic to achieve hardware-level parallel generation of any digital modulation scheme among ASK, FSK, PSK, QPSK, QAM, and OFDM.

4. The multi-channel digital vector signal source system of claim 1, wherein, The FPGA module sets up a programmable phase rotator for each channel. By comparing the output signal of each channel with the internally generated reference signal, the phase error of each channel is calculated in real time, and the offset of the phase rotator of each channel is adjusted based on the phase error.

5. The multi-channel digital vector signal source system of claim 1, wherein, The FPGA module uses a 32nd-order FIR low-pass filter to band-limit the IQ baseband signal. The filter has a passband ripple of <0.1dB, a stopband attenuation of >60dB, and increases the signal sampling rate to 4 times the Nyquist frequency.

6. The multi-channel digital vector signal source system of claim 1, wherein, The system has a built-in adaptive calibration module based on the least mean square algorithm, which automatically and iteratively adjusts the gain compensation coefficient and phase compensation coefficient in the FPGA digital domain until the image power is minimized.

7. The multi-channel digital vector signal source system of claim 1, wherein, The system concurrently outputs multiple independent radio frequency signals by time-division multiplexing of FPGA parallel logic resources and stacking of analog front-end modules.

8. The multi-channel digital vector signal source system of claim 1, wherein, Each channel is isolated by an independent metal shield, and an isolation slot is set on the PCB. The digital power supply and the RF power supply are powered independently.

9. The multi-channel digital vector signal source system of claim 1, wherein The system achieves multi-board cascading through the IEEE 1588 precision time protocol and external trigger signals.

10. The multi-channel digital vector signal source system of claim 1, wherein The system is based on FPGA dynamic partial reconfiguration technology, which updates the modulation algorithm and signal processing logic online without interrupting operation.

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